| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.46 | 99.40 | 99.31 | 100.00 | 99.83 | 99.46 | 98.77 |
| T541 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.332385180 | Sep 18 07:53:54 PM UTC 24 | Sep 18 07:54:06 PM UTC 24 | 2637091184 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.3779656008 | Sep 18 07:53:26 PM UTC 24 | Sep 18 07:54:09 PM UTC 24 | 8685136458 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.3997003668 | Sep 18 07:53:21 PM UTC 24 | Sep 18 07:54:13 PM UTC 24 | 14552608613 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.1063060719 | Sep 18 07:53:58 PM UTC 24 | Sep 18 07:54:16 PM UTC 24 | 4791315027 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.1067948178 | Sep 18 07:53:55 PM UTC 24 | Sep 18 07:54:21 PM UTC 24 | 5098356796 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3547930180 | Sep 18 07:53:58 PM UTC 24 | Sep 18 07:54:00 PM UTC 24 | 85954339 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.3104481135 | Sep 18 07:53:58 PM UTC 24 | Sep 18 07:54:00 PM UTC 24 | 56613540 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.13076157 | Sep 18 07:53:58 PM UTC 24 | Sep 18 07:54:01 PM UTC 24 | 462579007 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.1462717876 | Sep 18 07:54:17 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 70114323 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2638529036 | Sep 18 07:53:58 PM UTC 24 | Sep 18 07:54:01 PM UTC 24 | 223780688 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1026247100 | Sep 18 07:53:58 PM UTC 24 | Sep 18 07:54:02 PM UTC 24 | 153277399 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.770509544 | Sep 18 07:54:00 PM UTC 24 | Sep 18 07:54:02 PM UTC 24 | 75530027 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.3271687635 | Sep 18 07:53:58 PM UTC 24 | Sep 18 07:54:02 PM UTC 24 | 171114082 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1693452837 | Sep 18 07:54:00 PM UTC 24 | Sep 18 07:54:02 PM UTC 24 | 89705501 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3350305875 | Sep 18 07:53:59 PM UTC 24 | Sep 18 07:54:02 PM UTC 24 | 211526942 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2991398300 | Sep 18 07:54:01 PM UTC 24 | Sep 18 07:54:03 PM UTC 24 | 134404568 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.28187956 | Sep 18 07:54:01 PM UTC 24 | Sep 18 07:54:03 PM UTC 24 | 87284152 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3204877815 | Sep 18 07:54:01 PM UTC 24 | Sep 18 07:54:04 PM UTC 24 | 117948404 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.4177738711 | Sep 18 07:53:59 PM UTC 24 | Sep 18 07:54:04 PM UTC 24 | 443205379 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2178669889 | Sep 18 07:54:17 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 73064302 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2225581988 | Sep 18 07:54:01 PM UTC 24 | Sep 18 07:54:04 PM UTC 24 | 215858393 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2186078931 | Sep 18 07:53:59 PM UTC 24 | Sep 18 07:54:04 PM UTC 24 | 949947307 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3666360905 | Sep 18 07:54:01 PM UTC 24 | Sep 18 07:54:04 PM UTC 24 | 471033721 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.1930631980 | Sep 18 07:54:03 PM UTC 24 | Sep 18 07:54:05 PM UTC 24 | 80989635 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2597114658 | Sep 18 07:54:03 PM UTC 24 | Sep 18 07:54:05 PM UTC 24 | 134445856 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1031081457 | Sep 18 07:54:03 PM UTC 24 | Sep 18 07:54:05 PM UTC 24 | 100038183 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.3715511957 | Sep 18 07:54:03 PM UTC 24 | Sep 18 07:54:05 PM UTC 24 | 59147130 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.486055079 | Sep 18 07:54:03 PM UTC 24 | Sep 18 07:54:05 PM UTC 24 | 202814712 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2105373621 | Sep 18 07:54:01 PM UTC 24 | Sep 18 07:54:05 PM UTC 24 | 200324114 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.340670392 | Sep 18 07:54:03 PM UTC 24 | Sep 18 07:54:06 PM UTC 24 | 217278374 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3964787820 | Sep 18 07:53:58 PM UTC 24 | Sep 18 07:54:06 PM UTC 24 | 477701113 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.883287309 | Sep 18 07:54:03 PM UTC 24 | Sep 18 07:54:06 PM UTC 24 | 136283896 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1496670790 | Sep 18 07:54:00 PM UTC 24 | Sep 18 07:54:06 PM UTC 24 | 1175632051 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3654535531 | Sep 18 07:54:04 PM UTC 24 | Sep 18 07:54:06 PM UTC 24 | 104166329 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.1552749088 | Sep 18 07:54:04 PM UTC 24 | Sep 18 07:54:06 PM UTC 24 | 70444228 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1212112749 | Sep 18 07:54:03 PM UTC 24 | Sep 18 07:54:07 PM UTC 24 | 363914031 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1767186220 | Sep 18 07:54:04 PM UTC 24 | Sep 18 07:54:07 PM UTC 24 | 126610934 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2688166379 | Sep 18 07:54:04 PM UTC 24 | Sep 18 07:54:07 PM UTC 24 | 228292316 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1231318990 | Sep 18 07:54:12 PM UTC 24 | Sep 18 07:54:14 PM UTC 24 | 72938571 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.543518815 | Sep 18 07:54:04 PM UTC 24 | Sep 18 07:54:08 PM UTC 24 | 137370229 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3446259595 | Sep 18 07:54:04 PM UTC 24 | Sep 18 07:54:08 PM UTC 24 | 486945610 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.824956036 | Sep 18 07:54:03 PM UTC 24 | Sep 18 07:54:08 PM UTC 24 | 916991056 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.3230120241 | Sep 18 07:54:06 PM UTC 24 | Sep 18 07:54:08 PM UTC 24 | 73785050 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3945719228 | Sep 18 07:54:06 PM UTC 24 | Sep 18 07:54:08 PM UTC 24 | 198731978 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1606969739 | Sep 18 07:54:06 PM UTC 24 | Sep 18 07:54:08 PM UTC 24 | 112624713 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2353050474 | Sep 18 07:54:06 PM UTC 24 | Sep 18 07:54:08 PM UTC 24 | 105569556 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4289610430 | Sep 18 07:54:06 PM UTC 24 | Sep 18 07:54:09 PM UTC 24 | 240413754 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3511513766 | Sep 18 07:54:06 PM UTC 24 | Sep 18 07:54:09 PM UTC 24 | 504617131 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.1950482347 | Sep 18 07:54:08 PM UTC 24 | Sep 18 07:54:10 PM UTC 24 | 89736517 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.3187195151 | Sep 18 07:54:08 PM UTC 24 | Sep 18 07:54:10 PM UTC 24 | 57364666 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4189677753 | Sep 18 07:54:07 PM UTC 24 | Sep 18 07:54:10 PM UTC 24 | 207899800 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1370735300 | Sep 18 07:54:03 PM UTC 24 | Sep 18 07:54:10 PM UTC 24 | 1175876502 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.4221558937 | Sep 18 07:54:03 PM UTC 24 | Sep 18 07:54:10 PM UTC 24 | 484037776 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2028168718 | Sep 18 07:54:08 PM UTC 24 | Sep 18 07:54:10 PM UTC 24 | 113907862 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.485117531 | Sep 18 07:54:08 PM UTC 24 | Sep 18 07:54:11 PM UTC 24 | 224492422 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3889017038 | Sep 18 07:54:08 PM UTC 24 | Sep 18 07:54:11 PM UTC 24 | 226450232 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4248240037 | Sep 18 07:54:08 PM UTC 24 | Sep 18 07:54:11 PM UTC 24 | 238248614 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.3228179394 | Sep 18 07:54:06 PM UTC 24 | Sep 18 07:54:11 PM UTC 24 | 447833937 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.2193181685 | Sep 18 07:54:08 PM UTC 24 | Sep 18 07:54:11 PM UTC 24 | 145331641 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4107808328 | Sep 18 07:54:08 PM UTC 24 | Sep 18 07:54:11 PM UTC 24 | 486706465 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3934426652 | Sep 18 07:54:10 PM UTC 24 | Sep 18 07:54:14 PM UTC 24 | 1005623157 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1708053746 | Sep 18 07:54:08 PM UTC 24 | Sep 18 07:54:11 PM UTC 24 | 188489100 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.1883983360 | Sep 18 07:54:10 PM UTC 24 | Sep 18 07:54:12 PM UTC 24 | 74284669 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3123405141 | Sep 18 07:54:08 PM UTC 24 | Sep 18 07:54:12 PM UTC 24 | 877877208 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.110644243 | Sep 18 07:54:10 PM UTC 24 | Sep 18 07:54:12 PM UTC 24 | 62902248 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2244424011 | Sep 18 07:54:08 PM UTC 24 | Sep 18 07:54:12 PM UTC 24 | 504407525 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.845796557 | Sep 18 07:54:10 PM UTC 24 | Sep 18 07:54:12 PM UTC 24 | 112707518 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3669265841 | Sep 18 07:54:10 PM UTC 24 | Sep 18 07:54:12 PM UTC 24 | 132065020 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2863475894 | Sep 18 07:54:07 PM UTC 24 | Sep 18 07:54:12 PM UTC 24 | 476082812 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1529625553 | Sep 18 07:54:10 PM UTC 24 | Sep 18 07:54:12 PM UTC 24 | 232365342 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3439156663 | Sep 18 07:54:10 PM UTC 24 | Sep 18 07:54:12 PM UTC 24 | 181650611 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.2881075464 | Sep 18 07:54:10 PM UTC 24 | Sep 18 07:54:13 PM UTC 24 | 176697936 ps | ||
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| T583 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.3433355759 | Sep 18 07:54:12 PM UTC 24 | Sep 18 07:54:14 PM UTC 24 | 57730017 ps | ||
| T584 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.846042832 | Sep 18 07:54:12 PM UTC 24 | Sep 18 07:54:15 PM UTC 24 | 148703794 ps | ||
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| T145 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.255719319 | Sep 18 07:54:12 PM UTC 24 | Sep 18 07:54:15 PM UTC 24 | 436860784 ps | ||
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| T588 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.1381762247 | Sep 18 07:54:15 PM UTC 24 | Sep 18 07:54:17 PM UTC 24 | 81455458 ps | ||
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| T146 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2111967060 | Sep 18 07:54:12 PM UTC 24 | Sep 18 07:54:17 PM UTC 24 | 780629827 ps | ||
| T591 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2355040354 | Sep 18 07:54:14 PM UTC 24 | Sep 18 07:54:17 PM UTC 24 | 80190701 ps | ||
| T592 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.646050204 | Sep 18 07:54:15 PM UTC 24 | Sep 18 07:54:17 PM UTC 24 | 172483586 ps | ||
| T593 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2303200142 | Sep 18 07:54:15 PM UTC 24 | Sep 18 07:54:17 PM UTC 24 | 195656453 ps | ||
| T594 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3085448243 | Sep 18 07:54:06 PM UTC 24 | Sep 18 07:54:17 PM UTC 24 | 2311917802 ps | ||
| T595 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1150704236 | Sep 18 07:54:15 PM UTC 24 | Sep 18 07:54:17 PM UTC 24 | 200994916 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.461321768 | Sep 18 07:54:15 PM UTC 24 | Sep 18 07:54:17 PM UTC 24 | 424369439 ps | ||
| T596 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3475516284 | Sep 18 07:54:15 PM UTC 24 | Sep 18 07:54:17 PM UTC 24 | 210989854 ps | ||
| T597 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.3526952943 | Sep 18 07:54:15 PM UTC 24 | Sep 18 07:54:18 PM UTC 24 | 241149196 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3185306811 | Sep 18 07:54:14 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 793877273 ps | ||
| T598 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.3676653807 | Sep 18 07:54:14 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 203237032 ps | ||
| T599 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.3689032873 | Sep 18 07:54:15 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 480692972 ps | ||
| T600 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3213604123 | Sep 18 07:54:17 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 127831153 ps | ||
| T601 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3371653444 | Sep 18 07:54:15 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 769085507 ps | ||
| T602 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.1687940232 | Sep 18 07:54:17 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 85791082 ps | ||
| T603 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2381687725 | Sep 18 07:54:17 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 96071115 ps | ||
| T604 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1031089331 | Sep 18 07:54:17 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 126290769 ps | ||
| T605 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.691405111 | Sep 18 07:54:17 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 172827625 ps | ||
| T606 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3165805831 | Sep 18 07:54:17 PM UTC 24 | Sep 18 07:54:19 PM UTC 24 | 209988469 ps | ||
| T607 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1729062102 | Sep 18 07:54:17 PM UTC 24 | Sep 18 07:54:20 PM UTC 24 | 485871754 ps | ||
| T608 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.3808210778 | Sep 18 07:54:17 PM UTC 24 | Sep 18 07:54:20 PM UTC 24 | 187024768 ps | ||
| T609 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2198267618 | Sep 18 07:54:17 PM UTC 24 | Sep 18 07:54:21 PM UTC 24 | 793031721 ps | ||
| T610 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1998895914 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:23 PM UTC 24 | 78026850 ps | ||
| T611 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1902092727 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:23 PM UTC 24 | 84734690 ps | ||
| T612 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1420839374 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:23 PM UTC 24 | 79289392 ps | ||
| T613 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.533308945 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:23 PM UTC 24 | 82122199 ps | ||
| T614 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3354194203 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:23 PM UTC 24 | 126997307 ps | ||
| T615 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.614256188 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:23 PM UTC 24 | 167407440 ps | ||
| T616 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.134710232 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:23 PM UTC 24 | 144148537 ps | ||
| T617 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3828844561 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:24 PM UTC 24 | 183705590 ps | ||
| T618 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1923596977 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:25 PM UTC 24 | 171817390 ps | ||
| T619 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.953342127 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:25 PM UTC 24 | 786129399 ps | ||
| T620 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.625608399 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:25 PM UTC 24 | 503367597 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1289783586 | Sep 18 07:54:21 PM UTC 24 | Sep 18 07:54:25 PM UTC 24 | 915172744 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.4041459687 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 198231790 ps |
| CPU time | 1.59 seconds |
| Started | Sep 18 07:52:05 PM UTC 24 |
| Finished | Sep 18 07:52:08 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041459687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4041459687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.3003232451 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1350740401 ps |
| CPU time | 7.56 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:53 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003232451 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3003232451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.1960313273 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 282365064 ps |
| CPU time | 2.09 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:47 PM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960313273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1960313273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.3271687635 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 171114082 ps |
| CPU time | 2.67 seconds |
| Started | Sep 18 07:53:58 PM UTC 24 |
| Finished | Sep 18 07:54:02 PM UTC 24 |
| Peak memory | 217684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271687635 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3271687635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.875347214 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 8873607522 ps |
| CPU time | 14.28 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:52:00 PM UTC 24 |
| Peak memory | 243728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875347214 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.875347214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.869745591 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1265499537 ps |
| CPU time | 6.5 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:52 PM UTC 24 |
| Peak memory | 244096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869745591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.869745591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.13076157 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 462579007 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 07:53:58 PM UTC 24 |
| Finished | Sep 18 07:54:01 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13076157 -assert nopostproc +UVM_TESTNAM E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.13076157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.3359247915 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1927583870 ps |
| CPU time | 7.51 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:52 PM UTC 24 |
| Peak memory | 222320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359247915 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3359247915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.2781951863 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2436268609 ps |
| CPU time | 9.73 seconds |
| Started | Sep 18 07:51:58 PM UTC 24 |
| Finished | Sep 18 07:52:09 PM UTC 24 |
| Peak memory | 243644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781951863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2781951863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.2780642817 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 146903738 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:46 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780642817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2780642817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.27761083 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 97576274 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:51:51 PM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27761083 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.27761083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.831158425 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 146535853 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:46 PM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831158425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.831158425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.824956036 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 916991056 ps |
| CPU time | 4.02 seconds |
| Started | Sep 18 07:54:03 PM UTC 24 |
| Finished | Sep 18 07:54:08 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824956036 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.824956036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.3951964398 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 6206449937 ps |
| CPU time | 28.44 seconds |
| Started | Sep 18 07:51:53 PM UTC 24 |
| Finished | Sep 18 07:52:23 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951964398 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3951964398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.3499515084 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 199276743 ps |
| CPU time | 3.21 seconds |
| Started | Sep 18 07:54:10 PM UTC 24 |
| Finished | Sep 18 07:54:14 PM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499515084 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3499515084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.4290193695 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 108735658 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:45 PM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290193695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4290193695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.3415488834 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2262002112 ps |
| CPU time | 8.02 seconds |
| Started | Sep 18 07:52:15 PM UTC 24 |
| Finished | Sep 18 07:52:24 PM UTC 24 |
| Peak memory | 243244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415488834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3415488834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.3104481135 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 56613540 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 07:53:58 PM UTC 24 |
| Finished | Sep 18 07:54:00 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104481135 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3104481135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.181103157 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 301905902 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:47 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181103157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.181103157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2186078931 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 949947307 ps |
| CPU time | 3.8 seconds |
| Started | Sep 18 07:53:59 PM UTC 24 |
| Finished | Sep 18 07:54:04 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186078931 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.2186078931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3372897129 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 949421537 ps |
| CPU time | 3.04 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:16 PM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372897129 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.3372897129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.461321768 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 424369439 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:54:15 PM UTC 24 |
| Finished | Sep 18 07:54:17 PM UTC 24 |
| Peak memory | 207760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461321768 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.461321768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3934426652 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1005623157 ps |
| CPU time | 3.38 seconds |
| Started | Sep 18 07:54:10 PM UTC 24 |
| Finished | Sep 18 07:54:14 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934426652 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.3934426652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1026247100 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 153277399 ps |
| CPU time | 2.36 seconds |
| Started | Sep 18 07:53:58 PM UTC 24 |
| Finished | Sep 18 07:54:02 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026247100 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1026247100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3964787820 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 477701113 ps |
| CPU time | 6.5 seconds |
| Started | Sep 18 07:53:58 PM UTC 24 |
| Finished | Sep 18 07:54:06 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964787820 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3964787820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3547930180 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 85954339 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 07:53:58 PM UTC 24 |
| Finished | Sep 18 07:54:00 PM UTC 24 |
| Peak memory | 208032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547930180 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3547930180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3350305875 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 211526942 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:53:59 PM UTC 24 |
| Finished | Sep 18 07:54:02 PM UTC 24 |
| Peak memory | 217556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3350305875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_w ith_rand_reset.3350305875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2638529036 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 223780688 ps |
| CPU time | 1.99 seconds |
| Started | Sep 18 07:53:58 PM UTC 24 |
| Finished | Sep 18 07:54:01 PM UTC 24 |
| Peak memory | 207728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638529036 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.2638529036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2225581988 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 215858393 ps |
| CPU time | 2.45 seconds |
| Started | Sep 18 07:54:01 PM UTC 24 |
| Finished | Sep 18 07:54:04 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225581988 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2225581988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1496670790 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1175632051 ps |
| CPU time | 5.76 seconds |
| Started | Sep 18 07:54:00 PM UTC 24 |
| Finished | Sep 18 07:54:06 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496670790 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1496670790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1693452837 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 89705501 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 07:54:00 PM UTC 24 |
| Finished | Sep 18 07:54:02 PM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693452837 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1693452837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2991398300 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 134404568 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:54:01 PM UTC 24 |
| Finished | Sep 18 07:54:03 PM UTC 24 |
| Peak memory | 217556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2991398300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w ith_rand_reset.2991398300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.770509544 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 75530027 ps |
| CPU time | 1.05 seconds |
| Started | Sep 18 07:54:00 PM UTC 24 |
| Finished | Sep 18 07:54:02 PM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770509544 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.770509544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.28187956 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 87284152 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 07:54:01 PM UTC 24 |
| Finished | Sep 18 07:54:03 PM UTC 24 |
| Peak memory | 207768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28187956 -assert nopostproc +UV M_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.28187956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.4177738711 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 443205379 ps |
| CPU time | 3.71 seconds |
| Started | Sep 18 07:53:59 PM UTC 24 |
| Finished | Sep 18 07:54:04 PM UTC 24 |
| Peak memory | 225284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177738711 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.4177738711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1574161066 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 188327004 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:14 PM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1574161066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_ with_rand_reset.1574161066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.1516058471 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 67494246 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:14 PM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516058471 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1516058471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1231318990 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 72938571 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:14 PM UTC 24 |
| Peak memory | 207832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231318990 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.1231318990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.853169087 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 140583475 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:15 PM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=853169087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_w ith_rand_reset.853169087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.3762587716 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 80655150 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:14 PM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762587716 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3762587716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.846042832 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 148703794 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:15 PM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846042832 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.846042832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.566965846 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 141106033 ps |
| CPU time | 2.12 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:15 PM UTC 24 |
| Peak memory | 217764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566965846 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.566965846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.255719319 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 436860784 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:15 PM UTC 24 |
| Peak memory | 207724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255719319 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.255719319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1093193838 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 187117150 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 07:54:14 PM UTC 24 |
| Finished | Sep 18 07:54:17 PM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1093193838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_ with_rand_reset.1093193838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.3433355759 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 57730017 ps |
| CPU time | 1 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:14 PM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433355759 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3433355759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2355040354 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 80190701 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 07:54:14 PM UTC 24 |
| Finished | Sep 18 07:54:17 PM UTC 24 |
| Peak memory | 207832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355040354 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.2355040354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.1492599058 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 118733534 ps |
| CPU time | 1.92 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:15 PM UTC 24 |
| Peak memory | 217636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492599058 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1492599058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2111967060 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 780629827 ps |
| CPU time | 3.22 seconds |
| Started | Sep 18 07:54:12 PM UTC 24 |
| Finished | Sep 18 07:54:17 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111967060 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.2111967060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.646050204 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 172483586 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 07:54:15 PM UTC 24 |
| Finished | Sep 18 07:54:17 PM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=646050204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_w ith_rand_reset.646050204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.1381762247 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 81455458 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 07:54:15 PM UTC 24 |
| Finished | Sep 18 07:54:17 PM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381762247 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1381762247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2303200142 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 195656453 ps |
| CPU time | 1.6 seconds |
| Started | Sep 18 07:54:15 PM UTC 24 |
| Finished | Sep 18 07:54:17 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303200142 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.2303200142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.3676653807 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 203237032 ps |
| CPU time | 3.09 seconds |
| Started | Sep 18 07:54:14 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676653807 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3676653807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3185306811 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 793877273 ps |
| CPU time | 3.02 seconds |
| Started | Sep 18 07:54:14 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185306811 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.3185306811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1150704236 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 200994916 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 07:54:15 PM UTC 24 |
| Finished | Sep 18 07:54:17 PM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1150704236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_ with_rand_reset.1150704236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.1445835738 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 57324333 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 07:54:15 PM UTC 24 |
| Finished | Sep 18 07:54:17 PM UTC 24 |
| Peak memory | 207384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445835738 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1445835738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3475516284 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 210989854 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 07:54:15 PM UTC 24 |
| Finished | Sep 18 07:54:17 PM UTC 24 |
| Peak memory | 207832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475516284 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.3475516284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.3689032873 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 480692972 ps |
| CPU time | 3.26 seconds |
| Started | Sep 18 07:54:15 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 217684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689032873 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3689032873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.691405111 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 172827625 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:54:17 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=691405111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_w ith_rand_reset.691405111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.1462717876 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 70114323 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 07:54:17 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 207032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462717876 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1462717876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3213604123 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 127831153 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 07:54:17 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213604123 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.3213604123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.3526952943 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 241149196 ps |
| CPU time | 2.31 seconds |
| Started | Sep 18 07:54:15 PM UTC 24 |
| Finished | Sep 18 07:54:18 PM UTC 24 |
| Peak memory | 225276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526952943 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3526952943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3371653444 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 769085507 ps |
| CPU time | 2.97 seconds |
| Started | Sep 18 07:54:15 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371653444 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.3371653444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1031089331 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 126290769 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 07:54:17 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1031089331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_ with_rand_reset.1031089331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.1687940232 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 85791082 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 07:54:17 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687940232 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1687940232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3165805831 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 209988469 ps |
| CPU time | 1.49 seconds |
| Started | Sep 18 07:54:17 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165805831 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.3165805831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2381687725 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 96071115 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:54:17 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 217636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381687725 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2381687725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2198267618 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 793031721 ps |
| CPU time | 2.7 seconds |
| Started | Sep 18 07:54:17 PM UTC 24 |
| Finished | Sep 18 07:54:21 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198267618 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.2198267618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.134710232 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 144148537 ps |
| CPU time | 1.62 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:23 PM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=134710232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_w ith_rand_reset.134710232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2178669889 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 73064302 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 07:54:17 PM UTC 24 |
| Finished | Sep 18 07:54:19 PM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178669889 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2178669889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1998895914 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 78026850 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:23 PM UTC 24 |
| Peak memory | 207832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998895914 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.1998895914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.3808210778 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 187024768 ps |
| CPU time | 2.32 seconds |
| Started | Sep 18 07:54:17 PM UTC 24 |
| Finished | Sep 18 07:54:20 PM UTC 24 |
| Peak memory | 217840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808210778 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3808210778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1729062102 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 485871754 ps |
| CPU time | 2.01 seconds |
| Started | Sep 18 07:54:17 PM UTC 24 |
| Finished | Sep 18 07:54:20 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729062102 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.1729062102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.614256188 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 167407440 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:23 PM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=614256188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_w ith_rand_reset.614256188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1902092727 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 84734690 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:23 PM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902092727 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1902092727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.533308945 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 82122199 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:23 PM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533308945 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.533308945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.625608399 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 503367597 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:25 PM UTC 24 |
| Peak memory | 224840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625608399 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.625608399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1289783586 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 915172744 ps |
| CPU time | 3.58 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:25 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289783586 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.1289783586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3828844561 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 183705590 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:24 PM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3828844561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_ with_rand_reset.3828844561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1420839374 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 79289392 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:23 PM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420839374 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1420839374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3354194203 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 126997307 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:23 PM UTC 24 |
| Peak memory | 207832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354194203 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.3354194203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1923596977 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 171817390 ps |
| CPU time | 2.56 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:25 PM UTC 24 |
| Peak memory | 217776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923596977 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1923596977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.953342127 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 786129399 ps |
| CPU time | 2.78 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:25 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953342127 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.953342127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.486055079 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 202814712 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:54:03 PM UTC 24 |
| Finished | Sep 18 07:54:05 PM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486055079 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.486055079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.4221558937 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 484037776 ps |
| CPU time | 6.34 seconds |
| Started | Sep 18 07:54:03 PM UTC 24 |
| Finished | Sep 18 07:54:10 PM UTC 24 |
| Peak memory | 225152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221558937 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.4221558937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3204877815 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 117948404 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 07:54:01 PM UTC 24 |
| Finished | Sep 18 07:54:04 PM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204877815 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3204877815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2597114658 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 134445856 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 07:54:03 PM UTC 24 |
| Finished | Sep 18 07:54:05 PM UTC 24 |
| Peak memory | 207764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2597114658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_w ith_rand_reset.2597114658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.1930631980 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 80989635 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 07:54:03 PM UTC 24 |
| Finished | Sep 18 07:54:05 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930631980 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1930631980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.340670392 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 217278374 ps |
| CPU time | 1.85 seconds |
| Started | Sep 18 07:54:03 PM UTC 24 |
| Finished | Sep 18 07:54:06 PM UTC 24 |
| Peak memory | 207768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340670392 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.340670392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2105373621 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 200324114 ps |
| CPU time | 3.41 seconds |
| Started | Sep 18 07:54:01 PM UTC 24 |
| Finished | Sep 18 07:54:05 PM UTC 24 |
| Peak memory | 225032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105373621 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2105373621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3666360905 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 471033721 ps |
| CPU time | 2.27 seconds |
| Started | Sep 18 07:54:01 PM UTC 24 |
| Finished | Sep 18 07:54:04 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666360905 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.3666360905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1212112749 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 363914031 ps |
| CPU time | 2.57 seconds |
| Started | Sep 18 07:54:03 PM UTC 24 |
| Finished | Sep 18 07:54:07 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212112749 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1212112749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1370735300 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1175876502 ps |
| CPU time | 5.86 seconds |
| Started | Sep 18 07:54:03 PM UTC 24 |
| Finished | Sep 18 07:54:10 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370735300 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1370735300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1031081457 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 100038183 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 07:54:03 PM UTC 24 |
| Finished | Sep 18 07:54:05 PM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031081457 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1031081457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1767186220 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 126610934 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 07:54:04 PM UTC 24 |
| Finished | Sep 18 07:54:07 PM UTC 24 |
| Peak memory | 217636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1767186220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_w ith_rand_reset.1767186220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.3715511957 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 59147130 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 07:54:03 PM UTC 24 |
| Finished | Sep 18 07:54:05 PM UTC 24 |
| Peak memory | 207696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715511957 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3715511957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2688166379 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 228292316 ps |
| CPU time | 1.59 seconds |
| Started | Sep 18 07:54:04 PM UTC 24 |
| Finished | Sep 18 07:54:07 PM UTC 24 |
| Peak memory | 207724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688166379 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.2688166379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.883287309 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 136283896 ps |
| CPU time | 2.33 seconds |
| Started | Sep 18 07:54:03 PM UTC 24 |
| Finished | Sep 18 07:54:06 PM UTC 24 |
| Peak memory | 221780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883287309 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.883287309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2353050474 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 105569556 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 07:54:06 PM UTC 24 |
| Finished | Sep 18 07:54:08 PM UTC 24 |
| Peak memory | 207656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353050474 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2353050474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3085448243 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2311917802 ps |
| CPU time | 10.34 seconds |
| Started | Sep 18 07:54:06 PM UTC 24 |
| Finished | Sep 18 07:54:17 PM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085448243 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3085448243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3654535531 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 104166329 ps |
| CPU time | 1.15 seconds |
| Started | Sep 18 07:54:04 PM UTC 24 |
| Finished | Sep 18 07:54:06 PM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654535531 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3654535531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1606969739 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 112624713 ps |
| CPU time | 1.39 seconds |
| Started | Sep 18 07:54:06 PM UTC 24 |
| Finished | Sep 18 07:54:08 PM UTC 24 |
| Peak memory | 217556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1606969739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_w ith_rand_reset.1606969739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.1552749088 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 70444228 ps |
| CPU time | 1.09 seconds |
| Started | Sep 18 07:54:04 PM UTC 24 |
| Finished | Sep 18 07:54:06 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552749088 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1552749088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3945719228 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 198731978 ps |
| CPU time | 1.56 seconds |
| Started | Sep 18 07:54:06 PM UTC 24 |
| Finished | Sep 18 07:54:08 PM UTC 24 |
| Peak memory | 207772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945719228 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.3945719228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.543518815 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 137370229 ps |
| CPU time | 2.19 seconds |
| Started | Sep 18 07:54:04 PM UTC 24 |
| Finished | Sep 18 07:54:08 PM UTC 24 |
| Peak memory | 221844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543518815 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.543518815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3446259595 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 486945610 ps |
| CPU time | 2.26 seconds |
| Started | Sep 18 07:54:04 PM UTC 24 |
| Finished | Sep 18 07:54:08 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446259595 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.3446259595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4189677753 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 207899800 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 07:54:07 PM UTC 24 |
| Finished | Sep 18 07:54:10 PM UTC 24 |
| Peak memory | 207764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4189677753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w ith_rand_reset.4189677753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.3230120241 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 73785050 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 07:54:06 PM UTC 24 |
| Finished | Sep 18 07:54:08 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230120241 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3230120241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4289610430 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 240413754 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 07:54:06 PM UTC 24 |
| Finished | Sep 18 07:54:09 PM UTC 24 |
| Peak memory | 207764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289610430 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.4289610430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.3228179394 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 447833937 ps |
| CPU time | 3.92 seconds |
| Started | Sep 18 07:54:06 PM UTC 24 |
| Finished | Sep 18 07:54:11 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228179394 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3228179394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3511513766 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 504617131 ps |
| CPU time | 2.04 seconds |
| Started | Sep 18 07:54:06 PM UTC 24 |
| Finished | Sep 18 07:54:09 PM UTC 24 |
| Peak memory | 208552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511513766 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.3511513766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2028168718 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 113907862 ps |
| CPU time | 1.72 seconds |
| Started | Sep 18 07:54:08 PM UTC 24 |
| Finished | Sep 18 07:54:10 PM UTC 24 |
| Peak memory | 217556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2028168718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w ith_rand_reset.2028168718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.1950482347 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 89736517 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 07:54:08 PM UTC 24 |
| Finished | Sep 18 07:54:10 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950482347 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1950482347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4248240037 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 238248614 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 07:54:08 PM UTC 24 |
| Finished | Sep 18 07:54:11 PM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248240037 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.4248240037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2863475894 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 476082812 ps |
| CPU time | 3.7 seconds |
| Started | Sep 18 07:54:07 PM UTC 24 |
| Finished | Sep 18 07:54:12 PM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863475894 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2863475894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3123405141 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 877877208 ps |
| CPU time | 3.23 seconds |
| Started | Sep 18 07:54:08 PM UTC 24 |
| Finished | Sep 18 07:54:12 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123405141 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.3123405141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1708053746 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 188489100 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 07:54:08 PM UTC 24 |
| Finished | Sep 18 07:54:11 PM UTC 24 |
| Peak memory | 217776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1708053746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w ith_rand_reset.1708053746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.3187195151 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 57364666 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 07:54:08 PM UTC 24 |
| Finished | Sep 18 07:54:10 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187195151 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3187195151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3889017038 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 226450232 ps |
| CPU time | 1.8 seconds |
| Started | Sep 18 07:54:08 PM UTC 24 |
| Finished | Sep 18 07:54:11 PM UTC 24 |
| Peak memory | 207724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889017038 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.3889017038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.485117531 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 224492422 ps |
| CPU time | 1.82 seconds |
| Started | Sep 18 07:54:08 PM UTC 24 |
| Finished | Sep 18 07:54:11 PM UTC 24 |
| Peak memory | 224924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485117531 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.485117531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2244424011 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 504407525 ps |
| CPU time | 3.18 seconds |
| Started | Sep 18 07:54:08 PM UTC 24 |
| Finished | Sep 18 07:54:12 PM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244424011 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.2244424011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.845796557 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 112707518 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 07:54:10 PM UTC 24 |
| Finished | Sep 18 07:54:12 PM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=845796557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_wi th_rand_reset.845796557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.1883983360 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 74284669 ps |
| CPU time | 1.02 seconds |
| Started | Sep 18 07:54:10 PM UTC 24 |
| Finished | Sep 18 07:54:12 PM UTC 24 |
| Peak memory | 207680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883983360 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1883983360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1529625553 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 232365342 ps |
| CPU time | 1.75 seconds |
| Started | Sep 18 07:54:10 PM UTC 24 |
| Finished | Sep 18 07:54:12 PM UTC 24 |
| Peak memory | 207764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529625553 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.1529625553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.2193181685 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 145331641 ps |
| CPU time | 2.1 seconds |
| Started | Sep 18 07:54:08 PM UTC 24 |
| Finished | Sep 18 07:54:11 PM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193181685 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2193181685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4107808328 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 486706465 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 07:54:08 PM UTC 24 |
| Finished | Sep 18 07:54:11 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107808328 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.4107808328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3439156663 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 181650611 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 07:54:10 PM UTC 24 |
| Finished | Sep 18 07:54:12 PM UTC 24 |
| Peak memory | 217556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3439156663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_w ith_rand_reset.3439156663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.110644243 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 62902248 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 07:54:10 PM UTC 24 |
| Finished | Sep 18 07:54:12 PM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110644243 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.110644243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3669265841 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 132065020 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 07:54:10 PM UTC 24 |
| Finished | Sep 18 07:54:12 PM UTC 24 |
| Peak memory | 207736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669265841 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.3669265841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.2881075464 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 176697936 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 07:54:10 PM UTC 24 |
| Finished | Sep 18 07:54:13 PM UTC 24 |
| Peak memory | 225248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881075464 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2881075464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.3615956164 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 69249090 ps |
| CPU time | 1.02 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:46 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615956164 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3615956164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.1801212416 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2453667455 ps |
| CPU time | 8.85 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:53 PM UTC 24 |
| Peak memory | 244608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801212416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1801212416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.667674619 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1139780511 ps |
| CPU time | 5.06 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:49 PM UTC 24 |
| Peak memory | 211388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667674619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.667674619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.4187129257 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 8622634229 ps |
| CPU time | 15.67 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:52:00 PM UTC 24 |
| Peak memory | 243056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187129257 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4187129257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.3518211304 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 203607556 ps |
| CPU time | 1.83 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:46 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518211304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3518211304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.2138797152 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 81778225 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:46 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138797152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2138797152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.3679687785 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 62563462 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:46 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679687785 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3679687785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2764455412 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 302902924 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:47 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764455412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2764455412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.3092398018 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 108072926 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:46 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092398018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3092398018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.3498189874 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1920008659 ps |
| CPU time | 7.36 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:52 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498189874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3498189874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.329325172 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 179193348 ps |
| CPU time | 1.53 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:47 PM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329325172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.329325172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.2646087913 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 129284563 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 07:51:43 PM UTC 24 |
| Finished | Sep 18 07:51:46 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646087913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2646087913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.2375673348 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 342996254 ps |
| CPU time | 2.83 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:48 PM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375673348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2375673348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1474626752 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 256029481 ps |
| CPU time | 1.69 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:47 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474626752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1474626752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.2507321835 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 56734715 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 07:52:11 PM UTC 24 |
| Finished | Sep 18 07:52:13 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507321835 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2507321835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.3501587903 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1975178356 ps |
| CPU time | 7.99 seconds |
| Started | Sep 18 07:52:10 PM UTC 24 |
| Finished | Sep 18 07:52:19 PM UTC 24 |
| Peak memory | 243664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501587903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3501587903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.696693769 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 301277314 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 07:52:10 PM UTC 24 |
| Finished | Sep 18 07:52:13 PM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696693769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.696693769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.2407304790 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 150873511 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 07:52:08 PM UTC 24 |
| Finished | Sep 18 07:52:10 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407304790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2407304790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.2550354286 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 925780913 ps |
| CPU time | 6.47 seconds |
| Started | Sep 18 07:52:09 PM UTC 24 |
| Finished | Sep 18 07:52:17 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550354286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2550354286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3559275761 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 99152891 ps |
| CPU time | 1.52 seconds |
| Started | Sep 18 07:52:10 PM UTC 24 |
| Finished | Sep 18 07:52:12 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559275761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3559275761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.1256843872 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 111948305 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 07:52:08 PM UTC 24 |
| Finished | Sep 18 07:52:10 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256843872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1256843872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.1514411674 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 248153998 ps |
| CPU time | 2.71 seconds |
| Started | Sep 18 07:52:10 PM UTC 24 |
| Finished | Sep 18 07:52:14 PM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514411674 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1514411674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.637472346 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 137036241 ps |
| CPU time | 2.72 seconds |
| Started | Sep 18 07:52:10 PM UTC 24 |
| Finished | Sep 18 07:52:13 PM UTC 24 |
| Peak memory | 220276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637472346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.637472346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.213904271 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 108485426 ps |
| CPU time | 1.47 seconds |
| Started | Sep 18 07:52:09 PM UTC 24 |
| Finished | Sep 18 07:52:12 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213904271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.213904271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.871655827 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 72736025 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 07:52:14 PM UTC 24 |
| Finished | Sep 18 07:52:16 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871655827 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.871655827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.2997184833 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2452011078 ps |
| CPU time | 9.88 seconds |
| Started | Sep 18 07:52:12 PM UTC 24 |
| Finished | Sep 18 07:52:23 PM UTC 24 |
| Peak memory | 244476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997184833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2997184833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1302236476 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 303401105 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 07:52:13 PM UTC 24 |
| Finished | Sep 18 07:52:15 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302236476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1302236476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.279094466 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 129623482 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 07:52:11 PM UTC 24 |
| Finished | Sep 18 07:52:14 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279094466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.279094466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.3047997405 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1034628788 ps |
| CPU time | 6.19 seconds |
| Started | Sep 18 07:52:11 PM UTC 24 |
| Finished | Sep 18 07:52:18 PM UTC 24 |
| Peak memory | 211660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047997405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3047997405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1072054258 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 103232717 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 07:52:11 PM UTC 24 |
| Finished | Sep 18 07:52:14 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072054258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1072054258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.3019659496 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 263663819 ps |
| CPU time | 2.58 seconds |
| Started | Sep 18 07:52:11 PM UTC 24 |
| Finished | Sep 18 07:52:15 PM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019659496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3019659496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.2032212428 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 8875393564 ps |
| CPU time | 34.49 seconds |
| Started | Sep 18 07:52:13 PM UTC 24 |
| Finished | Sep 18 07:52:48 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032212428 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2032212428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.2574249998 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 526280033 ps |
| CPU time | 4.33 seconds |
| Started | Sep 18 07:52:11 PM UTC 24 |
| Finished | Sep 18 07:52:17 PM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574249998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2574249998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.1965663758 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 167441078 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 07:52:11 PM UTC 24 |
| Finished | Sep 18 07:52:14 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965663758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1965663758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.3534916271 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 71658159 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 07:52:17 PM UTC 24 |
| Finished | Sep 18 07:52:19 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534916271 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3534916271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3530604653 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 301574436 ps |
| CPU time | 2.06 seconds |
| Started | Sep 18 07:52:15 PM UTC 24 |
| Finished | Sep 18 07:52:18 PM UTC 24 |
| Peak memory | 240052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530604653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3530604653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.3588233840 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 141493965 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:52:14 PM UTC 24 |
| Finished | Sep 18 07:52:16 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588233840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3588233840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.333318614 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2183759424 ps |
| CPU time | 8.58 seconds |
| Started | Sep 18 07:52:14 PM UTC 24 |
| Finished | Sep 18 07:52:24 PM UTC 24 |
| Peak memory | 211660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333318614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.333318614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3460783859 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 171899390 ps |
| CPU time | 1.56 seconds |
| Started | Sep 18 07:52:15 PM UTC 24 |
| Finished | Sep 18 07:52:18 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460783859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3460783859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.515357491 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 196746299 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 07:52:14 PM UTC 24 |
| Finished | Sep 18 07:52:16 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515357491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.515357491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.2741278620 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 8785099068 ps |
| CPU time | 30.1 seconds |
| Started | Sep 18 07:52:15 PM UTC 24 |
| Finished | Sep 18 07:52:47 PM UTC 24 |
| Peak memory | 220516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741278620 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2741278620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.2027147095 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 450668720 ps |
| CPU time | 3.45 seconds |
| Started | Sep 18 07:52:15 PM UTC 24 |
| Finished | Sep 18 07:52:20 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027147095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2027147095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.116896761 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 219697703 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 07:52:15 PM UTC 24 |
| Finished | Sep 18 07:52:18 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116896761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.116896761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.1686289551 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 58989347 ps |
| CPU time | 0.92 seconds |
| Started | Sep 18 07:52:19 PM UTC 24 |
| Finished | Sep 18 07:52:22 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686289551 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1686289551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.1919780767 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1278700134 ps |
| CPU time | 6.62 seconds |
| Started | Sep 18 07:52:18 PM UTC 24 |
| Finished | Sep 18 07:52:26 PM UTC 24 |
| Peak memory | 242780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919780767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1919780767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3104470100 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 301534961 ps |
| CPU time | 1.55 seconds |
| Started | Sep 18 07:52:18 PM UTC 24 |
| Finished | Sep 18 07:52:21 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104470100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3104470100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.2449388916 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 95855471 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 07:52:17 PM UTC 24 |
| Finished | Sep 18 07:52:19 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449388916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2449388916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.1235061818 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 991533185 ps |
| CPU time | 6.71 seconds |
| Started | Sep 18 07:52:17 PM UTC 24 |
| Finished | Sep 18 07:52:25 PM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235061818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1235061818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3012627953 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 152581085 ps |
| CPU time | 1.45 seconds |
| Started | Sep 18 07:52:18 PM UTC 24 |
| Finished | Sep 18 07:52:20 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012627953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3012627953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.3252441487 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 255284066 ps |
| CPU time | 2.43 seconds |
| Started | Sep 18 07:52:17 PM UTC 24 |
| Finished | Sep 18 07:52:20 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252441487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3252441487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.4206433935 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1019584790 ps |
| CPU time | 7.24 seconds |
| Started | Sep 18 07:52:18 PM UTC 24 |
| Finished | Sep 18 07:52:27 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206433935 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.4206433935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.331592855 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 142732437 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 07:52:17 PM UTC 24 |
| Finished | Sep 18 07:52:20 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331592855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.331592855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.3248766734 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 113857815 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 07:52:17 PM UTC 24 |
| Finished | Sep 18 07:52:19 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248766734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3248766734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.683123714 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 75188177 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 07:52:21 PM UTC 24 |
| Finished | Sep 18 07:52:24 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683123714 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.683123714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.60171612 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1270257098 ps |
| CPU time | 6.62 seconds |
| Started | Sep 18 07:52:21 PM UTC 24 |
| Finished | Sep 18 07:52:29 PM UTC 24 |
| Peak memory | 242860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60171612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.60171612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2107168879 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 303286390 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 07:52:21 PM UTC 24 |
| Finished | Sep 18 07:52:24 PM UTC 24 |
| Peak memory | 238676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107168879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2107168879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.3341513065 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 191857519 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 07:52:19 PM UTC 24 |
| Finished | Sep 18 07:52:22 PM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341513065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3341513065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.74962802 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1517002115 ps |
| CPU time | 7.51 seconds |
| Started | Sep 18 07:52:20 PM UTC 24 |
| Finished | Sep 18 07:52:28 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74962802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.74962802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2046809939 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 104867699 ps |
| CPU time | 1.47 seconds |
| Started | Sep 18 07:52:20 PM UTC 24 |
| Finished | Sep 18 07:52:22 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046809939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2046809939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.3519451584 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 124905237 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 07:52:19 PM UTC 24 |
| Finished | Sep 18 07:52:22 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519451584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3519451584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.869036598 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3223231938 ps |
| CPU time | 12.07 seconds |
| Started | Sep 18 07:52:21 PM UTC 24 |
| Finished | Sep 18 07:52:35 PM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869036598 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.869036598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.1604071873 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 379232617 ps |
| CPU time | 3.34 seconds |
| Started | Sep 18 07:52:20 PM UTC 24 |
| Finished | Sep 18 07:52:24 PM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604071873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1604071873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.3422243309 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 87023201 ps |
| CPU time | 1.32 seconds |
| Started | Sep 18 07:52:20 PM UTC 24 |
| Finished | Sep 18 07:52:22 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422243309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3422243309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.1538989934 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 83456697 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 07:52:25 PM UTC 24 |
| Finished | Sep 18 07:52:27 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538989934 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1538989934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.2030501303 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1268585052 ps |
| CPU time | 5.7 seconds |
| Started | Sep 18 07:52:24 PM UTC 24 |
| Finished | Sep 18 07:52:30 PM UTC 24 |
| Peak memory | 244472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030501303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2030501303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3012129209 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 302126543 ps |
| CPU time | 1.55 seconds |
| Started | Sep 18 07:52:24 PM UTC 24 |
| Finished | Sep 18 07:52:27 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012129209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3012129209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.216159188 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 144624337 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 07:52:21 PM UTC 24 |
| Finished | Sep 18 07:52:24 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216159188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.216159188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.1512103265 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 844327232 ps |
| CPU time | 4.76 seconds |
| Started | Sep 18 07:52:21 PM UTC 24 |
| Finished | Sep 18 07:52:27 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512103265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1512103265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3318597453 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 169529353 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 07:52:24 PM UTC 24 |
| Finished | Sep 18 07:52:26 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318597453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3318597453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.1768261737 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 110611048 ps |
| CPU time | 1.87 seconds |
| Started | Sep 18 07:52:21 PM UTC 24 |
| Finished | Sep 18 07:52:24 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768261737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1768261737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.951042105 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 9692526601 ps |
| CPU time | 34.78 seconds |
| Started | Sep 18 07:52:24 PM UTC 24 |
| Finished | Sep 18 07:53:00 PM UTC 24 |
| Peak memory | 220404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951042105 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.951042105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.109088217 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 302696794 ps |
| CPU time | 2.66 seconds |
| Started | Sep 18 07:52:22 PM UTC 24 |
| Finished | Sep 18 07:52:26 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109088217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.109088217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.185829738 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 173067685 ps |
| CPU time | 1.49 seconds |
| Started | Sep 18 07:52:22 PM UTC 24 |
| Finished | Sep 18 07:52:25 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185829738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.185829738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.1343415255 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 81409916 ps |
| CPU time | 1.04 seconds |
| Started | Sep 18 07:52:27 PM UTC 24 |
| Finished | Sep 18 07:52:29 PM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343415255 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1343415255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.2330073902 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2455791385 ps |
| CPU time | 9.11 seconds |
| Started | Sep 18 07:52:25 PM UTC 24 |
| Finished | Sep 18 07:52:36 PM UTC 24 |
| Peak memory | 243848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330073902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2330073902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3365418275 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 301740678 ps |
| CPU time | 1.66 seconds |
| Started | Sep 18 07:52:25 PM UTC 24 |
| Finished | Sep 18 07:52:28 PM UTC 24 |
| Peak memory | 239220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365418275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3365418275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.3479192426 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 75997849 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 07:52:25 PM UTC 24 |
| Finished | Sep 18 07:52:28 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479192426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3479192426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.1021591590 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 902910570 ps |
| CPU time | 4.48 seconds |
| Started | Sep 18 07:52:25 PM UTC 24 |
| Finished | Sep 18 07:52:31 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021591590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1021591590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2538929314 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 109248068 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 07:52:25 PM UTC 24 |
| Finished | Sep 18 07:52:28 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538929314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2538929314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.215094707 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 196822641 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 07:52:25 PM UTC 24 |
| Finished | Sep 18 07:52:28 PM UTC 24 |
| Peak memory | 209900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215094707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.215094707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.3844760276 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 10075568798 ps |
| CPU time | 37.06 seconds |
| Started | Sep 18 07:52:26 PM UTC 24 |
| Finished | Sep 18 07:53:04 PM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844760276 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3844760276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.2870162613 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 144704215 ps |
| CPU time | 2.92 seconds |
| Started | Sep 18 07:52:25 PM UTC 24 |
| Finished | Sep 18 07:52:30 PM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870162613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2870162613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.1028012222 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 68274386 ps |
| CPU time | 0.96 seconds |
| Started | Sep 18 07:52:25 PM UTC 24 |
| Finished | Sep 18 07:52:28 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028012222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1028012222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.1244919779 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 86734482 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 07:52:29 PM UTC 24 |
| Finished | Sep 18 07:52:31 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244919779 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1244919779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.2289902815 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2253470203 ps |
| CPU time | 9.15 seconds |
| Started | Sep 18 07:52:28 PM UTC 24 |
| Finished | Sep 18 07:52:38 PM UTC 24 |
| Peak memory | 244480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289902815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2289902815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.379656686 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 301917272 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 07:52:28 PM UTC 24 |
| Finished | Sep 18 07:52:31 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379656686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.379656686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.3177209882 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 185076756 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 07:52:27 PM UTC 24 |
| Finished | Sep 18 07:52:29 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177209882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3177209882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.2636044845 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 897744458 ps |
| CPU time | 5.66 seconds |
| Started | Sep 18 07:52:27 PM UTC 24 |
| Finished | Sep 18 07:52:34 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636044845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2636044845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1628861772 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 153031407 ps |
| CPU time | 1.82 seconds |
| Started | Sep 18 07:52:28 PM UTC 24 |
| Finished | Sep 18 07:52:31 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628861772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1628861772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.3909586771 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 115038172 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 07:52:27 PM UTC 24 |
| Finished | Sep 18 07:52:29 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909586771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3909586771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.2497677584 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 6552917578 ps |
| CPU time | 26.6 seconds |
| Started | Sep 18 07:52:28 PM UTC 24 |
| Finished | Sep 18 07:52:56 PM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497677584 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2497677584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.3150857993 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 153453566 ps |
| CPU time | 2.68 seconds |
| Started | Sep 18 07:52:28 PM UTC 24 |
| Finished | Sep 18 07:52:32 PM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150857993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3150857993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.3029731325 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 262737506 ps |
| CPU time | 1.8 seconds |
| Started | Sep 18 07:52:27 PM UTC 24 |
| Finished | Sep 18 07:52:30 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029731325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3029731325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.3983329737 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 100945774 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 07:52:31 PM UTC 24 |
| Finished | Sep 18 07:52:33 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983329737 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3983329737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.3951882202 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1274292212 ps |
| CPU time | 6.53 seconds |
| Started | Sep 18 07:52:31 PM UTC 24 |
| Finished | Sep 18 07:52:38 PM UTC 24 |
| Peak memory | 243428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951882202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3951882202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3681478954 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 301909357 ps |
| CPU time | 1.52 seconds |
| Started | Sep 18 07:52:31 PM UTC 24 |
| Finished | Sep 18 07:52:33 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681478954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3681478954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.1184640903 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 114108768 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 07:52:29 PM UTC 24 |
| Finished | Sep 18 07:52:32 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184640903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1184640903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.952797904 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1597592797 ps |
| CPU time | 6.37 seconds |
| Started | Sep 18 07:52:29 PM UTC 24 |
| Finished | Sep 18 07:52:37 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952797904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.952797904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2890146711 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 110730662 ps |
| CPU time | 1.55 seconds |
| Started | Sep 18 07:52:31 PM UTC 24 |
| Finished | Sep 18 07:52:33 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890146711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2890146711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.3414912032 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 255208711 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 07:52:29 PM UTC 24 |
| Finished | Sep 18 07:52:32 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414912032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3414912032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.2349925691 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 9476193095 ps |
| CPU time | 33.33 seconds |
| Started | Sep 18 07:52:31 PM UTC 24 |
| Finished | Sep 18 07:53:06 PM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349925691 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2349925691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.274812991 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 300750638 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 07:52:30 PM UTC 24 |
| Finished | Sep 18 07:52:33 PM UTC 24 |
| Peak memory | 220036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274812991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.274812991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.3692056410 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 151411393 ps |
| CPU time | 1.67 seconds |
| Started | Sep 18 07:52:30 PM UTC 24 |
| Finished | Sep 18 07:52:32 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692056410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3692056410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.3435455953 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 66911164 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 07:52:34 PM UTC 24 |
| Finished | Sep 18 07:52:36 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435455953 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3435455953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.211367001 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1971759294 ps |
| CPU time | 8.55 seconds |
| Started | Sep 18 07:52:33 PM UTC 24 |
| Finished | Sep 18 07:52:42 PM UTC 24 |
| Peak memory | 243728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211367001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.211367001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2471649722 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 301083849 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 07:52:33 PM UTC 24 |
| Finished | Sep 18 07:52:35 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471649722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2471649722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.2314306709 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 160529752 ps |
| CPU time | 1.32 seconds |
| Started | Sep 18 07:52:32 PM UTC 24 |
| Finished | Sep 18 07:52:35 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314306709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2314306709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.1344789415 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2158805245 ps |
| CPU time | 8.5 seconds |
| Started | Sep 18 07:52:32 PM UTC 24 |
| Finished | Sep 18 07:52:42 PM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344789415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1344789415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.210090473 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 187067230 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 07:52:33 PM UTC 24 |
| Finished | Sep 18 07:52:35 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210090473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.210090473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.3827125436 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 191202763 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 07:52:32 PM UTC 24 |
| Finished | Sep 18 07:52:35 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827125436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3827125436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.2677023390 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4999034513 ps |
| CPU time | 17.22 seconds |
| Started | Sep 18 07:52:33 PM UTC 24 |
| Finished | Sep 18 07:52:51 PM UTC 24 |
| Peak memory | 220352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677023390 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2677023390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.3092883142 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 491112083 ps |
| CPU time | 2.78 seconds |
| Started | Sep 18 07:52:33 PM UTC 24 |
| Finished | Sep 18 07:52:36 PM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092883142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3092883142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.790694234 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 155571109 ps |
| CPU time | 2 seconds |
| Started | Sep 18 07:52:33 PM UTC 24 |
| Finished | Sep 18 07:52:35 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790694234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.790694234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.411582410 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1273967055 ps |
| CPU time | 6.61 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:51:56 PM UTC 24 |
| Peak memory | 243432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411582410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.411582410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3679763889 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 301275889 ps |
| CPU time | 1.52 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:51:51 PM UTC 24 |
| Peak memory | 239056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679763889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3679763889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.3552288765 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 197197337 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:47 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552288765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3552288765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.3228308231 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 964700868 ps |
| CPU time | 4.92 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:50 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228308231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3228308231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.1896345867 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8385469844 ps |
| CPU time | 13.71 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:52:04 PM UTC 24 |
| Peak memory | 244180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896345867 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1896345867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2127058086 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 142147717 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 07:51:47 PM UTC 24 |
| Finished | Sep 18 07:51:50 PM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127058086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2127058086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.396754424 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 186107196 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 07:51:44 PM UTC 24 |
| Finished | Sep 18 07:51:47 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396754424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.396754424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.4117487291 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 10460703882 ps |
| CPU time | 36.07 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:52:26 PM UTC 24 |
| Peak memory | 220464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117487291 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.4117487291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.2438814297 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 298734446 ps |
| CPU time | 2.58 seconds |
| Started | Sep 18 07:51:47 PM UTC 24 |
| Finished | Sep 18 07:51:51 PM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438814297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2438814297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.3228281494 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 61567477 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 07:52:37 PM UTC 24 |
| Finished | Sep 18 07:52:39 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228281494 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3228281494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/20.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.3398499236 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1268829896 ps |
| CPU time | 6.28 seconds |
| Started | Sep 18 07:52:35 PM UTC 24 |
| Finished | Sep 18 07:52:43 PM UTC 24 |
| Peak memory | 243712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398499236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3398499236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.889228192 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 302455543 ps |
| CPU time | 1.88 seconds |
| Started | Sep 18 07:52:36 PM UTC 24 |
| Finished | Sep 18 07:52:39 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889228192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.889228192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.1419039197 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 108814455 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 07:52:34 PM UTC 24 |
| Finished | Sep 18 07:52:36 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419039197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1419039197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.828962031 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 851534037 ps |
| CPU time | 5.4 seconds |
| Started | Sep 18 07:52:34 PM UTC 24 |
| Finished | Sep 18 07:52:41 PM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828962031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.828962031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/20.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1445903110 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 179571136 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 07:52:35 PM UTC 24 |
| Finished | Sep 18 07:52:38 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445903110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1445903110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.1275184853 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 254858348 ps |
| CPU time | 1.99 seconds |
| Started | Sep 18 07:52:34 PM UTC 24 |
| Finished | Sep 18 07:52:37 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275184853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1275184853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/20.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.3262658769 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 850123305 ps |
| CPU time | 4.48 seconds |
| Started | Sep 18 07:52:37 PM UTC 24 |
| Finished | Sep 18 07:52:42 PM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262658769 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3262658769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/20.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.2516862283 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 139118856 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 07:52:34 PM UTC 24 |
| Finished | Sep 18 07:52:37 PM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516862283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2516862283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.1670715109 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 109941042 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:52:34 PM UTC 24 |
| Finished | Sep 18 07:52:37 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670715109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1670715109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.1718840787 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 70993570 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 07:52:39 PM UTC 24 |
| Finished | Sep 18 07:52:41 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718840787 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1718840787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/21.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.543641170 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1274074250 ps |
| CPU time | 6.36 seconds |
| Started | Sep 18 07:52:38 PM UTC 24 |
| Finished | Sep 18 07:52:46 PM UTC 24 |
| Peak memory | 243648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543641170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.543641170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2832598281 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 300622355 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 07:52:38 PM UTC 24 |
| Finished | Sep 18 07:52:41 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832598281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2832598281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.1226512911 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 87998803 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 07:52:37 PM UTC 24 |
| Finished | Sep 18 07:52:39 PM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226512911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1226512911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.2690819979 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 893421187 ps |
| CPU time | 6.58 seconds |
| Started | Sep 18 07:52:37 PM UTC 24 |
| Finished | Sep 18 07:52:45 PM UTC 24 |
| Peak memory | 211660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690819979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2690819979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/21.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2611021769 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 152612090 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 07:52:38 PM UTC 24 |
| Finished | Sep 18 07:52:41 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611021769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2611021769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.2220203130 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 112197564 ps |
| CPU time | 1.62 seconds |
| Started | Sep 18 07:52:37 PM UTC 24 |
| Finished | Sep 18 07:52:40 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220203130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2220203130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/21.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.6466348 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 779659767 ps |
| CPU time | 4.07 seconds |
| Started | Sep 18 07:52:38 PM UTC 24 |
| Finished | Sep 18 07:52:44 PM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6466348 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.6466348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/21.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.2253139570 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 311290068 ps |
| CPU time | 2.39 seconds |
| Started | Sep 18 07:52:38 PM UTC 24 |
| Finished | Sep 18 07:52:42 PM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253139570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2253139570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.3345224499 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 84575786 ps |
| CPU time | 0.98 seconds |
| Started | Sep 18 07:52:37 PM UTC 24 |
| Finished | Sep 18 07:52:39 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345224499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3345224499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.4234611219 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 70993998 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 07:52:41 PM UTC 24 |
| Finished | Sep 18 07:52:43 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234611219 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.4234611219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/22.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.2198996327 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1261203708 ps |
| CPU time | 7.59 seconds |
| Started | Sep 18 07:52:40 PM UTC 24 |
| Finished | Sep 18 07:52:49 PM UTC 24 |
| Peak memory | 243484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198996327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2198996327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.99437587 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 301191651 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:52:41 PM UTC 24 |
| Finished | Sep 18 07:52:44 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99437587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.99437587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.1384382587 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 154274539 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 07:52:40 PM UTC 24 |
| Finished | Sep 18 07:52:42 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384382587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1384382587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.4136330627 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1398574034 ps |
| CPU time | 7.23 seconds |
| Started | Sep 18 07:52:40 PM UTC 24 |
| Finished | Sep 18 07:52:48 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136330627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.4136330627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/22.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1057723042 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 104113393 ps |
| CPU time | 1.45 seconds |
| Started | Sep 18 07:52:40 PM UTC 24 |
| Finished | Sep 18 07:52:42 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057723042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1057723042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.360967029 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 123280183 ps |
| CPU time | 1.48 seconds |
| Started | Sep 18 07:52:40 PM UTC 24 |
| Finished | Sep 18 07:52:42 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360967029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.360967029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/22.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.2020367035 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 9255902537 ps |
| CPU time | 35.12 seconds |
| Started | Sep 18 07:52:41 PM UTC 24 |
| Finished | Sep 18 07:53:18 PM UTC 24 |
| Peak memory | 220596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020367035 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2020367035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/22.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.692658000 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 149441772 ps |
| CPU time | 2.28 seconds |
| Started | Sep 18 07:52:40 PM UTC 24 |
| Finished | Sep 18 07:52:43 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692658000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.692658000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.2677174303 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 216494987 ps |
| CPU time | 1.82 seconds |
| Started | Sep 18 07:52:40 PM UTC 24 |
| Finished | Sep 18 07:52:43 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677174303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2677174303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.156851091 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 83288755 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 07:52:44 PM UTC 24 |
| Finished | Sep 18 07:52:46 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156851091 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.156851091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/23.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.2482901396 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2450251632 ps |
| CPU time | 10.77 seconds |
| Started | Sep 18 07:52:44 PM UTC 24 |
| Finished | Sep 18 07:52:56 PM UTC 24 |
| Peak memory | 243788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482901396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2482901396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3638464381 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 303444822 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 07:52:44 PM UTC 24 |
| Finished | Sep 18 07:52:46 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638464381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3638464381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.2658424553 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 239947810 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 07:52:42 PM UTC 24 |
| Finished | Sep 18 07:52:45 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658424553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2658424553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.753115223 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1703457795 ps |
| CPU time | 6.05 seconds |
| Started | Sep 18 07:52:42 PM UTC 24 |
| Finished | Sep 18 07:52:50 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753115223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.753115223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/23.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1040266761 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 96783740 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:52:44 PM UTC 24 |
| Finished | Sep 18 07:52:46 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040266761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1040266761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.3166536665 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 254324476 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 07:52:42 PM UTC 24 |
| Finished | Sep 18 07:52:45 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166536665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3166536665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/23.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.2494687653 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3439059466 ps |
| CPU time | 14.54 seconds |
| Started | Sep 18 07:52:44 PM UTC 24 |
| Finished | Sep 18 07:53:00 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494687653 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2494687653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/23.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.135306532 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 415326576 ps |
| CPU time | 3.23 seconds |
| Started | Sep 18 07:52:43 PM UTC 24 |
| Finished | Sep 18 07:52:47 PM UTC 24 |
| Peak memory | 220216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135306532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.135306532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.3663396762 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 128033443 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 07:52:42 PM UTC 24 |
| Finished | Sep 18 07:52:45 PM UTC 24 |
| Peak memory | 210044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663396762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3663396762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.989155881 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 83692586 ps |
| CPU time | 1.39 seconds |
| Started | Sep 18 07:52:47 PM UTC 24 |
| Finished | Sep 18 07:52:50 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989155881 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.989155881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/24.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.2938723372 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2472599306 ps |
| CPU time | 10.92 seconds |
| Started | Sep 18 07:52:46 PM UTC 24 |
| Finished | Sep 18 07:52:58 PM UTC 24 |
| Peak memory | 243800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938723372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2938723372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.374670853 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 303404278 ps |
| CPU time | 1.66 seconds |
| Started | Sep 18 07:52:46 PM UTC 24 |
| Finished | Sep 18 07:52:48 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374670853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.374670853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.3846044774 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 121485380 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 07:52:44 PM UTC 24 |
| Finished | Sep 18 07:52:46 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846044774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3846044774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.241978727 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1463914762 ps |
| CPU time | 5.51 seconds |
| Started | Sep 18 07:52:44 PM UTC 24 |
| Finished | Sep 18 07:52:51 PM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241978727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.241978727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/24.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1544246915 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 154577644 ps |
| CPU time | 1.8 seconds |
| Started | Sep 18 07:52:45 PM UTC 24 |
| Finished | Sep 18 07:52:48 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544246915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1544246915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.4060939964 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 231360193 ps |
| CPU time | 1.89 seconds |
| Started | Sep 18 07:52:44 PM UTC 24 |
| Finished | Sep 18 07:52:47 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060939964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4060939964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/24.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.4280329367 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 877197551 ps |
| CPU time | 4.87 seconds |
| Started | Sep 18 07:52:46 PM UTC 24 |
| Finished | Sep 18 07:52:52 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280329367 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4280329367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/24.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.2361152599 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 111077971 ps |
| CPU time | 1.67 seconds |
| Started | Sep 18 07:52:45 PM UTC 24 |
| Finished | Sep 18 07:52:48 PM UTC 24 |
| Peak memory | 209892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361152599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2361152599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.3116834293 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 89604951 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 07:52:44 PM UTC 24 |
| Finished | Sep 18 07:52:46 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116834293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3116834293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.915280388 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 70781137 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 07:52:50 PM UTC 24 |
| Finished | Sep 18 07:52:52 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915280388 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.915280388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/25.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.910980741 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1279045311 ps |
| CPU time | 6.19 seconds |
| Started | Sep 18 07:52:48 PM UTC 24 |
| Finished | Sep 18 07:52:56 PM UTC 24 |
| Peak memory | 244576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910980741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.910980741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2834569083 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 301815631 ps |
| CPU time | 2.15 seconds |
| Started | Sep 18 07:52:48 PM UTC 24 |
| Finished | Sep 18 07:52:51 PM UTC 24 |
| Peak memory | 240048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834569083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2834569083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.3046406769 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 162817745 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 07:52:47 PM UTC 24 |
| Finished | Sep 18 07:52:50 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046406769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3046406769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.1753296350 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1420587353 ps |
| CPU time | 8.77 seconds |
| Started | Sep 18 07:52:47 PM UTC 24 |
| Finished | Sep 18 07:52:57 PM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753296350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1753296350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/25.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1306754256 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 100372647 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:52:47 PM UTC 24 |
| Finished | Sep 18 07:52:50 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306754256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1306754256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.2416743176 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 203832421 ps |
| CPU time | 2.07 seconds |
| Started | Sep 18 07:52:47 PM UTC 24 |
| Finished | Sep 18 07:52:50 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416743176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2416743176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/25.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.3950424616 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 4403231011 ps |
| CPU time | 17.02 seconds |
| Started | Sep 18 07:52:48 PM UTC 24 |
| Finished | Sep 18 07:53:07 PM UTC 24 |
| Peak memory | 220400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950424616 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3950424616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/25.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.3079505229 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 437743352 ps |
| CPU time | 3.81 seconds |
| Started | Sep 18 07:52:47 PM UTC 24 |
| Finished | Sep 18 07:52:52 PM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079505229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3079505229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.3769949376 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 188445257 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 07:52:47 PM UTC 24 |
| Finished | Sep 18 07:52:50 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769949376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3769949376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.2150529075 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 67573706 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 07:52:51 PM UTC 24 |
| Finished | Sep 18 07:52:55 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150529075 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2150529075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/26.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.1707252845 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1270698787 ps |
| CPU time | 8.49 seconds |
| Started | Sep 18 07:52:51 PM UTC 24 |
| Finished | Sep 18 07:53:02 PM UTC 24 |
| Peak memory | 244080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707252845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1707252845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2095441064 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 301405564 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 07:52:51 PM UTC 24 |
| Finished | Sep 18 07:52:55 PM UTC 24 |
| Peak memory | 239612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095441064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2095441064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.3909619261 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 122362051 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 07:52:50 PM UTC 24 |
| Finished | Sep 18 07:52:52 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909619261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3909619261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.1953695447 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2181590027 ps |
| CPU time | 8.9 seconds |
| Started | Sep 18 07:52:50 PM UTC 24 |
| Finished | Sep 18 07:53:00 PM UTC 24 |
| Peak memory | 211664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953695447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1953695447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/26.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1604375441 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 95609092 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 07:52:51 PM UTC 24 |
| Finished | Sep 18 07:52:54 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604375441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1604375441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.3817957417 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 117856789 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 07:52:50 PM UTC 24 |
| Finished | Sep 18 07:52:52 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817957417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3817957417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/26.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.922847170 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 5096699288 ps |
| CPU time | 18.83 seconds |
| Started | Sep 18 07:52:51 PM UTC 24 |
| Finished | Sep 18 07:53:12 PM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922847170 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.922847170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/26.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.2725540845 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 501526394 ps |
| CPU time | 2.8 seconds |
| Started | Sep 18 07:52:50 PM UTC 24 |
| Finished | Sep 18 07:52:54 PM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725540845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2725540845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.4066586578 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 174147813 ps |
| CPU time | 1.65 seconds |
| Started | Sep 18 07:52:50 PM UTC 24 |
| Finished | Sep 18 07:52:53 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066586578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.4066586578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.16929462 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 76915932 ps |
| CPU time | 1.05 seconds |
| Started | Sep 18 07:52:54 PM UTC 24 |
| Finished | Sep 18 07:52:57 PM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16929462 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.16929462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/27.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.180515150 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1959161895 ps |
| CPU time | 7.82 seconds |
| Started | Sep 18 07:52:53 PM UTC 24 |
| Finished | Sep 18 07:53:03 PM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180515150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.180515150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.479799718 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 301942240 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 07:52:53 PM UTC 24 |
| Finished | Sep 18 07:52:56 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479799718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.479799718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.248071306 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 212947490 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 07:52:53 PM UTC 24 |
| Finished | Sep 18 07:52:56 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248071306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.248071306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.782551928 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1397879205 ps |
| CPU time | 5.88 seconds |
| Started | Sep 18 07:52:53 PM UTC 24 |
| Finished | Sep 18 07:53:00 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782551928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.782551928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/27.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1674183715 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 180576494 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 07:52:53 PM UTC 24 |
| Finished | Sep 18 07:52:56 PM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674183715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1674183715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.1100580016 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 111904704 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 07:52:51 PM UTC 24 |
| Finished | Sep 18 07:52:55 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100580016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1100580016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/27.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.1591179411 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 9951860220 ps |
| CPU time | 40.19 seconds |
| Started | Sep 18 07:52:54 PM UTC 24 |
| Finished | Sep 18 07:53:36 PM UTC 24 |
| Peak memory | 220352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591179411 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1591179411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/27.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.4064836266 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 127483501 ps |
| CPU time | 2.45 seconds |
| Started | Sep 18 07:52:53 PM UTC 24 |
| Finished | Sep 18 07:52:57 PM UTC 24 |
| Peak memory | 220248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064836266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4064836266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.897127886 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 145827685 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 07:52:53 PM UTC 24 |
| Finished | Sep 18 07:52:56 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897127886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.897127886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.1945194294 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 76363008 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 07:52:57 PM UTC 24 |
| Finished | Sep 18 07:52:59 PM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945194294 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1945194294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/28.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.1473476796 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2266924903 ps |
| CPU time | 11.77 seconds |
| Started | Sep 18 07:52:57 PM UTC 24 |
| Finished | Sep 18 07:53:10 PM UTC 24 |
| Peak memory | 244544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473476796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1473476796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3927624310 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 302357921 ps |
| CPU time | 1.69 seconds |
| Started | Sep 18 07:52:57 PM UTC 24 |
| Finished | Sep 18 07:53:00 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927624310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3927624310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.1385444038 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 79164005 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 07:52:55 PM UTC 24 |
| Finished | Sep 18 07:52:57 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385444038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1385444038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.847899386 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2091589724 ps |
| CPU time | 8.54 seconds |
| Started | Sep 18 07:52:55 PM UTC 24 |
| Finished | Sep 18 07:53:05 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847899386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.847899386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/28.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2036944217 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 111666068 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 07:52:57 PM UTC 24 |
| Finished | Sep 18 07:53:00 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036944217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2036944217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.2342369567 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 117316957 ps |
| CPU time | 1.72 seconds |
| Started | Sep 18 07:52:54 PM UTC 24 |
| Finished | Sep 18 07:52:58 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342369567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2342369567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/28.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.2486174131 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 14900484463 ps |
| CPU time | 49.47 seconds |
| Started | Sep 18 07:52:57 PM UTC 24 |
| Finished | Sep 18 07:53:48 PM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486174131 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2486174131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/28.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.3509831861 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 118580972 ps |
| CPU time | 1.95 seconds |
| Started | Sep 18 07:52:57 PM UTC 24 |
| Finished | Sep 18 07:53:00 PM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509831861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3509831861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.958548262 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 82825700 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 07:52:55 PM UTC 24 |
| Finished | Sep 18 07:52:58 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958548262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.958548262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.88302243 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 76956307 ps |
| CPU time | 1.15 seconds |
| Started | Sep 18 07:53:00 PM UTC 24 |
| Finished | Sep 18 07:53:02 PM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88302243 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.88302243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/29.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.556511186 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1965799471 ps |
| CPU time | 7.19 seconds |
| Started | Sep 18 07:52:59 PM UTC 24 |
| Finished | Sep 18 07:53:07 PM UTC 24 |
| Peak memory | 244456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556511186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.556511186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1000253809 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 300782213 ps |
| CPU time | 1.94 seconds |
| Started | Sep 18 07:52:59 PM UTC 24 |
| Finished | Sep 18 07:53:02 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000253809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1000253809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.2348937021 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 166905741 ps |
| CPU time | 1.45 seconds |
| Started | Sep 18 07:52:57 PM UTC 24 |
| Finished | Sep 18 07:53:00 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348937021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2348937021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.16766384 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1773762917 ps |
| CPU time | 9.4 seconds |
| Started | Sep 18 07:52:59 PM UTC 24 |
| Finished | Sep 18 07:53:09 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16766384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.16766384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/29.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2243461720 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 100832434 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 07:52:59 PM UTC 24 |
| Finished | Sep 18 07:53:01 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243461720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2243461720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.3278188612 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 130331259 ps |
| CPU time | 1.53 seconds |
| Started | Sep 18 07:52:57 PM UTC 24 |
| Finished | Sep 18 07:53:00 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278188612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3278188612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/29.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.2334833646 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 9124138220 ps |
| CPU time | 35.96 seconds |
| Started | Sep 18 07:52:59 PM UTC 24 |
| Finished | Sep 18 07:53:36 PM UTC 24 |
| Peak memory | 220340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334833646 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2334833646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/29.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.2003407282 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 367192048 ps |
| CPU time | 3.35 seconds |
| Started | Sep 18 07:52:59 PM UTC 24 |
| Finished | Sep 18 07:53:03 PM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003407282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2003407282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.555600334 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 235077353 ps |
| CPU time | 2.19 seconds |
| Started | Sep 18 07:52:59 PM UTC 24 |
| Finished | Sep 18 07:53:02 PM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555600334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.555600334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.3404020386 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 89947141 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 07:51:50 PM UTC 24 |
| Finished | Sep 18 07:51:53 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404020386 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3404020386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.1153164221 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1270579069 ps |
| CPU time | 6.6 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:51:57 PM UTC 24 |
| Peak memory | 244016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153164221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1153164221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.641506751 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 301909894 ps |
| CPU time | 1.85 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:51:52 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641506751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.641506751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.2663355221 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 235364477 ps |
| CPU time | 1.47 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:51:51 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663355221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2663355221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.306452262 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1594705033 ps |
| CPU time | 6.72 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:51:57 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306452262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.306452262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.3240406005 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 16518944949 ps |
| CPU time | 28.27 seconds |
| Started | Sep 18 07:51:50 PM UTC 24 |
| Finished | Sep 18 07:52:20 PM UTC 24 |
| Peak memory | 243800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240406005 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3240406005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3441333464 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 150954628 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:51:52 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441333464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3441333464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.3314290572 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 117037158 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:51:51 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314290572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3314290572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.2552562046 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3802611755 ps |
| CPU time | 14.4 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:52:05 PM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552562046 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2552562046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.2495923207 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 364583276 ps |
| CPU time | 3.11 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:51:53 PM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495923207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2495923207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.2357594839 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 85989027 ps |
| CPU time | 1.32 seconds |
| Started | Sep 18 07:51:49 PM UTC 24 |
| Finished | Sep 18 07:51:51 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357594839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2357594839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.493035360 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 82319338 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 07:53:02 PM UTC 24 |
| Finished | Sep 18 07:53:04 PM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493035360 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.493035360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/30.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.2456391851 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1264705189 ps |
| CPU time | 8.86 seconds |
| Started | Sep 18 07:53:01 PM UTC 24 |
| Finished | Sep 18 07:53:12 PM UTC 24 |
| Peak memory | 243908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456391851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2456391851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1854871713 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 301198854 ps |
| CPU time | 2.27 seconds |
| Started | Sep 18 07:53:02 PM UTC 24 |
| Finished | Sep 18 07:53:05 PM UTC 24 |
| Peak memory | 239972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854871713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1854871713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.2668532088 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 201994791 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 07:53:01 PM UTC 24 |
| Finished | Sep 18 07:53:04 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668532088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2668532088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.898889817 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1503165301 ps |
| CPU time | 6.5 seconds |
| Started | Sep 18 07:53:01 PM UTC 24 |
| Finished | Sep 18 07:53:09 PM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898889817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.898889817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/30.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3216241848 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 171859341 ps |
| CPU time | 1.78 seconds |
| Started | Sep 18 07:53:01 PM UTC 24 |
| Finished | Sep 18 07:53:04 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216241848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3216241848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.803980708 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 248416145 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 07:53:00 PM UTC 24 |
| Finished | Sep 18 07:53:03 PM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803980708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.803980708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/30.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.3364972387 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 9548356167 ps |
| CPU time | 42.13 seconds |
| Started | Sep 18 07:53:02 PM UTC 24 |
| Finished | Sep 18 07:53:45 PM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364972387 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3364972387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/30.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.254097776 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 113327210 ps |
| CPU time | 2.09 seconds |
| Started | Sep 18 07:53:01 PM UTC 24 |
| Finished | Sep 18 07:53:05 PM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254097776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.254097776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.3594891001 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 206280134 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 07:53:01 PM UTC 24 |
| Finished | Sep 18 07:53:04 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594891001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3594891001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.2852783113 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 71369724 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 07:53:05 PM UTC 24 |
| Finished | Sep 18 07:53:08 PM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852783113 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2852783113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/31.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.2590477246 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2441217751 ps |
| CPU time | 9.63 seconds |
| Started | Sep 18 07:53:04 PM UTC 24 |
| Finished | Sep 18 07:53:15 PM UTC 24 |
| Peak memory | 244472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590477246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2590477246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1697212011 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 302248169 ps |
| CPU time | 1.15 seconds |
| Started | Sep 18 07:53:04 PM UTC 24 |
| Finished | Sep 18 07:53:06 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697212011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1697212011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.2716415921 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 121358358 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 07:53:03 PM UTC 24 |
| Finished | Sep 18 07:53:05 PM UTC 24 |
| Peak memory | 210036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716415921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2716415921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.3170573398 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1276827903 ps |
| CPU time | 7.83 seconds |
| Started | Sep 18 07:53:03 PM UTC 24 |
| Finished | Sep 18 07:53:12 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170573398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3170573398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/31.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.740109200 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 148067804 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:53:04 PM UTC 24 |
| Finished | Sep 18 07:53:07 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740109200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.740109200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.2229391063 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 119788751 ps |
| CPU time | 1.82 seconds |
| Started | Sep 18 07:53:03 PM UTC 24 |
| Finished | Sep 18 07:53:06 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229391063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2229391063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/31.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.4263397002 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 5637959872 ps |
| CPU time | 17.56 seconds |
| Started | Sep 18 07:53:05 PM UTC 24 |
| Finished | Sep 18 07:53:24 PM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263397002 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.4263397002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/31.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.3809951540 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 120649149 ps |
| CPU time | 1.74 seconds |
| Started | Sep 18 07:53:04 PM UTC 24 |
| Finished | Sep 18 07:53:07 PM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809951540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3809951540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.3447214916 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 102662902 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 07:53:03 PM UTC 24 |
| Finished | Sep 18 07:53:06 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447214916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3447214916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.3392350742 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 91117987 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 07:53:07 PM UTC 24 |
| Finished | Sep 18 07:53:09 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392350742 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3392350742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/32.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.1914967809 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1946504740 ps |
| CPU time | 8.64 seconds |
| Started | Sep 18 07:53:07 PM UTC 24 |
| Finished | Sep 18 07:53:17 PM UTC 24 |
| Peak memory | 243496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914967809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1914967809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4261259309 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 301484152 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:53:07 PM UTC 24 |
| Finished | Sep 18 07:53:10 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261259309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4261259309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.1565942732 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 131870869 ps |
| CPU time | 1.05 seconds |
| Started | Sep 18 07:53:06 PM UTC 24 |
| Finished | Sep 18 07:53:08 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565942732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1565942732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.2984617950 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1044166853 ps |
| CPU time | 4.98 seconds |
| Started | Sep 18 07:53:06 PM UTC 24 |
| Finished | Sep 18 07:53:12 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984617950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2984617950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/32.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2869950308 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 153980788 ps |
| CPU time | 1.75 seconds |
| Started | Sep 18 07:53:07 PM UTC 24 |
| Finished | Sep 18 07:53:10 PM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869950308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2869950308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.3456860908 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 197648848 ps |
| CPU time | 1.52 seconds |
| Started | Sep 18 07:53:05 PM UTC 24 |
| Finished | Sep 18 07:53:08 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456860908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3456860908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/32.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.3759139109 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 6292632450 ps |
| CPU time | 23.52 seconds |
| Started | Sep 18 07:53:07 PM UTC 24 |
| Finished | Sep 18 07:53:32 PM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759139109 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3759139109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/32.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.3832980883 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 131906798 ps |
| CPU time | 2.02 seconds |
| Started | Sep 18 07:53:07 PM UTC 24 |
| Finished | Sep 18 07:53:10 PM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832980883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3832980883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.3353357828 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 232357634 ps |
| CPU time | 2.19 seconds |
| Started | Sep 18 07:53:06 PM UTC 24 |
| Finished | Sep 18 07:53:09 PM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353357828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3353357828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.2953672508 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 80192512 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 07:53:11 PM UTC 24 |
| Finished | Sep 18 07:53:13 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953672508 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2953672508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/33.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.1494615031 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1279740490 ps |
| CPU time | 6.13 seconds |
| Started | Sep 18 07:53:10 PM UTC 24 |
| Finished | Sep 18 07:53:17 PM UTC 24 |
| Peak memory | 244200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494615031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1494615031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.692587554 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 302454661 ps |
| CPU time | 1.75 seconds |
| Started | Sep 18 07:53:10 PM UTC 24 |
| Finished | Sep 18 07:53:13 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692587554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.692587554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.3030826821 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 160572104 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 07:53:08 PM UTC 24 |
| Finished | Sep 18 07:53:11 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030826821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3030826821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.3555588676 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 825913204 ps |
| CPU time | 6.59 seconds |
| Started | Sep 18 07:53:08 PM UTC 24 |
| Finished | Sep 18 07:53:16 PM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555588676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3555588676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/33.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.869025136 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 184115341 ps |
| CPU time | 2.04 seconds |
| Started | Sep 18 07:53:08 PM UTC 24 |
| Finished | Sep 18 07:53:12 PM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869025136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.869025136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.410611751 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 226193227 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 07:53:08 PM UTC 24 |
| Finished | Sep 18 07:53:11 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410611751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.410611751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/33.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.4140800913 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4671280608 ps |
| CPU time | 20.5 seconds |
| Started | Sep 18 07:53:10 PM UTC 24 |
| Finished | Sep 18 07:53:32 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140800913 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.4140800913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/33.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.294491225 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 153485257 ps |
| CPU time | 2.61 seconds |
| Started | Sep 18 07:53:08 PM UTC 24 |
| Finished | Sep 18 07:53:12 PM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294491225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.294491225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.382113637 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 155106041 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 07:53:08 PM UTC 24 |
| Finished | Sep 18 07:53:11 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382113637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.382113637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.2018460692 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 71195357 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 07:53:12 PM UTC 24 |
| Finished | Sep 18 07:53:15 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018460692 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2018460692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/34.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.490209590 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1261924650 ps |
| CPU time | 8.8 seconds |
| Started | Sep 18 07:53:12 PM UTC 24 |
| Finished | Sep 18 07:53:23 PM UTC 24 |
| Peak memory | 244476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490209590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.490209590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.294381155 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 302863962 ps |
| CPU time | 1.87 seconds |
| Started | Sep 18 07:53:12 PM UTC 24 |
| Finished | Sep 18 07:53:16 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294381155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.294381155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.4188470485 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 171232798 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 07:53:11 PM UTC 24 |
| Finished | Sep 18 07:53:14 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188470485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.4188470485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.345107291 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 855785120 ps |
| CPU time | 5.53 seconds |
| Started | Sep 18 07:53:11 PM UTC 24 |
| Finished | Sep 18 07:53:18 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345107291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.345107291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/34.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3952625863 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 106573437 ps |
| CPU time | 1.62 seconds |
| Started | Sep 18 07:53:12 PM UTC 24 |
| Finished | Sep 18 07:53:15 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952625863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3952625863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.1492893381 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 262120460 ps |
| CPU time | 2.46 seconds |
| Started | Sep 18 07:53:11 PM UTC 24 |
| Finished | Sep 18 07:53:15 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492893381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1492893381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/34.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.3929494459 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1833544723 ps |
| CPU time | 10.08 seconds |
| Started | Sep 18 07:53:12 PM UTC 24 |
| Finished | Sep 18 07:53:24 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929494459 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3929494459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/34.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.3869069229 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 122859044 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:53:11 PM UTC 24 |
| Finished | Sep 18 07:53:14 PM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869069229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3869069229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.3355324430 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 157450114 ps |
| CPU time | 1.98 seconds |
| Started | Sep 18 07:53:11 PM UTC 24 |
| Finished | Sep 18 07:53:14 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355324430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3355324430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.2370755289 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 59790085 ps |
| CPU time | 1.04 seconds |
| Started | Sep 18 07:53:15 PM UTC 24 |
| Finished | Sep 18 07:53:17 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370755289 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2370755289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/35.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.1830323471 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1275088059 ps |
| CPU time | 6.6 seconds |
| Started | Sep 18 07:53:15 PM UTC 24 |
| Finished | Sep 18 07:53:23 PM UTC 24 |
| Peak memory | 244512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830323471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1830323471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.80043114 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 301487297 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 07:53:15 PM UTC 24 |
| Finished | Sep 18 07:53:18 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80043114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.80043114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.2644783021 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 114405981 ps |
| CPU time | 1.15 seconds |
| Started | Sep 18 07:53:14 PM UTC 24 |
| Finished | Sep 18 07:53:16 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644783021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2644783021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.456277853 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1031002794 ps |
| CPU time | 5.99 seconds |
| Started | Sep 18 07:53:14 PM UTC 24 |
| Finished | Sep 18 07:53:21 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456277853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.456277853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/35.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2776790980 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 104779523 ps |
| CPU time | 1.71 seconds |
| Started | Sep 18 07:53:14 PM UTC 24 |
| Finished | Sep 18 07:53:17 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776790980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2776790980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.2389690287 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 191733236 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 07:53:13 PM UTC 24 |
| Finished | Sep 18 07:53:15 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389690287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2389690287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/35.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.2539270827 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 9447110925 ps |
| CPU time | 41.26 seconds |
| Started | Sep 18 07:53:15 PM UTC 24 |
| Finished | Sep 18 07:53:58 PM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539270827 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2539270827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/35.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.4030429725 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 116863277 ps |
| CPU time | 2.06 seconds |
| Started | Sep 18 07:53:14 PM UTC 24 |
| Finished | Sep 18 07:53:17 PM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030429725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4030429725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.809111725 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 223775008 ps |
| CPU time | 1.82 seconds |
| Started | Sep 18 07:53:14 PM UTC 24 |
| Finished | Sep 18 07:53:17 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809111725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.809111725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.2534796430 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 84487607 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 07:53:18 PM UTC 24 |
| Finished | Sep 18 07:53:20 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534796430 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2534796430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/36.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.478072999 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1988792831 ps |
| CPU time | 9.39 seconds |
| Started | Sep 18 07:53:18 PM UTC 24 |
| Finished | Sep 18 07:53:28 PM UTC 24 |
| Peak memory | 243664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478072999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.478072999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2091632301 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 302451598 ps |
| CPU time | 2.01 seconds |
| Started | Sep 18 07:53:18 PM UTC 24 |
| Finished | Sep 18 07:53:21 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091632301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2091632301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.3357691978 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 237360622 ps |
| CPU time | 1.53 seconds |
| Started | Sep 18 07:53:17 PM UTC 24 |
| Finished | Sep 18 07:53:19 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357691978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3357691978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.2841007511 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1605917817 ps |
| CPU time | 8.04 seconds |
| Started | Sep 18 07:53:17 PM UTC 24 |
| Finished | Sep 18 07:53:26 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841007511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2841007511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/36.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4077919017 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 135366212 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 07:53:17 PM UTC 24 |
| Finished | Sep 18 07:53:19 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077919017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4077919017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.4064018808 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 195358628 ps |
| CPU time | 1.8 seconds |
| Started | Sep 18 07:53:16 PM UTC 24 |
| Finished | Sep 18 07:53:19 PM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064018808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.4064018808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/36.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.24590546 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 6382917911 ps |
| CPU time | 26.94 seconds |
| Started | Sep 18 07:53:18 PM UTC 24 |
| Finished | Sep 18 07:53:46 PM UTC 24 |
| Peak memory | 220400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24590546 -assert nopostproc +UVM_TESTNAME=rs tmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.24590546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/36.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.1334016101 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 141869160 ps |
| CPU time | 2.54 seconds |
| Started | Sep 18 07:53:17 PM UTC 24 |
| Finished | Sep 18 07:53:20 PM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334016101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1334016101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.2954359726 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 165416343 ps |
| CPU time | 2.03 seconds |
| Started | Sep 18 07:53:17 PM UTC 24 |
| Finished | Sep 18 07:53:20 PM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954359726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2954359726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.4085462095 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 65791318 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 07:53:21 PM UTC 24 |
| Finished | Sep 18 07:53:23 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085462095 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.4085462095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/37.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.2029944660 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1967591580 ps |
| CPU time | 9.19 seconds |
| Started | Sep 18 07:53:21 PM UTC 24 |
| Finished | Sep 18 07:53:31 PM UTC 24 |
| Peak memory | 244064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029944660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2029944660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1443337651 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 302038521 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 07:53:21 PM UTC 24 |
| Finished | Sep 18 07:53:24 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443337651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1443337651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.4290852095 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 106207721 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 07:53:18 PM UTC 24 |
| Finished | Sep 18 07:53:20 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290852095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.4290852095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.3519154213 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1411800916 ps |
| CPU time | 5.7 seconds |
| Started | Sep 18 07:53:18 PM UTC 24 |
| Finished | Sep 18 07:53:25 PM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519154213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3519154213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/37.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1321359575 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 104778783 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 07:53:19 PM UTC 24 |
| Finished | Sep 18 07:53:22 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321359575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1321359575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.4154215034 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 208909538 ps |
| CPU time | 2.19 seconds |
| Started | Sep 18 07:53:18 PM UTC 24 |
| Finished | Sep 18 07:53:21 PM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154215034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.4154215034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/37.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.3997003668 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 14552608613 ps |
| CPU time | 50.74 seconds |
| Started | Sep 18 07:53:21 PM UTC 24 |
| Finished | Sep 18 07:54:13 PM UTC 24 |
| Peak memory | 220592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997003668 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3997003668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/37.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.2683192594 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 522079323 ps |
| CPU time | 3.21 seconds |
| Started | Sep 18 07:53:19 PM UTC 24 |
| Finished | Sep 18 07:53:24 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683192594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2683192594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.3563447801 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 212321328 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 07:53:19 PM UTC 24 |
| Finished | Sep 18 07:53:22 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563447801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3563447801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.1905586783 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 65985853 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:53:24 PM UTC 24 |
| Finished | Sep 18 07:53:26 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905586783 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1905586783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/38.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.1021089683 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1267166677 ps |
| CPU time | 5.77 seconds |
| Started | Sep 18 07:53:23 PM UTC 24 |
| Finished | Sep 18 07:53:30 PM UTC 24 |
| Peak memory | 244444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021089683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1021089683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2440658998 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 302409459 ps |
| CPU time | 2.13 seconds |
| Started | Sep 18 07:53:24 PM UTC 24 |
| Finished | Sep 18 07:53:27 PM UTC 24 |
| Peak memory | 239984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440658998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2440658998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.6402731 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 86995242 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 07:53:22 PM UTC 24 |
| Finished | Sep 18 07:53:24 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6402731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r stmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.6402731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.1640494664 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1600909740 ps |
| CPU time | 5.72 seconds |
| Started | Sep 18 07:53:22 PM UTC 24 |
| Finished | Sep 18 07:53:29 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640494664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1640494664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/38.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.453516113 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 180987948 ps |
| CPU time | 2.04 seconds |
| Started | Sep 18 07:53:22 PM UTC 24 |
| Finished | Sep 18 07:53:25 PM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453516113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.453516113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.523907351 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 198993950 ps |
| CPU time | 1.72 seconds |
| Started | Sep 18 07:53:22 PM UTC 24 |
| Finished | Sep 18 07:53:25 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523907351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.523907351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/38.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.702909805 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 8510480505 ps |
| CPU time | 31.21 seconds |
| Started | Sep 18 07:53:24 PM UTC 24 |
| Finished | Sep 18 07:53:56 PM UTC 24 |
| Peak memory | 220420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702909805 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.702909805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/38.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.377782304 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 555749308 ps |
| CPU time | 2.94 seconds |
| Started | Sep 18 07:53:22 PM UTC 24 |
| Finished | Sep 18 07:53:26 PM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377782304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.377782304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.1026267555 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 138039516 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 07:53:22 PM UTC 24 |
| Finished | Sep 18 07:53:25 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026267555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1026267555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.3408264488 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 75456611 ps |
| CPU time | 1.15 seconds |
| Started | Sep 18 07:53:26 PM UTC 24 |
| Finished | Sep 18 07:53:29 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408264488 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3408264488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/39.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.78242210 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2435000465 ps |
| CPU time | 10.5 seconds |
| Started | Sep 18 07:53:26 PM UTC 24 |
| Finished | Sep 18 07:53:38 PM UTC 24 |
| Peak memory | 243872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78242210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.78242210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2459394693 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 301786733 ps |
| CPU time | 2.1 seconds |
| Started | Sep 18 07:53:26 PM UTC 24 |
| Finished | Sep 18 07:53:29 PM UTC 24 |
| Peak memory | 239984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459394693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2459394693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.844973976 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 197533739 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 07:53:25 PM UTC 24 |
| Finished | Sep 18 07:53:27 PM UTC 24 |
| Peak memory | 210112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844973976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.844973976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.1094154322 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1361745385 ps |
| CPU time | 6.78 seconds |
| Started | Sep 18 07:53:25 PM UTC 24 |
| Finished | Sep 18 07:53:33 PM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094154322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1094154322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/39.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.456385295 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 148317612 ps |
| CPU time | 1.59 seconds |
| Started | Sep 18 07:53:26 PM UTC 24 |
| Finished | Sep 18 07:53:29 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456385295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.456385295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.466363026 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 114649864 ps |
| CPU time | 1.56 seconds |
| Started | Sep 18 07:53:24 PM UTC 24 |
| Finished | Sep 18 07:53:26 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466363026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.466363026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/39.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.3779656008 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 8685136458 ps |
| CPU time | 41.5 seconds |
| Started | Sep 18 07:53:26 PM UTC 24 |
| Finished | Sep 18 07:54:09 PM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779656008 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3779656008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/39.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.1325157815 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 540824835 ps |
| CPU time | 3.66 seconds |
| Started | Sep 18 07:53:25 PM UTC 24 |
| Finished | Sep 18 07:53:30 PM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325157815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1325157815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.4057684561 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 106689756 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:53:25 PM UTC 24 |
| Finished | Sep 18 07:53:27 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057684561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4057684561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.218397172 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 76913342 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:51:53 PM UTC 24 |
| Finished | Sep 18 07:51:55 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218397172 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.218397172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.290574753 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1962216719 ps |
| CPU time | 8.46 seconds |
| Started | Sep 18 07:51:53 PM UTC 24 |
| Finished | Sep 18 07:52:02 PM UTC 24 |
| Peak memory | 244136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290574753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.290574753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3844982771 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 301869934 ps |
| CPU time | 1.99 seconds |
| Started | Sep 18 07:51:53 PM UTC 24 |
| Finished | Sep 18 07:51:56 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844982771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3844982771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.3069522918 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 131273549 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:51:53 PM UTC 24 |
| Finished | Sep 18 07:51:55 PM UTC 24 |
| Peak memory | 210036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069522918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3069522918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.923285835 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1687999028 ps |
| CPU time | 7.63 seconds |
| Started | Sep 18 07:51:53 PM UTC 24 |
| Finished | Sep 18 07:52:01 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923285835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.923285835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.4251968745 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 16745700856 ps |
| CPU time | 29.9 seconds |
| Started | Sep 18 07:51:53 PM UTC 24 |
| Finished | Sep 18 07:52:24 PM UTC 24 |
| Peak memory | 244176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251968745 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4251968745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1761460240 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 154275675 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 07:51:53 PM UTC 24 |
| Finished | Sep 18 07:51:55 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761460240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1761460240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.4202340367 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 258777838 ps |
| CPU time | 1.91 seconds |
| Started | Sep 18 07:51:50 PM UTC 24 |
| Finished | Sep 18 07:51:53 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202340367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.4202340367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.3965150275 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 366282483 ps |
| CPU time | 3.14 seconds |
| Started | Sep 18 07:51:53 PM UTC 24 |
| Finished | Sep 18 07:51:57 PM UTC 24 |
| Peak memory | 220020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965150275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3965150275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.1366019777 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 111496592 ps |
| CPU time | 1.15 seconds |
| Started | Sep 18 07:51:53 PM UTC 24 |
| Finished | Sep 18 07:51:55 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366019777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1366019777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.950745935 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 72571770 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 07:53:30 PM UTC 24 |
| Finished | Sep 18 07:53:32 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950745935 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.950745935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/40.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.379874838 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1274334359 ps |
| CPU time | 7.08 seconds |
| Started | Sep 18 07:53:29 PM UTC 24 |
| Finished | Sep 18 07:53:37 PM UTC 24 |
| Peak memory | 244452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379874838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.379874838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.637227211 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 301031851 ps |
| CPU time | 2.19 seconds |
| Started | Sep 18 07:53:30 PM UTC 24 |
| Finished | Sep 18 07:53:33 PM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637227211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.637227211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.162317877 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 208151884 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 07:53:26 PM UTC 24 |
| Finished | Sep 18 07:53:29 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162317877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.162317877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.2767208121 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1649797431 ps |
| CPU time | 7.91 seconds |
| Started | Sep 18 07:53:28 PM UTC 24 |
| Finished | Sep 18 07:53:37 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767208121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2767208121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/40.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.4242999986 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 164111126 ps |
| CPU time | 1.45 seconds |
| Started | Sep 18 07:53:29 PM UTC 24 |
| Finished | Sep 18 07:53:31 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242999986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.4242999986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.3749522128 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 116147992 ps |
| CPU time | 1.69 seconds |
| Started | Sep 18 07:53:26 PM UTC 24 |
| Finished | Sep 18 07:53:29 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749522128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3749522128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/40.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.1621343660 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 9324555201 ps |
| CPU time | 32.24 seconds |
| Started | Sep 18 07:53:30 PM UTC 24 |
| Finished | Sep 18 07:54:04 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621343660 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1621343660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/40.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.2419229861 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 135941131 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 07:53:28 PM UTC 24 |
| Finished | Sep 18 07:53:31 PM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419229861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2419229861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.2766181010 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 97575137 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 07:53:28 PM UTC 24 |
| Finished | Sep 18 07:53:30 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766181010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2766181010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.2465832136 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 83565876 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 07:53:33 PM UTC 24 |
| Finished | Sep 18 07:53:35 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465832136 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2465832136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/41.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.3713772958 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 1262160909 ps |
| CPU time | 8.39 seconds |
| Started | Sep 18 07:53:32 PM UTC 24 |
| Finished | Sep 18 07:53:41 PM UTC 24 |
| Peak memory | 243660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713772958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3713772958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3158471283 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 302081344 ps |
| CPU time | 1.94 seconds |
| Started | Sep 18 07:53:32 PM UTC 24 |
| Finished | Sep 18 07:53:35 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158471283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3158471283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.895260329 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 109781823 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 07:53:30 PM UTC 24 |
| Finished | Sep 18 07:53:32 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895260329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.895260329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.128199203 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2020749745 ps |
| CPU time | 9.43 seconds |
| Started | Sep 18 07:53:30 PM UTC 24 |
| Finished | Sep 18 07:53:41 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128199203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.128199203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/41.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1675297042 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 110359538 ps |
| CPU time | 1.79 seconds |
| Started | Sep 18 07:53:32 PM UTC 24 |
| Finished | Sep 18 07:53:34 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675297042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1675297042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.4245766498 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 199831289 ps |
| CPU time | 1.75 seconds |
| Started | Sep 18 07:53:30 PM UTC 24 |
| Finished | Sep 18 07:53:33 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245766498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.4245766498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/41.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.2704449016 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 438942266 ps |
| CPU time | 3.69 seconds |
| Started | Sep 18 07:53:32 PM UTC 24 |
| Finished | Sep 18 07:53:37 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704449016 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2704449016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/41.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.2185927482 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 120990745 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 07:53:32 PM UTC 24 |
| Finished | Sep 18 07:53:35 PM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185927482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2185927482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.3444395175 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 117489091 ps |
| CPU time | 1.53 seconds |
| Started | Sep 18 07:53:30 PM UTC 24 |
| Finished | Sep 18 07:53:33 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444395175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3444395175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.3653945608 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 64778249 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 07:53:36 PM UTC 24 |
| Finished | Sep 18 07:53:38 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653945608 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3653945608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/42.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.424628654 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2444803539 ps |
| CPU time | 9.59 seconds |
| Started | Sep 18 07:53:35 PM UTC 24 |
| Finished | Sep 18 07:53:45 PM UTC 24 |
| Peak memory | 243852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424628654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.424628654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2716144061 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 301542268 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 07:53:35 PM UTC 24 |
| Finished | Sep 18 07:53:37 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716144061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2716144061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.468004490 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 146744094 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 07:53:33 PM UTC 24 |
| Finished | Sep 18 07:53:35 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468004490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.468004490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.2698166527 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 770582480 ps |
| CPU time | 4.88 seconds |
| Started | Sep 18 07:53:33 PM UTC 24 |
| Finished | Sep 18 07:53:39 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698166527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2698166527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/42.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2773152385 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 174942589 ps |
| CPU time | 1.8 seconds |
| Started | Sep 18 07:53:33 PM UTC 24 |
| Finished | Sep 18 07:53:36 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773152385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2773152385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.2595220513 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 111987158 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 07:53:33 PM UTC 24 |
| Finished | Sep 18 07:53:36 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595220513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2595220513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/42.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.2659363547 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 4574364507 ps |
| CPU time | 18.77 seconds |
| Started | Sep 18 07:53:36 PM UTC 24 |
| Finished | Sep 18 07:53:56 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659363547 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2659363547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/42.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.1497342588 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 144539992 ps |
| CPU time | 2.31 seconds |
| Started | Sep 18 07:53:33 PM UTC 24 |
| Finished | Sep 18 07:53:37 PM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497342588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1497342588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.2312226143 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 199415777 ps |
| CPU time | 2.14 seconds |
| Started | Sep 18 07:53:33 PM UTC 24 |
| Finished | Sep 18 07:53:36 PM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312226143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2312226143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.290611533 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 86991505 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 07:53:38 PM UTC 24 |
| Finished | Sep 18 07:53:40 PM UTC 24 |
| Peak memory | 209032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290611533 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.290611533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/43.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.416919557 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1273366665 ps |
| CPU time | 7.82 seconds |
| Started | Sep 18 07:53:38 PM UTC 24 |
| Finished | Sep 18 07:53:47 PM UTC 24 |
| Peak memory | 243668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416919557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.416919557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.781165375 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 302610624 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 07:53:38 PM UTC 24 |
| Finished | Sep 18 07:53:40 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781165375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.781165375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.3921446728 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 202107564 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 07:53:36 PM UTC 24 |
| Finished | Sep 18 07:53:39 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921446728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3921446728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.760116959 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1003545100 ps |
| CPU time | 6.38 seconds |
| Started | Sep 18 07:53:36 PM UTC 24 |
| Finished | Sep 18 07:53:44 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760116959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.760116959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/43.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2167610919 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 174536249 ps |
| CPU time | 1.6 seconds |
| Started | Sep 18 07:53:38 PM UTC 24 |
| Finished | Sep 18 07:53:40 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167610919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2167610919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.1695680711 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 193612636 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:53:36 PM UTC 24 |
| Finished | Sep 18 07:53:39 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695680711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1695680711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/43.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.3318634770 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4883027836 ps |
| CPU time | 21.43 seconds |
| Started | Sep 18 07:53:38 PM UTC 24 |
| Finished | Sep 18 07:54:00 PM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318634770 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3318634770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/43.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.2486247379 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 357782454 ps |
| CPU time | 3.18 seconds |
| Started | Sep 18 07:53:37 PM UTC 24 |
| Finished | Sep 18 07:53:42 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486247379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2486247379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.1123371726 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 147999615 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 07:53:37 PM UTC 24 |
| Finished | Sep 18 07:53:40 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123371726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1123371726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.3792289998 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 79189641 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 07:53:41 PM UTC 24 |
| Finished | Sep 18 07:53:43 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792289998 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3792289998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/44.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.2814841870 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1969371219 ps |
| CPU time | 9.2 seconds |
| Started | Sep 18 07:53:40 PM UTC 24 |
| Finished | Sep 18 07:53:50 PM UTC 24 |
| Peak memory | 243652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814841870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2814841870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1185476000 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 301289703 ps |
| CPU time | 1.79 seconds |
| Started | Sep 18 07:53:40 PM UTC 24 |
| Finished | Sep 18 07:53:43 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185476000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1185476000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.222393627 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 217371632 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 07:53:38 PM UTC 24 |
| Finished | Sep 18 07:53:40 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222393627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.222393627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.2357845316 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1366704202 ps |
| CPU time | 7.17 seconds |
| Started | Sep 18 07:53:39 PM UTC 24 |
| Finished | Sep 18 07:53:47 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357845316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2357845316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/44.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1696464905 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 101745691 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 07:53:40 PM UTC 24 |
| Finished | Sep 18 07:53:43 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696464905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1696464905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.2630349676 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 258750710 ps |
| CPU time | 2.42 seconds |
| Started | Sep 18 07:53:38 PM UTC 24 |
| Finished | Sep 18 07:53:41 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630349676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2630349676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/44.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.1592089055 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2263761811 ps |
| CPU time | 7.89 seconds |
| Started | Sep 18 07:53:41 PM UTC 24 |
| Finished | Sep 18 07:53:50 PM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592089055 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1592089055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/44.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.3733479179 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 367164927 ps |
| CPU time | 2.36 seconds |
| Started | Sep 18 07:53:39 PM UTC 24 |
| Finished | Sep 18 07:53:42 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733479179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3733479179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.1040240870 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 84740160 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 07:53:39 PM UTC 24 |
| Finished | Sep 18 07:53:41 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040240870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1040240870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.1041749945 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 74782371 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 07:53:46 PM UTC 24 |
| Finished | Sep 18 07:53:48 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041749945 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1041749945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/45.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.2154232867 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 1972621365 ps |
| CPU time | 7.09 seconds |
| Started | Sep 18 07:53:45 PM UTC 24 |
| Finished | Sep 18 07:53:54 PM UTC 24 |
| Peak memory | 243884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154232867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2154232867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1040305282 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 301527527 ps |
| CPU time | 1.61 seconds |
| Started | Sep 18 07:53:46 PM UTC 24 |
| Finished | Sep 18 07:53:48 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040305282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1040305282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.2959901245 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 112861878 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 07:53:42 PM UTC 24 |
| Finished | Sep 18 07:53:44 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959901245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2959901245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.229268124 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1474085753 ps |
| CPU time | 7.58 seconds |
| Started | Sep 18 07:53:42 PM UTC 24 |
| Finished | Sep 18 07:53:50 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229268124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.229268124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/45.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.830427678 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 161026694 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:53:45 PM UTC 24 |
| Finished | Sep 18 07:53:48 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830427678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.830427678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.3600436240 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 226652240 ps |
| CPU time | 2.32 seconds |
| Started | Sep 18 07:53:41 PM UTC 24 |
| Finished | Sep 18 07:53:45 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600436240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3600436240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/45.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.1842989413 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 3579901497 ps |
| CPU time | 14.81 seconds |
| Started | Sep 18 07:53:46 PM UTC 24 |
| Finished | Sep 18 07:54:02 PM UTC 24 |
| Peak memory | 220400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842989413 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1842989413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/45.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.3739418142 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 453581153 ps |
| CPU time | 2.82 seconds |
| Started | Sep 18 07:53:45 PM UTC 24 |
| Finished | Sep 18 07:53:49 PM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739418142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3739418142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.2170976785 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 62984540 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 07:53:42 PM UTC 24 |
| Finished | Sep 18 07:53:44 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170976785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2170976785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.1180136864 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 72663731 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 07:53:47 PM UTC 24 |
| Finished | Sep 18 07:53:49 PM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180136864 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1180136864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/46.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.2795219065 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2452060356 ps |
| CPU time | 8.34 seconds |
| Started | Sep 18 07:53:47 PM UTC 24 |
| Finished | Sep 18 07:53:57 PM UTC 24 |
| Peak memory | 243708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795219065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2795219065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3106833119 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 305240179 ps |
| CPU time | 1.88 seconds |
| Started | Sep 18 07:53:47 PM UTC 24 |
| Finished | Sep 18 07:53:50 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106833119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3106833119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.716114090 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 223032931 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 07:53:47 PM UTC 24 |
| Finished | Sep 18 07:53:49 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716114090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.716114090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.1380508467 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1708334780 ps |
| CPU time | 8.94 seconds |
| Started | Sep 18 07:53:47 PM UTC 24 |
| Finished | Sep 18 07:53:57 PM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380508467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1380508467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/46.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1530731930 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 110195251 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 07:53:47 PM UTC 24 |
| Finished | Sep 18 07:53:50 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530731930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1530731930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.3567129336 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 116398076 ps |
| CPU time | 1.84 seconds |
| Started | Sep 18 07:53:47 PM UTC 24 |
| Finished | Sep 18 07:53:50 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567129336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3567129336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/46.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.3391032782 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2244333210 ps |
| CPU time | 10.63 seconds |
| Started | Sep 18 07:53:47 PM UTC 24 |
| Finished | Sep 18 07:53:59 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391032782 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3391032782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/46.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.2520881667 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 312278003 ps |
| CPU time | 2.79 seconds |
| Started | Sep 18 07:53:47 PM UTC 24 |
| Finished | Sep 18 07:53:51 PM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520881667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2520881667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.2553916420 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 108995248 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 07:53:47 PM UTC 24 |
| Finished | Sep 18 07:53:50 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553916420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2553916420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.1108031021 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 74981075 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:53:56 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108031021 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1108031021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/47.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.169070577 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1271082832 ps |
| CPU time | 5.65 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:54:00 PM UTC 24 |
| Peak memory | 243728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169070577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.169070577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.565001772 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 305194531 ps |
| CPU time | 1.91 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:53:57 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565001772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.565001772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.3725719736 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 200453532 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:53:52 PM UTC 24 |
| Finished | Sep 18 07:53:55 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725719736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3725719736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.791499702 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 815830716 ps |
| CPU time | 5.44 seconds |
| Started | Sep 18 07:53:52 PM UTC 24 |
| Finished | Sep 18 07:53:59 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791499702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.791499702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/47.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2603048068 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 139705230 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:53:56 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603048068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2603048068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.1117726798 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 194495414 ps |
| CPU time | 1.99 seconds |
| Started | Sep 18 07:53:52 PM UTC 24 |
| Finished | Sep 18 07:53:55 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117726798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1117726798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/47.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.332385180 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 2637091184 ps |
| CPU time | 11.05 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:54:06 PM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332385180 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.332385180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/47.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.2914067247 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 516197903 ps |
| CPU time | 3.02 seconds |
| Started | Sep 18 07:53:52 PM UTC 24 |
| Finished | Sep 18 07:53:56 PM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914067247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2914067247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.765076318 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 64539193 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 07:53:52 PM UTC 24 |
| Finished | Sep 18 07:53:54 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765076318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.765076318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.4187469902 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 57576059 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 07:53:55 PM UTC 24 |
| Finished | Sep 18 07:53:57 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187469902 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4187469902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/48.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.2289602877 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1277841692 ps |
| CPU time | 6.24 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:54:01 PM UTC 24 |
| Peak memory | 244448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289602877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2289602877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1693924553 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 302043078 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:53:57 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693924553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1693924553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.3919205503 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 158698958 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:53:56 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919205503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3919205503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.406652385 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1798038278 ps |
| CPU time | 7.73 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:54:03 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406652385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.406652385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/48.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3637443616 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 191441255 ps |
| CPU time | 1.61 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:53:57 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637443616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3637443616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.875439285 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 129367018 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:53:57 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875439285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.875439285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/48.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.1067948178 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 5098356796 ps |
| CPU time | 24.24 seconds |
| Started | Sep 18 07:53:55 PM UTC 24 |
| Finished | Sep 18 07:54:21 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067948178 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1067948178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/48.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.3595471104 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 115608631 ps |
| CPU time | 2 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:53:57 PM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595471104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3595471104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.964247242 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 225241108 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 07:53:54 PM UTC 24 |
| Finished | Sep 18 07:53:57 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964247242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.964247242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.1476116697 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 55479792 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 07:53:58 PM UTC 24 |
| Finished | Sep 18 07:54:00 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476116697 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1476116697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/49.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.2427996051 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1273207488 ps |
| CPU time | 6.62 seconds |
| Started | Sep 18 07:53:58 PM UTC 24 |
| Finished | Sep 18 07:54:06 PM UTC 24 |
| Peak memory | 244472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427996051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2427996051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3804054253 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 303695003 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 07:53:58 PM UTC 24 |
| Finished | Sep 18 07:54:01 PM UTC 24 |
| Peak memory | 239180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804054253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3804054253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.1442033829 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 137953475 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 07:53:57 PM UTC 24 |
| Finished | Sep 18 07:53:59 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442033829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1442033829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.3559010923 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1329793139 ps |
| CPU time | 5.9 seconds |
| Started | Sep 18 07:53:57 PM UTC 24 |
| Finished | Sep 18 07:54:04 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559010923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3559010923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/49.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2797343815 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 145232587 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 07:53:57 PM UTC 24 |
| Finished | Sep 18 07:53:59 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797343815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2797343815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.2287363506 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 203708484 ps |
| CPU time | 2.02 seconds |
| Started | Sep 18 07:53:55 PM UTC 24 |
| Finished | Sep 18 07:53:58 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287363506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2287363506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/49.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.1063060719 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4791315027 ps |
| CPU time | 16.98 seconds |
| Started | Sep 18 07:53:58 PM UTC 24 |
| Finished | Sep 18 07:54:16 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063060719 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1063060719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/49.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.3381854345 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 316994206 ps |
| CPU time | 2.04 seconds |
| Started | Sep 18 07:53:57 PM UTC 24 |
| Finished | Sep 18 07:54:00 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381854345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3381854345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.3636498685 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 191070828 ps |
| CPU time | 1.6 seconds |
| Started | Sep 18 07:53:57 PM UTC 24 |
| Finished | Sep 18 07:53:59 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636498685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3636498685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.3246685552 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 68229865 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 07:51:58 PM UTC 24 |
| Finished | Sep 18 07:52:00 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246685552 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3246685552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.2523895837 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1272419889 ps |
| CPU time | 5.94 seconds |
| Started | Sep 18 07:51:55 PM UTC 24 |
| Finished | Sep 18 07:52:03 PM UTC 24 |
| Peak memory | 244124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523895837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2523895837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1905819898 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 301777757 ps |
| CPU time | 1.32 seconds |
| Started | Sep 18 07:51:56 PM UTC 24 |
| Finished | Sep 18 07:51:58 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905819898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1905819898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.3366861897 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 145694779 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 07:51:55 PM UTC 24 |
| Finished | Sep 18 07:51:58 PM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366861897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3366861897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.760598080 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1868748921 ps |
| CPU time | 8.12 seconds |
| Started | Sep 18 07:51:55 PM UTC 24 |
| Finished | Sep 18 07:52:05 PM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760598080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.760598080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2277415967 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 186617198 ps |
| CPU time | 1.93 seconds |
| Started | Sep 18 07:51:55 PM UTC 24 |
| Finished | Sep 18 07:51:59 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277415967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2277415967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.2301813987 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 111030502 ps |
| CPU time | 1.89 seconds |
| Started | Sep 18 07:51:55 PM UTC 24 |
| Finished | Sep 18 07:51:58 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301813987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2301813987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.1907426717 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 9619607126 ps |
| CPU time | 35.82 seconds |
| Started | Sep 18 07:51:56 PM UTC 24 |
| Finished | Sep 18 07:52:33 PM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907426717 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1907426717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.2580807864 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 137403791 ps |
| CPU time | 2.4 seconds |
| Started | Sep 18 07:51:55 PM UTC 24 |
| Finished | Sep 18 07:51:59 PM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580807864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2580807864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.692265227 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 226025286 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 07:51:55 PM UTC 24 |
| Finished | Sep 18 07:51:59 PM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692265227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.692265227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.831060907 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 69242525 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 07:52:01 PM UTC 24 |
| Finished | Sep 18 07:52:03 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831060907 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.831060907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1471353786 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 301750733 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 07:51:58 PM UTC 24 |
| Finished | Sep 18 07:52:02 PM UTC 24 |
| Peak memory | 239984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471353786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1471353786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.72137386 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 213944043 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 07:51:58 PM UTC 24 |
| Finished | Sep 18 07:52:01 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72137386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.72137386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.3126163923 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 901213378 ps |
| CPU time | 4.86 seconds |
| Started | Sep 18 07:51:58 PM UTC 24 |
| Finished | Sep 18 07:52:04 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126163923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3126163923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3579186678 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 104524684 ps |
| CPU time | 1.62 seconds |
| Started | Sep 18 07:51:58 PM UTC 24 |
| Finished | Sep 18 07:52:01 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579186678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3579186678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.240005917 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 229205634 ps |
| CPU time | 2.01 seconds |
| Started | Sep 18 07:51:58 PM UTC 24 |
| Finished | Sep 18 07:52:01 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240005917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.240005917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.2409914229 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 7744392087 ps |
| CPU time | 29.08 seconds |
| Started | Sep 18 07:52:01 PM UTC 24 |
| Finished | Sep 18 07:52:31 PM UTC 24 |
| Peak memory | 220352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409914229 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2409914229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.3868725663 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 324416357 ps |
| CPU time | 2.75 seconds |
| Started | Sep 18 07:51:58 PM UTC 24 |
| Finished | Sep 18 07:52:02 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868725663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3868725663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2887212065 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 202409291 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 07:51:58 PM UTC 24 |
| Finished | Sep 18 07:52:01 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887212065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2887212065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2324251496 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 74037762 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 07:52:03 PM UTC 24 |
| Finished | Sep 18 07:52:06 PM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324251496 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2324251496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.4294662316 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2445417932 ps |
| CPU time | 10.38 seconds |
| Started | Sep 18 07:52:03 PM UTC 24 |
| Finished | Sep 18 07:52:15 PM UTC 24 |
| Peak memory | 244424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294662316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.4294662316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2098700125 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 303190602 ps |
| CPU time | 1.85 seconds |
| Started | Sep 18 07:52:03 PM UTC 24 |
| Finished | Sep 18 07:52:06 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098700125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2098700125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.3233908002 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 201748663 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 07:52:01 PM UTC 24 |
| Finished | Sep 18 07:52:03 PM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233908002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3233908002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.2774193420 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1032581668 ps |
| CPU time | 5.47 seconds |
| Started | Sep 18 07:52:01 PM UTC 24 |
| Finished | Sep 18 07:52:07 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774193420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2774193420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1600559140 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 109409484 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 07:52:02 PM UTC 24 |
| Finished | Sep 18 07:52:04 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600559140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1600559140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.945094887 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 237000662 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 07:52:01 PM UTC 24 |
| Finished | Sep 18 07:52:04 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945094887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.945094887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.808118798 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2047389241 ps |
| CPU time | 8.83 seconds |
| Started | Sep 18 07:52:03 PM UTC 24 |
| Finished | Sep 18 07:52:13 PM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808118798 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.808118798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.2625264791 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 377199572 ps |
| CPU time | 2.57 seconds |
| Started | Sep 18 07:52:01 PM UTC 24 |
| Finished | Sep 18 07:52:05 PM UTC 24 |
| Peak memory | 220024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625264791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2625264791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.1667539989 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 106367277 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 07:52:01 PM UTC 24 |
| Finished | Sep 18 07:52:03 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667539989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1667539989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.578011199 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 79195270 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 07:52:05 PM UTC 24 |
| Finished | Sep 18 07:52:07 PM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578011199 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.578011199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.151878054 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1271288649 ps |
| CPU time | 7.65 seconds |
| Started | Sep 18 07:52:05 PM UTC 24 |
| Finished | Sep 18 07:52:14 PM UTC 24 |
| Peak memory | 243712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151878054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.151878054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1880017090 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 303149341 ps |
| CPU time | 1.71 seconds |
| Started | Sep 18 07:52:05 PM UTC 24 |
| Finished | Sep 18 07:52:08 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880017090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1880017090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.240608747 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 153813820 ps |
| CPU time | 0.98 seconds |
| Started | Sep 18 07:52:03 PM UTC 24 |
| Finished | Sep 18 07:52:06 PM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240608747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.240608747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.3586315234 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1303955265 ps |
| CPU time | 5.5 seconds |
| Started | Sep 18 07:52:05 PM UTC 24 |
| Finished | Sep 18 07:52:11 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586315234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3586315234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3975813880 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 166899609 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 07:52:05 PM UTC 24 |
| Finished | Sep 18 07:52:08 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975813880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3975813880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.3346174280 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 205283651 ps |
| CPU time | 2.39 seconds |
| Started | Sep 18 07:52:03 PM UTC 24 |
| Finished | Sep 18 07:52:07 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346174280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3346174280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.2343282125 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1655827980 ps |
| CPU time | 8.97 seconds |
| Started | Sep 18 07:52:05 PM UTC 24 |
| Finished | Sep 18 07:52:15 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343282125 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2343282125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.3646260400 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 301289743 ps |
| CPU time | 2.53 seconds |
| Started | Sep 18 07:52:05 PM UTC 24 |
| Finished | Sep 18 07:52:08 PM UTC 24 |
| Peak memory | 220024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646260400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3646260400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.4006823903 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 166568808 ps |
| CPU time | 1.9 seconds |
| Started | Sep 18 07:52:05 PM UTC 24 |
| Finished | Sep 18 07:52:08 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006823903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.4006823903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.2867623186 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 83690354 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 07:52:08 PM UTC 24 |
| Finished | Sep 18 07:52:10 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867623186 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2867623186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.1013143372 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1955217056 ps |
| CPU time | 8.7 seconds |
| Started | Sep 18 07:52:07 PM UTC 24 |
| Finished | Sep 18 07:52:17 PM UTC 24 |
| Peak memory | 243724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013143372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1013143372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3754441304 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 302375531 ps |
| CPU time | 1.93 seconds |
| Started | Sep 18 07:52:07 PM UTC 24 |
| Finished | Sep 18 07:52:10 PM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754441304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3754441304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.3066416245 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 100399818 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 07:52:05 PM UTC 24 |
| Finished | Sep 18 07:52:07 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066416245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3066416245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.1230075554 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1577466180 ps |
| CPU time | 8.18 seconds |
| Started | Sep 18 07:52:06 PM UTC 24 |
| Finished | Sep 18 07:52:16 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230075554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1230075554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2450874411 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 113160469 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 07:52:07 PM UTC 24 |
| Finished | Sep 18 07:52:09 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450874411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2450874411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.2519882254 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 8098767055 ps |
| CPU time | 31.87 seconds |
| Started | Sep 18 07:52:08 PM UTC 24 |
| Finished | Sep 18 07:52:41 PM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519882254 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2519882254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.3728965070 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 153162265 ps |
| CPU time | 1.88 seconds |
| Started | Sep 18 07:52:06 PM UTC 24 |
| Finished | Sep 18 07:52:10 PM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728965070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3728965070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.2445837787 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 145064227 ps |
| CPU time | 1.56 seconds |
| Started | Sep 18 07:52:06 PM UTC 24 |
| Finished | Sep 18 07:52:09 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445837787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2445837787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest |
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