Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8663

1

T3

19

T8

29

T11

4

auto[1]

11300

1

T1

4

T3

1

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6184	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6707	1			T1	2		T2	1		T3	1
reset_info_cp[2]	3076	1			T1	1		T4	1		T8	5
reset_info_cp[4]	4046	1			T1	1		T4	1		T8	10
reset_info_cp[8]	108	1			T3	1		T51	1		T26	1
reset_info_cp[16]	127	1			T35	1		T37	1		T57	1
reset_info_cp[32]	102	1			T8	1		T11	1		T13	2
reset_info_cp[64]	120	1			T3	1		T4	1		T52	1
reset_info_cp[128]	113	1			T3	1		T11	1		T13	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3275	1			T8	10		T13	16		T22	5
reset_info_cp[1]	auto[1]	2812	1			T1	1		T4	1		T8	11
reset_info_cp[2]	auto[0]	1028	1			T8	1		T22	3		T83	3
reset_info_cp[2]	auto[1]	2048	1			T1	1		T4	1		T8	4
reset_info_cp[4]	auto[0]	1481	1			T8	4		T22	11		T83	15
reset_info_cp[4]	auto[1]	2565	1			T1	1		T4	1		T8	6
reset_info_cp[8]	auto[0]	41	1			T3	1		T87	1		T88	1
reset_info_cp[8]	auto[1]	67	1			T51	1		T26	1		T101	1
reset_info_cp[16]	auto[0]	50	1			T37	1		T88	1		T99	1
reset_info_cp[16]	auto[1]	77	1			T35	1		T57	1		T87	1
reset_info_cp[32]	auto[0]	40	1			T8	1		T11	1		T136	2
reset_info_cp[32]	auto[1]	62	1			T13	2		T40	1		T57	1
reset_info_cp[64]	auto[0]	53	1			T3	1		T52	1		T35	1
reset_info_cp[64]	auto[1]	67	1			T4	1		T57	1		T26	1
reset_info_cp[128]	auto[0]	47	1			T11	1		T52	2		T83	1
reset_info_cp[128]	auto[1]	66	1			T3	1		T13	2		T23	1