Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7520

1

T3

15

T5

24

T13

11

auto[1]

10931

1

T1

4

T3

1

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5650	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6320	1			T1	2		T2	1		T3	1
reset_info_cp[2]	2891	1			T1	1		T4	1		T5	9
reset_info_cp[4]	3703	1			T1	1		T4	1		T5	10
reset_info_cp[8]	94	1			T11	1		T26	2		T27	1
reset_info_cp[16]	115	1			T13	2		T50	1		T104	1
reset_info_cp[32]	83	1			T5	1		T13	1		T26	1
reset_info_cp[64]	114	1			T3	1		T13	1		T27	2
reset_info_cp[128]	101	1			T3	1		T13	1		T27	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3028	1			T5	9		T14	18		T50	9
reset_info_cp[1]	auto[1]	2672	1			T1	1		T4	1		T5	11
reset_info_cp[2]	auto[0]	891	1			T5	6		T50	6		T41	5
reset_info_cp[2]	auto[1]	2000	1			T1	1		T4	1		T5	3
reset_info_cp[4]	auto[0]	1239	1			T5	4		T50	6		T41	6
reset_info_cp[4]	auto[1]	2464	1			T1	1		T4	1		T5	6
reset_info_cp[8]	auto[0]	43	1			T26	2		T42	1		T86	1
reset_info_cp[8]	auto[1]	51	1			T11	1		T27	1		T43	1
reset_info_cp[16]	auto[0]	36	1			T13	2		T104	1		T105	1
reset_info_cp[16]	auto[1]	79	1			T50	1		T85	1		T90	1
reset_info_cp[32]	auto[0]	36	1			T5	1		T13	1		T26	1
reset_info_cp[32]	auto[1]	47	1			T42	1		T101	1		T61	1
reset_info_cp[64]	auto[0]	41	1			T3	1		T13	1		T42	1
reset_info_cp[64]	auto[1]	73	1			T27	2		T41	1		T43	1
reset_info_cp[128]	auto[0]	40	1			T3	1		T13	1		T92	1
reset_info_cp[128]	auto[1]	61	1			T27	1		T42	2		T43	3