LINE 1361
EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | 1 | Covered | T1,T3,T5 |
| 1 | 1 | 0 | Covered | T78,T96,T97 |
| 1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 1364
EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | 1 | Covered | T1,T3,T5 |
| 1 | 1 | 0 | Covered | T75,T78,T96 |
| 1 | 1 | 1 | Covered | T1,T3,T7 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |