| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.46 | 99.40 | 99.31 | 100.00 | 99.83 | 99.46 | 98.77 |
| T538 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.254141560 | Oct 14 11:47:29 PM UTC 24 | Oct 14 11:47:37 PM UTC 24 | 1966297672 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.2987544478 | Oct 14 11:47:28 PM UTC 24 | Oct 14 11:47:39 PM UTC 24 | 2191081505 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.398803047 | Oct 14 11:47:21 PM UTC 24 | Oct 14 11:47:40 PM UTC 24 | 5222563961 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.2326399697 | Oct 14 11:47:29 PM UTC 24 | Oct 14 11:47:54 PM UTC 24 | 7512307581 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.2453880909 | Oct 14 11:47:16 PM UTC 24 | Oct 14 11:48:03 PM UTC 24 | 12407129781 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.290396814 | Oct 14 10:25:25 PM UTC 24 | Oct 14 10:25:28 PM UTC 24 | 237415421 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3049455764 | Oct 14 10:25:29 PM UTC 24 | Oct 14 10:25:32 PM UTC 24 | 404700372 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2262247634 | Oct 14 10:25:31 PM UTC 24 | Oct 14 10:25:33 PM UTC 24 | 104535061 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.2233039209 | Oct 14 10:25:32 PM UTC 24 | Oct 14 10:25:34 PM UTC 24 | 63358717 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2583481459 | Oct 14 10:25:34 PM UTC 24 | Oct 14 10:25:37 PM UTC 24 | 114199223 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2029486621 | Oct 14 10:25:34 PM UTC 24 | Oct 14 10:25:37 PM UTC 24 | 209998870 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.865074969 | Oct 14 10:25:35 PM UTC 24 | Oct 14 10:25:38 PM UTC 24 | 121359794 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2828182276 | Oct 14 10:25:38 PM UTC 24 | Oct 14 10:25:41 PM UTC 24 | 58780169 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2100189676 | Oct 14 10:25:38 PM UTC 24 | Oct 14 10:25:41 PM UTC 24 | 98362220 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.366565219 | Oct 14 10:25:40 PM UTC 24 | Oct 14 10:25:43 PM UTC 24 | 205941488 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.3514576855 | Oct 14 10:25:38 PM UTC 24 | Oct 14 10:25:43 PM UTC 24 | 410117912 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3463722619 | Oct 14 10:25:42 PM UTC 24 | Oct 14 10:25:44 PM UTC 24 | 70274014 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4056927824 | Oct 14 10:25:42 PM UTC 24 | Oct 14 10:25:45 PM UTC 24 | 189150261 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3688690723 | Oct 14 10:25:38 PM UTC 24 | Oct 14 10:25:45 PM UTC 24 | 1169624028 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.814822478 | Oct 14 10:25:38 PM UTC 24 | Oct 14 10:25:46 PM UTC 24 | 808375533 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.1628597240 | Oct 14 10:25:44 PM UTC 24 | Oct 14 10:25:47 PM UTC 24 | 94445184 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3353598461 | Oct 14 10:25:45 PM UTC 24 | Oct 14 10:25:47 PM UTC 24 | 121443367 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.2996470827 | Oct 14 10:25:46 PM UTC 24 | Oct 14 10:25:48 PM UTC 24 | 65564263 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1139235184 | Oct 14 10:25:46 PM UTC 24 | Oct 14 10:25:49 PM UTC 24 | 109323062 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2354244507 | Oct 14 10:25:46 PM UTC 24 | Oct 14 10:25:50 PM UTC 24 | 178565760 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2102983246 | Oct 14 10:25:33 PM UTC 24 | Oct 14 10:25:50 PM UTC 24 | 2286886549 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.25836522 | Oct 14 10:25:45 PM UTC 24 | Oct 14 10:25:50 PM UTC 24 | 908792797 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2500791626 | Oct 14 10:25:46 PM UTC 24 | Oct 14 10:25:51 PM UTC 24 | 353358066 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3043240862 | Oct 14 10:25:48 PM UTC 24 | Oct 14 10:25:51 PM UTC 24 | 147564442 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.1628983788 | Oct 14 10:25:47 PM UTC 24 | Oct 14 10:25:51 PM UTC 24 | 375418249 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.3562161953 | Oct 14 10:25:50 PM UTC 24 | Oct 14 10:25:52 PM UTC 24 | 73486258 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.877518177 | Oct 14 10:25:50 PM UTC 24 | Oct 14 10:25:52 PM UTC 24 | 120324400 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1916422262 | Oct 14 10:25:50 PM UTC 24 | Oct 14 10:25:53 PM UTC 24 | 112315731 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.330013981 | Oct 14 10:25:50 PM UTC 24 | Oct 14 10:25:53 PM UTC 24 | 236575065 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.2547638675 | Oct 14 10:25:51 PM UTC 24 | Oct 14 10:25:53 PM UTC 24 | 86156142 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4159761368 | Oct 14 10:25:51 PM UTC 24 | Oct 14 10:25:53 PM UTC 24 | 106410118 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1175439712 | Oct 14 10:25:48 PM UTC 24 | Oct 14 10:25:54 PM UTC 24 | 928749965 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.492790589 | Oct 14 10:25:51 PM UTC 24 | Oct 14 10:25:54 PM UTC 24 | 284541086 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3198921577 | Oct 14 10:25:52 PM UTC 24 | Oct 14 10:25:55 PM UTC 24 | 143037535 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1823031526 | Oct 14 10:25:50 PM UTC 24 | Oct 14 10:25:56 PM UTC 24 | 800208100 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.1228664387 | Oct 14 10:25:54 PM UTC 24 | Oct 14 10:25:56 PM UTC 24 | 63411967 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3314714848 | Oct 14 10:25:51 PM UTC 24 | Oct 14 10:25:56 PM UTC 24 | 936620399 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2959702576 | Oct 14 10:25:52 PM UTC 24 | Oct 14 10:25:56 PM UTC 24 | 203405633 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.723423084 | Oct 14 10:25:52 PM UTC 24 | Oct 14 10:25:56 PM UTC 24 | 215205300 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.708932743 | Oct 14 10:25:54 PM UTC 24 | Oct 14 10:25:56 PM UTC 24 | 139699959 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1565525066 | Oct 14 10:25:52 PM UTC 24 | Oct 14 10:25:56 PM UTC 24 | 270334526 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3424619716 | Oct 14 10:25:46 PM UTC 24 | Oct 14 10:25:57 PM UTC 24 | 2305206985 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2822975614 | Oct 14 10:25:55 PM UTC 24 | Oct 14 10:25:57 PM UTC 24 | 54984296 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1529783531 | Oct 14 10:25:55 PM UTC 24 | Oct 14 10:25:58 PM UTC 24 | 133657611 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.847937677 | Oct 14 10:25:55 PM UTC 24 | Oct 14 10:25:58 PM UTC 24 | 115905882 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.846058343 | Oct 14 10:25:55 PM UTC 24 | Oct 14 10:25:58 PM UTC 24 | 168239957 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1430552346 | Oct 14 10:25:54 PM UTC 24 | Oct 14 10:25:58 PM UTC 24 | 878199432 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1368398267 | Oct 14 10:25:56 PM UTC 24 | Oct 14 10:25:59 PM UTC 24 | 91791150 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4072176573 | Oct 14 10:25:55 PM UTC 24 | Oct 14 10:25:59 PM UTC 24 | 480542044 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.385704572 | Oct 14 10:25:56 PM UTC 24 | Oct 14 10:25:59 PM UTC 24 | 112274838 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2303044389 | Oct 14 10:25:56 PM UTC 24 | Oct 14 10:25:59 PM UTC 24 | 77900591 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3745370072 | Oct 14 10:25:56 PM UTC 24 | Oct 14 10:25:59 PM UTC 24 | 200789406 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1276182308 | Oct 14 10:25:56 PM UTC 24 | Oct 14 10:26:00 PM UTC 24 | 523574881 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.798903584 | Oct 14 10:25:58 PM UTC 24 | Oct 14 10:26:00 PM UTC 24 | 92440015 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1254559722 | Oct 14 10:25:58 PM UTC 24 | Oct 14 10:26:00 PM UTC 24 | 78081047 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3089058585 | Oct 14 10:25:58 PM UTC 24 | Oct 14 10:26:01 PM UTC 24 | 98399796 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.1344807622 | Oct 14 10:25:56 PM UTC 24 | Oct 14 10:26:01 PM UTC 24 | 441406381 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.3888193868 | Oct 14 10:25:59 PM UTC 24 | Oct 14 10:26:01 PM UTC 24 | 75492313 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2752511620 | Oct 14 10:25:59 PM UTC 24 | Oct 14 10:26:02 PM UTC 24 | 117992184 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3428346313 | Oct 14 10:25:59 PM UTC 24 | Oct 14 10:26:02 PM UTC 24 | 77701721 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.740612402 | Oct 14 10:26:01 PM UTC 24 | Oct 14 10:26:04 PM UTC 24 | 65445696 ps | ||
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| T573 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.4269179057 | Oct 14 10:26:00 PM UTC 24 | Oct 14 10:26:02 PM UTC 24 | 68116082 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.153681480 | Oct 14 10:26:00 PM UTC 24 | Oct 14 10:26:02 PM UTC 24 | 128155763 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.2002378874 | Oct 14 10:25:59 PM UTC 24 | Oct 14 10:26:03 PM UTC 24 | 147779225 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2328841314 | Oct 14 10:25:58 PM UTC 24 | Oct 14 10:26:03 PM UTC 24 | 897129189 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2150147446 | Oct 14 10:26:04 PM UTC 24 | Oct 14 10:26:07 PM UTC 24 | 75730627 ps | ||
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| T581 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.1585992059 | Oct 14 10:26:02 PM UTC 24 | Oct 14 10:26:04 PM UTC 24 | 92772379 ps | ||
| T582 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.227691905 | Oct 14 10:25:51 PM UTC 24 | Oct 14 10:26:04 PM UTC 24 | 2310597235 ps | ||
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| T587 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4124965447 | Oct 14 10:26:03 PM UTC 24 | Oct 14 10:26:06 PM UTC 24 | 77071539 ps | ||
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| T589 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2415787723 | Oct 14 10:26:03 PM UTC 24 | Oct 14 10:26:06 PM UTC 24 | 180248365 ps | ||
| T590 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.761112302 | Oct 14 10:26:04 PM UTC 24 | Oct 14 10:26:07 PM UTC 24 | 85528276 ps | ||
| T591 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.4068571383 | Oct 14 10:26:04 PM UTC 24 | Oct 14 10:26:08 PM UTC 24 | 223451104 ps | ||
| T592 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4221994470 | Oct 14 10:26:04 PM UTC 24 | Oct 14 10:26:08 PM UTC 24 | 174234850 ps | ||
| T593 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.2951492606 | Oct 14 10:26:05 PM UTC 24 | Oct 14 10:26:08 PM UTC 24 | 64407626 ps | ||
| T594 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.1681470742 | Oct 14 10:26:06 PM UTC 24 | Oct 14 10:26:08 PM UTC 24 | 54497312 ps | ||
| T595 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4254618007 | Oct 14 10:26:05 PM UTC 24 | Oct 14 10:26:08 PM UTC 24 | 106317129 ps | ||
| T596 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.205056906 | Oct 14 10:26:05 PM UTC 24 | Oct 14 10:26:08 PM UTC 24 | 193573281 ps | ||
| T597 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3058315758 | Oct 14 10:26:03 PM UTC 24 | Oct 14 10:26:09 PM UTC 24 | 900955029 ps | ||
| T598 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.237422284 | Oct 14 10:26:07 PM UTC 24 | Oct 14 10:26:09 PM UTC 24 | 77371612 ps | ||
| T599 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.216370886 | Oct 14 10:26:05 PM UTC 24 | Oct 14 10:26:09 PM UTC 24 | 506793480 ps | ||
| T600 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1652167448 | Oct 14 10:26:07 PM UTC 24 | Oct 14 10:26:09 PM UTC 24 | 172826210 ps | ||
| T601 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1819606614 | Oct 14 10:26:07 PM UTC 24 | Oct 14 10:26:09 PM UTC 24 | 158662222 ps | ||
| T602 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.669914088 | Oct 14 10:26:05 PM UTC 24 | Oct 14 10:26:09 PM UTC 24 | 479243190 ps | ||
| T603 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4258850044 | Oct 14 10:26:07 PM UTC 24 | Oct 14 10:26:10 PM UTC 24 | 210826744 ps | ||
| T604 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.1445791887 | Oct 14 10:26:05 PM UTC 24 | Oct 14 10:26:10 PM UTC 24 | 320862534 ps | ||
| T605 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.4126751874 | Oct 14 10:26:08 PM UTC 24 | Oct 14 10:26:10 PM UTC 24 | 76284037 ps | ||
| T606 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.3650266827 | Oct 14 10:26:07 PM UTC 24 | Oct 14 10:26:10 PM UTC 24 | 142699092 ps | ||
| T607 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.3456074635 | Oct 14 10:26:08 PM UTC 24 | Oct 14 10:26:11 PM UTC 24 | 98571383 ps | ||
| T608 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.871950519 | Oct 14 10:26:08 PM UTC 24 | Oct 14 10:26:11 PM UTC 24 | 145111010 ps | ||
| T609 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.4060918761 | Oct 14 10:26:08 PM UTC 24 | Oct 14 10:26:11 PM UTC 24 | 108365668 ps | ||
| T610 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.38610817 | Oct 14 10:26:08 PM UTC 24 | Oct 14 10:26:11 PM UTC 24 | 174192948 ps | ||
| T611 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3167756214 | Oct 14 10:26:07 PM UTC 24 | Oct 14 10:26:11 PM UTC 24 | 827910603 ps | ||
| T612 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1088394952 | Oct 14 10:26:10 PM UTC 24 | Oct 14 10:26:12 PM UTC 24 | 82564730 ps | ||
| T613 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3593257086 | Oct 14 10:26:09 PM UTC 24 | Oct 14 10:26:12 PM UTC 24 | 66995017 ps | ||
| T614 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3224992146 | Oct 14 10:26:09 PM UTC 24 | Oct 14 10:26:12 PM UTC 24 | 170124241 ps | ||
| T615 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3572053114 | Oct 14 10:26:10 PM UTC 24 | Oct 14 10:26:12 PM UTC 24 | 98898637 ps | ||
| T616 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3371908983 | Oct 14 10:26:10 PM UTC 24 | Oct 14 10:26:12 PM UTC 24 | 183403518 ps | ||
| T617 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.609708012 | Oct 14 10:26:09 PM UTC 24 | Oct 14 10:26:12 PM UTC 24 | 111537517 ps | ||
| T618 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1799434065 | Oct 14 10:26:08 PM UTC 24 | Oct 14 10:26:12 PM UTC 24 | 990160958 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1609924512 | Oct 14 10:26:10 PM UTC 24 | Oct 14 10:26:13 PM UTC 24 | 474585843 ps | ||
| T619 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2741493077 | Oct 14 10:26:08 PM UTC 24 | Oct 14 10:26:13 PM UTC 24 | 440167364 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.458359824 | Oct 14 10:26:09 PM UTC 24 | Oct 14 10:26:14 PM UTC 24 | 801198935 ps | ||
| T620 | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.3784295605 | Oct 14 10:26:09 PM UTC 24 | Oct 14 10:26:14 PM UTC 24 | 440868924 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.1031881421 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 129818024 ps |
| CPU time | 1.6 seconds |
| Started | Oct 14 11:44:37 PM UTC 24 |
| Finished | Oct 14 11:44:40 PM UTC 24 |
| Peak memory | 209904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031881421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1031881421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.3639127184 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 409948622 ps |
| CPU time | 3.12 seconds |
| Started | Oct 14 11:44:38 PM UTC 24 |
| Finished | Oct 14 11:44:43 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639127184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3639127184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.126353706 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1960459011 ps |
| CPU time | 9.52 seconds |
| Started | Oct 14 11:44:38 PM UTC 24 |
| Finished | Oct 14 11:44:49 PM UTC 24 |
| Peak memory | 244208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126353706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.126353706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3049455764 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 404700372 ps |
| CPU time | 2.06 seconds |
| Started | Oct 14 10:25:29 PM UTC 24 |
| Finished | Oct 14 10:25:32 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049455764 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.3049455764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.2916132365 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8406349879 ps |
| CPU time | 15.82 seconds |
| Started | Oct 14 11:44:36 PM UTC 24 |
| Finished | Oct 14 11:44:53 PM UTC 24 |
| Peak memory | 243468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916132365 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2916132365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.3514576855 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 410117912 ps |
| CPU time | 4.21 seconds |
| Started | Oct 14 10:25:38 PM UTC 24 |
| Finished | Oct 14 10:25:43 PM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514576855 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3514576855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.632905775 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4732946746 ps |
| CPU time | 15.6 seconds |
| Started | Oct 14 11:44:36 PM UTC 24 |
| Finished | Oct 14 11:44:52 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632905775 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.632905775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.1027777379 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1697166610 ps |
| CPU time | 8.33 seconds |
| Started | Oct 14 11:44:37 PM UTC 24 |
| Finished | Oct 14 11:44:47 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027777379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1027777379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.2003850909 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 368034893 ps |
| CPU time | 1.75 seconds |
| Started | Oct 14 11:44:36 PM UTC 24 |
| Finished | Oct 14 11:44:39 PM UTC 24 |
| Peak memory | 209912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003850909 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2003850909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2683657936 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 103746195 ps |
| CPU time | 1.44 seconds |
| Started | Oct 14 11:45:06 PM UTC 24 |
| Finished | Oct 14 11:45:08 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683657936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2683657936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1493531079 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 197868948 ps |
| CPU time | 1.82 seconds |
| Started | Oct 14 11:44:38 PM UTC 24 |
| Finished | Oct 14 11:44:41 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493531079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1493531079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.1383734081 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1269540017 ps |
| CPU time | 7.72 seconds |
| Started | Oct 14 11:45:02 PM UTC 24 |
| Finished | Oct 14 11:45:11 PM UTC 24 |
| Peak memory | 243356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383734081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1383734081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1430552346 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 878199432 ps |
| CPU time | 3.59 seconds |
| Started | Oct 14 10:25:54 PM UTC 24 |
| Finished | Oct 14 10:25:58 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430552346 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.1430552346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.2639082206 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1283576765 ps |
| CPU time | 5.54 seconds |
| Started | Oct 14 11:45:51 PM UTC 24 |
| Finished | Oct 14 11:45:57 PM UTC 24 |
| Peak memory | 244152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639082206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2639082206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.290396814 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 237415421 ps |
| CPU time | 2.65 seconds |
| Started | Oct 14 10:25:25 PM UTC 24 |
| Finished | Oct 14 10:25:28 PM UTC 24 |
| Peak memory | 217812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290396814 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.290396814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.458359824 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 801198935 ps |
| CPU time | 3.26 seconds |
| Started | Oct 14 10:26:09 PM UTC 24 |
| Finished | Oct 14 10:26:14 PM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458359824 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.458359824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.2233039209 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 63358717 ps |
| CPU time | 1.11 seconds |
| Started | Oct 14 10:25:32 PM UTC 24 |
| Finished | Oct 14 10:25:34 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233039209 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2233039209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.3871682950 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 151993557 ps |
| CPU time | 1.31 seconds |
| Started | Oct 14 11:44:31 PM UTC 24 |
| Finished | Oct 14 11:44:33 PM UTC 24 |
| Peak memory | 209648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871682950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3871682950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.36437208 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 301608761 ps |
| CPU time | 1.45 seconds |
| Started | Oct 14 11:44:35 PM UTC 24 |
| Finished | Oct 14 11:44:37 PM UTC 24 |
| Peak memory | 238776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36437208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.36437208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2661513914 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 950613564 ps |
| CPU time | 3.35 seconds |
| Started | Oct 14 10:26:02 PM UTC 24 |
| Finished | Oct 14 10:26:06 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661513914 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.2661513914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1609924512 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 474585843 ps |
| CPU time | 1.95 seconds |
| Started | Oct 14 10:26:10 PM UTC 24 |
| Finished | Oct 14 10:26:13 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609924512 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.1609924512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.2256378765 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 4675326121 ps |
| CPU time | 20.5 seconds |
| Started | Oct 14 11:45:22 PM UTC 24 |
| Finished | Oct 14 11:45:43 PM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256378765 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2256378765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2583481459 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 114199223 ps |
| CPU time | 1.95 seconds |
| Started | Oct 14 10:25:34 PM UTC 24 |
| Finished | Oct 14 10:25:37 PM UTC 24 |
| Peak memory | 207868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583481459 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2583481459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2102983246 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2286886549 ps |
| CPU time | 15.85 seconds |
| Started | Oct 14 10:25:33 PM UTC 24 |
| Finished | Oct 14 10:25:50 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102983246 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2102983246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2262247634 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 104535061 ps |
| CPU time | 1.29 seconds |
| Started | Oct 14 10:25:31 PM UTC 24 |
| Finished | Oct 14 10:25:33 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262247634 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2262247634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.865074969 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 121359794 ps |
| CPU time | 1.76 seconds |
| Started | Oct 14 10:25:35 PM UTC 24 |
| Finished | Oct 14 10:25:38 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=865074969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_wi th_rand_reset.865074969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2029486621 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 209998870 ps |
| CPU time | 2.06 seconds |
| Started | Oct 14 10:25:34 PM UTC 24 |
| Finished | Oct 14 10:25:37 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029486621 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.2029486621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.366565219 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 205941488 ps |
| CPU time | 2.2 seconds |
| Started | Oct 14 10:25:40 PM UTC 24 |
| Finished | Oct 14 10:25:43 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366565219 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.366565219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.814822478 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 808375533 ps |
| CPU time | 6.12 seconds |
| Started | Oct 14 10:25:38 PM UTC 24 |
| Finished | Oct 14 10:25:46 PM UTC 24 |
| Peak memory | 208656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814822478 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.814822478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2100189676 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 98362220 ps |
| CPU time | 1.4 seconds |
| Started | Oct 14 10:25:38 PM UTC 24 |
| Finished | Oct 14 10:25:41 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100189676 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2100189676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4056927824 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 189150261 ps |
| CPU time | 2.01 seconds |
| Started | Oct 14 10:25:42 PM UTC 24 |
| Finished | Oct 14 10:25:45 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4056927824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w ith_rand_reset.4056927824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2828182276 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 58780169 ps |
| CPU time | 1.18 seconds |
| Started | Oct 14 10:25:38 PM UTC 24 |
| Finished | Oct 14 10:25:41 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828182276 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2828182276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3463722619 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 70274014 ps |
| CPU time | 1.28 seconds |
| Started | Oct 14 10:25:42 PM UTC 24 |
| Finished | Oct 14 10:25:44 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463722619 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.3463722619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3688690723 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1169624028 ps |
| CPU time | 5.34 seconds |
| Started | Oct 14 10:25:38 PM UTC 24 |
| Finished | Oct 14 10:25:45 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688690723 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.3688690723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1351815373 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 223398977 ps |
| CPU time | 1.74 seconds |
| Started | Oct 14 10:26:00 PM UTC 24 |
| Finished | Oct 14 10:26:03 PM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1351815373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_ with_rand_reset.1351815373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.4269179057 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 68116082 ps |
| CPU time | 1.03 seconds |
| Started | Oct 14 10:26:00 PM UTC 24 |
| Finished | Oct 14 10:26:02 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269179057 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4269179057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.153681480 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 128155763 ps |
| CPU time | 1.25 seconds |
| Started | Oct 14 10:26:00 PM UTC 24 |
| Finished | Oct 14 10:26:02 PM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153681480 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.153681480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.2282845269 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 284697512 ps |
| CPU time | 3.14 seconds |
| Started | Oct 14 10:26:00 PM UTC 24 |
| Finished | Oct 14 10:26:04 PM UTC 24 |
| Peak memory | 208948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282845269 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2282845269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3763038007 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 432615948 ps |
| CPU time | 2.69 seconds |
| Started | Oct 14 10:26:00 PM UTC 24 |
| Finished | Oct 14 10:26:04 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763038007 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.3763038007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3749656397 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 179621622 ps |
| CPU time | 1.73 seconds |
| Started | Oct 14 10:26:02 PM UTC 24 |
| Finished | Oct 14 10:26:04 PM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3749656397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_ with_rand_reset.3749656397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.740612402 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 65445696 ps |
| CPU time | 1.07 seconds |
| Started | Oct 14 10:26:01 PM UTC 24 |
| Finished | Oct 14 10:26:04 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740612402 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.740612402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2958385899 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 123403427 ps |
| CPU time | 1.36 seconds |
| Started | Oct 14 10:26:01 PM UTC 24 |
| Finished | Oct 14 10:26:04 PM UTC 24 |
| Peak memory | 217368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958385899 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.2958385899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.1318444466 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 141081156 ps |
| CPU time | 2.67 seconds |
| Started | Oct 14 10:26:01 PM UTC 24 |
| Finished | Oct 14 10:26:05 PM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318444466 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1318444466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.306581930 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 943876996 ps |
| CPU time | 4.01 seconds |
| Started | Oct 14 10:26:01 PM UTC 24 |
| Finished | Oct 14 10:26:06 PM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306581930 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.306581930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2415787723 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 180248365 ps |
| CPU time | 1.8 seconds |
| Started | Oct 14 10:26:03 PM UTC 24 |
| Finished | Oct 14 10:26:06 PM UTC 24 |
| Peak memory | 217484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2415787723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_ with_rand_reset.2415787723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.130683852 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 66201899 ps |
| CPU time | 0.9 seconds |
| Started | Oct 14 10:26:03 PM UTC 24 |
| Finished | Oct 14 10:26:05 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130683852 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.130683852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4124965447 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 77071539 ps |
| CPU time | 1.46 seconds |
| Started | Oct 14 10:26:03 PM UTC 24 |
| Finished | Oct 14 10:26:06 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124965447 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.4124965447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.1585992059 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 92772379 ps |
| CPU time | 1.48 seconds |
| Started | Oct 14 10:26:02 PM UTC 24 |
| Finished | Oct 14 10:26:04 PM UTC 24 |
| Peak memory | 217488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585992059 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1585992059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4221994470 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 174234850 ps |
| CPU time | 1.78 seconds |
| Started | Oct 14 10:26:04 PM UTC 24 |
| Finished | Oct 14 10:26:08 PM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4221994470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_ with_rand_reset.4221994470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2150147446 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 75730627 ps |
| CPU time | 1.24 seconds |
| Started | Oct 14 10:26:04 PM UTC 24 |
| Finished | Oct 14 10:26:07 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150147446 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2150147446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.761112302 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 85528276 ps |
| CPU time | 1.16 seconds |
| Started | Oct 14 10:26:04 PM UTC 24 |
| Finished | Oct 14 10:26:07 PM UTC 24 |
| Peak memory | 207812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761112302 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.761112302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.1611113251 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 138908691 ps |
| CPU time | 1.78 seconds |
| Started | Oct 14 10:26:03 PM UTC 24 |
| Finished | Oct 14 10:26:06 PM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611113251 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1611113251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3058315758 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 900955029 ps |
| CPU time | 3.93 seconds |
| Started | Oct 14 10:26:03 PM UTC 24 |
| Finished | Oct 14 10:26:09 PM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058315758 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.3058315758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.205056906 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 193573281 ps |
| CPU time | 1.43 seconds |
| Started | Oct 14 10:26:05 PM UTC 24 |
| Finished | Oct 14 10:26:08 PM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=205056906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_w ith_rand_reset.205056906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.2951492606 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 64407626 ps |
| CPU time | 0.92 seconds |
| Started | Oct 14 10:26:05 PM UTC 24 |
| Finished | Oct 14 10:26:08 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951492606 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2951492606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4254618007 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 106317129 ps |
| CPU time | 1.33 seconds |
| Started | Oct 14 10:26:05 PM UTC 24 |
| Finished | Oct 14 10:26:08 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254618007 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.4254618007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.4068571383 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 223451104 ps |
| CPU time | 1.66 seconds |
| Started | Oct 14 10:26:04 PM UTC 24 |
| Finished | Oct 14 10:26:08 PM UTC 24 |
| Peak memory | 219452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068571383 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4068571383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.216370886 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 506793480 ps |
| CPU time | 2.19 seconds |
| Started | Oct 14 10:26:05 PM UTC 24 |
| Finished | Oct 14 10:26:09 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216370886 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.216370886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1652167448 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 172826210 ps |
| CPU time | 1.17 seconds |
| Started | Oct 14 10:26:07 PM UTC 24 |
| Finished | Oct 14 10:26:09 PM UTC 24 |
| Peak memory | 219456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1652167448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_ with_rand_reset.1652167448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.1681470742 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 54497312 ps |
| CPU time | 0.87 seconds |
| Started | Oct 14 10:26:06 PM UTC 24 |
| Finished | Oct 14 10:26:08 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681470742 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1681470742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4258850044 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 210826744 ps |
| CPU time | 1.71 seconds |
| Started | Oct 14 10:26:07 PM UTC 24 |
| Finished | Oct 14 10:26:10 PM UTC 24 |
| Peak memory | 207868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258850044 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.4258850044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.1445791887 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 320862534 ps |
| CPU time | 2.91 seconds |
| Started | Oct 14 10:26:05 PM UTC 24 |
| Finished | Oct 14 10:26:10 PM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445791887 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1445791887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.669914088 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 479243190 ps |
| CPU time | 2.63 seconds |
| Started | Oct 14 10:26:05 PM UTC 24 |
| Finished | Oct 14 10:26:09 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669914088 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.669914088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.871950519 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 145111010 ps |
| CPU time | 1.5 seconds |
| Started | Oct 14 10:26:08 PM UTC 24 |
| Finished | Oct 14 10:26:11 PM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=871950519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_w ith_rand_reset.871950519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.237422284 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 77371612 ps |
| CPU time | 0.9 seconds |
| Started | Oct 14 10:26:07 PM UTC 24 |
| Finished | Oct 14 10:26:09 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237422284 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.237422284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1819606614 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 158662222 ps |
| CPU time | 1.16 seconds |
| Started | Oct 14 10:26:07 PM UTC 24 |
| Finished | Oct 14 10:26:09 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819606614 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.1819606614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.3650266827 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 142699092 ps |
| CPU time | 2.39 seconds |
| Started | Oct 14 10:26:07 PM UTC 24 |
| Finished | Oct 14 10:26:10 PM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650266827 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3650266827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3167756214 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 827910603 ps |
| CPU time | 2.76 seconds |
| Started | Oct 14 10:26:07 PM UTC 24 |
| Finished | Oct 14 10:26:11 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167756214 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.3167756214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.38610817 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 174192948 ps |
| CPU time | 1.45 seconds |
| Started | Oct 14 10:26:08 PM UTC 24 |
| Finished | Oct 14 10:26:11 PM UTC 24 |
| Peak memory | 217420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=38610817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_wi th_rand_reset.38610817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.4126751874 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 76284037 ps |
| CPU time | 1.12 seconds |
| Started | Oct 14 10:26:08 PM UTC 24 |
| Finished | Oct 14 10:26:10 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126751874 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.4126751874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.4060918761 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 108365668 ps |
| CPU time | 1.35 seconds |
| Started | Oct 14 10:26:08 PM UTC 24 |
| Finished | Oct 14 10:26:11 PM UTC 24 |
| Peak memory | 207868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060918761 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.4060918761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.3456074635 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 98571383 ps |
| CPU time | 1.3 seconds |
| Started | Oct 14 10:26:08 PM UTC 24 |
| Finished | Oct 14 10:26:11 PM UTC 24 |
| Peak memory | 207924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456074635 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3456074635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1799434065 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 990160958 ps |
| CPU time | 3.23 seconds |
| Started | Oct 14 10:26:08 PM UTC 24 |
| Finished | Oct 14 10:26:12 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799434065 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.1799434065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3224992146 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 170124241 ps |
| CPU time | 1.27 seconds |
| Started | Oct 14 10:26:09 PM UTC 24 |
| Finished | Oct 14 10:26:12 PM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3224992146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_ with_rand_reset.3224992146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3593257086 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 66995017 ps |
| CPU time | 1.12 seconds |
| Started | Oct 14 10:26:09 PM UTC 24 |
| Finished | Oct 14 10:26:12 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593257086 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3593257086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.609708012 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 111537517 ps |
| CPU time | 1.63 seconds |
| Started | Oct 14 10:26:09 PM UTC 24 |
| Finished | Oct 14 10:26:12 PM UTC 24 |
| Peak memory | 207864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609708012 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.609708012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2741493077 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 440167364 ps |
| CPU time | 3.5 seconds |
| Started | Oct 14 10:26:08 PM UTC 24 |
| Finished | Oct 14 10:26:13 PM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741493077 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2741493077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3371908983 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 183403518 ps |
| CPU time | 1.42 seconds |
| Started | Oct 14 10:26:10 PM UTC 24 |
| Finished | Oct 14 10:26:12 PM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3371908983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_ with_rand_reset.3371908983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1088394952 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 82564730 ps |
| CPU time | 1.03 seconds |
| Started | Oct 14 10:26:10 PM UTC 24 |
| Finished | Oct 14 10:26:12 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088394952 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1088394952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3572053114 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 98898637 ps |
| CPU time | 1.31 seconds |
| Started | Oct 14 10:26:10 PM UTC 24 |
| Finished | Oct 14 10:26:12 PM UTC 24 |
| Peak memory | 207864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572053114 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.3572053114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.3784295605 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 440868924 ps |
| CPU time | 3.33 seconds |
| Started | Oct 14 10:26:09 PM UTC 24 |
| Finished | Oct 14 10:26:14 PM UTC 24 |
| Peak memory | 221828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784295605 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3784295605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2500791626 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 353358066 ps |
| CPU time | 3.43 seconds |
| Started | Oct 14 10:25:46 PM UTC 24 |
| Finished | Oct 14 10:25:51 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500791626 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2500791626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3424619716 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 2305206985 ps |
| CPU time | 9.76 seconds |
| Started | Oct 14 10:25:46 PM UTC 24 |
| Finished | Oct 14 10:25:57 PM UTC 24 |
| Peak memory | 209044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424619716 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3424619716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3353598461 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 121443367 ps |
| CPU time | 1.41 seconds |
| Started | Oct 14 10:25:45 PM UTC 24 |
| Finished | Oct 14 10:25:47 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353598461 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3353598461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2354244507 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 178565760 ps |
| CPU time | 2.45 seconds |
| Started | Oct 14 10:25:46 PM UTC 24 |
| Finished | Oct 14 10:25:50 PM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2354244507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_w ith_rand_reset.2354244507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.2996470827 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 65564263 ps |
| CPU time | 1.16 seconds |
| Started | Oct 14 10:25:46 PM UTC 24 |
| Finished | Oct 14 10:25:48 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996470827 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2996470827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1139235184 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 109323062 ps |
| CPU time | 1.9 seconds |
| Started | Oct 14 10:25:46 PM UTC 24 |
| Finished | Oct 14 10:25:49 PM UTC 24 |
| Peak memory | 207804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139235184 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.1139235184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.1628597240 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 94445184 ps |
| CPU time | 1.94 seconds |
| Started | Oct 14 10:25:44 PM UTC 24 |
| Finished | Oct 14 10:25:47 PM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628597240 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1628597240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.25836522 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 908792797 ps |
| CPU time | 4.5 seconds |
| Started | Oct 14 10:25:45 PM UTC 24 |
| Finished | Oct 14 10:25:50 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25836522 -assert nopostproc +UVM_TESTNAM E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.25836522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.330013981 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 236575065 ps |
| CPU time | 2.44 seconds |
| Started | Oct 14 10:25:50 PM UTC 24 |
| Finished | Oct 14 10:25:53 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330013981 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.330013981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1823031526 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 800208100 ps |
| CPU time | 4.81 seconds |
| Started | Oct 14 10:25:50 PM UTC 24 |
| Finished | Oct 14 10:25:56 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823031526 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1823031526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3043240862 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 147564442 ps |
| CPU time | 1.55 seconds |
| Started | Oct 14 10:25:48 PM UTC 24 |
| Finished | Oct 14 10:25:51 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043240862 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3043240862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1916422262 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 112315731 ps |
| CPU time | 1.77 seconds |
| Started | Oct 14 10:25:50 PM UTC 24 |
| Finished | Oct 14 10:25:53 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1916422262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_w ith_rand_reset.1916422262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.3562161953 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 73486258 ps |
| CPU time | 1.22 seconds |
| Started | Oct 14 10:25:50 PM UTC 24 |
| Finished | Oct 14 10:25:52 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562161953 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3562161953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.877518177 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 120324400 ps |
| CPU time | 1.54 seconds |
| Started | Oct 14 10:25:50 PM UTC 24 |
| Finished | Oct 14 10:25:52 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877518177 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.877518177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.1628983788 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 375418249 ps |
| CPU time | 2.97 seconds |
| Started | Oct 14 10:25:47 PM UTC 24 |
| Finished | Oct 14 10:25:51 PM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628983788 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1628983788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1175439712 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 928749965 ps |
| CPU time | 4.84 seconds |
| Started | Oct 14 10:25:48 PM UTC 24 |
| Finished | Oct 14 10:25:54 PM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175439712 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.1175439712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2959702576 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 203405633 ps |
| CPU time | 2.3 seconds |
| Started | Oct 14 10:25:52 PM UTC 24 |
| Finished | Oct 14 10:25:56 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959702576 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2959702576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.227691905 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2310597235 ps |
| CPU time | 11.83 seconds |
| Started | Oct 14 10:25:51 PM UTC 24 |
| Finished | Oct 14 10:26:04 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227691905 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.227691905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4159761368 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 106410118 ps |
| CPU time | 1.35 seconds |
| Started | Oct 14 10:25:51 PM UTC 24 |
| Finished | Oct 14 10:25:53 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159761368 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.4159761368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3198921577 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 143037535 ps |
| CPU time | 1.47 seconds |
| Started | Oct 14 10:25:52 PM UTC 24 |
| Finished | Oct 14 10:25:55 PM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3198921577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_w ith_rand_reset.3198921577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.2547638675 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 86156142 ps |
| CPU time | 1.3 seconds |
| Started | Oct 14 10:25:51 PM UTC 24 |
| Finished | Oct 14 10:25:53 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547638675 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2547638675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.723423084 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 215205300 ps |
| CPU time | 2.23 seconds |
| Started | Oct 14 10:25:52 PM UTC 24 |
| Finished | Oct 14 10:25:56 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723423084 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.723423084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.492790589 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 284541086 ps |
| CPU time | 2.45 seconds |
| Started | Oct 14 10:25:51 PM UTC 24 |
| Finished | Oct 14 10:25:54 PM UTC 24 |
| Peak memory | 217928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492790589 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.492790589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3314714848 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 936620399 ps |
| CPU time | 3.47 seconds |
| Started | Oct 14 10:25:51 PM UTC 24 |
| Finished | Oct 14 10:25:56 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314714848 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.3314714848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.846058343 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 168239957 ps |
| CPU time | 2.08 seconds |
| Started | Oct 14 10:25:55 PM UTC 24 |
| Finished | Oct 14 10:25:58 PM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=846058343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_wi th_rand_reset.846058343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.1228664387 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 63411967 ps |
| CPU time | 0.95 seconds |
| Started | Oct 14 10:25:54 PM UTC 24 |
| Finished | Oct 14 10:25:56 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228664387 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1228664387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.708932743 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 139699959 ps |
| CPU time | 1.24 seconds |
| Started | Oct 14 10:25:54 PM UTC 24 |
| Finished | Oct 14 10:25:56 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708932743 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.708932743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1565525066 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 270334526 ps |
| CPU time | 2.66 seconds |
| Started | Oct 14 10:25:52 PM UTC 24 |
| Finished | Oct 14 10:25:56 PM UTC 24 |
| Peak memory | 217948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565525066 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1565525066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3745370072 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 200789406 ps |
| CPU time | 1.53 seconds |
| Started | Oct 14 10:25:56 PM UTC 24 |
| Finished | Oct 14 10:25:59 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3745370072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w ith_rand_reset.3745370072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2822975614 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 54984296 ps |
| CPU time | 1.15 seconds |
| Started | Oct 14 10:25:55 PM UTC 24 |
| Finished | Oct 14 10:25:57 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822975614 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2822975614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1529783531 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 133657611 ps |
| CPU time | 1.57 seconds |
| Started | Oct 14 10:25:55 PM UTC 24 |
| Finished | Oct 14 10:25:58 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529783531 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.1529783531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.847937677 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 115905882 ps |
| CPU time | 1.9 seconds |
| Started | Oct 14 10:25:55 PM UTC 24 |
| Finished | Oct 14 10:25:58 PM UTC 24 |
| Peak memory | 217416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847937677 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.847937677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4072176573 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 480542044 ps |
| CPU time | 2.68 seconds |
| Started | Oct 14 10:25:55 PM UTC 24 |
| Finished | Oct 14 10:25:59 PM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072176573 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.4072176573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.385704572 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 112274838 ps |
| CPU time | 1.28 seconds |
| Started | Oct 14 10:25:56 PM UTC 24 |
| Finished | Oct 14 10:25:59 PM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=385704572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_wi th_rand_reset.385704572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1368398267 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 91791150 ps |
| CPU time | 1.38 seconds |
| Started | Oct 14 10:25:56 PM UTC 24 |
| Finished | Oct 14 10:25:59 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368398267 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1368398267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2303044389 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 77900591 ps |
| CPU time | 1.43 seconds |
| Started | Oct 14 10:25:56 PM UTC 24 |
| Finished | Oct 14 10:25:59 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303044389 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.2303044389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.1344807622 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 441406381 ps |
| CPU time | 3.47 seconds |
| Started | Oct 14 10:25:56 PM UTC 24 |
| Finished | Oct 14 10:26:01 PM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344807622 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1344807622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1276182308 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 523574881 ps |
| CPU time | 2.6 seconds |
| Started | Oct 14 10:25:56 PM UTC 24 |
| Finished | Oct 14 10:26:00 PM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276182308 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.1276182308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3089058585 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 98399796 ps |
| CPU time | 1.51 seconds |
| Started | Oct 14 10:25:58 PM UTC 24 |
| Finished | Oct 14 10:26:01 PM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3089058585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_w ith_rand_reset.3089058585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.798903584 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 92440015 ps |
| CPU time | 1.29 seconds |
| Started | Oct 14 10:25:58 PM UTC 24 |
| Finished | Oct 14 10:26:00 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798903584 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.798903584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1254559722 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 78081047 ps |
| CPU time | 1.28 seconds |
| Started | Oct 14 10:25:58 PM UTC 24 |
| Finished | Oct 14 10:26:00 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254559722 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.1254559722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.3666681493 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 453285570 ps |
| CPU time | 2.95 seconds |
| Started | Oct 14 10:25:57 PM UTC 24 |
| Finished | Oct 14 10:26:02 PM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666681493 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3666681493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2328841314 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 897129189 ps |
| CPU time | 4.08 seconds |
| Started | Oct 14 10:25:58 PM UTC 24 |
| Finished | Oct 14 10:26:03 PM UTC 24 |
| Peak memory | 208588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328841314 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.2328841314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2752511620 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 117992184 ps |
| CPU time | 1.32 seconds |
| Started | Oct 14 10:25:59 PM UTC 24 |
| Finished | Oct 14 10:26:02 PM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2752511620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_w ith_rand_reset.2752511620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.3888193868 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 75492313 ps |
| CPU time | 0.79 seconds |
| Started | Oct 14 10:25:59 PM UTC 24 |
| Finished | Oct 14 10:26:01 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888193868 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3888193868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3428346313 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 77701721 ps |
| CPU time | 1.42 seconds |
| Started | Oct 14 10:25:59 PM UTC 24 |
| Finished | Oct 14 10:26:02 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428346313 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.3428346313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.2002378874 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 147779225 ps |
| CPU time | 2.26 seconds |
| Started | Oct 14 10:25:59 PM UTC 24 |
| Finished | Oct 14 10:26:03 PM UTC 24 |
| Peak memory | 217772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002378874 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2002378874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2559333775 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 881617397 ps |
| CPU time | 4.41 seconds |
| Started | Oct 14 10:25:59 PM UTC 24 |
| Finished | Oct 14 10:26:05 PM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559333775 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.2559333775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.3653303256 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1263364711 ps |
| CPU time | 6.8 seconds |
| Started | Oct 14 11:44:33 PM UTC 24 |
| Finished | Oct 14 11:44:41 PM UTC 24 |
| Peak memory | 243484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653303256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3653303256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.985186754 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 930338525 ps |
| CPU time | 4.42 seconds |
| Started | Oct 14 11:44:31 PM UTC 24 |
| Finished | Oct 14 11:44:37 PM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985186754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.985186754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2091514972 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 184204022 ps |
| CPU time | 1.77 seconds |
| Started | Oct 14 11:44:33 PM UTC 24 |
| Finished | Oct 14 11:44:36 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091514972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2091514972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.2051093214 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 261152206 ps |
| CPU time | 2.27 seconds |
| Started | Oct 14 11:44:29 PM UTC 24 |
| Finished | Oct 14 11:44:32 PM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051093214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2051093214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.145728940 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 333997458 ps |
| CPU time | 3.14 seconds |
| Started | Oct 14 11:44:33 PM UTC 24 |
| Finished | Oct 14 11:44:38 PM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145728940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.145728940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1216741493 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 203405331 ps |
| CPU time | 1.69 seconds |
| Started | Oct 14 11:44:32 PM UTC 24 |
| Finished | Oct 14 11:44:35 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216741493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1216741493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.843844280 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 59698546 ps |
| CPU time | 1.11 seconds |
| Started | Oct 14 11:44:39 PM UTC 24 |
| Finished | Oct 14 11:44:41 PM UTC 24 |
| Peak memory | 209912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843844280 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.843844280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.4061238880 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 303041702 ps |
| CPU time | 1.31 seconds |
| Started | Oct 14 11:44:38 PM UTC 24 |
| Finished | Oct 14 11:44:41 PM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061238880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.4061238880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.384166582 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 203775524 ps |
| CPU time | 1.2 seconds |
| Started | Oct 14 11:44:37 PM UTC 24 |
| Finished | Oct 14 11:44:39 PM UTC 24 |
| Peak memory | 209668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384166582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.384166582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.4253907060 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8476689318 ps |
| CPU time | 23.53 seconds |
| Started | Oct 14 11:44:39 PM UTC 24 |
| Finished | Oct 14 11:45:03 PM UTC 24 |
| Peak memory | 243548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253907060 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4253907060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.989217882 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 95997948 ps |
| CPU time | 1.41 seconds |
| Started | Oct 14 11:44:38 PM UTC 24 |
| Finished | Oct 14 11:44:41 PM UTC 24 |
| Peak memory | 209720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989217882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.989217882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.118382465 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 5193607594 ps |
| CPU time | 23.67 seconds |
| Started | Oct 14 11:44:39 PM UTC 24 |
| Finished | Oct 14 11:45:03 PM UTC 24 |
| Peak memory | 220148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118382465 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.118382465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/1.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.205139338 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 70822035 ps |
| CPU time | 0.98 seconds |
| Started | Oct 14 11:45:18 PM UTC 24 |
| Finished | Oct 14 11:45:20 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205139338 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.205139338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.3015681300 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1961129298 ps |
| CPU time | 8.22 seconds |
| Started | Oct 14 11:45:18 PM UTC 24 |
| Finished | Oct 14 11:45:28 PM UTC 24 |
| Peak memory | 244264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015681300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3015681300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.4149548264 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 302159536 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 11:45:18 PM UTC 24 |
| Finished | Oct 14 11:45:21 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149548264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.4149548264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.2531109907 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 222330299 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 11:45:16 PM UTC 24 |
| Finished | Oct 14 11:45:18 PM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531109907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2531109907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.2620327973 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1768052189 ps |
| CPU time | 8.34 seconds |
| Started | Oct 14 11:45:16 PM UTC 24 |
| Finished | Oct 14 11:45:25 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620327973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2620327973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3854351326 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 143188615 ps |
| CPU time | 1.19 seconds |
| Started | Oct 14 11:45:17 PM UTC 24 |
| Finished | Oct 14 11:45:19 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854351326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3854351326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.3503778846 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 251366621 ps |
| CPU time | 2.01 seconds |
| Started | Oct 14 11:45:15 PM UTC 24 |
| Finished | Oct 14 11:45:19 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503778846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3503778846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.2825007894 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 4942907677 ps |
| CPU time | 23.7 seconds |
| Started | Oct 14 11:45:18 PM UTC 24 |
| Finished | Oct 14 11:45:43 PM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825007894 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2825007894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.649219806 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 507406044 ps |
| CPU time | 3.3 seconds |
| Started | Oct 14 11:45:17 PM UTC 24 |
| Finished | Oct 14 11:45:21 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649219806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.649219806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.3571217921 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 81650596 ps |
| CPU time | 1.29 seconds |
| Started | Oct 14 11:45:17 PM UTC 24 |
| Finished | Oct 14 11:45:19 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571217921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3571217921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.312844499 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 68900919 ps |
| CPU time | 0.86 seconds |
| Started | Oct 14 11:45:23 PM UTC 24 |
| Finished | Oct 14 11:45:25 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312844499 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.312844499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.1462603162 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1983499031 ps |
| CPU time | 10.71 seconds |
| Started | Oct 14 11:45:22 PM UTC 24 |
| Finished | Oct 14 11:45:33 PM UTC 24 |
| Peak memory | 244252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462603162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1462603162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.63041293 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 301496176 ps |
| CPU time | 2.07 seconds |
| Started | Oct 14 11:45:22 PM UTC 24 |
| Finished | Oct 14 11:45:25 PM UTC 24 |
| Peak memory | 239420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63041293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.63041293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.326463222 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 154743825 ps |
| CPU time | 1.35 seconds |
| Started | Oct 14 11:45:20 PM UTC 24 |
| Finished | Oct 14 11:45:22 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326463222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.326463222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.623264269 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1702416560 ps |
| CPU time | 6.87 seconds |
| Started | Oct 14 11:45:20 PM UTC 24 |
| Finished | Oct 14 11:45:28 PM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623264269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.623264269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.78788327 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 173744170 ps |
| CPU time | 1.78 seconds |
| Started | Oct 14 11:45:21 PM UTC 24 |
| Finished | Oct 14 11:45:24 PM UTC 24 |
| Peak memory | 209724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78788327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstm gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.78788327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.4033012249 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 114407505 ps |
| CPU time | 1.7 seconds |
| Started | Oct 14 11:45:20 PM UTC 24 |
| Finished | Oct 14 11:45:23 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033012249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.4033012249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.2407407450 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 138029224 ps |
| CPU time | 2.59 seconds |
| Started | Oct 14 11:45:20 PM UTC 24 |
| Finished | Oct 14 11:45:24 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407407450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2407407450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.2690237646 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 80195747 ps |
| CPU time | 1.21 seconds |
| Started | Oct 14 11:45:20 PM UTC 24 |
| Finished | Oct 14 11:45:22 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690237646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2690237646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.3589176496 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 77241713 ps |
| CPU time | 1.24 seconds |
| Started | Oct 14 11:45:27 PM UTC 24 |
| Finished | Oct 14 11:45:29 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589176496 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3589176496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.3059486708 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1990752296 ps |
| CPU time | 8.74 seconds |
| Started | Oct 14 11:45:25 PM UTC 24 |
| Finished | Oct 14 11:45:35 PM UTC 24 |
| Peak memory | 243772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059486708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3059486708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.645284130 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 301530485 ps |
| CPU time | 2.16 seconds |
| Started | Oct 14 11:45:25 PM UTC 24 |
| Finished | Oct 14 11:45:28 PM UTC 24 |
| Peak memory | 239456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645284130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.645284130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.152110277 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 176540909 ps |
| CPU time | 1.13 seconds |
| Started | Oct 14 11:45:23 PM UTC 24 |
| Finished | Oct 14 11:45:26 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152110277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.152110277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.3960855462 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 772372687 ps |
| CPU time | 4.65 seconds |
| Started | Oct 14 11:45:24 PM UTC 24 |
| Finished | Oct 14 11:45:29 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960855462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3960855462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3741945519 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 109564708 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 11:45:24 PM UTC 24 |
| Finished | Oct 14 11:45:26 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741945519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3741945519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.1998809013 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 236246741 ps |
| CPU time | 2.22 seconds |
| Started | Oct 14 11:45:23 PM UTC 24 |
| Finished | Oct 14 11:45:27 PM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998809013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1998809013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.581941540 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 4284306847 ps |
| CPU time | 19.11 seconds |
| Started | Oct 14 11:45:27 PM UTC 24 |
| Finished | Oct 14 11:45:47 PM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581941540 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.581941540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.858273883 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 153291187 ps |
| CPU time | 2.3 seconds |
| Started | Oct 14 11:45:24 PM UTC 24 |
| Finished | Oct 14 11:45:27 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858273883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.858273883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.2348506281 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 80359291 ps |
| CPU time | 1.21 seconds |
| Started | Oct 14 11:45:24 PM UTC 24 |
| Finished | Oct 14 11:45:26 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348506281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2348506281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.3746444142 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 87910412 ps |
| CPU time | 1.26 seconds |
| Started | Oct 14 11:45:30 PM UTC 24 |
| Finished | Oct 14 11:45:32 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746444142 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3746444142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.2565737485 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1267824203 ps |
| CPU time | 7.26 seconds |
| Started | Oct 14 11:45:28 PM UTC 24 |
| Finished | Oct 14 11:45:36 PM UTC 24 |
| Peak memory | 243852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565737485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2565737485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2944675277 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 302043021 ps |
| CPU time | 1.93 seconds |
| Started | Oct 14 11:45:28 PM UTC 24 |
| Finished | Oct 14 11:45:31 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944675277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2944675277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.99860131 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 122949533 ps |
| CPU time | 1.15 seconds |
| Started | Oct 14 11:45:27 PM UTC 24 |
| Finished | Oct 14 11:45:29 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99860131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.99860131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.2914507300 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 892163667 ps |
| CPU time | 4.3 seconds |
| Started | Oct 14 11:45:27 PM UTC 24 |
| Finished | Oct 14 11:45:32 PM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914507300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2914507300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1390718312 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 97872986 ps |
| CPU time | 1.34 seconds |
| Started | Oct 14 11:45:28 PM UTC 24 |
| Finished | Oct 14 11:45:30 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390718312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1390718312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.3952969818 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 119449597 ps |
| CPU time | 1.37 seconds |
| Started | Oct 14 11:45:27 PM UTC 24 |
| Finished | Oct 14 11:45:29 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952969818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3952969818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.260231695 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 5997450737 ps |
| CPU time | 21.3 seconds |
| Started | Oct 14 11:45:30 PM UTC 24 |
| Finished | Oct 14 11:45:52 PM UTC 24 |
| Peak memory | 210888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260231695 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.260231695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.1194228511 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 135500168 ps |
| CPU time | 2.29 seconds |
| Started | Oct 14 11:45:27 PM UTC 24 |
| Finished | Oct 14 11:45:30 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194228511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1194228511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.3493917487 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 140707614 ps |
| CPU time | 1.41 seconds |
| Started | Oct 14 11:45:27 PM UTC 24 |
| Finished | Oct 14 11:45:29 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493917487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3493917487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.466548433 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 74330168 ps |
| CPU time | 1.19 seconds |
| Started | Oct 14 11:45:33 PM UTC 24 |
| Finished | Oct 14 11:45:35 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466548433 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.466548433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.4109012503 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1975262691 ps |
| CPU time | 6.86 seconds |
| Started | Oct 14 11:45:31 PM UTC 24 |
| Finished | Oct 14 11:45:39 PM UTC 24 |
| Peak memory | 243420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109012503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.4109012503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2376420006 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 301667135 ps |
| CPU time | 2.04 seconds |
| Started | Oct 14 11:45:31 PM UTC 24 |
| Finished | Oct 14 11:45:35 PM UTC 24 |
| Peak memory | 239456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376420006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2376420006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.1650442162 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 175363406 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 11:45:30 PM UTC 24 |
| Finished | Oct 14 11:45:32 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650442162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1650442162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.612673701 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 975960020 ps |
| CPU time | 6.49 seconds |
| Started | Oct 14 11:45:30 PM UTC 24 |
| Finished | Oct 14 11:45:37 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612673701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.612673701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.354009876 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 145331913 ps |
| CPU time | 1.63 seconds |
| Started | Oct 14 11:45:31 PM UTC 24 |
| Finished | Oct 14 11:45:34 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354009876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.354009876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.3852197039 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 205192173 ps |
| CPU time | 2.12 seconds |
| Started | Oct 14 11:45:30 PM UTC 24 |
| Finished | Oct 14 11:45:33 PM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852197039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3852197039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.1448929521 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1034965011 ps |
| CPU time | 7.86 seconds |
| Started | Oct 14 11:45:33 PM UTC 24 |
| Finished | Oct 14 11:45:42 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448929521 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1448929521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.259191447 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 133286970 ps |
| CPU time | 2.33 seconds |
| Started | Oct 14 11:45:31 PM UTC 24 |
| Finished | Oct 14 11:45:35 PM UTC 24 |
| Peak memory | 219896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259191447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.259191447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.369128145 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 181655692 ps |
| CPU time | 1.67 seconds |
| Started | Oct 14 11:45:30 PM UTC 24 |
| Finished | Oct 14 11:45:32 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369128145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.369128145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.1581993782 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 70903362 ps |
| CPU time | 1.07 seconds |
| Started | Oct 14 11:45:37 PM UTC 24 |
| Finished | Oct 14 11:45:39 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581993782 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1581993782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.4110950455 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1270172845 ps |
| CPU time | 8.19 seconds |
| Started | Oct 14 11:45:35 PM UTC 24 |
| Finished | Oct 14 11:45:44 PM UTC 24 |
| Peak memory | 244056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110950455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.4110950455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3514025881 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 300663631 ps |
| CPU time | 2.09 seconds |
| Started | Oct 14 11:45:36 PM UTC 24 |
| Finished | Oct 14 11:45:40 PM UTC 24 |
| Peak memory | 239448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514025881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3514025881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.131269811 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 134868311 ps |
| CPU time | 1.31 seconds |
| Started | Oct 14 11:45:33 PM UTC 24 |
| Finished | Oct 14 11:45:36 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131269811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.131269811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.3861129326 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1589956324 ps |
| CPU time | 6.38 seconds |
| Started | Oct 14 11:45:33 PM UTC 24 |
| Finished | Oct 14 11:45:41 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861129326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3861129326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.695410911 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 169527138 ps |
| CPU time | 1.26 seconds |
| Started | Oct 14 11:45:35 PM UTC 24 |
| Finished | Oct 14 11:45:37 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695410911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.695410911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.32145991 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 200943485 ps |
| CPU time | 1.57 seconds |
| Started | Oct 14 11:45:33 PM UTC 24 |
| Finished | Oct 14 11:45:36 PM UTC 24 |
| Peak memory | 209780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32145991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.32145991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.954478928 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 966407590 ps |
| CPU time | 5.55 seconds |
| Started | Oct 14 11:45:36 PM UTC 24 |
| Finished | Oct 14 11:45:43 PM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954478928 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.954478928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.170938123 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 361001596 ps |
| CPU time | 2.65 seconds |
| Started | Oct 14 11:45:35 PM UTC 24 |
| Finished | Oct 14 11:45:38 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170938123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.170938123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.193210794 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 90790599 ps |
| CPU time | 1.24 seconds |
| Started | Oct 14 11:45:33 PM UTC 24 |
| Finished | Oct 14 11:45:36 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193210794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.193210794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.2697324144 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 61480877 ps |
| CPU time | 1.17 seconds |
| Started | Oct 14 11:45:40 PM UTC 24 |
| Finished | Oct 14 11:45:42 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697324144 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2697324144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.525141520 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1952212338 ps |
| CPU time | 6.99 seconds |
| Started | Oct 14 11:45:38 PM UTC 24 |
| Finished | Oct 14 11:45:46 PM UTC 24 |
| Peak memory | 243484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525141520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.525141520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.359880462 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 301705912 ps |
| CPU time | 1.97 seconds |
| Started | Oct 14 11:45:38 PM UTC 24 |
| Finished | Oct 14 11:45:41 PM UTC 24 |
| Peak memory | 238208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359880462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.359880462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.1655779477 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 152165550 ps |
| CPU time | 1.31 seconds |
| Started | Oct 14 11:45:37 PM UTC 24 |
| Finished | Oct 14 11:45:39 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655779477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1655779477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.3852700548 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 947586461 ps |
| CPU time | 7.03 seconds |
| Started | Oct 14 11:45:37 PM UTC 24 |
| Finished | Oct 14 11:45:45 PM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852700548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3852700548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1494297230 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 96454496 ps |
| CPU time | 1.23 seconds |
| Started | Oct 14 11:45:38 PM UTC 24 |
| Finished | Oct 14 11:45:41 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494297230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1494297230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.1290467795 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 112483938 ps |
| CPU time | 1.5 seconds |
| Started | Oct 14 11:45:37 PM UTC 24 |
| Finished | Oct 14 11:45:39 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290467795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1290467795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.3132820416 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 6927079455 ps |
| CPU time | 29.29 seconds |
| Started | Oct 14 11:45:39 PM UTC 24 |
| Finished | Oct 14 11:46:09 PM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132820416 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3132820416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.270686190 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 139398886 ps |
| CPU time | 2.29 seconds |
| Started | Oct 14 11:45:37 PM UTC 24 |
| Finished | Oct 14 11:45:40 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270686190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.270686190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.2613159179 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 227367368 ps |
| CPU time | 1.66 seconds |
| Started | Oct 14 11:45:37 PM UTC 24 |
| Finished | Oct 14 11:45:40 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613159179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2613159179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.3783851930 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 87914997 ps |
| CPU time | 1.22 seconds |
| Started | Oct 14 11:45:44 PM UTC 24 |
| Finished | Oct 14 11:45:46 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783851930 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3783851930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.1168694688 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1266290664 ps |
| CPU time | 5.61 seconds |
| Started | Oct 14 11:45:42 PM UTC 24 |
| Finished | Oct 14 11:45:49 PM UTC 24 |
| Peak memory | 244112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168694688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1168694688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1130509916 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 300736205 ps |
| CPU time | 1.84 seconds |
| Started | Oct 14 11:45:42 PM UTC 24 |
| Finished | Oct 14 11:45:45 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130509916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1130509916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.111584321 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 182942765 ps |
| CPU time | 1.44 seconds |
| Started | Oct 14 11:45:40 PM UTC 24 |
| Finished | Oct 14 11:45:43 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111584321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.111584321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.3425844979 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1444331683 ps |
| CPU time | 6.32 seconds |
| Started | Oct 14 11:45:40 PM UTC 24 |
| Finished | Oct 14 11:45:48 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425844979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3425844979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3761455657 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 95034014 ps |
| CPU time | 1.33 seconds |
| Started | Oct 14 11:45:42 PM UTC 24 |
| Finished | Oct 14 11:45:44 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761455657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3761455657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.2634951707 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 124153320 ps |
| CPU time | 1.63 seconds |
| Started | Oct 14 11:45:40 PM UTC 24 |
| Finished | Oct 14 11:45:43 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634951707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2634951707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.476638498 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 5373071792 ps |
| CPU time | 23.1 seconds |
| Started | Oct 14 11:45:42 PM UTC 24 |
| Finished | Oct 14 11:46:06 PM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476638498 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.476638498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.1298838854 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 358206872 ps |
| CPU time | 3.41 seconds |
| Started | Oct 14 11:45:42 PM UTC 24 |
| Finished | Oct 14 11:45:46 PM UTC 24 |
| Peak memory | 219892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298838854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1298838854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.1408949012 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 160746209 ps |
| CPU time | 1.78 seconds |
| Started | Oct 14 11:45:40 PM UTC 24 |
| Finished | Oct 14 11:45:43 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408949012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1408949012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.4116531924 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 67526860 ps |
| CPU time | 1.16 seconds |
| Started | Oct 14 11:45:46 PM UTC 24 |
| Finished | Oct 14 11:45:49 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116531924 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4116531924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.3794106808 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1265364670 ps |
| CPU time | 5.96 seconds |
| Started | Oct 14 11:45:46 PM UTC 24 |
| Finished | Oct 14 11:45:53 PM UTC 24 |
| Peak memory | 243984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794106808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3794106808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1932104903 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 301900130 ps |
| CPU time | 1.3 seconds |
| Started | Oct 14 11:45:46 PM UTC 24 |
| Finished | Oct 14 11:45:49 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932104903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1932104903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.2998112926 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 94873179 ps |
| CPU time | 1.17 seconds |
| Started | Oct 14 11:45:44 PM UTC 24 |
| Finished | Oct 14 11:45:46 PM UTC 24 |
| Peak memory | 208296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998112926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2998112926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.3684301137 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1157155741 ps |
| CPU time | 7.82 seconds |
| Started | Oct 14 11:45:44 PM UTC 24 |
| Finished | Oct 14 11:45:53 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684301137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3684301137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3427007387 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 157399260 ps |
| CPU time | 1.36 seconds |
| Started | Oct 14 11:45:46 PM UTC 24 |
| Finished | Oct 14 11:45:49 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427007387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3427007387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.1960861823 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 187916238 ps |
| CPU time | 1.94 seconds |
| Started | Oct 14 11:45:44 PM UTC 24 |
| Finished | Oct 14 11:45:47 PM UTC 24 |
| Peak memory | 208576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960861823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1960861823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.969433025 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3732183372 ps |
| CPU time | 15.24 seconds |
| Started | Oct 14 11:45:46 PM UTC 24 |
| Finished | Oct 14 11:46:03 PM UTC 24 |
| Peak memory | 220220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969433025 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.969433025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.4218520887 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 380500038 ps |
| CPU time | 2.38 seconds |
| Started | Oct 14 11:45:44 PM UTC 24 |
| Finished | Oct 14 11:45:47 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218520887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.4218520887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.3001067553 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 191277533 ps |
| CPU time | 1.68 seconds |
| Started | Oct 14 11:45:44 PM UTC 24 |
| Finished | Oct 14 11:45:47 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001067553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3001067553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.1692982359 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 86608082 ps |
| CPU time | 1.24 seconds |
| Started | Oct 14 11:45:49 PM UTC 24 |
| Finished | Oct 14 11:45:51 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692982359 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1692982359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.562125926 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1949588579 ps |
| CPU time | 10.46 seconds |
| Started | Oct 14 11:45:49 PM UTC 24 |
| Finished | Oct 14 11:46:00 PM UTC 24 |
| Peak memory | 244404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562125926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.562125926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3214307744 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 302696208 ps |
| CPU time | 1.75 seconds |
| Started | Oct 14 11:45:49 PM UTC 24 |
| Finished | Oct 14 11:45:51 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214307744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3214307744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.2244606049 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 133360396 ps |
| CPU time | 1.29 seconds |
| Started | Oct 14 11:45:46 PM UTC 24 |
| Finished | Oct 14 11:45:49 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244606049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2244606049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.3394140262 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1385703961 ps |
| CPU time | 5.24 seconds |
| Started | Oct 14 11:45:48 PM UTC 24 |
| Finished | Oct 14 11:45:55 PM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394140262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3394140262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.958647393 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 103909781 ps |
| CPU time | 1.54 seconds |
| Started | Oct 14 11:45:49 PM UTC 24 |
| Finished | Oct 14 11:45:51 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958647393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.958647393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.1098238986 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 111783052 ps |
| CPU time | 1.43 seconds |
| Started | Oct 14 11:45:46 PM UTC 24 |
| Finished | Oct 14 11:45:49 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098238986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1098238986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.1442440847 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 9908527766 ps |
| CPU time | 32.9 seconds |
| Started | Oct 14 11:45:49 PM UTC 24 |
| Finished | Oct 14 11:46:23 PM UTC 24 |
| Peak memory | 220120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442440847 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1442440847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.3088480820 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 512953282 ps |
| CPU time | 3.07 seconds |
| Started | Oct 14 11:45:49 PM UTC 24 |
| Finished | Oct 14 11:45:53 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088480820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3088480820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.413683986 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 108699174 ps |
| CPU time | 1.32 seconds |
| Started | Oct 14 11:45:48 PM UTC 24 |
| Finished | Oct 14 11:45:51 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413683986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.413683986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.1991648099 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 77984595 ps |
| CPU time | 1.24 seconds |
| Started | Oct 14 11:44:43 PM UTC 24 |
| Finished | Oct 14 11:44:46 PM UTC 24 |
| Peak memory | 209912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991648099 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1991648099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.2103397034 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2455500194 ps |
| CPU time | 9.61 seconds |
| Started | Oct 14 11:44:42 PM UTC 24 |
| Finished | Oct 14 11:44:53 PM UTC 24 |
| Peak memory | 243548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103397034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2103397034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3318569437 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 302322429 ps |
| CPU time | 1.77 seconds |
| Started | Oct 14 11:44:42 PM UTC 24 |
| Finished | Oct 14 11:44:45 PM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318569437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3318569437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.1443496380 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 118273862 ps |
| CPU time | 0.8 seconds |
| Started | Oct 14 11:44:40 PM UTC 24 |
| Finished | Oct 14 11:44:42 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443496380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1443496380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.3208639499 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1967829650 ps |
| CPU time | 11.16 seconds |
| Started | Oct 14 11:44:40 PM UTC 24 |
| Finished | Oct 14 11:44:52 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208639499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3208639499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.325256497 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 8331555325 ps |
| CPU time | 15.2 seconds |
| Started | Oct 14 11:44:42 PM UTC 24 |
| Finished | Oct 14 11:44:59 PM UTC 24 |
| Peak memory | 243776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325256497 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.325256497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2624324693 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 148956160 ps |
| CPU time | 1.65 seconds |
| Started | Oct 14 11:44:42 PM UTC 24 |
| Finished | Oct 14 11:44:45 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624324693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2624324693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.81812379 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 198153065 ps |
| CPU time | 1.82 seconds |
| Started | Oct 14 11:44:40 PM UTC 24 |
| Finished | Oct 14 11:44:43 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81812379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.81812379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.3177976666 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 3671777425 ps |
| CPU time | 13.81 seconds |
| Started | Oct 14 11:44:42 PM UTC 24 |
| Finished | Oct 14 11:44:57 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177976666 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3177976666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.4196727912 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 255329391 ps |
| CPU time | 2.58 seconds |
| Started | Oct 14 11:44:42 PM UTC 24 |
| Finished | Oct 14 11:44:46 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196727912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.4196727912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.1655282957 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 185696712 ps |
| CPU time | 1.29 seconds |
| Started | Oct 14 11:44:41 PM UTC 24 |
| Finished | Oct 14 11:44:43 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655282957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1655282957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.1178654777 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 62955578 ps |
| CPU time | 1.13 seconds |
| Started | Oct 14 11:45:52 PM UTC 24 |
| Finished | Oct 14 11:45:55 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178654777 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1178654777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/20.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1919374093 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 301488016 ps |
| CPU time | 2.1 seconds |
| Started | Oct 14 11:45:51 PM UTC 24 |
| Finished | Oct 14 11:45:54 PM UTC 24 |
| Peak memory | 239520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919374093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1919374093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.885344648 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 85612335 ps |
| CPU time | 1.13 seconds |
| Started | Oct 14 11:45:51 PM UTC 24 |
| Finished | Oct 14 11:45:53 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885344648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.885344648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.1705710710 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1387374095 ps |
| CPU time | 6.51 seconds |
| Started | Oct 14 11:45:51 PM UTC 24 |
| Finished | Oct 14 11:45:58 PM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705710710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1705710710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/20.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4081684784 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 112326069 ps |
| CPU time | 1.56 seconds |
| Started | Oct 14 11:45:51 PM UTC 24 |
| Finished | Oct 14 11:45:53 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081684784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4081684784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.2827390129 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 117778040 ps |
| CPU time | 1.75 seconds |
| Started | Oct 14 11:45:50 PM UTC 24 |
| Finished | Oct 14 11:45:53 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827390129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2827390129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/20.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.569192444 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 6731825126 ps |
| CPU time | 23.25 seconds |
| Started | Oct 14 11:45:52 PM UTC 24 |
| Finished | Oct 14 11:46:17 PM UTC 24 |
| Peak memory | 220064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569192444 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.569192444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/20.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.38401580 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 138534573 ps |
| CPU time | 2.22 seconds |
| Started | Oct 14 11:45:51 PM UTC 24 |
| Finished | Oct 14 11:45:54 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38401580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.38401580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.3558815306 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 177150509 ps |
| CPU time | 1.84 seconds |
| Started | Oct 14 11:45:51 PM UTC 24 |
| Finished | Oct 14 11:45:53 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558815306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3558815306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.3848380550 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 57657026 ps |
| CPU time | 1.09 seconds |
| Started | Oct 14 11:45:55 PM UTC 24 |
| Finished | Oct 14 11:45:57 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848380550 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3848380550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/21.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.3184203625 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2444752585 ps |
| CPU time | 9.1 seconds |
| Started | Oct 14 11:45:55 PM UTC 24 |
| Finished | Oct 14 11:46:05 PM UTC 24 |
| Peak memory | 243476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184203625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3184203625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1263175055 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 301167375 ps |
| CPU time | 1.67 seconds |
| Started | Oct 14 11:45:55 PM UTC 24 |
| Finished | Oct 14 11:45:58 PM UTC 24 |
| Peak memory | 239704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263175055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1263175055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.3291426697 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 135815422 ps |
| CPU time | 1.3 seconds |
| Started | Oct 14 11:45:53 PM UTC 24 |
| Finished | Oct 14 11:45:55 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291426697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3291426697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.3379938112 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 672616719 ps |
| CPU time | 4.39 seconds |
| Started | Oct 14 11:45:53 PM UTC 24 |
| Finished | Oct 14 11:45:58 PM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379938112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3379938112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/21.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2674560975 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 108953811 ps |
| CPU time | 1.55 seconds |
| Started | Oct 14 11:45:55 PM UTC 24 |
| Finished | Oct 14 11:45:58 PM UTC 24 |
| Peak memory | 209624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674560975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2674560975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.940390597 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 128231734 ps |
| CPU time | 1.42 seconds |
| Started | Oct 14 11:45:52 PM UTC 24 |
| Finished | Oct 14 11:45:55 PM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940390597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.940390597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/21.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.2649800133 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5002900411 ps |
| CPU time | 17.13 seconds |
| Started | Oct 14 11:45:55 PM UTC 24 |
| Finished | Oct 14 11:46:14 PM UTC 24 |
| Peak memory | 220148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649800133 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2649800133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/21.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.1418966113 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 492733408 ps |
| CPU time | 3.06 seconds |
| Started | Oct 14 11:45:55 PM UTC 24 |
| Finished | Oct 14 11:45:59 PM UTC 24 |
| Peak memory | 210600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418966113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1418966113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.604140459 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 68651214 ps |
| CPU time | 1.21 seconds |
| Started | Oct 14 11:45:55 PM UTC 24 |
| Finished | Oct 14 11:45:57 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604140459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.604140459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.3758072797 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 80031067 ps |
| CPU time | 1.29 seconds |
| Started | Oct 14 11:46:01 PM UTC 24 |
| Finished | Oct 14 11:46:03 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758072797 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3758072797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/22.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.2311566783 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1272293762 ps |
| CPU time | 8.06 seconds |
| Started | Oct 14 11:45:58 PM UTC 24 |
| Finished | Oct 14 11:46:07 PM UTC 24 |
| Peak memory | 243360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311566783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2311566783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1183713472 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 301578479 ps |
| CPU time | 1.88 seconds |
| Started | Oct 14 11:45:58 PM UTC 24 |
| Finished | Oct 14 11:46:01 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183713472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1183713472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.3612230892 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 210151267 ps |
| CPU time | 1.47 seconds |
| Started | Oct 14 11:45:55 PM UTC 24 |
| Finished | Oct 14 11:45:58 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612230892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3612230892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.2693889266 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1997213301 ps |
| CPU time | 8.69 seconds |
| Started | Oct 14 11:45:55 PM UTC 24 |
| Finished | Oct 14 11:46:05 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693889266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2693889266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/22.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3477005038 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 106525043 ps |
| CPU time | 1.41 seconds |
| Started | Oct 14 11:45:57 PM UTC 24 |
| Finished | Oct 14 11:46:00 PM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477005038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3477005038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.2053185830 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 123730775 ps |
| CPU time | 1.48 seconds |
| Started | Oct 14 11:45:55 PM UTC 24 |
| Finished | Oct 14 11:45:58 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053185830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2053185830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/22.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.50473301 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 9897161637 ps |
| CPU time | 32.99 seconds |
| Started | Oct 14 11:46:01 PM UTC 24 |
| Finished | Oct 14 11:46:35 PM UTC 24 |
| Peak memory | 220084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50473301 -assert nopostproc +UVM_TESTNAME=rs tmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.50473301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/22.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.185779081 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 153031468 ps |
| CPU time | 2.37 seconds |
| Started | Oct 14 11:45:57 PM UTC 24 |
| Finished | Oct 14 11:46:01 PM UTC 24 |
| Peak memory | 210620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185779081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.185779081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.184054765 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 68492380 ps |
| CPU time | 1.16 seconds |
| Started | Oct 14 11:45:55 PM UTC 24 |
| Finished | Oct 14 11:45:58 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184054765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.184054765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.3047855401 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 77156860 ps |
| CPU time | 1.26 seconds |
| Started | Oct 14 11:46:03 PM UTC 24 |
| Finished | Oct 14 11:46:05 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047855401 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3047855401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/23.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.1374316943 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1282674650 ps |
| CPU time | 6.72 seconds |
| Started | Oct 14 11:46:01 PM UTC 24 |
| Finished | Oct 14 11:46:09 PM UTC 24 |
| Peak memory | 243172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374316943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1374316943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.266901105 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 302693561 ps |
| CPU time | 1.72 seconds |
| Started | Oct 14 11:46:01 PM UTC 24 |
| Finished | Oct 14 11:46:04 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266901105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.266901105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.3145892610 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 184279691 ps |
| CPU time | 1.4 seconds |
| Started | Oct 14 11:46:01 PM UTC 24 |
| Finished | Oct 14 11:46:03 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145892610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3145892610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.317622867 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 965619564 ps |
| CPU time | 5.47 seconds |
| Started | Oct 14 11:46:01 PM UTC 24 |
| Finished | Oct 14 11:46:07 PM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317622867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.317622867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/23.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2002195314 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 175997391 ps |
| CPU time | 1.36 seconds |
| Started | Oct 14 11:46:01 PM UTC 24 |
| Finished | Oct 14 11:46:03 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002195314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2002195314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.2821821010 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 254248094 ps |
| CPU time | 2.31 seconds |
| Started | Oct 14 11:46:01 PM UTC 24 |
| Finished | Oct 14 11:46:04 PM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821821010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2821821010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/23.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.246235553 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1937080045 ps |
| CPU time | 6.18 seconds |
| Started | Oct 14 11:46:01 PM UTC 24 |
| Finished | Oct 14 11:46:09 PM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246235553 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.246235553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/23.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.3749934433 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 430543657 ps |
| CPU time | 3.47 seconds |
| Started | Oct 14 11:46:01 PM UTC 24 |
| Finished | Oct 14 11:46:06 PM UTC 24 |
| Peak memory | 219836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749934433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3749934433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.754969821 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 86858009 ps |
| CPU time | 1.36 seconds |
| Started | Oct 14 11:46:01 PM UTC 24 |
| Finished | Oct 14 11:46:03 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754969821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.754969821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.4240726772 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 73077349 ps |
| CPU time | 1.01 seconds |
| Started | Oct 14 11:46:06 PM UTC 24 |
| Finished | Oct 14 11:46:08 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240726772 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.4240726772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/24.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.2395993985 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1966580909 ps |
| CPU time | 8.74 seconds |
| Started | Oct 14 11:46:06 PM UTC 24 |
| Finished | Oct 14 11:46:16 PM UTC 24 |
| Peak memory | 243844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395993985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2395993985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3637672914 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 302165301 ps |
| CPU time | 1.58 seconds |
| Started | Oct 14 11:46:06 PM UTC 24 |
| Finished | Oct 14 11:46:08 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637672914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3637672914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.3246991087 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 84734284 ps |
| CPU time | 1.19 seconds |
| Started | Oct 14 11:46:03 PM UTC 24 |
| Finished | Oct 14 11:46:05 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246991087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3246991087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.248742580 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1270991132 ps |
| CPU time | 5.49 seconds |
| Started | Oct 14 11:46:03 PM UTC 24 |
| Finished | Oct 14 11:46:10 PM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248742580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.248742580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/24.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1812727581 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 153733336 ps |
| CPU time | 1.77 seconds |
| Started | Oct 14 11:46:06 PM UTC 24 |
| Finished | Oct 14 11:46:09 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812727581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1812727581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.3324799 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 111731305 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 11:46:03 PM UTC 24 |
| Finished | Oct 14 11:46:06 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r stmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3324799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/24.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.4212581612 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4203396685 ps |
| CPU time | 18.8 seconds |
| Started | Oct 14 11:46:06 PM UTC 24 |
| Finished | Oct 14 11:46:26 PM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212581612 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4212581612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/24.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.639910876 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 118829613 ps |
| CPU time | 2.02 seconds |
| Started | Oct 14 11:46:06 PM UTC 24 |
| Finished | Oct 14 11:46:09 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639910876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.639910876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.4272917763 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 97693814 ps |
| CPU time | 1.33 seconds |
| Started | Oct 14 11:46:06 PM UTC 24 |
| Finished | Oct 14 11:46:08 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272917763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.4272917763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.1963408891 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 60063673 ps |
| CPU time | 1.12 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:12 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963408891 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1963408891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/25.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.21744644 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2459551372 ps |
| CPU time | 8.66 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:20 PM UTC 24 |
| Peak memory | 244280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21744644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.21744644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.187658802 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 300815627 ps |
| CPU time | 2.11 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:13 PM UTC 24 |
| Peak memory | 239456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187658802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.187658802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.2840205518 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 101447883 ps |
| CPU time | 1.22 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:12 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840205518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2840205518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.732548505 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1085004203 ps |
| CPU time | 6.95 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:18 PM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732548505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.732548505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/25.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3102796714 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 171205396 ps |
| CPU time | 1.77 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:13 PM UTC 24 |
| Peak memory | 209724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102796714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3102796714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.828674261 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 117117687 ps |
| CPU time | 1.79 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:12 PM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828674261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.828674261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/25.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.1380557386 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 222536410 ps |
| CPU time | 1.77 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:13 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380557386 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1380557386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/25.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.724739019 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 286584301 ps |
| CPU time | 1.94 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:13 PM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724739019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.724739019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.3797110397 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 264865864 ps |
| CPU time | 1.6 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:12 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797110397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3797110397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.1332771528 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 54331734 ps |
| CPU time | 0.92 seconds |
| Started | Oct 14 11:46:13 PM UTC 24 |
| Finished | Oct 14 11:46:15 PM UTC 24 |
| Peak memory | 209916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332771528 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1332771528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/26.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.3696563591 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2450250993 ps |
| CPU time | 8.94 seconds |
| Started | Oct 14 11:46:13 PM UTC 24 |
| Finished | Oct 14 11:46:23 PM UTC 24 |
| Peak memory | 244340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696563591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3696563591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1662119504 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 303908915 ps |
| CPU time | 1.9 seconds |
| Started | Oct 14 11:46:13 PM UTC 24 |
| Finished | Oct 14 11:46:16 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662119504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1662119504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.113581178 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 145234627 ps |
| CPU time | 1.26 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:12 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113581178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.113581178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.3699668294 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 847533035 ps |
| CPU time | 4.36 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:16 PM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699668294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3699668294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/26.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3743677189 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 157280888 ps |
| CPU time | 1.7 seconds |
| Started | Oct 14 11:46:13 PM UTC 24 |
| Finished | Oct 14 11:46:16 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743677189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3743677189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.4140644220 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 186279486 ps |
| CPU time | 1.65 seconds |
| Started | Oct 14 11:46:10 PM UTC 24 |
| Finished | Oct 14 11:46:13 PM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140644220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4140644220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/26.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.821836166 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5007449485 ps |
| CPU time | 20.78 seconds |
| Started | Oct 14 11:46:13 PM UTC 24 |
| Finished | Oct 14 11:46:35 PM UTC 24 |
| Peak memory | 220344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821836166 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.821836166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/26.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.3725268692 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 118869983 ps |
| CPU time | 1.86 seconds |
| Started | Oct 14 11:46:13 PM UTC 24 |
| Finished | Oct 14 11:46:16 PM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725268692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3725268692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.1528298148 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 216369076 ps |
| CPU time | 1.84 seconds |
| Started | Oct 14 11:46:13 PM UTC 24 |
| Finished | Oct 14 11:46:16 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528298148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1528298148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.2459621207 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 83665390 ps |
| CPU time | 1.16 seconds |
| Started | Oct 14 11:46:16 PM UTC 24 |
| Finished | Oct 14 11:46:19 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459621207 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2459621207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/27.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.1770953126 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1274043450 ps |
| CPU time | 5.25 seconds |
| Started | Oct 14 11:46:16 PM UTC 24 |
| Finished | Oct 14 11:46:22 PM UTC 24 |
| Peak memory | 243420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770953126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1770953126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3510518399 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 301285165 ps |
| CPU time | 1.88 seconds |
| Started | Oct 14 11:46:16 PM UTC 24 |
| Finished | Oct 14 11:46:19 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510518399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3510518399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.1253554836 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 143405559 ps |
| CPU time | 1.32 seconds |
| Started | Oct 14 11:46:16 PM UTC 24 |
| Finished | Oct 14 11:46:18 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253554836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1253554836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.962459621 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1430497593 ps |
| CPU time | 7.9 seconds |
| Started | Oct 14 11:46:16 PM UTC 24 |
| Finished | Oct 14 11:46:25 PM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962459621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.962459621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/27.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.881459014 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 107488886 ps |
| CPU time | 1.58 seconds |
| Started | Oct 14 11:46:16 PM UTC 24 |
| Finished | Oct 14 11:46:18 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881459014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.881459014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.1655388362 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 121330213 ps |
| CPU time | 1.58 seconds |
| Started | Oct 14 11:46:13 PM UTC 24 |
| Finished | Oct 14 11:46:16 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655388362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1655388362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/27.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.2506979346 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 9118442606 ps |
| CPU time | 32.86 seconds |
| Started | Oct 14 11:46:16 PM UTC 24 |
| Finished | Oct 14 11:46:51 PM UTC 24 |
| Peak memory | 220092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506979346 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2506979346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/27.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.2121015117 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 136981607 ps |
| CPU time | 2.06 seconds |
| Started | Oct 14 11:46:16 PM UTC 24 |
| Finished | Oct 14 11:46:19 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121015117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2121015117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.364779729 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 98743490 ps |
| CPU time | 1.41 seconds |
| Started | Oct 14 11:46:16 PM UTC 24 |
| Finished | Oct 14 11:46:18 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364779729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.364779729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.3170193760 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 61363066 ps |
| CPU time | 1.16 seconds |
| Started | Oct 14 11:46:21 PM UTC 24 |
| Finished | Oct 14 11:46:24 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170193760 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3170193760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/28.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.3442445243 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2438474681 ps |
| CPU time | 10.77 seconds |
| Started | Oct 14 11:46:18 PM UTC 24 |
| Finished | Oct 14 11:46:30 PM UTC 24 |
| Peak memory | 243480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442445243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3442445243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1315901857 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 302898398 ps |
| CPU time | 2.1 seconds |
| Started | Oct 14 11:46:21 PM UTC 24 |
| Finished | Oct 14 11:46:25 PM UTC 24 |
| Peak memory | 239456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315901857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1315901857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.2370624671 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 94331910 ps |
| CPU time | 1.21 seconds |
| Started | Oct 14 11:46:18 PM UTC 24 |
| Finished | Oct 14 11:46:20 PM UTC 24 |
| Peak memory | 209624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370624671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2370624671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.832528133 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1464255474 ps |
| CPU time | 8.96 seconds |
| Started | Oct 14 11:46:18 PM UTC 24 |
| Finished | Oct 14 11:46:28 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832528133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.832528133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/28.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3616437128 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 161331057 ps |
| CPU time | 1.72 seconds |
| Started | Oct 14 11:46:18 PM UTC 24 |
| Finished | Oct 14 11:46:21 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616437128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3616437128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.3012541254 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 254667653 ps |
| CPU time | 2.31 seconds |
| Started | Oct 14 11:46:18 PM UTC 24 |
| Finished | Oct 14 11:46:21 PM UTC 24 |
| Peak memory | 210944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012541254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3012541254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/28.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.2050362225 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 330908820 ps |
| CPU time | 1.88 seconds |
| Started | Oct 14 11:46:21 PM UTC 24 |
| Finished | Oct 14 11:46:25 PM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050362225 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2050362225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/28.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.2858421184 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 320194281 ps |
| CPU time | 3.14 seconds |
| Started | Oct 14 11:46:18 PM UTC 24 |
| Finished | Oct 14 11:46:22 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858421184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2858421184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.1718084065 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 176569260 ps |
| CPU time | 1.76 seconds |
| Started | Oct 14 11:46:18 PM UTC 24 |
| Finished | Oct 14 11:46:21 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718084065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1718084065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.1376031552 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 66272386 ps |
| CPU time | 0.92 seconds |
| Started | Oct 14 11:46:23 PM UTC 24 |
| Finished | Oct 14 11:46:26 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376031552 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1376031552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/29.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.854457880 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1267879964 ps |
| CPU time | 5.64 seconds |
| Started | Oct 14 11:46:23 PM UTC 24 |
| Finished | Oct 14 11:46:30 PM UTC 24 |
| Peak memory | 243288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854457880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.854457880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1954777936 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 302701322 ps |
| CPU time | 1.76 seconds |
| Started | Oct 14 11:46:23 PM UTC 24 |
| Finished | Oct 14 11:46:26 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954777936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1954777936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.352556518 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 234577665 ps |
| CPU time | 1.11 seconds |
| Started | Oct 14 11:46:21 PM UTC 24 |
| Finished | Oct 14 11:46:24 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352556518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.352556518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.4099882767 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1309831107 ps |
| CPU time | 6.63 seconds |
| Started | Oct 14 11:46:21 PM UTC 24 |
| Finished | Oct 14 11:46:29 PM UTC 24 |
| Peak memory | 211020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099882767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.4099882767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/29.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.637919471 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 149359731 ps |
| CPU time | 1.58 seconds |
| Started | Oct 14 11:46:21 PM UTC 24 |
| Finished | Oct 14 11:46:24 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637919471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.637919471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.227914382 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 250233881 ps |
| CPU time | 2.06 seconds |
| Started | Oct 14 11:46:21 PM UTC 24 |
| Finished | Oct 14 11:46:25 PM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227914382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.227914382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/29.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.2165011568 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 9661273036 ps |
| CPU time | 36.96 seconds |
| Started | Oct 14 11:46:23 PM UTC 24 |
| Finished | Oct 14 11:47:02 PM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165011568 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2165011568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/29.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.639746444 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 139565865 ps |
| CPU time | 1.84 seconds |
| Started | Oct 14 11:46:21 PM UTC 24 |
| Finished | Oct 14 11:46:24 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639746444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.639746444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.1137746627 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 73650237 ps |
| CPU time | 0.87 seconds |
| Started | Oct 14 11:46:21 PM UTC 24 |
| Finished | Oct 14 11:46:24 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137746627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1137746627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.920144774 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 70112598 ps |
| CPU time | 1.22 seconds |
| Started | Oct 14 11:44:49 PM UTC 24 |
| Finished | Oct 14 11:44:52 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920144774 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.920144774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.3800868636 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1967217005 ps |
| CPU time | 11.42 seconds |
| Started | Oct 14 11:44:48 PM UTC 24 |
| Finished | Oct 14 11:45:01 PM UTC 24 |
| Peak memory | 243612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800868636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3800868636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2611472443 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 301742097 ps |
| CPU time | 1.92 seconds |
| Started | Oct 14 11:44:48 PM UTC 24 |
| Finished | Oct 14 11:44:51 PM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611472443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2611472443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.2919419733 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 111118562 ps |
| CPU time | 1.23 seconds |
| Started | Oct 14 11:44:44 PM UTC 24 |
| Finished | Oct 14 11:44:47 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919419733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2919419733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.3442709183 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1490580053 ps |
| CPU time | 8.63 seconds |
| Started | Oct 14 11:44:46 PM UTC 24 |
| Finished | Oct 14 11:44:55 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442709183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3442709183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.553257641 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 16682324625 ps |
| CPU time | 28.88 seconds |
| Started | Oct 14 11:44:48 PM UTC 24 |
| Finished | Oct 14 11:45:19 PM UTC 24 |
| Peak memory | 243340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553257641 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.553257641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3502545054 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 109079365 ps |
| CPU time | 1.35 seconds |
| Started | Oct 14 11:44:47 PM UTC 24 |
| Finished | Oct 14 11:44:49 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502545054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3502545054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.2605445191 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 186862298 ps |
| CPU time | 1.97 seconds |
| Started | Oct 14 11:44:43 PM UTC 24 |
| Finished | Oct 14 11:44:46 PM UTC 24 |
| Peak memory | 209904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605445191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2605445191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.1363638370 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 8024059489 ps |
| CPU time | 27.09 seconds |
| Started | Oct 14 11:44:48 PM UTC 24 |
| Finished | Oct 14 11:45:17 PM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363638370 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1363638370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.3205263612 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 137457181 ps |
| CPU time | 2.14 seconds |
| Started | Oct 14 11:44:47 PM UTC 24 |
| Finished | Oct 14 11:44:50 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205263612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3205263612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.3503145199 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 147527697 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 11:44:46 PM UTC 24 |
| Finished | Oct 14 11:44:48 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503145199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3503145199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.579236759 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 82248319 ps |
| CPU time | 1.15 seconds |
| Started | Oct 14 11:46:26 PM UTC 24 |
| Finished | Oct 14 11:46:28 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579236759 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.579236759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/30.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.1317627868 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1967089617 ps |
| CPU time | 7.48 seconds |
| Started | Oct 14 11:46:26 PM UTC 24 |
| Finished | Oct 14 11:46:35 PM UTC 24 |
| Peak memory | 244212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317627868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1317627868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2085736844 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 301249562 ps |
| CPU time | 1.25 seconds |
| Started | Oct 14 11:46:26 PM UTC 24 |
| Finished | Oct 14 11:46:28 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085736844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2085736844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.3607679155 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 165539003 ps |
| CPU time | 1.02 seconds |
| Started | Oct 14 11:46:23 PM UTC 24 |
| Finished | Oct 14 11:46:26 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607679155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3607679155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.4184762851 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 734112701 ps |
| CPU time | 3.87 seconds |
| Started | Oct 14 11:46:26 PM UTC 24 |
| Finished | Oct 14 11:46:31 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184762851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4184762851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/30.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3002498577 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 184750223 ps |
| CPU time | 1.2 seconds |
| Started | Oct 14 11:46:26 PM UTC 24 |
| Finished | Oct 14 11:46:28 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002498577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3002498577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.180994784 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 240736029 ps |
| CPU time | 2.31 seconds |
| Started | Oct 14 11:46:23 PM UTC 24 |
| Finished | Oct 14 11:46:27 PM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180994784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.180994784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/30.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.380326497 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4875778736 ps |
| CPU time | 17.61 seconds |
| Started | Oct 14 11:46:26 PM UTC 24 |
| Finished | Oct 14 11:46:45 PM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380326497 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.380326497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/30.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.3387928044 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 143203569 ps |
| CPU time | 2.39 seconds |
| Started | Oct 14 11:46:26 PM UTC 24 |
| Finished | Oct 14 11:46:29 PM UTC 24 |
| Peak memory | 219836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387928044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3387928044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.4101688052 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 136070215 ps |
| CPU time | 1.56 seconds |
| Started | Oct 14 11:46:26 PM UTC 24 |
| Finished | Oct 14 11:46:29 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101688052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.4101688052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.3343764775 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 66442966 ps |
| CPU time | 0.84 seconds |
| Started | Oct 14 11:46:30 PM UTC 24 |
| Finished | Oct 14 11:46:32 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343764775 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3343764775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/31.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.51735675 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2454916201 ps |
| CPU time | 9.5 seconds |
| Started | Oct 14 11:46:29 PM UTC 24 |
| Finished | Oct 14 11:46:40 PM UTC 24 |
| Peak memory | 244208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51735675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.51735675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.53743954 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 301372274 ps |
| CPU time | 1.32 seconds |
| Started | Oct 14 11:46:29 PM UTC 24 |
| Finished | Oct 14 11:46:32 PM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53743954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.53743954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.1727927797 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 128362243 ps |
| CPU time | 0.99 seconds |
| Started | Oct 14 11:46:29 PM UTC 24 |
| Finished | Oct 14 11:46:31 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727927797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1727927797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.1990353790 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1016834500 ps |
| CPU time | 6.15 seconds |
| Started | Oct 14 11:46:29 PM UTC 24 |
| Finished | Oct 14 11:46:37 PM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990353790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1990353790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/31.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3270161498 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 147189007 ps |
| CPU time | 1.7 seconds |
| Started | Oct 14 11:46:29 PM UTC 24 |
| Finished | Oct 14 11:46:32 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270161498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3270161498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.3113519267 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 128823288 ps |
| CPU time | 1.73 seconds |
| Started | Oct 14 11:46:26 PM UTC 24 |
| Finished | Oct 14 11:46:29 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113519267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3113519267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/31.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.4268182217 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 14487858130 ps |
| CPU time | 46.04 seconds |
| Started | Oct 14 11:46:29 PM UTC 24 |
| Finished | Oct 14 11:47:17 PM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268182217 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.4268182217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/31.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.207857157 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 301781147 ps |
| CPU time | 2.73 seconds |
| Started | Oct 14 11:46:29 PM UTC 24 |
| Finished | Oct 14 11:46:33 PM UTC 24 |
| Peak memory | 219836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207857157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.207857157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.1544560769 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 58566187 ps |
| CPU time | 1.13 seconds |
| Started | Oct 14 11:46:29 PM UTC 24 |
| Finished | Oct 14 11:46:32 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544560769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1544560769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.734276730 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 57448483 ps |
| CPU time | 0.99 seconds |
| Started | Oct 14 11:46:33 PM UTC 24 |
| Finished | Oct 14 11:46:35 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734276730 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.734276730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/32.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.912280634 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1972001179 ps |
| CPU time | 7.37 seconds |
| Started | Oct 14 11:46:33 PM UTC 24 |
| Finished | Oct 14 11:46:41 PM UTC 24 |
| Peak memory | 243360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912280634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.912280634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1368018074 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 301989290 ps |
| CPU time | 1.6 seconds |
| Started | Oct 14 11:46:33 PM UTC 24 |
| Finished | Oct 14 11:46:35 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368018074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1368018074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.1887324214 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 230698755 ps |
| CPU time | 1.41 seconds |
| Started | Oct 14 11:46:30 PM UTC 24 |
| Finished | Oct 14 11:46:32 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887324214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1887324214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.1235877040 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1760328683 ps |
| CPU time | 6.29 seconds |
| Started | Oct 14 11:46:32 PM UTC 24 |
| Finished | Oct 14 11:46:40 PM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235877040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1235877040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/32.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.150024594 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 112194415 ps |
| CPU time | 1.48 seconds |
| Started | Oct 14 11:46:33 PM UTC 24 |
| Finished | Oct 14 11:46:35 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150024594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.150024594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.2223924118 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 201570311 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 11:46:30 PM UTC 24 |
| Finished | Oct 14 11:46:33 PM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223924118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2223924118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/32.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.4284114480 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2676918514 ps |
| CPU time | 12.79 seconds |
| Started | Oct 14 11:46:33 PM UTC 24 |
| Finished | Oct 14 11:46:47 PM UTC 24 |
| Peak memory | 220064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284114480 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.4284114480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/32.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.1061765009 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 114902999 ps |
| CPU time | 1.93 seconds |
| Started | Oct 14 11:46:33 PM UTC 24 |
| Finished | Oct 14 11:46:36 PM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061765009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1061765009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.3415484463 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 169113754 ps |
| CPU time | 1.68 seconds |
| Started | Oct 14 11:46:32 PM UTC 24 |
| Finished | Oct 14 11:46:35 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415484463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3415484463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.3868277745 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 73450933 ps |
| CPU time | 1.18 seconds |
| Started | Oct 14 11:46:38 PM UTC 24 |
| Finished | Oct 14 11:46:40 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868277745 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3868277745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/33.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.549068972 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1273881072 ps |
| CPU time | 5.72 seconds |
| Started | Oct 14 11:46:35 PM UTC 24 |
| Finished | Oct 14 11:46:42 PM UTC 24 |
| Peak memory | 243396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549068972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.549068972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3213025760 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 302274317 ps |
| CPU time | 1.43 seconds |
| Started | Oct 14 11:46:35 PM UTC 24 |
| Finished | Oct 14 11:46:38 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213025760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3213025760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.1904789044 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 163283454 ps |
| CPU time | 1.2 seconds |
| Started | Oct 14 11:46:33 PM UTC 24 |
| Finished | Oct 14 11:46:35 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904789044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1904789044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.3120716060 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1736218008 ps |
| CPU time | 6.31 seconds |
| Started | Oct 14 11:46:33 PM UTC 24 |
| Finished | Oct 14 11:46:41 PM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120716060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3120716060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/33.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2468099766 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 137577291 ps |
| CPU time | 1.73 seconds |
| Started | Oct 14 11:46:35 PM UTC 24 |
| Finished | Oct 14 11:46:38 PM UTC 24 |
| Peak memory | 209736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468099766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2468099766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.3467816775 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 226323374 ps |
| CPU time | 1.71 seconds |
| Started | Oct 14 11:46:33 PM UTC 24 |
| Finished | Oct 14 11:46:36 PM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467816775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3467816775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/33.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.1801233409 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3312685994 ps |
| CPU time | 11.64 seconds |
| Started | Oct 14 11:46:35 PM UTC 24 |
| Finished | Oct 14 11:46:48 PM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801233409 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1801233409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/33.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.128847440 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 133951292 ps |
| CPU time | 2.28 seconds |
| Started | Oct 14 11:46:35 PM UTC 24 |
| Finished | Oct 14 11:46:38 PM UTC 24 |
| Peak memory | 210744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128847440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.128847440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.378200682 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 211622857 ps |
| CPU time | 1.98 seconds |
| Started | Oct 14 11:46:35 PM UTC 24 |
| Finished | Oct 14 11:46:38 PM UTC 24 |
| Peak memory | 209696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378200682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.378200682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.3035900156 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 61191532 ps |
| CPU time | 1.03 seconds |
| Started | Oct 14 11:46:42 PM UTC 24 |
| Finished | Oct 14 11:46:44 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035900156 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3035900156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/34.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.852653207 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1957623538 ps |
| CPU time | 8.07 seconds |
| Started | Oct 14 11:46:38 PM UTC 24 |
| Finished | Oct 14 11:46:48 PM UTC 24 |
| Peak memory | 243356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852653207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.852653207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.4128594310 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 301082267 ps |
| CPU time | 1.86 seconds |
| Started | Oct 14 11:46:38 PM UTC 24 |
| Finished | Oct 14 11:46:41 PM UTC 24 |
| Peak memory | 239704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128594310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.4128594310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.371860297 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 225040473 ps |
| CPU time | 1.67 seconds |
| Started | Oct 14 11:46:38 PM UTC 24 |
| Finished | Oct 14 11:46:41 PM UTC 24 |
| Peak memory | 209712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371860297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.371860297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.966254508 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 685753220 ps |
| CPU time | 4.05 seconds |
| Started | Oct 14 11:46:38 PM UTC 24 |
| Finished | Oct 14 11:46:43 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966254508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.966254508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/34.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3844397863 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 142999135 ps |
| CPU time | 1.61 seconds |
| Started | Oct 14 11:46:38 PM UTC 24 |
| Finished | Oct 14 11:46:41 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844397863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3844397863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.607847654 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 190024507 ps |
| CPU time | 1.91 seconds |
| Started | Oct 14 11:46:38 PM UTC 24 |
| Finished | Oct 14 11:46:41 PM UTC 24 |
| Peak memory | 209776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607847654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.607847654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/34.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.897613254 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3031011188 ps |
| CPU time | 11.87 seconds |
| Started | Oct 14 11:46:38 PM UTC 24 |
| Finished | Oct 14 11:46:52 PM UTC 24 |
| Peak memory | 220092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897613254 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.897613254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/34.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.710110519 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 441452820 ps |
| CPU time | 2.61 seconds |
| Started | Oct 14 11:46:38 PM UTC 24 |
| Finished | Oct 14 11:46:42 PM UTC 24 |
| Peak memory | 219836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710110519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.710110519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.4284207116 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 120162412 ps |
| CPU time | 1.51 seconds |
| Started | Oct 14 11:46:38 PM UTC 24 |
| Finished | Oct 14 11:46:41 PM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284207116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.4284207116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.1495921334 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 79574478 ps |
| CPU time | 0.95 seconds |
| Started | Oct 14 11:46:43 PM UTC 24 |
| Finished | Oct 14 11:46:45 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495921334 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1495921334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/35.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.53422251 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1266047873 ps |
| CPU time | 5.96 seconds |
| Started | Oct 14 11:46:42 PM UTC 24 |
| Finished | Oct 14 11:46:50 PM UTC 24 |
| Peak memory | 243636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53422251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.53422251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1221586084 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 302532974 ps |
| CPU time | 1.27 seconds |
| Started | Oct 14 11:46:43 PM UTC 24 |
| Finished | Oct 14 11:46:45 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221586084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1221586084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.2124692589 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 200242405 ps |
| CPU time | 1.06 seconds |
| Started | Oct 14 11:46:42 PM UTC 24 |
| Finished | Oct 14 11:46:44 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124692589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2124692589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.2688384232 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 755003869 ps |
| CPU time | 3.77 seconds |
| Started | Oct 14 11:46:42 PM UTC 24 |
| Finished | Oct 14 11:46:47 PM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688384232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2688384232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/35.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1171391545 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 146196461 ps |
| CPU time | 1.18 seconds |
| Started | Oct 14 11:46:42 PM UTC 24 |
| Finished | Oct 14 11:46:45 PM UTC 24 |
| Peak memory | 209768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171391545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1171391545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.297670514 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 200775840 ps |
| CPU time | 1.56 seconds |
| Started | Oct 14 11:46:42 PM UTC 24 |
| Finished | Oct 14 11:46:45 PM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297670514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.297670514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/35.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.3391792651 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 9698326429 ps |
| CPU time | 34.89 seconds |
| Started | Oct 14 11:46:43 PM UTC 24 |
| Finished | Oct 14 11:47:19 PM UTC 24 |
| Peak memory | 220200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391792651 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3391792651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/35.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.4015303254 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 111072834 ps |
| CPU time | 1.68 seconds |
| Started | Oct 14 11:46:42 PM UTC 24 |
| Finished | Oct 14 11:46:45 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015303254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4015303254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.2548880965 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 130115748 ps |
| CPU time | 1.63 seconds |
| Started | Oct 14 11:46:42 PM UTC 24 |
| Finished | Oct 14 11:46:45 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548880965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2548880965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.1180965411 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 71445797 ps |
| CPU time | 1.22 seconds |
| Started | Oct 14 11:46:47 PM UTC 24 |
| Finished | Oct 14 11:46:49 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180965411 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1180965411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/36.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.2456461297 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2441792840 ps |
| CPU time | 8.24 seconds |
| Started | Oct 14 11:46:47 PM UTC 24 |
| Finished | Oct 14 11:46:56 PM UTC 24 |
| Peak memory | 244204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456461297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2456461297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.979866888 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 300862084 ps |
| CPU time | 1.28 seconds |
| Started | Oct 14 11:46:47 PM UTC 24 |
| Finished | Oct 14 11:46:49 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979866888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.979866888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.1107058051 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 107984872 ps |
| CPU time | 1.07 seconds |
| Started | Oct 14 11:46:46 PM UTC 24 |
| Finished | Oct 14 11:46:48 PM UTC 24 |
| Peak memory | 209744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107058051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1107058051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.1258510866 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2303417485 ps |
| CPU time | 7.91 seconds |
| Started | Oct 14 11:46:46 PM UTC 24 |
| Finished | Oct 14 11:46:55 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258510866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1258510866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/36.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3376103590 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 105688807 ps |
| CPU time | 1.52 seconds |
| Started | Oct 14 11:46:46 PM UTC 24 |
| Finished | Oct 14 11:46:49 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376103590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3376103590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.3488057180 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 117780105 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 11:46:46 PM UTC 24 |
| Finished | Oct 14 11:46:49 PM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488057180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3488057180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/36.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.163609408 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 4330973389 ps |
| CPU time | 14.8 seconds |
| Started | Oct 14 11:46:47 PM UTC 24 |
| Finished | Oct 14 11:47:03 PM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163609408 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.163609408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/36.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.3949146485 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 149069827 ps |
| CPU time | 2.02 seconds |
| Started | Oct 14 11:46:46 PM UTC 24 |
| Finished | Oct 14 11:46:49 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949146485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3949146485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.476694160 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 76706275 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 11:46:46 PM UTC 24 |
| Finished | Oct 14 11:46:48 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476694160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.476694160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.1621113540 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 71447490 ps |
| CPU time | 1.07 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:46:54 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621113540 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1621113540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/37.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.2476812717 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1962209709 ps |
| CPU time | 6.66 seconds |
| Started | Oct 14 11:46:51 PM UTC 24 |
| Finished | Oct 14 11:46:59 PM UTC 24 |
| Peak memory | 243548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476812717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2476812717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3771182315 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 302315752 ps |
| CPU time | 1.9 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:46:55 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771182315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3771182315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.787537821 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 106282268 ps |
| CPU time | 1.1 seconds |
| Started | Oct 14 11:46:47 PM UTC 24 |
| Finished | Oct 14 11:46:49 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787537821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.787537821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.252397911 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 661252187 ps |
| CPU time | 3.83 seconds |
| Started | Oct 14 11:46:47 PM UTC 24 |
| Finished | Oct 14 11:46:52 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252397911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.252397911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/37.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2642944679 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 180950992 ps |
| CPU time | 1.41 seconds |
| Started | Oct 14 11:46:47 PM UTC 24 |
| Finished | Oct 14 11:46:49 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642944679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2642944679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.3196446291 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 126279545 ps |
| CPU time | 1.28 seconds |
| Started | Oct 14 11:46:47 PM UTC 24 |
| Finished | Oct 14 11:46:49 PM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196446291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3196446291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/37.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.157719250 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3317853639 ps |
| CPU time | 15.58 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:47:09 PM UTC 24 |
| Peak memory | 220064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157719250 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.157719250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/37.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.1192991804 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 539241389 ps |
| CPU time | 2.86 seconds |
| Started | Oct 14 11:46:47 PM UTC 24 |
| Finished | Oct 14 11:46:51 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192991804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1192991804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.3823517200 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 92317268 ps |
| CPU time | 1.11 seconds |
| Started | Oct 14 11:46:47 PM UTC 24 |
| Finished | Oct 14 11:46:49 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823517200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3823517200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.3839066417 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 100033033 ps |
| CPU time | 1.12 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:46:55 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839066417 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3839066417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/38.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.3306806811 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1274910654 ps |
| CPU time | 5.63 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:46:59 PM UTC 24 |
| Peak memory | 244208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306806811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3306806811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3161422276 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 301082602 ps |
| CPU time | 1.58 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:46:55 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161422276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3161422276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.3905608660 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 153108944 ps |
| CPU time | 0.97 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:46:54 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905608660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3905608660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.888541870 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1860460438 ps |
| CPU time | 6.43 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:47:00 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888541870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.888541870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/38.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.30721283 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 155322414 ps |
| CPU time | 1.25 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:46:55 PM UTC 24 |
| Peak memory | 209724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30721283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstm gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.30721283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.1933025817 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 194705856 ps |
| CPU time | 1.56 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:46:55 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933025817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1933025817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/38.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.1448985928 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1291281863 ps |
| CPU time | 4.66 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:46:58 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448985928 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1448985928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/38.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.2364072840 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 438411193 ps |
| CPU time | 2.74 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:46:56 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364072840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2364072840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.968945456 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 73864919 ps |
| CPU time | 1.14 seconds |
| Started | Oct 14 11:46:52 PM UTC 24 |
| Finished | Oct 14 11:46:54 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968945456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.968945456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.4082274626 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 72533655 ps |
| CPU time | 1.08 seconds |
| Started | Oct 14 11:46:57 PM UTC 24 |
| Finished | Oct 14 11:46:59 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082274626 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.4082274626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/39.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.4062570105 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1273289713 ps |
| CPU time | 5.36 seconds |
| Started | Oct 14 11:46:57 PM UTC 24 |
| Finished | Oct 14 11:47:03 PM UTC 24 |
| Peak memory | 243420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062570105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4062570105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.370644015 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 302082948 ps |
| CPU time | 1.31 seconds |
| Started | Oct 14 11:46:57 PM UTC 24 |
| Finished | Oct 14 11:46:59 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370644015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.370644015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.727826389 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 177414940 ps |
| CPU time | 0.85 seconds |
| Started | Oct 14 11:46:56 PM UTC 24 |
| Finished | Oct 14 11:46:58 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727826389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.727826389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.65425747 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1700012151 ps |
| CPU time | 6.87 seconds |
| Started | Oct 14 11:46:56 PM UTC 24 |
| Finished | Oct 14 11:47:04 PM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65425747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.65425747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/39.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1437177236 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 149817259 ps |
| CPU time | 1.62 seconds |
| Started | Oct 14 11:46:56 PM UTC 24 |
| Finished | Oct 14 11:46:59 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437177236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1437177236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.761667569 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 115873581 ps |
| CPU time | 1.62 seconds |
| Started | Oct 14 11:46:53 PM UTC 24 |
| Finished | Oct 14 11:46:55 PM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761667569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.761667569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/39.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.708063832 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 5339490431 ps |
| CPU time | 22.85 seconds |
| Started | Oct 14 11:46:57 PM UTC 24 |
| Finished | Oct 14 11:47:21 PM UTC 24 |
| Peak memory | 220028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708063832 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.708063832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/39.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.38136257 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 339792466 ps |
| CPU time | 2.15 seconds |
| Started | Oct 14 11:46:56 PM UTC 24 |
| Finished | Oct 14 11:47:00 PM UTC 24 |
| Peak memory | 219896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38136257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.38136257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.2944451172 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 191789600 ps |
| CPU time | 1.36 seconds |
| Started | Oct 14 11:46:56 PM UTC 24 |
| Finished | Oct 14 11:46:59 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944451172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2944451172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.700434939 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 61780211 ps |
| CPU time | 1.08 seconds |
| Started | Oct 14 11:44:54 PM UTC 24 |
| Finished | Oct 14 11:44:56 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700434939 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.700434939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.2766081281 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1954877072 ps |
| CPU time | 8.45 seconds |
| Started | Oct 14 11:44:54 PM UTC 24 |
| Finished | Oct 14 11:45:04 PM UTC 24 |
| Peak memory | 243632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766081281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2766081281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1585516195 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 301915501 ps |
| CPU time | 1.89 seconds |
| Started | Oct 14 11:44:54 PM UTC 24 |
| Finished | Oct 14 11:44:57 PM UTC 24 |
| Peak memory | 239556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585516195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1585516195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.836160499 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 127413320 ps |
| CPU time | 1.28 seconds |
| Started | Oct 14 11:44:50 PM UTC 24 |
| Finished | Oct 14 11:44:53 PM UTC 24 |
| Peak memory | 209668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836160499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.836160499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.2339681907 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 999292505 ps |
| CPU time | 7.19 seconds |
| Started | Oct 14 11:44:50 PM UTC 24 |
| Finished | Oct 14 11:44:59 PM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339681907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2339681907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.668688669 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 9132025433 ps |
| CPU time | 15.94 seconds |
| Started | Oct 14 11:44:54 PM UTC 24 |
| Finished | Oct 14 11:45:11 PM UTC 24 |
| Peak memory | 243980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668688669 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.668688669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3903401524 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 104483887 ps |
| CPU time | 1.3 seconds |
| Started | Oct 14 11:44:53 PM UTC 24 |
| Finished | Oct 14 11:44:55 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903401524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3903401524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.3431207377 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 128732454 ps |
| CPU time | 1.68 seconds |
| Started | Oct 14 11:44:50 PM UTC 24 |
| Finished | Oct 14 11:44:53 PM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431207377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3431207377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.1538449983 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1810219284 ps |
| CPU time | 11.28 seconds |
| Started | Oct 14 11:44:54 PM UTC 24 |
| Finished | Oct 14 11:45:07 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538449983 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1538449983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.1313964982 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 243541069 ps |
| CPU time | 2.27 seconds |
| Started | Oct 14 11:44:53 PM UTC 24 |
| Finished | Oct 14 11:44:56 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313964982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1313964982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.88316719 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 99531097 ps |
| CPU time | 1.03 seconds |
| Started | Oct 14 11:44:51 PM UTC 24 |
| Finished | Oct 14 11:44:54 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88316719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.88316719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.3364789980 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 64319019 ps |
| CPU time | 1.14 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:04 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364789980 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3364789980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/40.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.2392617441 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2435930775 ps |
| CPU time | 8.13 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 244204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392617441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2392617441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1473582298 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 301575363 ps |
| CPU time | 1.62 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:05 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473582298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1473582298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.2634189135 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 135025155 ps |
| CPU time | 1.1 seconds |
| Started | Oct 14 11:46:57 PM UTC 24 |
| Finished | Oct 14 11:46:59 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634189135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2634189135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.351052792 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1184540165 ps |
| CPU time | 4.85 seconds |
| Started | Oct 14 11:46:57 PM UTC 24 |
| Finished | Oct 14 11:47:03 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351052792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.351052792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/40.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.402588581 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 142239230 ps |
| CPU time | 1.14 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:04 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402588581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.402588581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.1633958467 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 225041747 ps |
| CPU time | 1.85 seconds |
| Started | Oct 14 11:46:57 PM UTC 24 |
| Finished | Oct 14 11:47:00 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633958467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1633958467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/40.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.4204307130 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 5738999027 ps |
| CPU time | 18.8 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:22 PM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204307130 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.4204307130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/40.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.3376522943 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 270209243 ps |
| CPU time | 2.59 seconds |
| Started | Oct 14 11:46:57 PM UTC 24 |
| Finished | Oct 14 11:47:01 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376522943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3376522943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.1283609967 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 115193697 ps |
| CPU time | 1.29 seconds |
| Started | Oct 14 11:46:57 PM UTC 24 |
| Finished | Oct 14 11:46:59 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283609967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1283609967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.2157650615 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 56484464 ps |
| CPU time | 1 seconds |
| Started | Oct 14 11:47:03 PM UTC 24 |
| Finished | Oct 14 11:47:05 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157650615 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2157650615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/41.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.3649341549 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2438428267 ps |
| CPU time | 9.76 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:13 PM UTC 24 |
| Peak memory | 244244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649341549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3649341549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.268951511 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 302194943 ps |
| CPU time | 1.56 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:05 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268951511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.268951511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.3758811080 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 121649042 ps |
| CPU time | 0.8 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:04 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758811080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3758811080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.3362982275 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2086048123 ps |
| CPU time | 6.96 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:10 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362982275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3362982275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/41.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1279185835 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 106950686 ps |
| CPU time | 1.29 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:05 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279185835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1279185835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.2204461368 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 248495813 ps |
| CPU time | 1.77 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:05 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204461368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2204461368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/41.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.1052302580 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 5735944821 ps |
| CPU time | 18.83 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:23 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052302580 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1052302580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/41.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.2092545562 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 375042698 ps |
| CPU time | 2.94 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:06 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092545562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2092545562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.2411915232 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 115871526 ps |
| CPU time | 1.24 seconds |
| Started | Oct 14 11:47:02 PM UTC 24 |
| Finished | Oct 14 11:47:05 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411915232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2411915232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.3679924596 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 74578849 ps |
| CPU time | 1.25 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679924596 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3679924596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/42.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.91159614 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1958678068 ps |
| CPU time | 6.8 seconds |
| Started | Oct 14 11:47:08 PM UTC 24 |
| Finished | Oct 14 11:47:16 PM UTC 24 |
| Peak memory | 243028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91159614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.91159614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1964413883 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 301658844 ps |
| CPU time | 1.39 seconds |
| Started | Oct 14 11:47:08 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 239704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964413883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1964413883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.4063957853 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 171370588 ps |
| CPU time | 0.99 seconds |
| Started | Oct 14 11:47:03 PM UTC 24 |
| Finished | Oct 14 11:47:05 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063957853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.4063957853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.97358171 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 1521505882 ps |
| CPU time | 6.28 seconds |
| Started | Oct 14 11:47:08 PM UTC 24 |
| Finished | Oct 14 11:47:16 PM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97358171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.97358171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/42.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1980275333 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 101703977 ps |
| CPU time | 1.42 seconds |
| Started | Oct 14 11:47:08 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980275333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1980275333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.226509520 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 193945500 ps |
| CPU time | 1.43 seconds |
| Started | Oct 14 11:47:03 PM UTC 24 |
| Finished | Oct 14 11:47:05 PM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226509520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.226509520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/42.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.2436694230 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 5120563006 ps |
| CPU time | 17.97 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:28 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436694230 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2436694230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/42.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.112293925 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 271158545 ps |
| CPU time | 1.92 seconds |
| Started | Oct 14 11:47:08 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112293925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.112293925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.2681739580 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 139374396 ps |
| CPU time | 1.21 seconds |
| Started | Oct 14 11:47:08 PM UTC 24 |
| Finished | Oct 14 11:47:10 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681739580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2681739580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.193923215 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 72327455 ps |
| CPU time | 1.15 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193923215 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.193923215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/43.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.3746983682 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1965721971 ps |
| CPU time | 7.59 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:18 PM UTC 24 |
| Peak memory | 243356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746983682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3746983682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1593064700 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 302782896 ps |
| CPU time | 1.4 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 239704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593064700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1593064700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.25136370 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 241699960 ps |
| CPU time | 1.42 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 209412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25136370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.25136370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.1101683272 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1670837725 ps |
| CPU time | 6.25 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:16 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101683272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1101683272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/43.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3223879683 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 105414086 ps |
| CPU time | 1.39 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223879683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3223879683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.624426026 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 122732438 ps |
| CPU time | 1.26 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624426026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.624426026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/43.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.1757954572 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2124377185 ps |
| CPU time | 7.48 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:18 PM UTC 24 |
| Peak memory | 220088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757954572 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1757954572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/43.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.475964519 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 534871541 ps |
| CPU time | 3.18 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:13 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475964519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.475964519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.1232251155 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 294375089 ps |
| CPU time | 1.78 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:12 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232251155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1232251155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.1139557518 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 64105277 ps |
| CPU time | 1.02 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:18 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139557518 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1139557518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/44.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.4079475546 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2442213096 ps |
| CPU time | 7.79 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:25 PM UTC 24 |
| Peak memory | 244272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079475546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.4079475546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3021301123 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 301750463 ps |
| CPU time | 1.21 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:18 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021301123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3021301123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.664090061 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 147531756 ps |
| CPU time | 1.14 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664090061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.664090061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.339069981 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 817237381 ps |
| CPU time | 5.05 seconds |
| Started | Oct 14 11:47:12 PM UTC 24 |
| Finished | Oct 14 11:47:18 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339069981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.339069981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/44.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1292122627 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 190114792 ps |
| CPU time | 1.27 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:18 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292122627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1292122627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.1732429160 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 193703208 ps |
| CPU time | 1.25 seconds |
| Started | Oct 14 11:47:09 PM UTC 24 |
| Finished | Oct 14 11:47:11 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732429160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1732429160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/44.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.1975432100 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 232666744 ps |
| CPU time | 1.5 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:19 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975432100 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1975432100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/44.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.470355534 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 285909414 ps |
| CPU time | 2.03 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:19 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470355534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.470355534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.1711292861 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 194903702 ps |
| CPU time | 1.38 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:18 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711292861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1711292861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.3030608355 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 65648113 ps |
| CPU time | 0.92 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:23 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030608355 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3030608355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/45.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.1968400739 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1264621608 ps |
| CPU time | 5.58 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:23 PM UTC 24 |
| Peak memory | 243768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968400739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1968400739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3862633985 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 301733620 ps |
| CPU time | 1.68 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:19 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862633985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3862633985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.1258512920 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 128357621 ps |
| CPU time | 1.15 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:18 PM UTC 24 |
| Peak memory | 209772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258512920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1258512920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.143542507 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 678694020 ps |
| CPU time | 3.68 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:21 PM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143542507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.143542507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/45.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.649862170 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 143402315 ps |
| CPU time | 1.08 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:18 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649862170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.649862170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.2769213187 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 115491718 ps |
| CPU time | 1.51 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:19 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769213187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2769213187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/45.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.2453880909 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 12407129781 ps |
| CPU time | 44.71 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:48:03 PM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453880909 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2453880909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/45.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.4194012359 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 113446844 ps |
| CPU time | 1.62 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:19 PM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194012359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.4194012359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.4212417103 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 237450606 ps |
| CPU time | 1.55 seconds |
| Started | Oct 14 11:47:16 PM UTC 24 |
| Finished | Oct 14 11:47:19 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212417103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.4212417103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.3924813795 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 69534316 ps |
| CPU time | 1.09 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:24 PM UTC 24 |
| Peak memory | 209744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924813795 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3924813795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/46.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.3261373018 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1278007092 ps |
| CPU time | 5.35 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:28 PM UTC 24 |
| Peak memory | 243360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261373018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3261373018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1760814643 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 302286173 ps |
| CPU time | 1.26 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:24 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760814643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1760814643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.3368235064 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 186373196 ps |
| CPU time | 0.91 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:23 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368235064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3368235064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.1824938008 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1880082871 ps |
| CPU time | 6.2 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:28 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824938008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1824938008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/46.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.31325558 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 141105833 ps |
| CPU time | 1.27 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:24 PM UTC 24 |
| Peak memory | 209724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31325558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstm gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.31325558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.2417500342 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 123482217 ps |
| CPU time | 1.5 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:23 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417500342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2417500342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/46.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.398803047 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 5222563961 ps |
| CPU time | 17.63 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:40 PM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398803047 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.398803047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/46.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.963381776 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 262164047 ps |
| CPU time | 1.99 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:24 PM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963381776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.963381776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.2965960780 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 137364977 ps |
| CPU time | 1.44 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:24 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965960780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2965960780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.2744151540 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 70082968 ps |
| CPU time | 0.82 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:30 PM UTC 24 |
| Peak memory | 209516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744151540 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2744151540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/47.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.2258766416 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1272962355 ps |
| CPU time | 5.85 seconds |
| Started | Oct 14 11:47:22 PM UTC 24 |
| Finished | Oct 14 11:47:29 PM UTC 24 |
| Peak memory | 244056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258766416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2258766416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3519316836 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 301285028 ps |
| CPU time | 1.27 seconds |
| Started | Oct 14 11:47:22 PM UTC 24 |
| Finished | Oct 14 11:47:24 PM UTC 24 |
| Peak memory | 239704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519316836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3519316836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.277802017 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 240738547 ps |
| CPU time | 1.51 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:24 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277802017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.277802017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.1711401996 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1244085790 ps |
| CPU time | 4.8 seconds |
| Started | Oct 14 11:47:22 PM UTC 24 |
| Finished | Oct 14 11:47:27 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711401996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1711401996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/47.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2072950408 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 112116630 ps |
| CPU time | 1.18 seconds |
| Started | Oct 14 11:47:22 PM UTC 24 |
| Finished | Oct 14 11:47:24 PM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072950408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2072950408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.2831276702 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 110232989 ps |
| CPU time | 1.08 seconds |
| Started | Oct 14 11:47:21 PM UTC 24 |
| Finished | Oct 14 11:47:24 PM UTC 24 |
| Peak memory | 209668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831276702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2831276702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/47.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.3460540117 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 238914041 ps |
| CPU time | 1.73 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:31 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460540117 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3460540117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/47.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.2898604706 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 445919281 ps |
| CPU time | 2.17 seconds |
| Started | Oct 14 11:47:22 PM UTC 24 |
| Finished | Oct 14 11:47:25 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898604706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2898604706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.2014825924 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 184733042 ps |
| CPU time | 1.48 seconds |
| Started | Oct 14 11:47:22 PM UTC 24 |
| Finished | Oct 14 11:47:24 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014825924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2014825924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.780423757 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 71410612 ps |
| CPU time | 1.04 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:30 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780423757 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.780423757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/48.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.204253477 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1269790732 ps |
| CPU time | 4.81 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:34 PM UTC 24 |
| Peak memory | 243816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204253477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.204253477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1313588941 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 301873813 ps |
| CPU time | 1.45 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:31 PM UTC 24 |
| Peak memory | 239704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313588941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1313588941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.3891514255 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 116202429 ps |
| CPU time | 0.9 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:30 PM UTC 24 |
| Peak memory | 209644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891514255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3891514255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.2745802656 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1703371618 ps |
| CPU time | 5.73 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:35 PM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745802656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2745802656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/48.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.4169909289 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 99749598 ps |
| CPU time | 1.11 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:30 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169909289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.4169909289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.4267038956 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 119539261 ps |
| CPU time | 1.44 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:31 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267038956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.4267038956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/48.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.2987544478 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2191081505 ps |
| CPU time | 9.3 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:39 PM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987544478 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2987544478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/48.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.3040553582 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 268497639 ps |
| CPU time | 2.04 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:31 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040553582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3040553582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.3520078877 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 74774867 ps |
| CPU time | 0.78 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:30 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520078877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3520078877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.2076324826 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 68575086 ps |
| CPU time | 0.72 seconds |
| Started | Oct 14 11:47:29 PM UTC 24 |
| Finished | Oct 14 11:47:31 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076324826 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2076324826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/49.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.254141560 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1966297672 ps |
| CPU time | 7.19 seconds |
| Started | Oct 14 11:47:29 PM UTC 24 |
| Finished | Oct 14 11:47:37 PM UTC 24 |
| Peak memory | 243416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254141560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.254141560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.205796761 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 302608553 ps |
| CPU time | 1.33 seconds |
| Started | Oct 14 11:47:29 PM UTC 24 |
| Finished | Oct 14 11:47:31 PM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205796761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.205796761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.1400974479 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 133121341 ps |
| CPU time | 1.05 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:31 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400974479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1400974479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.879278601 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1203415649 ps |
| CPU time | 4.61 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:34 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879278601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.879278601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/49.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.691349685 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 141540722 ps |
| CPU time | 1.44 seconds |
| Started | Oct 14 11:47:29 PM UTC 24 |
| Finished | Oct 14 11:47:31 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691349685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.691349685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.1267266827 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 231868083 ps |
| CPU time | 1.54 seconds |
| Started | Oct 14 11:47:28 PM UTC 24 |
| Finished | Oct 14 11:47:31 PM UTC 24 |
| Peak memory | 209544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267266827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1267266827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/49.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.2326399697 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 7512307581 ps |
| CPU time | 23.86 seconds |
| Started | Oct 14 11:47:29 PM UTC 24 |
| Finished | Oct 14 11:47:54 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326399697 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2326399697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/49.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.4242939364 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 362997358 ps |
| CPU time | 1.96 seconds |
| Started | Oct 14 11:47:29 PM UTC 24 |
| Finished | Oct 14 11:47:32 PM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242939364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.4242939364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.1978801639 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 112829270 ps |
| CPU time | 1.08 seconds |
| Started | Oct 14 11:47:29 PM UTC 24 |
| Finished | Oct 14 11:47:31 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978801639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1978801639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.1803425515 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 61123344 ps |
| CPU time | 1.11 seconds |
| Started | Oct 14 11:45:00 PM UTC 24 |
| Finished | Oct 14 11:45:02 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803425515 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1803425515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.1255355561 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1276786142 ps |
| CPU time | 8.04 seconds |
| Started | Oct 14 11:44:58 PM UTC 24 |
| Finished | Oct 14 11:45:07 PM UTC 24 |
| Peak memory | 244280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255355561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1255355561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2929884047 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 302574231 ps |
| CPU time | 2.03 seconds |
| Started | Oct 14 11:44:58 PM UTC 24 |
| Finished | Oct 14 11:45:01 PM UTC 24 |
| Peak memory | 239452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929884047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2929884047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.1395531556 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 156455275 ps |
| CPU time | 1.36 seconds |
| Started | Oct 14 11:44:56 PM UTC 24 |
| Finished | Oct 14 11:44:59 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395531556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1395531556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.579544032 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1463325022 ps |
| CPU time | 8.61 seconds |
| Started | Oct 14 11:44:57 PM UTC 24 |
| Finished | Oct 14 11:45:06 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579544032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.579544032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2160732664 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 179022738 ps |
| CPU time | 1.89 seconds |
| Started | Oct 14 11:44:58 PM UTC 24 |
| Finished | Oct 14 11:45:01 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160732664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2160732664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.2733810230 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 203023020 ps |
| CPU time | 2.18 seconds |
| Started | Oct 14 11:44:55 PM UTC 24 |
| Finished | Oct 14 11:44:59 PM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733810230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2733810230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.3986776764 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 6336959529 ps |
| CPU time | 33.27 seconds |
| Started | Oct 14 11:45:00 PM UTC 24 |
| Finished | Oct 14 11:45:35 PM UTC 24 |
| Peak memory | 220056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986776764 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3986776764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.2250691969 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 148958021 ps |
| CPU time | 2.7 seconds |
| Started | Oct 14 11:44:57 PM UTC 24 |
| Finished | Oct 14 11:45:00 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250691969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2250691969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.3781923089 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 131951587 ps |
| CPU time | 1.69 seconds |
| Started | Oct 14 11:44:57 PM UTC 24 |
| Finished | Oct 14 11:44:59 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781923089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3781923089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1358197213 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 68365452 ps |
| CPU time | 1.12 seconds |
| Started | Oct 14 11:45:04 PM UTC 24 |
| Finished | Oct 14 11:45:06 PM UTC 24 |
| Peak memory | 209912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358197213 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1358197213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2893904661 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 301524011 ps |
| CPU time | 2.03 seconds |
| Started | Oct 14 11:45:03 PM UTC 24 |
| Finished | Oct 14 11:45:06 PM UTC 24 |
| Peak memory | 239520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893904661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2893904661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.1184655667 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 220449385 ps |
| CPU time | 1.6 seconds |
| Started | Oct 14 11:45:00 PM UTC 24 |
| Finished | Oct 14 11:45:03 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184655667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1184655667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.934672124 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1762042792 ps |
| CPU time | 7.82 seconds |
| Started | Oct 14 11:45:00 PM UTC 24 |
| Finished | Oct 14 11:45:09 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934672124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.934672124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1488967050 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 108235656 ps |
| CPU time | 1.52 seconds |
| Started | Oct 14 11:45:02 PM UTC 24 |
| Finished | Oct 14 11:45:04 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488967050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1488967050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2435130006 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 208064988 ps |
| CPU time | 2.04 seconds |
| Started | Oct 14 11:45:00 PM UTC 24 |
| Finished | Oct 14 11:45:03 PM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435130006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2435130006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.4000400321 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 187541481 ps |
| CPU time | 2.2 seconds |
| Started | Oct 14 11:45:04 PM UTC 24 |
| Finished | Oct 14 11:45:07 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000400321 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.4000400321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.3952217588 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 264361331 ps |
| CPU time | 1.92 seconds |
| Started | Oct 14 11:45:02 PM UTC 24 |
| Finished | Oct 14 11:45:05 PM UTC 24 |
| Peak memory | 209724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952217588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3952217588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2220347573 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 146957889 ps |
| CPU time | 1.85 seconds |
| Started | Oct 14 11:45:02 PM UTC 24 |
| Finished | Oct 14 11:45:05 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220347573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2220347573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.3319831340 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 68314690 ps |
| CPU time | 1.18 seconds |
| Started | Oct 14 11:45:08 PM UTC 24 |
| Finished | Oct 14 11:45:11 PM UTC 24 |
| Peak memory | 209912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319831340 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3319831340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.905561267 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1977915300 ps |
| CPU time | 9.33 seconds |
| Started | Oct 14 11:45:07 PM UTC 24 |
| Finished | Oct 14 11:45:17 PM UTC 24 |
| Peak memory | 244212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905561267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.905561267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.4032785276 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 303035087 ps |
| CPU time | 1.66 seconds |
| Started | Oct 14 11:45:07 PM UTC 24 |
| Finished | Oct 14 11:45:10 PM UTC 24 |
| Peak memory | 239700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032785276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.4032785276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.1065994953 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 78498589 ps |
| CPU time | 1.08 seconds |
| Started | Oct 14 11:45:05 PM UTC 24 |
| Finished | Oct 14 11:45:08 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065994953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1065994953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.3442340774 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 854364604 ps |
| CPU time | 3.95 seconds |
| Started | Oct 14 11:45:05 PM UTC 24 |
| Finished | Oct 14 11:45:11 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442340774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3442340774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.9110913 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 126246387 ps |
| CPU time | 1.75 seconds |
| Started | Oct 14 11:45:04 PM UTC 24 |
| Finished | Oct 14 11:45:07 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9110913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r stmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.9110913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.3604200443 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 6781869941 ps |
| CPU time | 27.46 seconds |
| Started | Oct 14 11:45:08 PM UTC 24 |
| Finished | Oct 14 11:45:37 PM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604200443 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3604200443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.3435761952 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 318407497 ps |
| CPU time | 2.82 seconds |
| Started | Oct 14 11:45:06 PM UTC 24 |
| Finished | Oct 14 11:45:10 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435761952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3435761952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.64898093 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 273195984 ps |
| CPU time | 2.33 seconds |
| Started | Oct 14 11:45:05 PM UTC 24 |
| Finished | Oct 14 11:45:09 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64898093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.64898093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.623350933 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 71491923 ps |
| CPU time | 1.2 seconds |
| Started | Oct 14 11:45:13 PM UTC 24 |
| Finished | Oct 14 11:45:15 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623350933 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.623350933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.1856224775 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2431167808 ps |
| CPU time | 9.91 seconds |
| Started | Oct 14 11:45:11 PM UTC 24 |
| Finished | Oct 14 11:45:22 PM UTC 24 |
| Peak memory | 244216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856224775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1856224775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3164854247 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 301571150 ps |
| CPU time | 1.59 seconds |
| Started | Oct 14 11:45:11 PM UTC 24 |
| Finished | Oct 14 11:45:14 PM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164854247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3164854247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.947716497 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 119954983 ps |
| CPU time | 1.26 seconds |
| Started | Oct 14 11:45:08 PM UTC 24 |
| Finished | Oct 14 11:45:11 PM UTC 24 |
| Peak memory | 208320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947716497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.947716497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.2705985034 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1090373119 ps |
| CPU time | 5.17 seconds |
| Started | Oct 14 11:45:09 PM UTC 24 |
| Finished | Oct 14 11:45:15 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705985034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2705985034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.929178886 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 103830224 ps |
| CPU time | 1.11 seconds |
| Started | Oct 14 11:45:10 PM UTC 24 |
| Finished | Oct 14 11:45:12 PM UTC 24 |
| Peak memory | 209720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929178886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.929178886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.405331008 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 117526863 ps |
| CPU time | 1.69 seconds |
| Started | Oct 14 11:45:08 PM UTC 24 |
| Finished | Oct 14 11:45:11 PM UTC 24 |
| Peak memory | 208136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405331008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.405331008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.1766818735 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2507585922 ps |
| CPU time | 12.3 seconds |
| Started | Oct 14 11:45:11 PM UTC 24 |
| Finished | Oct 14 11:45:25 PM UTC 24 |
| Peak memory | 220344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766818735 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1766818735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.2855877906 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 149564463 ps |
| CPU time | 2.28 seconds |
| Started | Oct 14 11:45:10 PM UTC 24 |
| Finished | Oct 14 11:45:13 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855877906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2855877906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.2519945315 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 101149974 ps |
| CPU time | 1.27 seconds |
| Started | Oct 14 11:45:09 PM UTC 24 |
| Finished | Oct 14 11:45:11 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519945315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2519945315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.1602694117 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 55866692 ps |
| CPU time | 0.98 seconds |
| Started | Oct 14 11:45:15 PM UTC 24 |
| Finished | Oct 14 11:45:18 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602694117 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1602694117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.1865260787 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1276298536 ps |
| CPU time | 8.33 seconds |
| Started | Oct 14 11:45:13 PM UTC 24 |
| Finished | Oct 14 11:45:22 PM UTC 24 |
| Peak memory | 243924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865260787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1865260787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1205966173 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 301444172 ps |
| CPU time | 1.35 seconds |
| Started | Oct 14 11:45:14 PM UTC 24 |
| Finished | Oct 14 11:45:17 PM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205966173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1205966173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.761486599 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 169207863 ps |
| CPU time | 1.31 seconds |
| Started | Oct 14 11:45:13 PM UTC 24 |
| Finished | Oct 14 11:45:15 PM UTC 24 |
| Peak memory | 209668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761486599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.761486599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.1858302829 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1769627134 ps |
| CPU time | 7.43 seconds |
| Started | Oct 14 11:45:13 PM UTC 24 |
| Finished | Oct 14 11:45:21 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858302829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1858302829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.87959371 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 188861322 ps |
| CPU time | 1.37 seconds |
| Started | Oct 14 11:45:13 PM UTC 24 |
| Finished | Oct 14 11:45:15 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87959371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstm gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.87959371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.2439229809 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 249124301 ps |
| CPU time | 2.16 seconds |
| Started | Oct 14 11:45:13 PM UTC 24 |
| Finished | Oct 14 11:45:16 PM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439229809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2439229809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.2547042256 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 12398428926 ps |
| CPU time | 40.27 seconds |
| Started | Oct 14 11:45:14 PM UTC 24 |
| Finished | Oct 14 11:45:56 PM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547042256 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2547042256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.3658433960 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 122735552 ps |
| CPU time | 1.87 seconds |
| Started | Oct 14 11:45:13 PM UTC 24 |
| Finished | Oct 14 11:45:16 PM UTC 24 |
| Peak memory | 218968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658433960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3658433960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.633677941 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 83573361 ps |
| CPU time | 1.18 seconds |
| Started | Oct 14 11:45:13 PM UTC 24 |
| Finished | Oct 14 11:45:15 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633677941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.633677941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest |
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