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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T543 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.4096978226 Feb 09 06:26:29 AM UTC 25 Feb 09 06:27:15 AM UTC 25 15169315271 ps
T544 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.4212724784 Feb 09 06:26:45 AM UTC 25 Feb 09 06:27:22 AM UTC 25 11466249879 ps
T545 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.3442600485 Feb 09 06:26:47 AM UTC 25 Feb 09 06:27:23 AM UTC 25 9433444086 ps
T546 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.2519061947 Feb 09 06:26:56 AM UTC 25 Feb 09 06:27:29 AM UTC 25 10324270560 ps
T547 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.1866202026 Feb 09 06:26:52 AM UTC 25 Feb 09 06:27:30 AM UTC 25 11764455078 ps
T61 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.961369897 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:00 AM UTC 25 83203573 ps
T62 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1261054288 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:00 AM UTC 25 142825113 ps
T63 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1278852824 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:00 AM UTC 25 112695488 ps
T66 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4025502201 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:00 AM UTC 25 79908226 ps
T112 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.1766610707 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:01 AM UTC 25 67203935 ps
T64 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1208995854 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:01 AM UTC 25 203818208 ps
T65 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1058141180 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:01 AM UTC 25 269083090 ps
T70 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3995667715 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:01 AM UTC 25 481109357 ps
T120 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.2262793801 Feb 09 06:26:59 AM UTC 25 Feb 09 06:27:01 AM UTC 25 67116926 ps
T71 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.2716514146 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:01 AM UTC 25 175107074 ps
T548 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1060697254 Feb 09 06:26:59 AM UTC 25 Feb 09 06:27:01 AM UTC 25 143073373 ps
T113 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3250329569 Feb 09 06:26:59 AM UTC 25 Feb 09 06:27:01 AM UTC 25 130825312 ps
T72 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.2633322009 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:02 AM UTC 25 183037029 ps
T73 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.844945553 Feb 09 06:26:59 AM UTC 25 Feb 09 06:27:02 AM UTC 25 220496214 ps
T91 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3369888717 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:02 AM UTC 25 933207508 ps
T549 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3157436063 Feb 09 06:26:59 AM UTC 25 Feb 09 06:27:02 AM UTC 25 160241961 ps
T97 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2182185846 Feb 09 06:26:59 AM UTC 25 Feb 09 06:27:02 AM UTC 25 552618391 ps
T144 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2759778634 Feb 09 06:26:58 AM UTC 25 Feb 09 06:27:02 AM UTC 25 264083143 ps
T92 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.3707575297 Feb 09 06:26:59 AM UTC 25 Feb 09 06:27:03 AM UTC 25 270912160 ps
T93 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3459476111 Feb 09 06:27:00 AM UTC 25 Feb 09 06:27:03 AM UTC 25 121747886 ps
T550 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.789513876 Feb 09 06:27:01 AM UTC 25 Feb 09 06:27:03 AM UTC 25 82582426 ps
T551 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3983500433 Feb 09 06:27:01 AM UTC 25 Feb 09 06:27:03 AM UTC 25 149290540 ps
T114 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1873868113 Feb 09 06:27:00 AM UTC 25 Feb 09 06:27:03 AM UTC 25 142278188 ps
T552 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.705651457 Feb 09 06:27:00 AM UTC 25 Feb 09 06:27:03 AM UTC 25 206731223 ps
T94 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2882999268 Feb 09 06:27:00 AM UTC 25 Feb 09 06:27:03 AM UTC 25 105453211 ps
T553 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2649711321 Feb 09 06:26:59 AM UTC 25 Feb 09 06:27:04 AM UTC 25 268750595 ps
T115 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2516655319 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:04 AM UTC 25 115989837 ps
T554 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.503375786 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:04 AM UTC 25 114535652 ps
T95 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.203009081 Feb 09 06:27:00 AM UTC 25 Feb 09 06:27:04 AM UTC 25 783994022 ps
T96 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1830790533 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:05 AM UTC 25 187402986 ps
T98 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.432537337 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:05 AM UTC 25 269084539 ps
T555 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.299920477 Feb 09 06:27:00 AM UTC 25 Feb 09 06:27:06 AM UTC 25 804420862 ps
T143 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2338809339 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:06 AM UTC 25 956745337 ps
T116 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.4254127673 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:07 AM UTC 25 62488019 ps
T556 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3977333556 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:07 AM UTC 25 92196687 ps
T557 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3962614459 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:07 AM UTC 25 113823626 ps
T558 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3428997941 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:07 AM UTC 25 820796565 ps
T117 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1153519425 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:07 AM UTC 25 89538413 ps
T118 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.3573836009 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:08 AM UTC 25 83905586 ps
T559 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1659052486 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:08 AM UTC 25 190944038 ps
T560 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.226540235 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:08 AM UTC 25 246788257 ps
T119 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2754946066 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:08 AM UTC 25 277535949 ps
T561 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.4049605570 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:08 AM UTC 25 209607828 ps
T123 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.387564063 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:09 AM UTC 25 929278296 ps
T562 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.856706886 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:09 AM UTC 25 269150409 ps
T121 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.1537643240 Feb 09 06:27:02 AM UTC 25 Feb 09 06:27:09 AM UTC 25 407582291 ps
T563 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.2211060238 Feb 09 06:27:15 AM UTC 25 Feb 09 06:27:18 AM UTC 25 70409389 ps
T564 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.4002045586 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:23 AM UTC 25 63522335 ps
T565 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.2246125513 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:23 AM UTC 25 64105197 ps
T566 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3744496107 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:23 AM UTC 25 111068222 ps
T567 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.263876176 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:23 AM UTC 25 193247679 ps
T568 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1463506302 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:23 AM UTC 25 241909941 ps
T569 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3809309739 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:24 AM UTC 25 254414415 ps
T125 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3154464173 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:24 AM UTC 25 512664069 ps
T126 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.564629224 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:25 AM UTC 25 864529923 ps
T570 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2919770094 Feb 09 06:27:25 AM UTC 25 Feb 09 06:27:28 AM UTC 25 65610210 ps
T571 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1555852384 Feb 09 06:27:25 AM UTC 25 Feb 09 06:27:28 AM UTC 25 85279851 ps
T122 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2748041654 Feb 09 06:27:25 AM UTC 25 Feb 09 06:27:28 AM UTC 25 151273622 ps
T572 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3006135168 Feb 09 06:27:16 AM UTC 25 Feb 09 06:27:28 AM UTC 25 197536693 ps
T130 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.556850382 Feb 09 06:27:25 AM UTC 25 Feb 09 06:27:29 AM UTC 25 455873680 ps
T573 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.2543757737 Feb 09 06:27:28 AM UTC 25 Feb 09 06:27:33 AM UTC 25 78576811 ps
T574 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.2452797389 Feb 09 06:27:08 AM UTC 25 Feb 09 06:27:33 AM UTC 25 77026907 ps
T575 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.896790944 Feb 09 06:27:08 AM UTC 25 Feb 09 06:27:33 AM UTC 25 86283696 ps
T576 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2166336123 Feb 09 06:27:08 AM UTC 25 Feb 09 06:27:33 AM UTC 25 75858483 ps
T577 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.2812206179 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:33 AM UTC 25 104818563 ps
T578 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2987188510 Feb 09 06:27:08 AM UTC 25 Feb 09 06:27:34 AM UTC 25 206106876 ps
T579 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.750386388 Feb 09 06:27:08 AM UTC 25 Feb 09 06:27:34 AM UTC 25 218031949 ps
T580 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2944540889 Feb 09 06:27:11 AM UTC 25 Feb 09 06:27:34 AM UTC 25 139443342 ps
T131 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.911831550 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:34 AM UTC 25 285541192 ps
T581 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.1257316359 Feb 09 06:27:08 AM UTC 25 Feb 09 06:27:34 AM UTC 25 271153539 ps
T582 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.29972090 Feb 09 06:27:31 AM UTC 25 Feb 09 06:27:34 AM UTC 25 264369116 ps
T583 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.3158028003 Feb 09 06:27:29 AM UTC 25 Feb 09 06:27:35 AM UTC 25 55744286 ps
T584 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.847863249 Feb 09 06:27:11 AM UTC 25 Feb 09 06:27:35 AM UTC 25 249405299 ps
T585 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4037705354 Feb 09 06:27:11 AM UTC 25 Feb 09 06:27:35 AM UTC 25 205905087 ps
T586 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2629766450 Feb 09 06:27:29 AM UTC 25 Feb 09 06:27:35 AM UTC 25 144448896 ps
T587 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1113126035 Feb 09 06:27:29 AM UTC 25 Feb 09 06:27:35 AM UTC 25 139372698 ps
T128 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3942479188 Feb 09 06:27:08 AM UTC 25 Feb 09 06:27:35 AM UTC 25 801627393 ps
T141 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1319846419 Feb 09 06:27:08 AM UTC 25 Feb 09 06:27:35 AM UTC 25 795834623 ps
T129 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.150318447 Feb 09 06:27:29 AM UTC 25 Feb 09 06:27:35 AM UTC 25 425319711 ps
T588 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1179516847 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:36 AM UTC 25 76779687 ps
T589 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.2229072873 Feb 09 06:27:29 AM UTC 25 Feb 09 06:27:36 AM UTC 25 341657817 ps
T127 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3900096493 Feb 09 06:27:12 AM UTC 25 Feb 09 06:27:36 AM UTC 25 987250770 ps
T590 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4038627713 Feb 09 06:27:24 AM UTC 25 Feb 09 06:27:36 AM UTC 25 122941448 ps
T142 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1128901222 Feb 09 06:27:22 AM UTC 25 Feb 09 06:27:36 AM UTC 25 963489323 ps
T591 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1339983269 Feb 09 06:27:24 AM UTC 25 Feb 09 06:27:37 AM UTC 25 507116239 ps
T592 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3377839554 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:38 AM UTC 25 446331811 ps
T593 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.2976768158 Feb 09 06:27:05 AM UTC 25 Feb 09 06:27:38 AM UTC 25 54316677 ps
T594 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3704147303 Feb 09 06:27:05 AM UTC 25 Feb 09 06:27:39 AM UTC 25 172820764 ps
T595 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1860816697 Feb 09 06:27:05 AM UTC 25 Feb 09 06:27:39 AM UTC 25 139949847 ps
T596 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1477542221 Feb 09 06:27:05 AM UTC 25 Feb 09 06:27:39 AM UTC 25 132441855 ps
T597 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1812140969 Feb 09 06:27:19 AM UTC 25 Feb 09 06:27:39 AM UTC 25 158365518 ps
T598 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1179487976 Feb 09 06:27:25 AM UTC 25 Feb 09 06:27:40 AM UTC 25 374403566 ps
T599 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.511749675 Feb 09 06:27:19 AM UTC 25 Feb 09 06:27:40 AM UTC 25 451911765 ps
T600 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3618941445 Feb 09 06:27:05 AM UTC 25 Feb 09 06:27:41 AM UTC 25 1146252246 ps
T601 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.33356492 Feb 09 06:27:24 AM UTC 25 Feb 09 06:27:43 AM UTC 25 82819384 ps
T602 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.428908578 Feb 09 06:27:24 AM UTC 25 Feb 09 06:27:43 AM UTC 25 218661281 ps
T603 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2592362023 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:44 AM UTC 25 428400957 ps
T604 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.945138014 Feb 09 06:27:05 AM UTC 25 Feb 09 06:27:48 AM UTC 25 70608552 ps
T605 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.2845682484 Feb 09 06:27:09 AM UTC 25 Feb 09 06:27:49 AM UTC 25 54331871 ps
T606 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2665612854 Feb 09 06:27:09 AM UTC 25 Feb 09 06:27:49 AM UTC 25 167197581 ps
T607 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2690673260 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:49 AM UTC 25 62326133 ps
T608 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.4172034244 Feb 09 06:27:07 AM UTC 25 Feb 09 06:27:49 AM UTC 25 72860587 ps
T609 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1466717709 Feb 09 06:27:07 AM UTC 25 Feb 09 06:27:49 AM UTC 25 115857982 ps
T610 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1346748427 Feb 09 06:27:05 AM UTC 25 Feb 09 06:27:49 AM UTC 25 210202476 ps
T611 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1148398293 Feb 09 06:27:07 AM UTC 25 Feb 09 06:27:49 AM UTC 25 133285882 ps
T612 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3569955459 Feb 09 06:27:07 AM UTC 25 Feb 09 06:27:50 AM UTC 25 479827928 ps
T124 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1915563283 Feb 09 06:27:09 AM UTC 25 Feb 09 06:27:50 AM UTC 25 474360318 ps
T613 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.921583631 Feb 09 06:27:04 AM UTC 25 Feb 09 06:27:50 AM UTC 25 202532434 ps
T614 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.3715072975 Feb 09 06:27:24 AM UTC 25 Feb 09 06:27:50 AM UTC 25 118832510 ps
T615 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.1437329817 Feb 09 06:27:09 AM UTC 25 Feb 09 06:27:51 AM UTC 25 399703995 ps
T616 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.1024952913 Feb 09 06:27:05 AM UTC 25 Feb 09 06:27:51 AM UTC 25 414776238 ps
T617 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.3730604826 Feb 09 06:27:07 AM UTC 25 Feb 09 06:27:51 AM UTC 25 211818373 ps
T618 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1135432169 Feb 09 06:27:34 AM UTC 25 Feb 09 06:27:53 AM UTC 25 115565748 ps
T619 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1665213527 Feb 09 06:27:05 AM UTC 25 Feb 09 06:27:53 AM UTC 25 2448096516 ps
T620 /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.552980562 Feb 09 06:27:07 AM UTC 25 Feb 09 06:27:55 AM UTC 25 183272380 ps

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.1767246799
Short name T1
Test name
Test status
Simulation time 224415388 ps
CPU time 2.3 seconds
Started Feb 09 06:24:26 AM UTC 25
Finished Feb 09 06:24:30 AM UTC 25
Peak memory 209116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767246799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.rstmgr_smoke.1767246799
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.2327284944
Short name T60
Test name
Test status
Simulation time 395124543 ps
CPU time 3.08 seconds
Started Feb 09 06:24:37 AM UTC 25
Finished Feb 09 06:24:41 AM UTC 25
Peak memory 208580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327284944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.rstmgr_sw_rst.2327284944
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1208995854
Short name T64
Test name
Test status
Simulation time 203818208 ps
CPU time 1.32 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 216328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208995
854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1208995854
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.1120841632
Short name T13
Test name
Test status
Simulation time 1227383222 ps
CPU time 9.7 seconds
Started Feb 09 06:24:31 AM UTC 25
Finished Feb 09 06:24:42 AM UTC 25
Peak memory 241444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120841632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1120841632
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.3833195128
Short name T67
Test name
Test status
Simulation time 16520708435 ps
CPU time 31.06 seconds
Started Feb 09 06:24:34 AM UTC 25
Finished Feb 09 06:25:06 AM UTC 25
Peak memory 241616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833195128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3833195128
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.1292251905
Short name T87
Test name
Test status
Simulation time 7407260988 ps
CPU time 38.03 seconds
Started Feb 09 06:24:34 AM UTC 25
Finished Feb 09 06:25:13 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292251905 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1292251905
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3369888717
Short name T91
Test name
Test status
Simulation time 933207508 ps
CPU time 3.1 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:02 AM UTC 25
Peak memory 208664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369888717 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.3369888717
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.1437425196
Short name T108
Test name
Test status
Simulation time 10663147832 ps
CPU time 35.06 seconds
Started Feb 09 06:25:15 AM UTC 25
Finished Feb 09 06:25:51 AM UTC 25
Peak memory 225264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437425196 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1437425196
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.2633322009
Short name T72
Test name
Test status
Simulation time 183037029 ps
CPU time 2.39 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:02 AM UTC 25
Peak memory 217524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633322009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2633322009
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2610166542
Short name T4
Test name
Test status
Simulation time 149287374 ps
CPU time 1.65 seconds
Started Feb 09 06:24:31 AM UTC 25
Finished Feb 09 06:24:34 AM UTC 25
Peak memory 207524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610166542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2610166542
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.3869311740
Short name T7
Test name
Test status
Simulation time 72149045 ps
CPU time 1.22 seconds
Started Feb 09 06:24:34 AM UTC 25
Finished Feb 09 06:24:36 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869311740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3869311740
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.2257221653
Short name T28
Test name
Test status
Simulation time 1884967640 ps
CPU time 12.03 seconds
Started Feb 09 06:25:24 AM UTC 25
Finished Feb 09 06:25:37 AM UTC 25
Peak memory 240404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257221653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2257221653
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.4220703137
Short name T83
Test name
Test status
Simulation time 1716993016 ps
CPU time 9.45 seconds
Started Feb 09 06:25:10 AM UTC 25
Finished Feb 09 06:25:21 AM UTC 25
Peak memory 208916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220703137 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.4220703137
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3900096493
Short name T127
Test name
Test status
Simulation time 987250770 ps
CPU time 2.85 seconds
Started Feb 09 06:27:12 AM UTC 25
Finished Feb 09 06:27:36 AM UTC 25
Peak memory 208664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900096493 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.3900096493
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1827038777
Short name T3
Test name
Test status
Simulation time 267365836 ps
CPU time 1.73 seconds
Started Feb 09 06:24:30 AM UTC 25
Finished Feb 09 06:24:33 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827038777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1827038777
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.54230150
Short name T58
Test name
Test status
Simulation time 1219961788 ps
CPU time 5.82 seconds
Started Feb 09 06:25:15 AM UTC 25
Finished Feb 09 06:25:22 AM UTC 25
Peak memory 241468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54230150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf
_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.54230150
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.556850382
Short name T130
Test name
Test status
Simulation time 455873680 ps
CPU time 1.46 seconds
Started Feb 09 06:27:25 AM UTC 25
Finished Feb 09 06:27:29 AM UTC 25
Peak memory 207620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556850382 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.556850382
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.961369897
Short name T61
Test name
Test status
Simulation time 83203573 ps
CPU time 0.95 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:00 AM UTC 25
Peak memory 207852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961369897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.961369897
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.3175526848
Short name T2
Test name
Test status
Simulation time 214482634 ps
CPU time 1.74 seconds
Started Feb 09 06:24:28 AM UTC 25
Finished Feb 09 06:24:31 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175526848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3175526848
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1915563283
Short name T124
Test name
Test status
Simulation time 474360318 ps
CPU time 1.88 seconds
Started Feb 09 06:27:09 AM UTC 25
Finished Feb 09 06:27:50 AM UTC 25
Peak memory 207656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915563283 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.1915563283
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.3057837499
Short name T233
Test name
Test status
Simulation time 4617034334 ps
CPU time 28.78 seconds
Started Feb 09 06:25:33 AM UTC 25
Finished Feb 09 06:26:03 AM UTC 25
Peak memory 217764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057837499 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3057837499
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1058141180
Short name T65
Test name
Test status
Simulation time 269083090 ps
CPU time 1.8 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 207620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058141180 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1058141180
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2759778634
Short name T144
Test name
Test status
Simulation time 264083143 ps
CPU time 3.22 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:02 AM UTC 25
Peak memory 208668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759778634 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2759778634
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1278852824
Short name T63
Test name
Test status
Simulation time 112695488 ps
CPU time 1.29 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:00 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278852824 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1278852824
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4025502201
Short name T66
Test name
Test status
Simulation time 79908226 ps
CPU time 1.09 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:00 AM UTC 25
Peak memory 207560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025502201 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.4025502201
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.2716514146
Short name T71
Test name
Test status
Simulation time 175107074 ps
CPU time 2.39 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 221868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716514146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2716514146
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3157436063
Short name T549
Test name
Test status
Simulation time 160241961 ps
CPU time 1.86 seconds
Started Feb 09 06:26:59 AM UTC 25
Finished Feb 09 06:27:02 AM UTC 25
Peak memory 207620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157436063 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3157436063
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2649711321
Short name T553
Test name
Test status
Simulation time 268750595 ps
CPU time 3.11 seconds
Started Feb 09 06:26:59 AM UTC 25
Finished Feb 09 06:27:04 AM UTC 25
Peak memory 208552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649711321 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2649711321
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1261054288
Short name T62
Test name
Test status
Simulation time 142825113 ps
CPU time 0.94 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:00 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261054288 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1261054288
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.844945553
Short name T73
Test name
Test status
Simulation time 220496214 ps
CPU time 1.3 seconds
Started Feb 09 06:26:59 AM UTC 25
Finished Feb 09 06:27:02 AM UTC 25
Peak memory 216372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8449455
53 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.844945553
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.1766610707
Short name T112
Test name
Test status
Simulation time 67203935 ps
CPU time 1.14 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766610707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1766610707
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3250329569
Short name T113
Test name
Test status
Simulation time 130825312 ps
CPU time 1.06 seconds
Started Feb 09 06:26:59 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250329569 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.3250329569
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3995667715
Short name T70
Test name
Test status
Simulation time 481109357 ps
CPU time 1.94 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 207616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995667715 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.3995667715
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1346748427
Short name T610
Test name
Test status
Simulation time 210202476 ps
CPU time 1.42 seconds
Started Feb 09 06:27:05 AM UTC 25
Finished Feb 09 06:27:49 AM UTC 25
Peak memory 216392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346748
427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1346748427
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.945138014
Short name T604
Test name
Test status
Simulation time 70608552 ps
CPU time 0.71 seconds
Started Feb 09 06:27:05 AM UTC 25
Finished Feb 09 06:27:48 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945138014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.945138014
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1477542221
Short name T596
Test name
Test status
Simulation time 132441855 ps
CPU time 1.08 seconds
Started Feb 09 06:27:05 AM UTC 25
Finished Feb 09 06:27:39 AM UTC 25
Peak memory 207676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477542221 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.1477542221
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.1024952913
Short name T616
Test name
Test status
Simulation time 414776238 ps
CPU time 2.87 seconds
Started Feb 09 06:27:05 AM UTC 25
Finished Feb 09 06:27:51 AM UTC 25
Peak memory 217700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024952913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1024952913
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1665213527
Short name T619
Test name
Test status
Simulation time 2448096516 ps
CPU time 5.75 seconds
Started Feb 09 06:27:05 AM UTC 25
Finished Feb 09 06:27:53 AM UTC 25
Peak memory 208728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665213527 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.1665213527
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1466717709
Short name T609
Test name
Test status
Simulation time 115857982 ps
CPU time 0.88 seconds
Started Feb 09 06:27:07 AM UTC 25
Finished Feb 09 06:27:49 AM UTC 25
Peak memory 207612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466717
709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1466717709
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.4172034244
Short name T608
Test name
Test status
Simulation time 72860587 ps
CPU time 1.02 seconds
Started Feb 09 06:27:07 AM UTC 25
Finished Feb 09 06:27:49 AM UTC 25
Peak memory 207080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172034244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4172034244
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1148398293
Short name T611
Test name
Test status
Simulation time 133285882 ps
CPU time 1.32 seconds
Started Feb 09 06:27:07 AM UTC 25
Finished Feb 09 06:27:49 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148398293 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.1148398293
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.552980562
Short name T620
Test name
Test status
Simulation time 183272380 ps
CPU time 2.58 seconds
Started Feb 09 06:27:07 AM UTC 25
Finished Feb 09 06:27:55 AM UTC 25
Peak memory 221796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552980562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UV
M_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.552980562
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3569955459
Short name T612
Test name
Test status
Simulation time 479827928 ps
CPU time 1.74 seconds
Started Feb 09 06:27:07 AM UTC 25
Finished Feb 09 06:27:50 AM UTC 25
Peak memory 207052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569955459 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.3569955459
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2987188510
Short name T578
Test name
Test status
Simulation time 206106876 ps
CPU time 1.19 seconds
Started Feb 09 06:27:08 AM UTC 25
Finished Feb 09 06:27:34 AM UTC 25
Peak memory 216388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987188
510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2987188510
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.2452797389
Short name T574
Test name
Test status
Simulation time 77026907 ps
CPU time 0.68 seconds
Started Feb 09 06:27:08 AM UTC 25
Finished Feb 09 06:27:33 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452797389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2452797389
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.750386388
Short name T579
Test name
Test status
Simulation time 218031949 ps
CPU time 1.31 seconds
Started Feb 09 06:27:08 AM UTC 25
Finished Feb 09 06:27:34 AM UTC 25
Peak memory 207680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750386388 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rs
tmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.750386388
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.3730604826
Short name T617
Test name
Test status
Simulation time 211818373 ps
CPU time 2.91 seconds
Started Feb 09 06:27:07 AM UTC 25
Finished Feb 09 06:27:51 AM UTC 25
Peak memory 217700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730604826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3730604826
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3942479188
Short name T128
Test name
Test status
Simulation time 801627393 ps
CPU time 2.58 seconds
Started Feb 09 06:27:08 AM UTC 25
Finished Feb 09 06:27:35 AM UTC 25
Peak memory 208644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942479188 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.3942479188
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2665612854
Short name T606
Test name
Test status
Simulation time 167197581 ps
CPU time 1.06 seconds
Started Feb 09 06:27:09 AM UTC 25
Finished Feb 09 06:27:49 AM UTC 25
Peak memory 207676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665612
854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2665612854
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.896790944
Short name T575
Test name
Test status
Simulation time 86283696 ps
CPU time 0.72 seconds
Started Feb 09 06:27:08 AM UTC 25
Finished Feb 09 06:27:33 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896790944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.896790944
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2166336123
Short name T576
Test name
Test status
Simulation time 75858483 ps
CPU time 0.8 seconds
Started Feb 09 06:27:08 AM UTC 25
Finished Feb 09 06:27:33 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166336123 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.2166336123
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.1257316359
Short name T581
Test name
Test status
Simulation time 271153539 ps
CPU time 1.86 seconds
Started Feb 09 06:27:08 AM UTC 25
Finished Feb 09 06:27:34 AM UTC 25
Peak memory 217660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257316359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1257316359
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1319846419
Short name T141
Test name
Test status
Simulation time 795834623 ps
CPU time 2.47 seconds
Started Feb 09 06:27:08 AM UTC 25
Finished Feb 09 06:27:35 AM UTC 25
Peak memory 208664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319846419 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.1319846419
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4037705354
Short name T585
Test name
Test status
Simulation time 205905087 ps
CPU time 1.73 seconds
Started Feb 09 06:27:11 AM UTC 25
Finished Feb 09 06:27:35 AM UTC 25
Peak memory 215816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037705
354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.4037705354
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.2845682484
Short name T605
Test name
Test status
Simulation time 54331871 ps
CPU time 0.77 seconds
Started Feb 09 06:27:09 AM UTC 25
Finished Feb 09 06:27:49 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845682484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2845682484
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2944540889
Short name T580
Test name
Test status
Simulation time 139443342 ps
CPU time 0.95 seconds
Started Feb 09 06:27:11 AM UTC 25
Finished Feb 09 06:27:34 AM UTC 25
Peak memory 207656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944540889 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.2944540889
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.1437329817
Short name T615
Test name
Test status
Simulation time 399703995 ps
CPU time 2.81 seconds
Started Feb 09 06:27:09 AM UTC 25
Finished Feb 09 06:27:51 AM UTC 25
Peak memory 217648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437329817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1437329817
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1812140969
Short name T597
Test name
Test status
Simulation time 158365518 ps
CPU time 1.29 seconds
Started Feb 09 06:27:19 AM UTC 25
Finished Feb 09 06:27:39 AM UTC 25
Peak memory 217664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812140
969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1812140969
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.2211060238
Short name T563
Test name
Test status
Simulation time 70409389 ps
CPU time 0.64 seconds
Started Feb 09 06:27:15 AM UTC 25
Finished Feb 09 06:27:18 AM UTC 25
Peak memory 207596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211060238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2211060238
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3006135168
Short name T572
Test name
Test status
Simulation time 197536693 ps
CPU time 1.18 seconds
Started Feb 09 06:27:16 AM UTC 25
Finished Feb 09 06:27:28 AM UTC 25
Peak memory 207680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006135168 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.3006135168
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.847863249
Short name T584
Test name
Test status
Simulation time 249405299 ps
CPU time 1.69 seconds
Started Feb 09 06:27:11 AM UTC 25
Finished Feb 09 06:27:35 AM UTC 25
Peak memory 217716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847863249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UV
M_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.847863249
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4038627713
Short name T590
Test name
Test status
Simulation time 122941448 ps
CPU time 1.15 seconds
Started Feb 09 06:27:24 AM UTC 25
Finished Feb 09 06:27:36 AM UTC 25
Peak memory 216392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038627
713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.4038627713
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.33356492
Short name T601
Test name
Test status
Simulation time 82819384 ps
CPU time 0.73 seconds
Started Feb 09 06:27:24 AM UTC 25
Finished Feb 09 06:27:43 AM UTC 25
Peak memory 207656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33356492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +
UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.33356492
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.428908578
Short name T602
Test name
Test status
Simulation time 218661281 ps
CPU time 1.25 seconds
Started Feb 09 06:27:24 AM UTC 25
Finished Feb 09 06:27:43 AM UTC 25
Peak memory 207680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428908578 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rs
tmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.428908578
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.511749675
Short name T599
Test name
Test status
Simulation time 451911765 ps
CPU time 2.59 seconds
Started Feb 09 06:27:19 AM UTC 25
Finished Feb 09 06:27:40 AM UTC 25
Peak memory 225236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511749675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UV
M_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.511749675
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1128901222
Short name T142
Test name
Test status
Simulation time 963489323 ps
CPU time 2.74 seconds
Started Feb 09 06:27:22 AM UTC 25
Finished Feb 09 06:27:36 AM UTC 25
Peak memory 208708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128901222 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.1128901222
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2748041654
Short name T122
Test name
Test status
Simulation time 151273622 ps
CPU time 1.07 seconds
Started Feb 09 06:27:25 AM UTC 25
Finished Feb 09 06:27:28 AM UTC 25
Peak memory 216452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748041
654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2748041654
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2919770094
Short name T570
Test name
Test status
Simulation time 65610210 ps
CPU time 0.65 seconds
Started Feb 09 06:27:25 AM UTC 25
Finished Feb 09 06:27:28 AM UTC 25
Peak memory 207244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919770094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2919770094
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1555852384
Short name T571
Test name
Test status
Simulation time 85279851 ps
CPU time 0.78 seconds
Started Feb 09 06:27:25 AM UTC 25
Finished Feb 09 06:27:28 AM UTC 25
Peak memory 207244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555852384 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.1555852384
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.3715072975
Short name T614
Test name
Test status
Simulation time 118832510 ps
CPU time 1.62 seconds
Started Feb 09 06:27:24 AM UTC 25
Finished Feb 09 06:27:50 AM UTC 25
Peak memory 217660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715072975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3715072975
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1339983269
Short name T591
Test name
Test status
Simulation time 507116239 ps
CPU time 1.62 seconds
Started Feb 09 06:27:24 AM UTC 25
Finished Feb 09 06:27:37 AM UTC 25
Peak memory 207616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339983269 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.1339983269
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1113126035
Short name T587
Test name
Test status
Simulation time 139372698 ps
CPU time 0.94 seconds
Started Feb 09 06:27:29 AM UTC 25
Finished Feb 09 06:27:35 AM UTC 25
Peak memory 216288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113126
035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1113126035
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.2543757737
Short name T573
Test name
Test status
Simulation time 78576811 ps
CPU time 0.68 seconds
Started Feb 09 06:27:28 AM UTC 25
Finished Feb 09 06:27:33 AM UTC 25
Peak memory 207596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543757737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2543757737
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2629766450
Short name T586
Test name
Test status
Simulation time 144448896 ps
CPU time 0.95 seconds
Started Feb 09 06:27:29 AM UTC 25
Finished Feb 09 06:27:35 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629766450 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.2629766450
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1179487976
Short name T598
Test name
Test status
Simulation time 374403566 ps
CPU time 2.25 seconds
Started Feb 09 06:27:25 AM UTC 25
Finished Feb 09 06:27:40 AM UTC 25
Peak memory 225028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179487976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1179487976
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1135432169
Short name T618
Test name
Test status
Simulation time 115565748 ps
CPU time 1.21 seconds
Started Feb 09 06:27:34 AM UTC 25
Finished Feb 09 06:27:53 AM UTC 25
Peak memory 216392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135432
169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1135432169
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.3158028003
Short name T583
Test name
Test status
Simulation time 55744286 ps
CPU time 0.64 seconds
Started Feb 09 06:27:29 AM UTC 25
Finished Feb 09 06:27:35 AM UTC 25
Peak memory 207596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158028003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3158028003
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.29972090
Short name T582
Test name
Test status
Simulation time 264369116 ps
CPU time 1.33 seconds
Started Feb 09 06:27:31 AM UTC 25
Finished Feb 09 06:27:34 AM UTC 25
Peak memory 205936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29972090 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rst
mgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.29972090
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.2229072873
Short name T589
Test name
Test status
Simulation time 341657817 ps
CPU time 2.07 seconds
Started Feb 09 06:27:29 AM UTC 25
Finished Feb 09 06:27:36 AM UTC 25
Peak memory 217572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229072873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2229072873
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.150318447
Short name T129
Test name
Test status
Simulation time 425319711 ps
CPU time 1.51 seconds
Started Feb 09 06:27:29 AM UTC 25
Finished Feb 09 06:27:35 AM UTC 25
Peak memory 207620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150318447 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.150318447
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.705651457
Short name T552
Test name
Test status
Simulation time 206731223 ps
CPU time 1.65 seconds
Started Feb 09 06:27:00 AM UTC 25
Finished Feb 09 06:27:03 AM UTC 25
Peak memory 207616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705651457 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.705651457
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.299920477
Short name T555
Test name
Test status
Simulation time 804420862 ps
CPU time 4.11 seconds
Started Feb 09 06:27:00 AM UTC 25
Finished Feb 09 06:27:06 AM UTC 25
Peak memory 208664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299920477 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.299920477
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1060697254
Short name T548
Test name
Test status
Simulation time 143073373 ps
CPU time 1 seconds
Started Feb 09 06:26:59 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 207588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060697254 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1060697254
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3459476111
Short name T93
Test name
Test status
Simulation time 121747886 ps
CPU time 0.91 seconds
Started Feb 09 06:27:00 AM UTC 25
Finished Feb 09 06:27:03 AM UTC 25
Peak memory 207612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459476
111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3459476111
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.2262793801
Short name T120
Test name
Test status
Simulation time 67116926 ps
CPU time 0.72 seconds
Started Feb 09 06:26:59 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262793801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2262793801
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1873868113
Short name T114
Test name
Test status
Simulation time 142278188 ps
CPU time 1.18 seconds
Started Feb 09 06:27:00 AM UTC 25
Finished Feb 09 06:27:03 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873868113 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.1873868113
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.3707575297
Short name T92
Test name
Test status
Simulation time 270912160 ps
CPU time 2.15 seconds
Started Feb 09 06:26:59 AM UTC 25
Finished Feb 09 06:27:03 AM UTC 25
Peak memory 221796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707575297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3707575297
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2182185846
Short name T97
Test name
Test status
Simulation time 552618391 ps
CPU time 1.85 seconds
Started Feb 09 06:26:59 AM UTC 25
Finished Feb 09 06:27:02 AM UTC 25
Peak memory 207616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182185846 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.2182185846
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.503375786
Short name T554
Test name
Test status
Simulation time 114535652 ps
CPU time 1.23 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:04 AM UTC 25
Peak memory 217528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503375786 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.503375786
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3428997941
Short name T558
Test name
Test status
Simulation time 820796565 ps
CPU time 4.18 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:07 AM UTC 25
Peak memory 208652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428997941 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3428997941
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3983500433
Short name T551
Test name
Test status
Simulation time 149290540 ps
CPU time 0.92 seconds
Started Feb 09 06:27:01 AM UTC 25
Finished Feb 09 06:27:03 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983500433 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3983500433
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1830790533
Short name T96
Test name
Test status
Simulation time 187402986 ps
CPU time 1.68 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:05 AM UTC 25
Peak memory 217664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830790
533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1830790533
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.789513876
Short name T550
Test name
Test status
Simulation time 82582426 ps
CPU time 0.79 seconds
Started Feb 09 06:27:01 AM UTC 25
Finished Feb 09 06:27:03 AM UTC 25
Peak memory 207600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789513876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.789513876
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2516655319
Short name T115
Test name
Test status
Simulation time 115989837 ps
CPU time 1.09 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:04 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516655319 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.2516655319
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2882999268
Short name T94
Test name
Test status
Simulation time 105453211 ps
CPU time 1.59 seconds
Started Feb 09 06:27:00 AM UTC 25
Finished Feb 09 06:27:03 AM UTC 25
Peak memory 219696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882999268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2882999268
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.203009081
Short name T95
Test name
Test status
Simulation time 783994022 ps
CPU time 2.68 seconds
Started Feb 09 06:27:00 AM UTC 25
Finished Feb 09 06:27:04 AM UTC 25
Peak memory 208668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203009081 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.203009081
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.226540235
Short name T560
Test name
Test status
Simulation time 246788257 ps
CPU time 1.54 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:08 AM UTC 25
Peak memory 207680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226540235 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.226540235
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.856706886
Short name T562
Test name
Test status
Simulation time 269150409 ps
CPU time 2.89 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:09 AM UTC 25
Peak memory 208876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856706886 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.856706886
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3977333556
Short name T556
Test name
Test status
Simulation time 92196687 ps
CPU time 0.81 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:07 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977333556 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3977333556
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3962614459
Short name T557
Test name
Test status
Simulation time 113823626 ps
CPU time 0.9 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:07 AM UTC 25
Peak memory 207612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962614
459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3962614459
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.4254127673
Short name T116
Test name
Test status
Simulation time 62488019 ps
CPU time 0.79 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:07 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254127673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.4254127673
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1153519425
Short name T117
Test name
Test status
Simulation time 89538413 ps
CPU time 0.91 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:07 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153519425 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.1153519425
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.432537337
Short name T98
Test name
Test status
Simulation time 269084539 ps
CPU time 1.95 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:05 AM UTC 25
Peak memory 217708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432537337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UV
M_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.432537337
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2338809339
Short name T143
Test name
Test status
Simulation time 956745337 ps
CPU time 2.89 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:06 AM UTC 25
Peak memory 208664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338809339 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.2338809339
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1659052486
Short name T559
Test name
Test status
Simulation time 190944038 ps
CPU time 1.13 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:08 AM UTC 25
Peak memory 216452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659052
486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1659052486
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.3573836009
Short name T118
Test name
Test status
Simulation time 83905586 ps
CPU time 0.84 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:08 AM UTC 25
Peak memory 206464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573836009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3573836009
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2754946066
Short name T119
Test name
Test status
Simulation time 277535949 ps
CPU time 1.47 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:08 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754946066 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.2754946066
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.4049605570
Short name T561
Test name
Test status
Simulation time 209607828 ps
CPU time 1.55 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:08 AM UTC 25
Peak memory 217700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049605570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.4049605570
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.387564063
Short name T123
Test name
Test status
Simulation time 929278296 ps
CPU time 2.67 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:09 AM UTC 25
Peak memory 208088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387564063 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.387564063
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.921583631
Short name T613
Test name
Test status
Simulation time 202532434 ps
CPU time 1.48 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:50 AM UTC 25
Peak memory 216388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9215836
31 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.921583631
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2690673260
Short name T607
Test name
Test status
Simulation time 62326133 ps
CPU time 0.78 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:49 AM UTC 25
Peak memory 207604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690673260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2690673260
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1179516847
Short name T588
Test name
Test status
Simulation time 76779687 ps
CPU time 0.83 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:36 AM UTC 25
Peak memory 207600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179516847 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.1179516847
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.1537643240
Short name T121
Test name
Test status
Simulation time 407582291 ps
CPU time 2.64 seconds
Started Feb 09 06:27:02 AM UTC 25
Finished Feb 09 06:27:09 AM UTC 25
Peak memory 221816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537643240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1537643240
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2592362023
Short name T603
Test name
Test status
Simulation time 428400957 ps
CPU time 1.57 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:44 AM UTC 25
Peak memory 207536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592362023 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.2592362023
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3744496107
Short name T566
Test name
Test status
Simulation time 111068222 ps
CPU time 0.83 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:23 AM UTC 25
Peak memory 207612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744496
107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3744496107
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.4002045586
Short name T564
Test name
Test status
Simulation time 63522335 ps
CPU time 0.75 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:23 AM UTC 25
Peak memory 207368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002045586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.4002045586
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1463506302
Short name T568
Test name
Test status
Simulation time 241909941 ps
CPU time 1.43 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:23 AM UTC 25
Peak memory 207404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463506302 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.1463506302
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3377839554
Short name T592
Test name
Test status
Simulation time 446331811 ps
CPU time 2.71 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:38 AM UTC 25
Peak memory 221688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377839554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3377839554
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3154464173
Short name T125
Test name
Test status
Simulation time 512664069 ps
CPU time 1.67 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:24 AM UTC 25
Peak memory 207616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154464173 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.3154464173
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.263876176
Short name T567
Test name
Test status
Simulation time 193247679 ps
CPU time 1.03 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:23 AM UTC 25
Peak memory 216444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638761
76 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.263876176
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.2246125513
Short name T565
Test name
Test status
Simulation time 64105197 ps
CPU time 0.71 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:23 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246125513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2246125513
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3809309739
Short name T569
Test name
Test status
Simulation time 254414415 ps
CPU time 1.39 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:24 AM UTC 25
Peak memory 207744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809309739 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.3809309739
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.911831550
Short name T131
Test name
Test status
Simulation time 285541192 ps
CPU time 1.93 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:34 AM UTC 25
Peak memory 217656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911831550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UV
M_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.911831550
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.564629224
Short name T126
Test name
Test status
Simulation time 864529923 ps
CPU time 2.37 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:25 AM UTC 25
Peak memory 208724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564629224 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.564629224
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3704147303
Short name T594
Test name
Test status
Simulation time 172820764 ps
CPU time 1.04 seconds
Started Feb 09 06:27:05 AM UTC 25
Finished Feb 09 06:27:39 AM UTC 25
Peak memory 207676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704147
303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3704147303
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.2976768158
Short name T593
Test name
Test status
Simulation time 54316677 ps
CPU time 0.66 seconds
Started Feb 09 06:27:05 AM UTC 25
Finished Feb 09 06:27:38 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976768158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2976768158
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1860816697
Short name T595
Test name
Test status
Simulation time 139949847 ps
CPU time 1.14 seconds
Started Feb 09 06:27:05 AM UTC 25
Finished Feb 09 06:27:39 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860816697 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.1860816697
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.2812206179
Short name T577
Test name
Test status
Simulation time 104818563 ps
CPU time 1.28 seconds
Started Feb 09 06:27:04 AM UTC 25
Finished Feb 09 06:27:33 AM UTC 25
Peak memory 223824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812206179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +U
VM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2812206179
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3618941445
Short name T600
Test name
Test status
Simulation time 1146252246 ps
CPU time 3 seconds
Started Feb 09 06:27:05 AM UTC 25
Finished Feb 09 06:27:41 AM UTC 25
Peak memory 208648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618941445 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.3618941445
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1667754724
Short name T6
Test name
Test status
Simulation time 243153854 ps
CPU time 1.79 seconds
Started Feb 09 06:24:33 AM UTC 25
Finished Feb 09 06:24:36 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667754724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1667754724
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.2061686839
Short name T8
Test name
Test status
Simulation time 1478341851 ps
CPU time 6.72 seconds
Started Feb 09 06:24:28 AM UTC 25
Finished Feb 09 06:24:36 AM UTC 25
Peak memory 208796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061686839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.rstmgr_reset.2061686839
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.2507044772
Short name T5
Test name
Test status
Simulation time 280733076 ps
CPU time 3.07 seconds
Started Feb 09 06:24:30 AM UTC 25
Finished Feb 09 06:24:35 AM UTC 25
Peak memory 208728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507044772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.rstmgr_sw_rst.2507044772
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.3572883868
Short name T50
Test name
Test status
Simulation time 70118111 ps
CPU time 1.15 seconds
Started Feb 09 06:24:40 AM UTC 25
Finished Feb 09 06:24:43 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572883868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3572883868
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.2270872283
Short name T25
Test name
Test status
Simulation time 1887456571 ps
CPU time 10.49 seconds
Started Feb 09 06:24:39 AM UTC 25
Finished Feb 09 06:24:51 AM UTC 25
Peak memory 241856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270872283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2270872283
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.631433239
Short name T24
Test name
Test status
Simulation time 244787133 ps
CPU time 1.84 seconds
Started Feb 09 06:24:39 AM UTC 25
Finished Feb 09 06:24:42 AM UTC 25
Peak memory 236720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631433239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.631433239
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.1677356467
Short name T10
Test name
Test status
Simulation time 83329139 ps
CPU time 1.19 seconds
Started Feb 09 06:24:36 AM UTC 25
Finished Feb 09 06:24:38 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677356467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1677356467
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.278796492
Short name T22
Test name
Test status
Simulation time 1189621729 ps
CPU time 5.73 seconds
Started Feb 09 06:24:36 AM UTC 25
Finished Feb 09 06:24:43 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278796492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.rstmgr_reset.278796492
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.510208148
Short name T75
Test name
Test status
Simulation time 26367940565 ps
CPU time 59.73 seconds
Started Feb 09 06:24:39 AM UTC 25
Finished Feb 09 06:25:41 AM UTC 25
Peak memory 241992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510208148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.510208148
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3107854672
Short name T12
Test name
Test status
Simulation time 144452542 ps
CPU time 1.63 seconds
Started Feb 09 06:24:37 AM UTC 25
Finished Feb 09 06:24:40 AM UTC 25
Peak memory 207448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107854672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3107854672
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.2429174370
Short name T9
Test name
Test status
Simulation time 188909330 ps
CPU time 2.06 seconds
Started Feb 09 06:24:35 AM UTC 25
Finished Feb 09 06:24:38 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429174370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.rstmgr_smoke.2429174370
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.103570103
Short name T56
Test name
Test status
Simulation time 110198890 ps
CPU time 1.32 seconds
Started Feb 09 06:24:39 AM UTC 25
Finished Feb 09 06:24:42 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103570103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.103570103
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1369388835
Short name T11
Test name
Test status
Simulation time 107082780 ps
CPU time 1.41 seconds
Started Feb 09 06:24:36 AM UTC 25
Finished Feb 09 06:24:39 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369388835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1369388835
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.1359341749
Short name T171
Test name
Test status
Simulation time 68533861 ps
CPU time 1.23 seconds
Started Feb 09 06:25:33 AM UTC 25
Finished Feb 09 06:25:35 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359341749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1359341749
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.3382931258
Short name T29
Test name
Test status
Simulation time 1881292663 ps
CPU time 10.76 seconds
Started Feb 09 06:25:33 AM UTC 25
Finished Feb 09 06:25:45 AM UTC 25
Peak memory 251328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382931258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3382931258
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3222940738
Short name T172
Test name
Test status
Simulation time 243525799 ps
CPU time 1.7 seconds
Started Feb 09 06:25:33 AM UTC 25
Finished Feb 09 06:25:36 AM UTC 25
Peak memory 236620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222940738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3222940738
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.2535452255
Short name T165
Test name
Test status
Simulation time 88619087 ps
CPU time 1.18 seconds
Started Feb 09 06:25:30 AM UTC 25
Finished Feb 09 06:25:32 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535452255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2535452255
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.2621570651
Short name T107
Test name
Test status
Simulation time 2109389691 ps
CPU time 12.34 seconds
Started Feb 09 06:25:30 AM UTC 25
Finished Feb 09 06:25:43 AM UTC 25
Peak memory 208984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621570651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.rstmgr_reset.2621570651
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3796412987
Short name T168
Test name
Test status
Simulation time 173772669 ps
CPU time 1.83 seconds
Started Feb 09 06:25:32 AM UTC 25
Finished Feb 09 06:25:35 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796412987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3796412987
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.2807078639
Short name T166
Test name
Test status
Simulation time 254955965 ps
CPU time 2.46 seconds
Started Feb 09 06:25:30 AM UTC 25
Finished Feb 09 06:25:33 AM UTC 25
Peak memory 208988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807078639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.rstmgr_smoke.2807078639
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.1734715703
Short name T169
Test name
Test status
Simulation time 359611078 ps
CPU time 3.18 seconds
Started Feb 09 06:25:31 AM UTC 25
Finished Feb 09 06:25:35 AM UTC 25
Peak memory 208660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734715703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.rstmgr_sw_rst.1734715703
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.2712920068
Short name T167
Test name
Test status
Simulation time 193411359 ps
CPU time 1.98 seconds
Started Feb 09 06:25:31 AM UTC 25
Finished Feb 09 06:25:34 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712920068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2712920068
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.3156651541
Short name T178
Test name
Test status
Simulation time 71694684 ps
CPU time 1.15 seconds
Started Feb 09 06:25:38 AM UTC 25
Finished Feb 09 06:25:40 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156651541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3156651541
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.741823575
Short name T46
Test name
Test status
Simulation time 1221159605 ps
CPU time 8.46 seconds
Started Feb 09 06:25:37 AM UTC 25
Finished Feb 09 06:25:46 AM UTC 25
Peak memory 241388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741823575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.741823575
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3690744367
Short name T177
Test name
Test status
Simulation time 243779677 ps
CPU time 1.85 seconds
Started Feb 09 06:25:37 AM UTC 25
Finished Feb 09 06:25:40 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690744367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3690744367
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.186475032
Short name T173
Test name
Test status
Simulation time 171333536 ps
CPU time 1.47 seconds
Started Feb 09 06:25:34 AM UTC 25
Finished Feb 09 06:25:37 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186475032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por
_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.186475032
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.1911496555
Short name T183
Test name
Test status
Simulation time 1061574487 ps
CPU time 7.61 seconds
Started Feb 09 06:25:34 AM UTC 25
Finished Feb 09 06:25:43 AM UTC 25
Peak memory 208796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911496555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.rstmgr_reset.1911496555
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1446503850
Short name T176
Test name
Test status
Simulation time 157660104 ps
CPU time 1.82 seconds
Started Feb 09 06:25:36 AM UTC 25
Finished Feb 09 06:25:40 AM UTC 25
Peak memory 207652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446503850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1446503850
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.3621473645
Short name T174
Test name
Test status
Simulation time 188401997 ps
CPU time 1.96 seconds
Started Feb 09 06:25:34 AM UTC 25
Finished Feb 09 06:25:37 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621473645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.rstmgr_smoke.3621473645
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.1801294900
Short name T110
Test name
Test status
Simulation time 4107102555 ps
CPU time 22.02 seconds
Started Feb 09 06:25:37 AM UTC 25
Finished Feb 09 06:26:00 AM UTC 25
Peak memory 220008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801294900 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1801294900
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.1797366437
Short name T180
Test name
Test status
Simulation time 139871113 ps
CPU time 2.46 seconds
Started Feb 09 06:25:36 AM UTC 25
Finished Feb 09 06:25:40 AM UTC 25
Peak memory 208600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797366437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.rstmgr_sw_rst.1797366437
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.1676124124
Short name T175
Test name
Test status
Simulation time 81745928 ps
CPU time 1.3 seconds
Started Feb 09 06:25:35 AM UTC 25
Finished Feb 09 06:25:38 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676124124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1676124124
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.1103389356
Short name T187
Test name
Test status
Simulation time 71364234 ps
CPU time 1.26 seconds
Started Feb 09 06:25:42 AM UTC 25
Finished Feb 09 06:25:45 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103389356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1103389356
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.654034260
Short name T59
Test name
Test status
Simulation time 2345129124 ps
CPU time 12.23 seconds
Started Feb 09 06:25:41 AM UTC 25
Finished Feb 09 06:25:55 AM UTC 25
Peak memory 241460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654034260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.654034260
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.587654857
Short name T185
Test name
Test status
Simulation time 244107813 ps
CPU time 1.93 seconds
Started Feb 09 06:25:41 AM UTC 25
Finished Feb 09 06:25:44 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587654857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.587654857
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.3683842845
Short name T179
Test name
Test status
Simulation time 75911029 ps
CPU time 1.17 seconds
Started Feb 09 06:25:38 AM UTC 25
Finished Feb 09 06:25:40 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683842845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3683842845
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.368055251
Short name T192
Test name
Test status
Simulation time 834169014 ps
CPU time 6.85 seconds
Started Feb 09 06:25:39 AM UTC 25
Finished Feb 09 06:25:47 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368055251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.rstmgr_reset.368055251
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2925585624
Short name T184
Test name
Test status
Simulation time 177817674 ps
CPU time 1.86 seconds
Started Feb 09 06:25:41 AM UTC 25
Finished Feb 09 06:25:44 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925585624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2925585624
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.289364285
Short name T181
Test name
Test status
Simulation time 247781187 ps
CPU time 2.22 seconds
Started Feb 09 06:25:38 AM UTC 25
Finished Feb 09 06:25:41 AM UTC 25
Peak memory 208984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289364285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.rstmgr_smoke.289364285
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.2730848915
Short name T206
Test name
Test status
Simulation time 2802213756 ps
CPU time 10.12 seconds
Started Feb 09 06:25:41 AM UTC 25
Finished Feb 09 06:25:53 AM UTC 25
Peak memory 217764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730848915 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2730848915
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.1054741197
Short name T186
Test name
Test status
Simulation time 477495480 ps
CPU time 3.57 seconds
Started Feb 09 06:25:40 AM UTC 25
Finished Feb 09 06:25:45 AM UTC 25
Peak memory 208660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054741197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.rstmgr_sw_rst.1054741197
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.1157334821
Short name T182
Test name
Test status
Simulation time 139283955 ps
CPU time 1.56 seconds
Started Feb 09 06:25:40 AM UTC 25
Finished Feb 09 06:25:43 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157334821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1157334821
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.1454199446
Short name T196
Test name
Test status
Simulation time 54162336 ps
CPU time 1.1 seconds
Started Feb 09 06:25:46 AM UTC 25
Finished Feb 09 06:25:48 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454199446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1454199446
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.323790644
Short name T47
Test name
Test status
Simulation time 2167963322 ps
CPU time 12.68 seconds
Started Feb 09 06:25:45 AM UTC 25
Finished Feb 09 06:25:59 AM UTC 25
Peak memory 241528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323790644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.323790644
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.979775289
Short name T195
Test name
Test status
Simulation time 245444193 ps
CPU time 1.73 seconds
Started Feb 09 06:25:45 AM UTC 25
Finished Feb 09 06:25:48 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979775289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.979775289
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.1039845239
Short name T188
Test name
Test status
Simulation time 138873682 ps
CPU time 1.34 seconds
Started Feb 09 06:25:42 AM UTC 25
Finished Feb 09 06:25:45 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039845239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1039845239
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.2335878478
Short name T203
Test name
Test status
Simulation time 796954024 ps
CPU time 6.19 seconds
Started Feb 09 06:25:44 AM UTC 25
Finished Feb 09 06:25:51 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335878478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.rstmgr_reset.2335878478
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.773628843
Short name T193
Test name
Test status
Simulation time 153278055 ps
CPU time 1.76 seconds
Started Feb 09 06:25:45 AM UTC 25
Finished Feb 09 06:25:48 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773628843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec
_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.773628843
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.116527852
Short name T189
Test name
Test status
Simulation time 199319773 ps
CPU time 2.15 seconds
Started Feb 09 06:25:42 AM UTC 25
Finished Feb 09 06:25:46 AM UTC 25
Peak memory 209028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116527852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 13.rstmgr_smoke.116527852
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.1008355617
Short name T207
Test name
Test status
Simulation time 1511330904 ps
CPU time 5.54 seconds
Started Feb 09 06:25:46 AM UTC 25
Finished Feb 09 06:25:53 AM UTC 25
Peak memory 208852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008355617 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1008355617
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.1290054158
Short name T194
Test name
Test status
Simulation time 144664804 ps
CPU time 1.82 seconds
Started Feb 09 06:25:45 AM UTC 25
Finished Feb 09 06:25:48 AM UTC 25
Peak memory 216404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290054158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.rstmgr_sw_rst.1290054158
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.973404677
Short name T191
Test name
Test status
Simulation time 102536686 ps
CPU time 1.5 seconds
Started Feb 09 06:25:44 AM UTC 25
Finished Feb 09 06:25:46 AM UTC 25
Peak memory 207604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973404677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.973404677
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.1736504833
Short name T201
Test name
Test status
Simulation time 76697317 ps
CPU time 1.21 seconds
Started Feb 09 06:25:48 AM UTC 25
Finished Feb 09 06:25:51 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736504833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1736504833
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.549753598
Short name T48
Test name
Test status
Simulation time 2372016548 ps
CPU time 10 seconds
Started Feb 09 06:25:48 AM UTC 25
Finished Feb 09 06:26:00 AM UTC 25
Peak memory 242112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549753598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.549753598
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2614513183
Short name T204
Test name
Test status
Simulation time 244163431 ps
CPU time 1.75 seconds
Started Feb 09 06:25:48 AM UTC 25
Finished Feb 09 06:25:51 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614513183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2614513183
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.2090215951
Short name T197
Test name
Test status
Simulation time 172026968 ps
CPU time 1.54 seconds
Started Feb 09 06:25:46 AM UTC 25
Finished Feb 09 06:25:49 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090215951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2090215951
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.4154814828
Short name T109
Test name
Test status
Simulation time 808366633 ps
CPU time 5.31 seconds
Started Feb 09 06:25:47 AM UTC 25
Finished Feb 09 06:25:54 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154814828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.rstmgr_reset.4154814828
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3935272491
Short name T202
Test name
Test status
Simulation time 102619613 ps
CPU time 1.53 seconds
Started Feb 09 06:25:48 AM UTC 25
Finished Feb 09 06:25:51 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935272491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3935272491
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.363451148
Short name T198
Test name
Test status
Simulation time 204371950 ps
CPU time 2.22 seconds
Started Feb 09 06:25:46 AM UTC 25
Finished Feb 09 06:25:49 AM UTC 25
Peak memory 209052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363451148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 14.rstmgr_smoke.363451148
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.3436749037
Short name T309
Test name
Test status
Simulation time 7159416902 ps
CPU time 33.79 seconds
Started Feb 09 06:25:48 AM UTC 25
Finished Feb 09 06:26:24 AM UTC 25
Peak memory 208916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436749037 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3436749037
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.2757823375
Short name T200
Test name
Test status
Simulation time 130406584 ps
CPU time 2.3 seconds
Started Feb 09 06:25:47 AM UTC 25
Finished Feb 09 06:25:51 AM UTC 25
Peak memory 217508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757823375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.rstmgr_sw_rst.2757823375
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.813435571
Short name T199
Test name
Test status
Simulation time 217450587 ps
CPU time 2.15 seconds
Started Feb 09 06:25:47 AM UTC 25
Finished Feb 09 06:25:51 AM UTC 25
Peak memory 208588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813435571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.813435571
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.2804701746
Short name T210
Test name
Test status
Simulation time 66230114 ps
CPU time 1.18 seconds
Started Feb 09 06:25:52 AM UTC 25
Finished Feb 09 06:25:54 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804701746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2804701746
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.651090208
Short name T229
Test name
Test status
Simulation time 2165305418 ps
CPU time 9.51 seconds
Started Feb 09 06:25:52 AM UTC 25
Finished Feb 09 06:26:03 AM UTC 25
Peak memory 242124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651090208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.651090208
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3021201066
Short name T211
Test name
Test status
Simulation time 244568895 ps
CPU time 1.21 seconds
Started Feb 09 06:25:52 AM UTC 25
Finished Feb 09 06:25:54 AM UTC 25
Peak memory 236868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021201066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3021201066
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.1218320754
Short name T205
Test name
Test status
Simulation time 172582992 ps
CPU time 1.39 seconds
Started Feb 09 06:25:50 AM UTC 25
Finished Feb 09 06:25:52 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218320754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1218320754
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.1510096157
Short name T104
Test name
Test status
Simulation time 1937210677 ps
CPU time 7.15 seconds
Started Feb 09 06:25:51 AM UTC 25
Finished Feb 09 06:25:59 AM UTC 25
Peak memory 208984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510096157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.rstmgr_reset.1510096157
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.193165265
Short name T209
Test name
Test status
Simulation time 109987589 ps
CPU time 1.21 seconds
Started Feb 09 06:25:52 AM UTC 25
Finished Feb 09 06:25:54 AM UTC 25
Peak memory 207656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193165265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec
_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.193165265
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.1170039162
Short name T208
Test name
Test status
Simulation time 255859088 ps
CPU time 2.47 seconds
Started Feb 09 06:25:50 AM UTC 25
Finished Feb 09 06:25:53 AM UTC 25
Peak memory 208984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170039162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.rstmgr_smoke.1170039162
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.1767768552
Short name T250
Test name
Test status
Simulation time 4059271948 ps
CPU time 15.41 seconds
Started Feb 09 06:25:52 AM UTC 25
Finished Feb 09 06:26:09 AM UTC 25
Peak memory 209048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767768552 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1767768552
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.732293627
Short name T215
Test name
Test status
Simulation time 479377638 ps
CPU time 3.33 seconds
Started Feb 09 06:25:52 AM UTC 25
Finished Feb 09 06:25:56 AM UTC 25
Peak memory 208664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732293627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.rstmgr_sw_rst.732293627
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.3138528553
Short name T212
Test name
Test status
Simulation time 231367673 ps
CPU time 2.17 seconds
Started Feb 09 06:25:52 AM UTC 25
Finished Feb 09 06:25:55 AM UTC 25
Peak memory 208780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138528553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3138528553
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.1649797256
Short name T220
Test name
Test status
Simulation time 57950885 ps
CPU time 1.1 seconds
Started Feb 09 06:25:57 AM UTC 25
Finished Feb 09 06:25:59 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649797256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1649797256
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.333950766
Short name T49
Test name
Test status
Simulation time 1225206230 ps
CPU time 5.29 seconds
Started Feb 09 06:25:55 AM UTC 25
Finished Feb 09 06:26:02 AM UTC 25
Peak memory 241628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333950766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.333950766
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2919429705
Short name T219
Test name
Test status
Simulation time 244275747 ps
CPU time 1.94 seconds
Started Feb 09 06:25:55 AM UTC 25
Finished Feb 09 06:25:59 AM UTC 25
Peak memory 236868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919429705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2919429705
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.2546993492
Short name T213
Test name
Test status
Simulation time 210661021 ps
CPU time 1.23 seconds
Started Feb 09 06:25:53 AM UTC 25
Finished Feb 09 06:25:55 AM UTC 25
Peak memory 207512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546993492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2546993492
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.3982789677
Short name T226
Test name
Test status
Simulation time 1463327649 ps
CPU time 7.31 seconds
Started Feb 09 06:25:53 AM UTC 25
Finished Feb 09 06:26:02 AM UTC 25
Peak memory 208984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982789677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.rstmgr_reset.3982789677
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1555708690
Short name T218
Test name
Test status
Simulation time 148822836 ps
CPU time 1.72 seconds
Started Feb 09 06:25:55 AM UTC 25
Finished Feb 09 06:25:58 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555708690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1555708690
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.3575477836
Short name T214
Test name
Test status
Simulation time 118536841 ps
CPU time 1.76 seconds
Started Feb 09 06:25:53 AM UTC 25
Finished Feb 09 06:25:56 AM UTC 25
Peak memory 207444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575477836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.rstmgr_smoke.3575477836
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.2437403263
Short name T223
Test name
Test status
Simulation time 902335688 ps
CPU time 4.47 seconds
Started Feb 09 06:25:55 AM UTC 25
Finished Feb 09 06:26:01 AM UTC 25
Peak memory 208792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437403263 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2437403263
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.2303121439
Short name T217
Test name
Test status
Simulation time 112745809 ps
CPU time 2.11 seconds
Started Feb 09 06:25:54 AM UTC 25
Finished Feb 09 06:25:58 AM UTC 25
Peak memory 208792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303121439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.rstmgr_sw_rst.2303121439
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.3771194464
Short name T216
Test name
Test status
Simulation time 87949674 ps
CPU time 1.27 seconds
Started Feb 09 06:25:54 AM UTC 25
Finished Feb 09 06:25:57 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771194464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3771194464
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.389816494
Short name T228
Test name
Test status
Simulation time 69568497 ps
CPU time 1.12 seconds
Started Feb 09 06:26:00 AM UTC 25
Finished Feb 09 06:26:03 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389816494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.389816494
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.2131793735
Short name T30
Test name
Test status
Simulation time 1907872486 ps
CPU time 8.99 seconds
Started Feb 09 06:25:58 AM UTC 25
Finished Feb 09 06:26:08 AM UTC 25
Peak memory 241024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131793735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2131793735
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.474824323
Short name T227
Test name
Test status
Simulation time 244332755 ps
CPU time 1.93 seconds
Started Feb 09 06:25:59 AM UTC 25
Finished Feb 09 06:26:02 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474824323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.474824323
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.1120703426
Short name T221
Test name
Test status
Simulation time 131744447 ps
CPU time 1.29 seconds
Started Feb 09 06:25:57 AM UTC 25
Finished Feb 09 06:25:59 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120703426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1120703426
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.3776246363
Short name T111
Test name
Test status
Simulation time 997828728 ps
CPU time 4.93 seconds
Started Feb 09 06:25:57 AM UTC 25
Finished Feb 09 06:26:03 AM UTC 25
Peak memory 208860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776246363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.rstmgr_reset.3776246363
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3395736033
Short name T222
Test name
Test status
Simulation time 108444439 ps
CPU time 1.52 seconds
Started Feb 09 06:25:58 AM UTC 25
Finished Feb 09 06:26:01 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395736033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3395736033
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.3845024184
Short name T190
Test name
Test status
Simulation time 206958810 ps
CPU time 2.24 seconds
Started Feb 09 06:25:57 AM UTC 25
Finished Feb 09 06:26:00 AM UTC 25
Peak memory 209052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845024184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.rstmgr_smoke.3845024184
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.186061732
Short name T344
Test name
Test status
Simulation time 7635268185 ps
CPU time 29.53 seconds
Started Feb 09 06:25:59 AM UTC 25
Finished Feb 09 06:26:30 AM UTC 25
Peak memory 217832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186061732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.186061732
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.3841909616
Short name T225
Test name
Test status
Simulation time 154566114 ps
CPU time 2.5 seconds
Started Feb 09 06:25:58 AM UTC 25
Finished Feb 09 06:26:02 AM UTC 25
Peak memory 208600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841909616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.rstmgr_sw_rst.3841909616
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.3805831455
Short name T224
Test name
Test status
Simulation time 221365332 ps
CPU time 2.1 seconds
Started Feb 09 06:25:58 AM UTC 25
Finished Feb 09 06:26:01 AM UTC 25
Peak memory 208588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805831455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3805831455
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.634493844
Short name T235
Test name
Test status
Simulation time 86908011 ps
CPU time 0.95 seconds
Started Feb 09 06:26:02 AM UTC 25
Finished Feb 09 06:26:04 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634493844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.634493844
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.4100931015
Short name T255
Test name
Test status
Simulation time 1899209429 ps
CPU time 7.13 seconds
Started Feb 09 06:26:02 AM UTC 25
Finished Feb 09 06:26:10 AM UTC 25
Peak memory 242056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100931015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.4100931015
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3258147982
Short name T238
Test name
Test status
Simulation time 244831294 ps
CPU time 1.94 seconds
Started Feb 09 06:26:02 AM UTC 25
Finished Feb 09 06:26:05 AM UTC 25
Peak memory 236868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258147982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3258147982
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.4013830608
Short name T230
Test name
Test status
Simulation time 122622144 ps
CPU time 1.28 seconds
Started Feb 09 06:26:00 AM UTC 25
Finished Feb 09 06:26:03 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013830608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.4013830608
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.2260480690
Short name T242
Test name
Test status
Simulation time 898532023 ps
CPU time 4.65 seconds
Started Feb 09 06:26:00 AM UTC 25
Finished Feb 09 06:26:06 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260480690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.rstmgr_reset.2260480690
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1616042838
Short name T237
Test name
Test status
Simulation time 106773865 ps
CPU time 1.41 seconds
Started Feb 09 06:26:02 AM UTC 25
Finished Feb 09 06:26:04 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616042838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1616042838
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.896562805
Short name T232
Test name
Test status
Simulation time 113661452 ps
CPU time 1.78 seconds
Started Feb 09 06:26:00 AM UTC 25
Finished Feb 09 06:26:03 AM UTC 25
Peak memory 207584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896562805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.rstmgr_smoke.896562805
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.303657484
Short name T500
Test name
Test status
Simulation time 16642119830 ps
CPU time 52.49 seconds
Started Feb 09 06:26:02 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 217832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303657484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.303657484
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.3951747196
Short name T236
Test name
Test status
Simulation time 300500242 ps
CPU time 2.3 seconds
Started Feb 09 06:26:00 AM UTC 25
Finished Feb 09 06:26:04 AM UTC 25
Peak memory 217576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951747196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.rstmgr_sw_rst.3951747196
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.3701302438
Short name T234
Test name
Test status
Simulation time 233455938 ps
CPU time 1.71 seconds
Started Feb 09 06:26:00 AM UTC 25
Finished Feb 09 06:26:03 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701302438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3701302438
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.2572509119
Short name T244
Test name
Test status
Simulation time 68737318 ps
CPU time 1.11 seconds
Started Feb 09 06:26:04 AM UTC 25
Finished Feb 09 06:26:07 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572509119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2572509119
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.409269843
Short name T266
Test name
Test status
Simulation time 2176293360 ps
CPU time 8.03 seconds
Started Feb 09 06:26:04 AM UTC 25
Finished Feb 09 06:26:14 AM UTC 25
Peak memory 242020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409269843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.409269843
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.539689586
Short name T247
Test name
Test status
Simulation time 243959315 ps
CPU time 1.82 seconds
Started Feb 09 06:26:04 AM UTC 25
Finished Feb 09 06:26:07 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539689586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.539689586
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.2970955127
Short name T241
Test name
Test status
Simulation time 192734060 ps
CPU time 1.59 seconds
Started Feb 09 06:26:03 AM UTC 25
Finished Feb 09 06:26:06 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970955127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2970955127
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.3535258352
Short name T133
Test name
Test status
Simulation time 1965080448 ps
CPU time 6.94 seconds
Started Feb 09 06:26:03 AM UTC 25
Finished Feb 09 06:26:11 AM UTC 25
Peak memory 208796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535258352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.rstmgr_reset.3535258352
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2251740539
Short name T245
Test name
Test status
Simulation time 98325501 ps
CPU time 1.53 seconds
Started Feb 09 06:26:04 AM UTC 25
Finished Feb 09 06:26:07 AM UTC 25
Peak memory 207700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251740539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2251740539
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.3452234606
Short name T239
Test name
Test status
Simulation time 225608531 ps
CPU time 1.45 seconds
Started Feb 09 06:26:03 AM UTC 25
Finished Feb 09 06:26:06 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452234606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.rstmgr_smoke.3452234606
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.2698708204
Short name T135
Test name
Test status
Simulation time 2052083042 ps
CPU time 7.12 seconds
Started Feb 09 06:26:04 AM UTC 25
Finished Feb 09 06:26:13 AM UTC 25
Peak memory 208980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698708204 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2698708204
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.2336374954
Short name T246
Test name
Test status
Simulation time 106938352 ps
CPU time 1.63 seconds
Started Feb 09 06:26:04 AM UTC 25
Finished Feb 09 06:26:07 AM UTC 25
Peak memory 207740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336374954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.rstmgr_sw_rst.2336374954
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.2788570454
Short name T240
Test name
Test status
Simulation time 134122822 ps
CPU time 1.54 seconds
Started Feb 09 06:26:03 AM UTC 25
Finished Feb 09 06:26:06 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788570454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2788570454
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.3017552811
Short name T55
Test name
Test status
Simulation time 75040837 ps
CPU time 1.23 seconds
Started Feb 09 06:24:48 AM UTC 25
Finished Feb 09 06:24:50 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017552811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3017552811
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.1218708229
Short name T57
Test name
Test status
Simulation time 1882883945 ps
CPU time 12.08 seconds
Started Feb 09 06:24:45 AM UTC 25
Finished Feb 09 06:24:58 AM UTC 25
Peak memory 242028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218708229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1218708229
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.906806630
Short name T54
Test name
Test status
Simulation time 244487267 ps
CPU time 1.79 seconds
Started Feb 09 06:24:46 AM UTC 25
Finished Feb 09 06:24:49 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906806630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.906806630
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.2054140863
Short name T14
Test name
Test status
Simulation time 165317538 ps
CPU time 1.48 seconds
Started Feb 09 06:24:42 AM UTC 25
Finished Feb 09 06:24:45 AM UTC 25
Peak memory 207496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054140863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2054140863
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.2897655247
Short name T37
Test name
Test status
Simulation time 1397797764 ps
CPU time 8.65 seconds
Started Feb 09 06:24:44 AM UTC 25
Finished Feb 09 06:24:53 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897655247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.rstmgr_reset.2897655247
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.3309071296
Short name T69
Test name
Test status
Simulation time 16529422004 ps
CPU time 39.24 seconds
Started Feb 09 06:24:47 AM UTC 25
Finished Feb 09 06:25:28 AM UTC 25
Peak memory 242260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309071296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3309071296
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3578928594
Short name T51
Test name
Test status
Simulation time 142039192 ps
CPU time 1.67 seconds
Started Feb 09 06:24:44 AM UTC 25
Finished Feb 09 06:24:46 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578928594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3578928594
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.2733079119
Short name T23
Test name
Test status
Simulation time 120819745 ps
CPU time 1.69 seconds
Started Feb 09 06:24:42 AM UTC 25
Finished Feb 09 06:24:45 AM UTC 25
Peak memory 207376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733079119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.rstmgr_smoke.2733079119
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.3962727449
Short name T88
Test name
Test status
Simulation time 3945265106 ps
CPU time 26.2 seconds
Started Feb 09 06:24:46 AM UTC 25
Finished Feb 09 06:25:13 AM UTC 25
Peak memory 217764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962727449 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3962727449
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.4116579484
Short name T53
Test name
Test status
Simulation time 370068695 ps
CPU time 3.71 seconds
Started Feb 09 06:24:44 AM UTC 25
Finished Feb 09 06:24:49 AM UTC 25
Peak memory 208660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116579484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.rstmgr_sw_rst.4116579484
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.1991328686
Short name T52
Test name
Test status
Simulation time 268736023 ps
CPU time 2.22 seconds
Started Feb 09 06:24:44 AM UTC 25
Finished Feb 09 06:24:47 AM UTC 25
Peak memory 208584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991328686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1991328686
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.1131678560
Short name T251
Test name
Test status
Simulation time 67235869 ps
CPU time 0.89 seconds
Started Feb 09 06:26:07 AM UTC 25
Finished Feb 09 06:26:09 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131678560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1131678560
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/20.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.1732216500
Short name T31
Test name
Test status
Simulation time 1231030998 ps
CPU time 6.27 seconds
Started Feb 09 06:26:07 AM UTC 25
Finished Feb 09 06:26:14 AM UTC 25
Peak memory 242068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732216500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1732216500
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2582465373
Short name T253
Test name
Test status
Simulation time 243872054 ps
CPU time 1.3 seconds
Started Feb 09 06:26:07 AM UTC 25
Finished Feb 09 06:26:09 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582465373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2582465373
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.3188537329
Short name T243
Test name
Test status
Simulation time 168905038 ps
CPU time 1.1 seconds
Started Feb 09 06:26:04 AM UTC 25
Finished Feb 09 06:26:07 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188537329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3188537329
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.4257891141
Short name T134
Test name
Test status
Simulation time 1407460717 ps
CPU time 5.47 seconds
Started Feb 09 06:26:06 AM UTC 25
Finished Feb 09 06:26:12 AM UTC 25
Peak memory 208924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257891141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.rstmgr_reset.4257891141
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/20.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.357506692
Short name T249
Test name
Test status
Simulation time 103367071 ps
CPU time 1.55 seconds
Started Feb 09 06:26:06 AM UTC 25
Finished Feb 09 06:26:08 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357506692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec
_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.357506692
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.2995322870
Short name T248
Test name
Test status
Simulation time 226074621 ps
CPU time 2.21 seconds
Started Feb 09 06:26:04 AM UTC 25
Finished Feb 09 06:26:08 AM UTC 25
Peak memory 208860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995322870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.rstmgr_smoke.2995322870
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/20.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.31504089
Short name T264
Test name
Test status
Simulation time 3261636493 ps
CPU time 11.74 seconds
Started Feb 09 06:26:07 AM UTC 25
Finished Feb 09 06:26:20 AM UTC 25
Peak memory 208920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31504089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_t
est +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.31504089
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/20.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.679792907
Short name T254
Test name
Test status
Simulation time 359450398 ps
CPU time 3.11 seconds
Started Feb 09 06:26:06 AM UTC 25
Finished Feb 09 06:26:10 AM UTC 25
Peak memory 208664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679792907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.rstmgr_sw_rst.679792907
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.3010950854
Short name T252
Test name
Test status
Simulation time 284082416 ps
CPU time 2.53 seconds
Started Feb 09 06:26:06 AM UTC 25
Finished Feb 09 06:26:09 AM UTC 25
Peak memory 208988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010950854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3010950854
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.1471080877
Short name T260
Test name
Test status
Simulation time 67832266 ps
CPU time 1.06 seconds
Started Feb 09 06:26:09 AM UTC 25
Finished Feb 09 06:26:13 AM UTC 25
Peak memory 207456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471080877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1471080877
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/21.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.1763370349
Short name T32
Test name
Test status
Simulation time 1899298611 ps
CPU time 7.59 seconds
Started Feb 09 06:26:08 AM UTC 25
Finished Feb 09 06:26:18 AM UTC 25
Peak memory 251700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763370349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1763370349
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3771691654
Short name T262
Test name
Test status
Simulation time 243820632 ps
CPU time 1.23 seconds
Started Feb 09 06:26:09 AM UTC 25
Finished Feb 09 06:26:13 AM UTC 25
Peak memory 236556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771691654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3771691654
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.1696254065
Short name T256
Test name
Test status
Simulation time 139567449 ps
CPU time 1.37 seconds
Started Feb 09 06:26:08 AM UTC 25
Finished Feb 09 06:26:11 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696254065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1696254065
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.2680805784
Short name T277
Test name
Test status
Simulation time 952748387 ps
CPU time 6.3 seconds
Started Feb 09 06:26:08 AM UTC 25
Finished Feb 09 06:26:17 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680805784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.rstmgr_reset.2680805784
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/21.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2779063169
Short name T258
Test name
Test status
Simulation time 138401153 ps
CPU time 1.15 seconds
Started Feb 09 06:26:08 AM UTC 25
Finished Feb 09 06:26:12 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779063169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2779063169
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.3619948491
Short name T257
Test name
Test status
Simulation time 198654032 ps
CPU time 1.5 seconds
Started Feb 09 06:26:08 AM UTC 25
Finished Feb 09 06:26:11 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619948491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.rstmgr_smoke.3619948491
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/21.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.2821664406
Short name T528
Test name
Test status
Simulation time 15693412875 ps
CPU time 48.46 seconds
Started Feb 09 06:26:09 AM UTC 25
Finished Feb 09 06:27:00 AM UTC 25
Peak memory 217892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821664406 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2821664406
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/21.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.3184053899
Short name T261
Test name
Test status
Simulation time 309109025 ps
CPU time 2.29 seconds
Started Feb 09 06:26:08 AM UTC 25
Finished Feb 09 06:26:13 AM UTC 25
Peak memory 208724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184053899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.rstmgr_sw_rst.3184053899
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.3389659638
Short name T259
Test name
Test status
Simulation time 219696173 ps
CPU time 1.5 seconds
Started Feb 09 06:26:08 AM UTC 25
Finished Feb 09 06:26:12 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389659638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3389659638
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.1980669721
Short name T271
Test name
Test status
Simulation time 69523768 ps
CPU time 1.17 seconds
Started Feb 09 06:26:12 AM UTC 25
Finished Feb 09 06:26:15 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980669721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1980669721
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/22.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.656465301
Short name T33
Test name
Test status
Simulation time 1233168714 ps
CPU time 5.68 seconds
Started Feb 09 06:26:11 AM UTC 25
Finished Feb 09 06:26:18 AM UTC 25
Peak memory 242096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656465301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.656465301
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2338014901
Short name T269
Test name
Test status
Simulation time 245282287 ps
CPU time 1.17 seconds
Started Feb 09 06:26:12 AM UTC 25
Finished Feb 09 06:26:14 AM UTC 25
Peak memory 238896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338014901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2338014901
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.2598426144
Short name T263
Test name
Test status
Simulation time 114493719 ps
CPU time 1.23 seconds
Started Feb 09 06:26:10 AM UTC 25
Finished Feb 09 06:26:13 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598426144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2598426144
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.2456977263
Short name T273
Test name
Test status
Simulation time 798113019 ps
CPU time 4.11 seconds
Started Feb 09 06:26:10 AM UTC 25
Finished Feb 09 06:26:16 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456977263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.rstmgr_reset.2456977263
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/22.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1845290131
Short name T267
Test name
Test status
Simulation time 185690547 ps
CPU time 1.46 seconds
Started Feb 09 06:26:11 AM UTC 25
Finished Feb 09 06:26:14 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845290131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1845290131
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.3067055941
Short name T265
Test name
Test status
Simulation time 258617073 ps
CPU time 1.87 seconds
Started Feb 09 06:26:10 AM UTC 25
Finished Feb 09 06:26:13 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067055941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.rstmgr_smoke.3067055941
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/22.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.4100459652
Short name T464
Test name
Test status
Simulation time 11142583698 ps
CPU time 37.23 seconds
Started Feb 09 06:26:12 AM UTC 25
Finished Feb 09 06:26:51 AM UTC 25
Peak memory 217772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100459652 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.4100459652
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/22.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.140076674
Short name T268
Test name
Test status
Simulation time 337575011 ps
CPU time 2.23 seconds
Started Feb 09 06:26:11 AM UTC 25
Finished Feb 09 06:26:14 AM UTC 25
Peak memory 208732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140076674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.rstmgr_sw_rst.140076674
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.1364459409
Short name T270
Test name
Test status
Simulation time 235542299 ps
CPU time 2.05 seconds
Started Feb 09 06:26:11 AM UTC 25
Finished Feb 09 06:26:15 AM UTC 25
Peak memory 208716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364459409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1364459409
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.599054254
Short name T278
Test name
Test status
Simulation time 79987245 ps
CPU time 0.87 seconds
Started Feb 09 06:26:15 AM UTC 25
Finished Feb 09 06:26:17 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599054254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.599054254
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/23.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.2900768963
Short name T34
Test name
Test status
Simulation time 2165720033 ps
CPU time 7.96 seconds
Started Feb 09 06:26:14 AM UTC 25
Finished Feb 09 06:26:24 AM UTC 25
Peak memory 241644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900768963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2900768963
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2344117614
Short name T281
Test name
Test status
Simulation time 245568543 ps
CPU time 1.85 seconds
Started Feb 09 06:26:14 AM UTC 25
Finished Feb 09 06:26:18 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344117614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2344117614
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.3774223275
Short name T274
Test name
Test status
Simulation time 101702651 ps
CPU time 1.22 seconds
Started Feb 09 06:26:13 AM UTC 25
Finished Feb 09 06:26:16 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774223275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3774223275
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.2954289598
Short name T286
Test name
Test status
Simulation time 829579873 ps
CPU time 4.23 seconds
Started Feb 09 06:26:13 AM UTC 25
Finished Feb 09 06:26:19 AM UTC 25
Peak memory 208860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954289598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.rstmgr_reset.2954289598
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/23.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2743562947
Short name T279
Test name
Test status
Simulation time 100490673 ps
CPU time 1.14 seconds
Started Feb 09 06:26:14 AM UTC 25
Finished Feb 09 06:26:17 AM UTC 25
Peak memory 207252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743562947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2743562947
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.1238941024
Short name T272
Test name
Test status
Simulation time 215653987 ps
CPU time 2.26 seconds
Started Feb 09 06:26:12 AM UTC 25
Finished Feb 09 06:26:16 AM UTC 25
Peak memory 208860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238941024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.rstmgr_smoke.1238941024
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/23.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.2309686809
Short name T284
Test name
Test status
Simulation time 382365727 ps
CPU time 2.69 seconds
Started Feb 09 06:26:15 AM UTC 25
Finished Feb 09 06:26:19 AM UTC 25
Peak memory 208660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309686809 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2309686809
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/23.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.1964105976
Short name T276
Test name
Test status
Simulation time 301195823 ps
CPU time 1.94 seconds
Started Feb 09 06:26:13 AM UTC 25
Finished Feb 09 06:26:17 AM UTC 25
Peak memory 216404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964105976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.rstmgr_sw_rst.1964105976
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.2840440075
Short name T275
Test name
Test status
Simulation time 127907272 ps
CPU time 1.54 seconds
Started Feb 09 06:26:13 AM UTC 25
Finished Feb 09 06:26:16 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840440075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2840440075
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.2781784575
Short name T288
Test name
Test status
Simulation time 72563721 ps
CPU time 0.86 seconds
Started Feb 09 06:26:17 AM UTC 25
Finished Feb 09 06:26:19 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781784575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2781784575
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/24.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.3757723585
Short name T310
Test name
Test status
Simulation time 1235833360 ps
CPU time 6.58 seconds
Started Feb 09 06:26:16 AM UTC 25
Finished Feb 09 06:26:24 AM UTC 25
Peak memory 241864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757723585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3757723585
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.10262358
Short name T290
Test name
Test status
Simulation time 244737158 ps
CPU time 1.28 seconds
Started Feb 09 06:26:17 AM UTC 25
Finished Feb 09 06:26:20 AM UTC 25
Peak memory 236868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10262358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf
_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.10262358
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.1426393835
Short name T280
Test name
Test status
Simulation time 114357314 ps
CPU time 1.34 seconds
Started Feb 09 06:26:15 AM UTC 25
Finished Feb 09 06:26:17 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426393835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1426393835
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.1141073852
Short name T306
Test name
Test status
Simulation time 1741244754 ps
CPU time 6.32 seconds
Started Feb 09 06:26:16 AM UTC 25
Finished Feb 09 06:26:23 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141073852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.rstmgr_reset.1141073852
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/24.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1236487083
Short name T285
Test name
Test status
Simulation time 134372926 ps
CPU time 1.65 seconds
Started Feb 09 06:26:16 AM UTC 25
Finished Feb 09 06:26:19 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236487083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1236487083
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.3132419769
Short name T282
Test name
Test status
Simulation time 189860669 ps
CPU time 1.68 seconds
Started Feb 09 06:26:15 AM UTC 25
Finished Feb 09 06:26:18 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132419769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.rstmgr_smoke.3132419769
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/24.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.3045325051
Short name T347
Test name
Test status
Simulation time 3814432250 ps
CPU time 12.43 seconds
Started Feb 09 06:26:17 AM UTC 25
Finished Feb 09 06:26:31 AM UTC 25
Peak memory 217892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045325051 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3045325051
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/24.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.1113287531
Short name T287
Test name
Test status
Simulation time 120534113 ps
CPU time 1.85 seconds
Started Feb 09 06:26:16 AM UTC 25
Finished Feb 09 06:26:19 AM UTC 25
Peak memory 207744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113287531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.rstmgr_sw_rst.1113287531
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.4081989829
Short name T283
Test name
Test status
Simulation time 103945073 ps
CPU time 1.1 seconds
Started Feb 09 06:26:16 AM UTC 25
Finished Feb 09 06:26:18 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081989829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.4081989829
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.119590061
Short name T294
Test name
Test status
Simulation time 63036396 ps
CPU time 0.87 seconds
Started Feb 09 06:26:18 AM UTC 25
Finished Feb 09 06:26:21 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119590061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.119590061
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/25.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.267769989
Short name T319
Test name
Test status
Simulation time 1228039434 ps
CPU time 5.79 seconds
Started Feb 09 06:26:18 AM UTC 25
Finished Feb 09 06:26:25 AM UTC 25
Peak memory 242120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267769989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.267769989
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2065176579
Short name T296
Test name
Test status
Simulation time 249361988 ps
CPU time 1.76 seconds
Started Feb 09 06:26:18 AM UTC 25
Finished Feb 09 06:26:21 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065176579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2065176579
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.70849466
Short name T289
Test name
Test status
Simulation time 168576347 ps
CPU time 0.96 seconds
Started Feb 09 06:26:17 AM UTC 25
Finished Feb 09 06:26:19 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70849466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_
stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 25.rstmgr_por_stretcher.70849466
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.4083344277
Short name T304
Test name
Test status
Simulation time 900073748 ps
CPU time 4.44 seconds
Started Feb 09 06:26:17 AM UTC 25
Finished Feb 09 06:26:23 AM UTC 25
Peak memory 209048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083344277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 25.rstmgr_reset.4083344277
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/25.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2639689095
Short name T295
Test name
Test status
Simulation time 112693009 ps
CPU time 1.54 seconds
Started Feb 09 06:26:18 AM UTC 25
Finished Feb 09 06:26:21 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639689095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2639689095
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.1261278567
Short name T292
Test name
Test status
Simulation time 245741334 ps
CPU time 1.92 seconds
Started Feb 09 06:26:17 AM UTC 25
Finished Feb 09 06:26:20 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261278567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 25.rstmgr_smoke.1261278567
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/25.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.904566413
Short name T457
Test name
Test status
Simulation time 9537358858 ps
CPU time 29.65 seconds
Started Feb 09 06:26:18 AM UTC 25
Finished Feb 09 06:26:50 AM UTC 25
Peak memory 208836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904566413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.904566413
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/25.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.3082823919
Short name T297
Test name
Test status
Simulation time 382651766 ps
CPU time 2.26 seconds
Started Feb 09 06:26:18 AM UTC 25
Finished Feb 09 06:26:22 AM UTC 25
Peak memory 208660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082823919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 25.rstmgr_sw_rst.3082823919
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.3157197584
Short name T293
Test name
Test status
Simulation time 117739804 ps
CPU time 0.99 seconds
Started Feb 09 06:26:18 AM UTC 25
Finished Feb 09 06:26:20 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157197584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3157197584
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.2650623413
Short name T299
Test name
Test status
Simulation time 61199108 ps
CPU time 0.88 seconds
Started Feb 09 06:26:20 AM UTC 25
Finished Feb 09 06:26:22 AM UTC 25
Peak memory 207416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650623413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2650623413
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.1429945313
Short name T336
Test name
Test status
Simulation time 2174672667 ps
CPU time 7.16 seconds
Started Feb 09 06:26:20 AM UTC 25
Finished Feb 09 06:26:28 AM UTC 25
Peak memory 242052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429945313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1429945313
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.193745956
Short name T302
Test name
Test status
Simulation time 245858808 ps
CPU time 1.34 seconds
Started Feb 09 06:26:20 AM UTC 25
Finished Feb 09 06:26:23 AM UTC 25
Peak memory 236988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193745956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.193745956
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.988221724
Short name T298
Test name
Test status
Simulation time 87856427 ps
CPU time 1.13 seconds
Started Feb 09 06:26:20 AM UTC 25
Finished Feb 09 06:26:22 AM UTC 25
Peak memory 207496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988221724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por
_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.988221724
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.209117112
Short name T333
Test name
Test status
Simulation time 1789955761 ps
CPU time 7.3 seconds
Started Feb 09 06:26:20 AM UTC 25
Finished Feb 09 06:26:28 AM UTC 25
Peak memory 208796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209117112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.rstmgr_reset.209117112
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2821950822
Short name T300
Test name
Test status
Simulation time 187957989 ps
CPU time 1.18 seconds
Started Feb 09 06:26:20 AM UTC 25
Finished Feb 09 06:26:22 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821950822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2821950822
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.3810155017
Short name T301
Test name
Test status
Simulation time 118030766 ps
CPU time 1.42 seconds
Started Feb 09 06:26:20 AM UTC 25
Finished Feb 09 06:26:22 AM UTC 25
Peak memory 207360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810155017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 26.rstmgr_smoke.3810155017
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.3652609212
Short name T372
Test name
Test status
Simulation time 3081593859 ps
CPU time 14.58 seconds
Started Feb 09 06:26:20 AM UTC 25
Finished Feb 09 06:26:36 AM UTC 25
Peak memory 217892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652609212 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3652609212
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.1078063569
Short name T311
Test name
Test status
Simulation time 501111380 ps
CPU time 2.77 seconds
Started Feb 09 06:26:20 AM UTC 25
Finished Feb 09 06:26:24 AM UTC 25
Peak memory 208600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078063569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 26.rstmgr_sw_rst.1078063569
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.3423098559
Short name T303
Test name
Test status
Simulation time 179065565 ps
CPU time 1.54 seconds
Started Feb 09 06:26:20 AM UTC 25
Finished Feb 09 06:26:23 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423098559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3423098559
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.2707206217
Short name T315
Test name
Test status
Simulation time 54442114 ps
CPU time 1.01 seconds
Started Feb 09 06:26:23 AM UTC 25
Finished Feb 09 06:26:25 AM UTC 25
Peak memory 207592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707206217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2707206217
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/27.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.1485073263
Short name T337
Test name
Test status
Simulation time 1227574939 ps
CPU time 5.8 seconds
Started Feb 09 06:26:21 AM UTC 25
Finished Feb 09 06:26:29 AM UTC 25
Peak memory 241400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485073263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1485073263
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.355393848
Short name T317
Test name
Test status
Simulation time 245286478 ps
CPU time 1.14 seconds
Started Feb 09 06:26:22 AM UTC 25
Finished Feb 09 06:26:25 AM UTC 25
Peak memory 236868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355393848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.355393848
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.576563050
Short name T307
Test name
Test status
Simulation time 124406494 ps
CPU time 1.03 seconds
Started Feb 09 06:26:21 AM UTC 25
Finished Feb 09 06:26:24 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576563050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por
_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.576563050
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.51597521
Short name T327
Test name
Test status
Simulation time 1327781688 ps
CPU time 4.88 seconds
Started Feb 09 06:26:21 AM UTC 25
Finished Feb 09 06:26:27 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51597521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.rstmgr_reset.51597521
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/27.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1280118832
Short name T308
Test name
Test status
Simulation time 171239224 ps
CPU time 1.11 seconds
Started Feb 09 06:26:21 AM UTC 25
Finished Feb 09 06:26:24 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280118832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1280118832
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.3448157226
Short name T305
Test name
Test status
Simulation time 188488462 ps
CPU time 1.65 seconds
Started Feb 09 06:26:20 AM UTC 25
Finished Feb 09 06:26:23 AM UTC 25
Peak memory 207352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448157226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.rstmgr_smoke.3448157226
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/27.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.3010683410
Short name T389
Test name
Test status
Simulation time 3970228162 ps
CPU time 15.05 seconds
Started Feb 09 06:26:22 AM UTC 25
Finished Feb 09 06:26:39 AM UTC 25
Peak memory 217700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010683410 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3010683410
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/27.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.1693498655
Short name T313
Test name
Test status
Simulation time 151871214 ps
CPU time 1.65 seconds
Started Feb 09 06:26:21 AM UTC 25
Finished Feb 09 06:26:24 AM UTC 25
Peak memory 207744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693498655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.rstmgr_sw_rst.1693498655
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.2480511087
Short name T314
Test name
Test status
Simulation time 212440360 ps
CPU time 1.76 seconds
Started Feb 09 06:26:21 AM UTC 25
Finished Feb 09 06:26:24 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480511087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2480511087
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.3427201974
Short name T321
Test name
Test status
Simulation time 74854968 ps
CPU time 0.76 seconds
Started Feb 09 06:26:24 AM UTC 25
Finished Feb 09 06:26:26 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427201974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3427201974
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/28.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.3957101383
Short name T360
Test name
Test status
Simulation time 2375463617 ps
CPU time 8.25 seconds
Started Feb 09 06:26:24 AM UTC 25
Finished Feb 09 06:26:33 AM UTC 25
Peak memory 241908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957101383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3957101383
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.940623911
Short name T322
Test name
Test status
Simulation time 244363422 ps
CPU time 1.08 seconds
Started Feb 09 06:26:24 AM UTC 25
Finished Feb 09 06:26:26 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940623911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.940623911
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.1383573968
Short name T316
Test name
Test status
Simulation time 118617042 ps
CPU time 0.91 seconds
Started Feb 09 06:26:23 AM UTC 25
Finished Feb 09 06:26:25 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383573968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1383573968
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.1320732042
Short name T348
Test name
Test status
Simulation time 1969091895 ps
CPU time 6.87 seconds
Started Feb 09 06:26:23 AM UTC 25
Finished Feb 09 06:26:31 AM UTC 25
Peak memory 208796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320732042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 28.rstmgr_reset.1320732042
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/28.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.774052070
Short name T324
Test name
Test status
Simulation time 95323557 ps
CPU time 1.32 seconds
Started Feb 09 06:26:24 AM UTC 25
Finished Feb 09 06:26:27 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774052070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec
_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.774052070
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.4087248704
Short name T318
Test name
Test status
Simulation time 125736235 ps
CPU time 1.18 seconds
Started Feb 09 06:26:23 AM UTC 25
Finished Feb 09 06:26:25 AM UTC 25
Peak memory 207404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087248704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 28.rstmgr_smoke.4087248704
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/28.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.278030914
Short name T349
Test name
Test status
Simulation time 1747219079 ps
CPU time 6.32 seconds
Started Feb 09 06:26:24 AM UTC 25
Finished Feb 09 06:26:32 AM UTC 25
Peak memory 208792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278030914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.278030914
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/28.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.1772648359
Short name T325
Test name
Test status
Simulation time 136194174 ps
CPU time 1.96 seconds
Started Feb 09 06:26:24 AM UTC 25
Finished Feb 09 06:26:27 AM UTC 25
Peak memory 207740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772648359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 28.rstmgr_sw_rst.1772648359
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.817609280
Short name T320
Test name
Test status
Simulation time 120065779 ps
CPU time 1.01 seconds
Started Feb 09 06:26:24 AM UTC 25
Finished Feb 09 06:26:26 AM UTC 25
Peak memory 207604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817609280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.817609280
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.2566793276
Short name T328
Test name
Test status
Simulation time 52606562 ps
CPU time 0.86 seconds
Started Feb 09 06:26:25 AM UTC 25
Finished Feb 09 06:26:28 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566793276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2566793276
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/29.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.3353927400
Short name T362
Test name
Test status
Simulation time 1881463383 ps
CPU time 6.77 seconds
Started Feb 09 06:26:25 AM UTC 25
Finished Feb 09 06:26:34 AM UTC 25
Peak memory 242064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353927400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3353927400
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.4171028446
Short name T329
Test name
Test status
Simulation time 244190575 ps
CPU time 1.49 seconds
Started Feb 09 06:26:25 AM UTC 25
Finished Feb 09 06:26:28 AM UTC 25
Peak memory 236728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171028446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.4171028446
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.43555509
Short name T323
Test name
Test status
Simulation time 155993767 ps
CPU time 0.93 seconds
Started Feb 09 06:26:24 AM UTC 25
Finished Feb 09 06:26:26 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43555509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_
stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 29.rstmgr_por_stretcher.43555509
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.3351648240
Short name T358
Test name
Test status
Simulation time 1622177407 ps
CPU time 6.21 seconds
Started Feb 09 06:26:25 AM UTC 25
Finished Feb 09 06:26:33 AM UTC 25
Peak memory 208624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351648240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.rstmgr_reset.3351648240
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/29.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3606980886
Short name T335
Test name
Test status
Simulation time 184037615 ps
CPU time 1.74 seconds
Started Feb 09 06:26:25 AM UTC 25
Finished Feb 09 06:26:28 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606980886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3606980886
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.2098777052
Short name T326
Test name
Test status
Simulation time 238774300 ps
CPU time 1.78 seconds
Started Feb 09 06:26:24 AM UTC 25
Finished Feb 09 06:26:27 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098777052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.rstmgr_smoke.2098777052
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/29.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.3006205317
Short name T472
Test name
Test status
Simulation time 5773530348 ps
CPU time 25.19 seconds
Started Feb 09 06:26:25 AM UTC 25
Finished Feb 09 06:26:52 AM UTC 25
Peak memory 208916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006205317 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3006205317
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/29.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.2262680876
Short name T338
Test name
Test status
Simulation time 411705593 ps
CPU time 2.07 seconds
Started Feb 09 06:26:25 AM UTC 25
Finished Feb 09 06:26:29 AM UTC 25
Peak memory 208668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262680876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.rstmgr_sw_rst.2262680876
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.1272578733
Short name T330
Test name
Test status
Simulation time 208869849 ps
CPU time 1.5 seconds
Started Feb 09 06:26:25 AM UTC 25
Finished Feb 09 06:26:28 AM UTC 25
Peak memory 207564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272578733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1272578733
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.172562739
Short name T42
Test name
Test status
Simulation time 75327839 ps
CPU time 1.19 seconds
Started Feb 09 06:24:55 AM UTC 25
Finished Feb 09 06:24:57 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172562739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.172562739
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.2730766765
Short name T26
Test name
Test status
Simulation time 1896304587 ps
CPU time 11.96 seconds
Started Feb 09 06:24:52 AM UTC 25
Finished Feb 09 06:25:06 AM UTC 25
Peak memory 242036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730766765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2730766765
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2171037159
Short name T41
Test name
Test status
Simulation time 243083607 ps
CPU time 1.92 seconds
Started Feb 09 06:24:52 AM UTC 25
Finished Feb 09 06:24:56 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171037159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2171037159
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.637316101
Short name T15
Test name
Test status
Simulation time 93235524 ps
CPU time 1.07 seconds
Started Feb 09 06:24:49 AM UTC 25
Finished Feb 09 06:24:51 AM UTC 25
Peak memory 207400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637316101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por
_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.637316101
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.1682139120
Short name T40
Test name
Test status
Simulation time 913324180 ps
CPU time 4.69 seconds
Started Feb 09 06:24:49 AM UTC 25
Finished Feb 09 06:24:55 AM UTC 25
Peak memory 208796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682139120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.rstmgr_reset.1682139120
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.3662945730
Short name T68
Test name
Test status
Simulation time 8345304671 ps
CPU time 27.52 seconds
Started Feb 09 06:24:54 AM UTC 25
Finished Feb 09 06:25:23 AM UTC 25
Peak memory 241276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662945730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3662945730
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2140681905
Short name T38
Test name
Test status
Simulation time 111073970 ps
CPU time 1.54 seconds
Started Feb 09 06:24:51 AM UTC 25
Finished Feb 09 06:24:54 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140681905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2140681905
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.2167501134
Short name T36
Test name
Test status
Simulation time 248038981 ps
CPU time 2.37 seconds
Started Feb 09 06:24:49 AM UTC 25
Finished Feb 09 06:24:53 AM UTC 25
Peak memory 208628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167501134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.rstmgr_smoke.2167501134
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.3640799660
Short name T101
Test name
Test status
Simulation time 6916535581 ps
CPU time 30.7 seconds
Started Feb 09 06:24:54 AM UTC 25
Finished Feb 09 06:25:26 AM UTC 25
Peak memory 208808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640799660 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3640799660
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.3857124494
Short name T39
Test name
Test status
Simulation time 113029754 ps
CPU time 2.12 seconds
Started Feb 09 06:24:51 AM UTC 25
Finished Feb 09 06:24:55 AM UTC 25
Peak memory 208792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857124494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.rstmgr_sw_rst.3857124494
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.1118129920
Short name T35
Test name
Test status
Simulation time 232706669 ps
CPU time 2.15 seconds
Started Feb 09 06:24:49 AM UTC 25
Finished Feb 09 06:24:53 AM UTC 25
Peak memory 208584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118129920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1118129920
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.2707720686
Short name T341
Test name
Test status
Simulation time 72702381 ps
CPU time 1.08 seconds
Started Feb 09 06:26:28 AM UTC 25
Finished Feb 09 06:26:30 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707720686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2707720686
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/30.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.823980964
Short name T374
Test name
Test status
Simulation time 2169754273 ps
CPU time 8.67 seconds
Started Feb 09 06:26:26 AM UTC 25
Finished Feb 09 06:26:36 AM UTC 25
Peak memory 241820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823980964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.823980964
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2808942510
Short name T346
Test name
Test status
Simulation time 243901326 ps
CPU time 1.85 seconds
Started Feb 09 06:26:28 AM UTC 25
Finished Feb 09 06:26:31 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808942510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2808942510
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.357484201
Short name T331
Test name
Test status
Simulation time 208578815 ps
CPU time 1.49 seconds
Started Feb 09 06:26:25 AM UTC 25
Finished Feb 09 06:26:28 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357484201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por
_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.357484201
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.2025300163
Short name T351
Test name
Test status
Simulation time 873488235 ps
CPU time 4.04 seconds
Started Feb 09 06:26:26 AM UTC 25
Finished Feb 09 06:26:32 AM UTC 25
Peak memory 208848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025300163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.rstmgr_reset.2025300163
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/30.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3956792354
Short name T339
Test name
Test status
Simulation time 142608520 ps
CPU time 1.04 seconds
Started Feb 09 06:26:26 AM UTC 25
Finished Feb 09 06:26:29 AM UTC 25
Peak memory 207596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956792354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3956792354
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.3976777826
Short name T334
Test name
Test status
Simulation time 195583668 ps
CPU time 1.69 seconds
Started Feb 09 06:26:25 AM UTC 25
Finished Feb 09 06:26:28 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976777826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.rstmgr_smoke.3976777826
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/30.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.1691759847
Short name T432
Test name
Test status
Simulation time 4755356057 ps
CPU time 16.69 seconds
Started Feb 09 06:26:28 AM UTC 25
Finished Feb 09 06:26:46 AM UTC 25
Peak memory 219812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691759847 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1691759847
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/30.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.2464247874
Short name T343
Test name
Test status
Simulation time 424074153 ps
CPU time 2.4 seconds
Started Feb 09 06:26:26 AM UTC 25
Finished Feb 09 06:26:30 AM UTC 25
Peak memory 217576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464247874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.rstmgr_sw_rst.2464247874
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.2940072255
Short name T340
Test name
Test status
Simulation time 169998350 ps
CPU time 1.4 seconds
Started Feb 09 06:26:26 AM UTC 25
Finished Feb 09 06:26:29 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940072255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2940072255
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.1302880474
Short name T355
Test name
Test status
Simulation time 71329967 ps
CPU time 1.2 seconds
Started Feb 09 06:26:29 AM UTC 25
Finished Feb 09 06:26:32 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302880474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1302880474
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/31.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.2891554845
Short name T376
Test name
Test status
Simulation time 1227834331 ps
CPU time 5.47 seconds
Started Feb 09 06:26:29 AM UTC 25
Finished Feb 09 06:26:37 AM UTC 25
Peak memory 241652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891554845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2891554845
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.4252691315
Short name T354
Test name
Test status
Simulation time 243949056 ps
CPU time 1.16 seconds
Started Feb 09 06:26:29 AM UTC 25
Finished Feb 09 06:26:32 AM UTC 25
Peak memory 236868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252691315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.4252691315
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.2435139289
Short name T342
Test name
Test status
Simulation time 116122582 ps
CPU time 0.96 seconds
Started Feb 09 06:26:28 AM UTC 25
Finished Feb 09 06:26:30 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435139289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2435139289
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.1969042955
Short name T377
Test name
Test status
Simulation time 2066711856 ps
CPU time 7.61 seconds
Started Feb 09 06:26:28 AM UTC 25
Finished Feb 09 06:26:37 AM UTC 25
Peak memory 208796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969042955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.rstmgr_reset.1969042955
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/31.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1077693438
Short name T353
Test name
Test status
Simulation time 145290272 ps
CPU time 1.4 seconds
Started Feb 09 06:26:29 AM UTC 25
Finished Feb 09 06:26:32 AM UTC 25
Peak memory 207696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077693438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1077693438
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.3224248102
Short name T345
Test name
Test status
Simulation time 120453440 ps
CPU time 1.55 seconds
Started Feb 09 06:26:28 AM UTC 25
Finished Feb 09 06:26:30 AM UTC 25
Peak memory 207684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224248102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.rstmgr_smoke.3224248102
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/31.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.4096978226
Short name T543
Test name
Test status
Simulation time 15169315271 ps
CPU time 43.2 seconds
Started Feb 09 06:26:29 AM UTC 25
Finished Feb 09 06:27:15 AM UTC 25
Peak memory 209044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096978226 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.4096978226
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/31.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.1838442956
Short name T363
Test name
Test status
Simulation time 394607766 ps
CPU time 2.78 seconds
Started Feb 09 06:26:29 AM UTC 25
Finished Feb 09 06:26:34 AM UTC 25
Peak memory 208656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838442956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.rstmgr_sw_rst.1838442956
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.1065395628
Short name T352
Test name
Test status
Simulation time 79201523 ps
CPU time 1.03 seconds
Started Feb 09 06:26:29 AM UTC 25
Finished Feb 09 06:26:32 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065395628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1065395628
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.298099324
Short name T367
Test name
Test status
Simulation time 79324855 ps
CPU time 0.95 seconds
Started Feb 09 06:26:32 AM UTC 25
Finished Feb 09 06:26:34 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298099324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.298099324
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/32.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.1706069484
Short name T384
Test name
Test status
Simulation time 1233748894 ps
CPU time 5.69 seconds
Started Feb 09 06:26:30 AM UTC 25
Finished Feb 09 06:26:38 AM UTC 25
Peak memory 242064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706069484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1706069484
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1611888715
Short name T361
Test name
Test status
Simulation time 244736507 ps
CPU time 1.16 seconds
Started Feb 09 06:26:30 AM UTC 25
Finished Feb 09 06:26:33 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611888715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1611888715
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.1961644314
Short name T356
Test name
Test status
Simulation time 137781269 ps
CPU time 1.22 seconds
Started Feb 09 06:26:29 AM UTC 25
Finished Feb 09 06:26:32 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961644314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1961644314
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.1802075360
Short name T373
Test name
Test status
Simulation time 1126872019 ps
CPU time 5.04 seconds
Started Feb 09 06:26:29 AM UTC 25
Finished Feb 09 06:26:36 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802075360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.rstmgr_reset.1802075360
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/32.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1243839220
Short name T359
Test name
Test status
Simulation time 159453712 ps
CPU time 1.33 seconds
Started Feb 09 06:26:30 AM UTC 25
Finished Feb 09 06:26:33 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243839220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1243839220
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.504062001
Short name T357
Test name
Test status
Simulation time 199708674 ps
CPU time 1.46 seconds
Started Feb 09 06:26:29 AM UTC 25
Finished Feb 09 06:26:33 AM UTC 25
Peak memory 207556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504062001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 32.rstmgr_smoke.504062001
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/32.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.1135147189
Short name T455
Test name
Test status
Simulation time 3923524180 ps
CPU time 16.04 seconds
Started Feb 09 06:26:32 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 217764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135147189 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1135147189
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/32.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.1687032567
Short name T365
Test name
Test status
Simulation time 267567830 ps
CPU time 1.77 seconds
Started Feb 09 06:26:30 AM UTC 25
Finished Feb 09 06:26:34 AM UTC 25
Peak memory 207740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687032567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.rstmgr_sw_rst.1687032567
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.3948511113
Short name T364
Test name
Test status
Simulation time 147696659 ps
CPU time 1.6 seconds
Started Feb 09 06:26:30 AM UTC 25
Finished Feb 09 06:26:34 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948511113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3948511113
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.2345881859
Short name T370
Test name
Test status
Simulation time 84081539 ps
CPU time 1.28 seconds
Started Feb 09 06:26:33 AM UTC 25
Finished Feb 09 06:26:36 AM UTC 25
Peak memory 207776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345881859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2345881859
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/33.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.2675216177
Short name T413
Test name
Test status
Simulation time 2350373065 ps
CPU time 8.36 seconds
Started Feb 09 06:26:33 AM UTC 25
Finished Feb 09 06:26:43 AM UTC 25
Peak memory 241940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675216177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2675216177
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2911131148
Short name T332
Test name
Test status
Simulation time 244568825 ps
CPU time 1.12 seconds
Started Feb 09 06:26:33 AM UTC 25
Finished Feb 09 06:26:36 AM UTC 25
Peak memory 236920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911131148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2911131148
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.1170816837
Short name T366
Test name
Test status
Simulation time 116906764 ps
CPU time 0.96 seconds
Started Feb 09 06:26:32 AM UTC 25
Finished Feb 09 06:26:34 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170816837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1170816837
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.2402099808
Short name T393
Test name
Test status
Simulation time 1663161441 ps
CPU time 6.26 seconds
Started Feb 09 06:26:32 AM UTC 25
Finished Feb 09 06:26:39 AM UTC 25
Peak memory 208920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402099808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.rstmgr_reset.2402099808
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/33.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1478651881
Short name T371
Test name
Test status
Simulation time 188069650 ps
CPU time 1.11 seconds
Started Feb 09 06:26:33 AM UTC 25
Finished Feb 09 06:26:36 AM UTC 25
Peak memory 207652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478651881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1478651881
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.2846636362
Short name T369
Test name
Test status
Simulation time 249999008 ps
CPU time 1.8 seconds
Started Feb 09 06:26:32 AM UTC 25
Finished Feb 09 06:26:35 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846636362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.rstmgr_smoke.2846636362
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/33.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.1556598208
Short name T495
Test name
Test status
Simulation time 5046825667 ps
CPU time 20.59 seconds
Started Feb 09 06:26:33 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 208912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556598208 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1556598208
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/33.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.344979849
Short name T291
Test name
Test status
Simulation time 148110707 ps
CPU time 1.77 seconds
Started Feb 09 06:26:32 AM UTC 25
Finished Feb 09 06:26:35 AM UTC 25
Peak memory 207684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344979849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.rstmgr_sw_rst.344979849
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.108791854
Short name T368
Test name
Test status
Simulation time 175856905 ps
CPU time 1.24 seconds
Started Feb 09 06:26:32 AM UTC 25
Finished Feb 09 06:26:34 AM UTC 25
Peak memory 207572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108791854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.108791854
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.2173058800
Short name T378
Test name
Test status
Simulation time 59740422 ps
CPU time 0.93 seconds
Started Feb 09 06:26:34 AM UTC 25
Finished Feb 09 06:26:37 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173058800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2173058800
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/34.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.1977558550
Short name T427
Test name
Test status
Simulation time 2346418772 ps
CPU time 8.73 seconds
Started Feb 09 06:26:34 AM UTC 25
Finished Feb 09 06:26:45 AM UTC 25
Peak memory 241672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977558550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1977558550
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3924694309
Short name T380
Test name
Test status
Simulation time 244167222 ps
CPU time 1.01 seconds
Started Feb 09 06:26:34 AM UTC 25
Finished Feb 09 06:26:37 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924694309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3924694309
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.1309939260
Short name T350
Test name
Test status
Simulation time 148281891 ps
CPU time 0.95 seconds
Started Feb 09 06:26:33 AM UTC 25
Finished Feb 09 06:26:36 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309939260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1309939260
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.3711391732
Short name T410
Test name
Test status
Simulation time 1631043513 ps
CPU time 6.28 seconds
Started Feb 09 06:26:34 AM UTC 25
Finished Feb 09 06:26:42 AM UTC 25
Peak memory 208800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711391732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.rstmgr_reset.3711391732
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/34.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.4025668320
Short name T381
Test name
Test status
Simulation time 171445521 ps
CPU time 1.18 seconds
Started Feb 09 06:26:34 AM UTC 25
Finished Feb 09 06:26:37 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025668320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.4025668320
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.3649317024
Short name T312
Test name
Test status
Simulation time 119402848 ps
CPU time 1.28 seconds
Started Feb 09 06:26:33 AM UTC 25
Finished Feb 09 06:26:36 AM UTC 25
Peak memory 207684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649317024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.rstmgr_smoke.3649317024
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/34.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.3546939217
Short name T499
Test name
Test status
Simulation time 4814155899 ps
CPU time 19.34 seconds
Started Feb 09 06:26:34 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 209052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546939217 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3546939217
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/34.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.1009280524
Short name T383
Test name
Test status
Simulation time 133204094 ps
CPU time 1.61 seconds
Started Feb 09 06:26:34 AM UTC 25
Finished Feb 09 06:26:37 AM UTC 25
Peak memory 216460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009280524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.rstmgr_sw_rst.1009280524
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.1400908865
Short name T379
Test name
Test status
Simulation time 133618067 ps
CPU time 1.17 seconds
Started Feb 09 06:26:34 AM UTC 25
Finished Feb 09 06:26:37 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400908865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1400908865
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.2912749734
Short name T386
Test name
Test status
Simulation time 96166353 ps
CPU time 0.91 seconds
Started Feb 09 06:26:36 AM UTC 25
Finished Feb 09 06:26:38 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912749734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2912749734
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/35.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.1770343856
Short name T414
Test name
Test status
Simulation time 1230705601 ps
CPU time 5.52 seconds
Started Feb 09 06:26:36 AM UTC 25
Finished Feb 09 06:26:43 AM UTC 25
Peak memory 242048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770343856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1770343856
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.179230712
Short name T388
Test name
Test status
Simulation time 244163169 ps
CPU time 1.33 seconds
Started Feb 09 06:26:36 AM UTC 25
Finished Feb 09 06:26:39 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179230712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.179230712
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.697740391
Short name T382
Test name
Test status
Simulation time 79689368 ps
CPU time 1.03 seconds
Started Feb 09 06:26:35 AM UTC 25
Finished Feb 09 06:26:37 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697740391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por
_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.697740391
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.1232600548
Short name T430
Test name
Test status
Simulation time 2160965056 ps
CPU time 7.91 seconds
Started Feb 09 06:26:36 AM UTC 25
Finished Feb 09 06:26:45 AM UTC 25
Peak memory 208920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232600548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.rstmgr_reset.1232600548
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/35.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1422621750
Short name T387
Test name
Test status
Simulation time 152864813 ps
CPU time 1.13 seconds
Started Feb 09 06:26:36 AM UTC 25
Finished Feb 09 06:26:39 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422621750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1422621750
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.3203443280
Short name T385
Test name
Test status
Simulation time 249784242 ps
CPU time 1.52 seconds
Started Feb 09 06:26:35 AM UTC 25
Finished Feb 09 06:26:38 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203443280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.rstmgr_smoke.3203443280
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/35.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.256150031
Short name T476
Test name
Test status
Simulation time 3998970959 ps
CPU time 15.07 seconds
Started Feb 09 06:26:36 AM UTC 25
Finished Feb 09 06:26:53 AM UTC 25
Peak memory 208916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256150031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.256150031
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/35.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.2173905330
Short name T391
Test name
Test status
Simulation time 264697551 ps
CPU time 1.81 seconds
Started Feb 09 06:26:36 AM UTC 25
Finished Feb 09 06:26:39 AM UTC 25
Peak memory 207740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173905330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.rstmgr_sw_rst.2173905330
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.3185510662
Short name T390
Test name
Test status
Simulation time 152998282 ps
CPU time 1.7 seconds
Started Feb 09 06:26:36 AM UTC 25
Finished Feb 09 06:26:39 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185510662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3185510662
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.9528635
Short name T399
Test name
Test status
Simulation time 77949143 ps
CPU time 0.91 seconds
Started Feb 09 06:26:38 AM UTC 25
Finished Feb 09 06:26:41 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9528635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.9528635
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.3589131699
Short name T422
Test name
Test status
Simulation time 1226506638 ps
CPU time 5.96 seconds
Started Feb 09 06:26:37 AM UTC 25
Finished Feb 09 06:26:45 AM UTC 25
Peak memory 241976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589131699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3589131699
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.424995635
Short name T396
Test name
Test status
Simulation time 244486067 ps
CPU time 1.14 seconds
Started Feb 09 06:26:37 AM UTC 25
Finished Feb 09 06:26:40 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424995635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.424995635
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.3584257460
Short name T392
Test name
Test status
Simulation time 75243424 ps
CPU time 0.99 seconds
Started Feb 09 06:26:37 AM UTC 25
Finished Feb 09 06:26:39 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584257460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3584257460
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.259535546
Short name T425
Test name
Test status
Simulation time 1416837452 ps
CPU time 6.34 seconds
Started Feb 09 06:26:37 AM UTC 25
Finished Feb 09 06:26:45 AM UTC 25
Peak memory 208860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259535546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 36.rstmgr_reset.259535546
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2418366796
Short name T395
Test name
Test status
Simulation time 113123844 ps
CPU time 1.16 seconds
Started Feb 09 06:26:37 AM UTC 25
Finished Feb 09 06:26:40 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418366796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2418366796
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.2474047477
Short name T397
Test name
Test status
Simulation time 193398890 ps
CPU time 1.37 seconds
Started Feb 09 06:26:37 AM UTC 25
Finished Feb 09 06:26:40 AM UTC 25
Peak memory 207404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474047477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.rstmgr_smoke.2474047477
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.930848476
Short name T532
Test name
Test status
Simulation time 5322080947 ps
CPU time 21.53 seconds
Started Feb 09 06:26:38 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 208916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930848476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.930848476
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.3895946237
Short name T398
Test name
Test status
Simulation time 125439092 ps
CPU time 1.7 seconds
Started Feb 09 06:26:37 AM UTC 25
Finished Feb 09 06:26:40 AM UTC 25
Peak memory 216404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895946237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.rstmgr_sw_rst.3895946237
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.765407013
Short name T394
Test name
Test status
Simulation time 162193725 ps
CPU time 1.11 seconds
Started Feb 09 06:26:37 AM UTC 25
Finished Feb 09 06:26:39 AM UTC 25
Peak memory 207376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765407013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.765407013
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.2867428668
Short name T404
Test name
Test status
Simulation time 71321089 ps
CPU time 0.76 seconds
Started Feb 09 06:26:40 AM UTC 25
Finished Feb 09 06:26:42 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867428668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2867428668
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/37.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.4234179067
Short name T431
Test name
Test status
Simulation time 1235951028 ps
CPU time 5.81 seconds
Started Feb 09 06:26:39 AM UTC 25
Finished Feb 09 06:26:46 AM UTC 25
Peak memory 242032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234179067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.4234179067
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.4002222343
Short name T405
Test name
Test status
Simulation time 244363439 ps
CPU time 1.71 seconds
Started Feb 09 06:26:39 AM UTC 25
Finished Feb 09 06:26:42 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002222343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.4002222343
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.3534929753
Short name T400
Test name
Test status
Simulation time 104290346 ps
CPU time 0.91 seconds
Started Feb 09 06:26:38 AM UTC 25
Finished Feb 09 06:26:41 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534929753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3534929753
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.115745669
Short name T421
Test name
Test status
Simulation time 905285786 ps
CPU time 4.27 seconds
Started Feb 09 06:26:38 AM UTC 25
Finished Feb 09 06:26:44 AM UTC 25
Peak memory 208796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115745669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.rstmgr_reset.115745669
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/37.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.946230412
Short name T401
Test name
Test status
Simulation time 110855825 ps
CPU time 1.17 seconds
Started Feb 09 06:26:39 AM UTC 25
Finished Feb 09 06:26:41 AM UTC 25
Peak memory 207784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946230412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec
_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.946230412
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.783495412
Short name T406
Test name
Test status
Simulation time 252151203 ps
CPU time 2.18 seconds
Started Feb 09 06:26:38 AM UTC 25
Finished Feb 09 06:26:42 AM UTC 25
Peak memory 208860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783495412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.rstmgr_smoke.783495412
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/37.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.1944547705
Short name T531
Test name
Test status
Simulation time 5934003134 ps
CPU time 20.04 seconds
Started Feb 09 06:26:40 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 208980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944547705 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1944547705
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/37.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.602469108
Short name T411
Test name
Test status
Simulation time 504234868 ps
CPU time 3.07 seconds
Started Feb 09 06:26:38 AM UTC 25
Finished Feb 09 06:26:43 AM UTC 25
Peak memory 208604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602469108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 37.rstmgr_sw_rst.602469108
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.1828054083
Short name T402
Test name
Test status
Simulation time 95789126 ps
CPU time 1.38 seconds
Started Feb 09 06:26:38 AM UTC 25
Finished Feb 09 06:26:41 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828054083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1828054083
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.1605985004
Short name T415
Test name
Test status
Simulation time 63831781 ps
CPU time 0.8 seconds
Started Feb 09 06:26:41 AM UTC 25
Finished Feb 09 06:26:43 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605985004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1605985004
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/38.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.1076700959
Short name T450
Test name
Test status
Simulation time 1895382816 ps
CPU time 6.58 seconds
Started Feb 09 06:26:41 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 241396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076700959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1076700959
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2434026508
Short name T416
Test name
Test status
Simulation time 243827146 ps
CPU time 1.18 seconds
Started Feb 09 06:26:41 AM UTC 25
Finished Feb 09 06:26:43 AM UTC 25
Peak memory 237044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434026508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2434026508
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.949055165
Short name T408
Test name
Test status
Simulation time 117456908 ps
CPU time 1.08 seconds
Started Feb 09 06:26:40 AM UTC 25
Finished Feb 09 06:26:42 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949055165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por
_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.949055165
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.1524554828
Short name T452
Test name
Test status
Simulation time 1892496431 ps
CPU time 8.11 seconds
Started Feb 09 06:26:40 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 208988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524554828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.rstmgr_reset.1524554828
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/38.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.148819347
Short name T418
Test name
Test status
Simulation time 104742020 ps
CPU time 1.49 seconds
Started Feb 09 06:26:41 AM UTC 25
Finished Feb 09 06:26:44 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148819347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec
_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.148819347
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.149943281
Short name T409
Test name
Test status
Simulation time 123120751 ps
CPU time 1.27 seconds
Started Feb 09 06:26:40 AM UTC 25
Finished Feb 09 06:26:42 AM UTC 25
Peak memory 207748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149943281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.rstmgr_smoke.149943281
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/38.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.753184020
Short name T473
Test name
Test status
Simulation time 2875341468 ps
CPU time 9.79 seconds
Started Feb 09 06:26:41 AM UTC 25
Finished Feb 09 06:26:52 AM UTC 25
Peak memory 217764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753184020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.753184020
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/38.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.3620785137
Short name T419
Test name
Test status
Simulation time 309734076 ps
CPU time 2.7 seconds
Started Feb 09 06:26:40 AM UTC 25
Finished Feb 09 06:26:44 AM UTC 25
Peak memory 217576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620785137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.rstmgr_sw_rst.3620785137
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.3906814357
Short name T407
Test name
Test status
Simulation time 112748109 ps
CPU time 0.97 seconds
Started Feb 09 06:26:40 AM UTC 25
Finished Feb 09 06:26:42 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906814357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3906814357
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.1156642661
Short name T424
Test name
Test status
Simulation time 75484286 ps
CPU time 0.96 seconds
Started Feb 09 06:26:42 AM UTC 25
Finished Feb 09 06:26:45 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156642661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1156642661
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/39.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.1988091401
Short name T463
Test name
Test status
Simulation time 1902469932 ps
CPU time 6.92 seconds
Started Feb 09 06:26:42 AM UTC 25
Finished Feb 09 06:26:51 AM UTC 25
Peak memory 242052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988091401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1988091401
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1837394885
Short name T423
Test name
Test status
Simulation time 244910034 ps
CPU time 1.03 seconds
Started Feb 09 06:26:42 AM UTC 25
Finished Feb 09 06:26:45 AM UTC 25
Peak memory 236916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837394885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1837394885
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.2337086547
Short name T417
Test name
Test status
Simulation time 229076787 ps
CPU time 0.96 seconds
Started Feb 09 06:26:41 AM UTC 25
Finished Feb 09 06:26:43 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337086547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2337086547
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.628735103
Short name T448
Test name
Test status
Simulation time 1598085280 ps
CPU time 6.28 seconds
Started Feb 09 06:26:41 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628735103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.rstmgr_reset.628735103
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/39.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1677259351
Short name T428
Test name
Test status
Simulation time 174154712 ps
CPU time 1.41 seconds
Started Feb 09 06:26:42 AM UTC 25
Finished Feb 09 06:26:45 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677259351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1677259351
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.703267561
Short name T420
Test name
Test status
Simulation time 201067272 ps
CPU time 1.6 seconds
Started Feb 09 06:26:41 AM UTC 25
Finished Feb 09 06:26:44 AM UTC 25
Peak memory 207744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703267561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.rstmgr_smoke.703267561
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/39.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.3790170624
Short name T538
Test name
Test status
Simulation time 5451983685 ps
CPU time 21.19 seconds
Started Feb 09 06:26:42 AM UTC 25
Finished Feb 09 06:27:05 AM UTC 25
Peak memory 217764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790170624 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3790170624
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/39.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.2127509093
Short name T429
Test name
Test status
Simulation time 112609310 ps
CPU time 1.63 seconds
Started Feb 09 06:26:42 AM UTC 25
Finished Feb 09 06:26:45 AM UTC 25
Peak memory 207744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127509093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 39.rstmgr_sw_rst.2127509093
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.1143594256
Short name T426
Test name
Test status
Simulation time 168075988 ps
CPU time 1.18 seconds
Started Feb 09 06:26:42 AM UTC 25
Finished Feb 09 06:26:45 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143594256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1143594256
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.3133307614
Short name T148
Test name
Test status
Simulation time 72070341 ps
CPU time 1.2 seconds
Started Feb 09 06:25:02 AM UTC 25
Finished Feb 09 06:25:05 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133307614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3133307614
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.660700304
Short name T27
Test name
Test status
Simulation time 2368180369 ps
CPU time 10.49 seconds
Started Feb 09 06:24:59 AM UTC 25
Finished Feb 09 06:25:11 AM UTC 25
Peak memory 241388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660700304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.660700304
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1275441819
Short name T147
Test name
Test status
Simulation time 244731119 ps
CPU time 1.79 seconds
Started Feb 09 06:24:59 AM UTC 25
Finished Feb 09 06:25:02 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275441819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1275441819
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.3334726176
Short name T16
Test name
Test status
Simulation time 86401754 ps
CPU time 1.18 seconds
Started Feb 09 06:24:56 AM UTC 25
Finished Feb 09 06:24:58 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334726176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3334726176
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.388798717
Short name T76
Test name
Test status
Simulation time 1380124728 ps
CPU time 9.48 seconds
Started Feb 09 06:24:56 AM UTC 25
Finished Feb 09 06:25:07 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388798717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 4.rstmgr_reset.388798717
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.890529130
Short name T74
Test name
Test status
Simulation time 8287630400 ps
CPU time 29.78 seconds
Started Feb 09 06:25:01 AM UTC 25
Finished Feb 09 06:25:33 AM UTC 25
Peak memory 241540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890529130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.890529130
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2917240343
Short name T146
Test name
Test status
Simulation time 109689332 ps
CPU time 1.52 seconds
Started Feb 09 06:24:59 AM UTC 25
Finished Feb 09 06:25:02 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917240343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2917240343
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.27561352
Short name T84
Test name
Test status
Simulation time 110991487 ps
CPU time 1.73 seconds
Started Feb 09 06:24:55 AM UTC 25
Finished Feb 09 06:24:58 AM UTC 25
Peak memory 207576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27561352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.rstmgr_smoke.27561352
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.2938164632
Short name T106
Test name
Test status
Simulation time 9369569678 ps
CPU time 37.82 seconds
Started Feb 09 06:25:01 AM UTC 25
Finished Feb 09 06:25:41 AM UTC 25
Peak memory 217764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938164632 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2938164632
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.605236726
Short name T85
Test name
Test status
Simulation time 478954850 ps
CPU time 4.17 seconds
Started Feb 09 06:24:58 AM UTC 25
Finished Feb 09 06:25:03 AM UTC 25
Peak memory 208664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605236726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.rstmgr_sw_rst.605236726
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.4212235804
Short name T136
Test name
Test status
Simulation time 257611314 ps
CPU time 2.25 seconds
Started Feb 09 06:24:57 AM UTC 25
Finished Feb 09 06:25:00 AM UTC 25
Peak memory 208584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212235804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.4212235804
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.1939618412
Short name T434
Test name
Test status
Simulation time 85438746 ps
CPU time 0.96 seconds
Started Feb 09 06:26:44 AM UTC 25
Finished Feb 09 06:26:46 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939618412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1939618412
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/40.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.4239709091
Short name T461
Test name
Test status
Simulation time 1225419204 ps
CPU time 5.21 seconds
Started Feb 09 06:26:44 AM UTC 25
Finished Feb 09 06:26:50 AM UTC 25
Peak memory 241128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239709091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.4239709091
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.6836533
Short name T435
Test name
Test status
Simulation time 245243307 ps
CPU time 1.03 seconds
Started Feb 09 06:26:44 AM UTC 25
Finished Feb 09 06:26:46 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6836533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_
rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.6836533
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.1877736954
Short name T433
Test name
Test status
Simulation time 181414794 ps
CPU time 1.02 seconds
Started Feb 09 06:26:44 AM UTC 25
Finished Feb 09 06:26:46 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877736954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1877736954
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.3267270639
Short name T403
Test name
Test status
Simulation time 888369630 ps
CPU time 4.19 seconds
Started Feb 09 06:26:44 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 208924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267270639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.rstmgr_reset.3267270639
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/40.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.469732581
Short name T436
Test name
Test status
Simulation time 141276874 ps
CPU time 1.2 seconds
Started Feb 09 06:26:44 AM UTC 25
Finished Feb 09 06:26:46 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469732581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec
_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.469732581
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.4215964941
Short name T438
Test name
Test status
Simulation time 197534097 ps
CPU time 1.55 seconds
Started Feb 09 06:26:44 AM UTC 25
Finished Feb 09 06:26:46 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215964941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.rstmgr_smoke.4215964941
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/40.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.322005235
Short name T542
Test name
Test status
Simulation time 7876468814 ps
CPU time 25.96 seconds
Started Feb 09 06:26:44 AM UTC 25
Finished Feb 09 06:27:11 AM UTC 25
Peak memory 217892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322005235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.322005235
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/40.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.2198819434
Short name T443
Test name
Test status
Simulation time 442322132 ps
CPU time 2.53 seconds
Started Feb 09 06:26:44 AM UTC 25
Finished Feb 09 06:26:48 AM UTC 25
Peak memory 208660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198819434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.rstmgr_sw_rst.2198819434
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.872135815
Short name T437
Test name
Test status
Simulation time 168411805 ps
CPU time 1.46 seconds
Started Feb 09 06:26:44 AM UTC 25
Finished Feb 09 06:26:46 AM UTC 25
Peak memory 207604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872135815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.872135815
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.1487884745
Short name T440
Test name
Test status
Simulation time 69457828 ps
CPU time 0.84 seconds
Started Feb 09 06:26:45 AM UTC 25
Finished Feb 09 06:26:47 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487884745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1487884745
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.2720355017
Short name T470
Test name
Test status
Simulation time 1227256760 ps
CPU time 5.38 seconds
Started Feb 09 06:26:45 AM UTC 25
Finished Feb 09 06:26:52 AM UTC 25
Peak memory 242040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720355017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2720355017
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.900799015
Short name T445
Test name
Test status
Simulation time 245241560 ps
CPU time 1.21 seconds
Started Feb 09 06:26:45 AM UTC 25
Finished Feb 09 06:26:48 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900799015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.900799015
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.2688945726
Short name T441
Test name
Test status
Simulation time 223440271 ps
CPU time 1.11 seconds
Started Feb 09 06:26:45 AM UTC 25
Finished Feb 09 06:26:47 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688945726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2688945726
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.2727005495
Short name T474
Test name
Test status
Simulation time 1741126567 ps
CPU time 5.86 seconds
Started Feb 09 06:26:45 AM UTC 25
Finished Feb 09 06:26:52 AM UTC 25
Peak memory 208784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727005495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.rstmgr_reset.2727005495
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3682106029
Short name T444
Test name
Test status
Simulation time 163577944 ps
CPU time 1.38 seconds
Started Feb 09 06:26:45 AM UTC 25
Finished Feb 09 06:26:48 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682106029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3682106029
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.2911683979
Short name T442
Test name
Test status
Simulation time 124040437 ps
CPU time 1.26 seconds
Started Feb 09 06:26:45 AM UTC 25
Finished Feb 09 06:26:48 AM UTC 25
Peak memory 207568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911683979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.rstmgr_smoke.2911683979
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.4212724784
Short name T544
Test name
Test status
Simulation time 11466249879 ps
CPU time 35.57 seconds
Started Feb 09 06:26:45 AM UTC 25
Finished Feb 09 06:27:22 AM UTC 25
Peak memory 217704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212724784 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4212724784
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.3668037479
Short name T447
Test name
Test status
Simulation time 358025523 ps
CPU time 2.23 seconds
Started Feb 09 06:26:45 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 217448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668037479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.rstmgr_sw_rst.3668037479
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.3396403865
Short name T439
Test name
Test status
Simulation time 108830798 ps
CPU time 0.95 seconds
Started Feb 09 06:26:45 AM UTC 25
Finished Feb 09 06:26:47 AM UTC 25
Peak memory 207460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396403865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3396403865
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.327246199
Short name T412
Test name
Test status
Simulation time 56579233 ps
CPU time 0.97 seconds
Started Feb 09 06:26:47 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 206832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327246199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.327246199
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/42.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.2551100299
Short name T510
Test name
Test status
Simulation time 2367847029 ps
CPU time 9.16 seconds
Started Feb 09 06:26:47 AM UTC 25
Finished Feb 09 06:26:57 AM UTC 25
Peak memory 241336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551100299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2551100299
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3925368134
Short name T451
Test name
Test status
Simulation time 243704626 ps
CPU time 1.06 seconds
Started Feb 09 06:26:47 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 236868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925368134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3925368134
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.4013552698
Short name T446
Test name
Test status
Simulation time 82119004 ps
CPU time 0.82 seconds
Started Feb 09 06:26:46 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013552698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.4013552698
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.3090124328
Short name T467
Test name
Test status
Simulation time 725376860 ps
CPU time 3.79 seconds
Started Feb 09 06:26:47 AM UTC 25
Finished Feb 09 06:26:52 AM UTC 25
Peak memory 208800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090124328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.rstmgr_reset.3090124328
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/42.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1867318495
Short name T458
Test name
Test status
Simulation time 148483968 ps
CPU time 1.78 seconds
Started Feb 09 06:26:47 AM UTC 25
Finished Feb 09 06:26:50 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867318495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1867318495
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.1620509363
Short name T453
Test name
Test status
Simulation time 114107334 ps
CPU time 1.63 seconds
Started Feb 09 06:26:46 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620509363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.rstmgr_smoke.1620509363
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/42.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.3442600485
Short name T545
Test name
Test status
Simulation time 9433444086 ps
CPU time 35.19 seconds
Started Feb 09 06:26:47 AM UTC 25
Finished Feb 09 06:27:23 AM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442600485 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3442600485
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/42.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.1834205983
Short name T454
Test name
Test status
Simulation time 123356666 ps
CPU time 1.65 seconds
Started Feb 09 06:26:47 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 207744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834205983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.rstmgr_sw_rst.1834205983
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.606182905
Short name T449
Test name
Test status
Simulation time 178953739 ps
CPU time 1.09 seconds
Started Feb 09 06:26:47 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 207604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606182905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.606182905
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.191442972
Short name T466
Test name
Test status
Simulation time 59486981 ps
CPU time 0.81 seconds
Started Feb 09 06:26:49 AM UTC 25
Finished Feb 09 06:26:51 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191442972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.191442972
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/43.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.3611880200
Short name T504
Test name
Test status
Simulation time 1899872011 ps
CPU time 6.78 seconds
Started Feb 09 06:26:48 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 241044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611880200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3611880200
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2087315199
Short name T462
Test name
Test status
Simulation time 244125528 ps
CPU time 1.2 seconds
Started Feb 09 06:26:48 AM UTC 25
Finished Feb 09 06:26:50 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087315199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2087315199
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.3826536776
Short name T375
Test name
Test status
Simulation time 180276643 ps
CPU time 1.03 seconds
Started Feb 09 06:26:47 AM UTC 25
Finished Feb 09 06:26:49 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826536776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3826536776
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.3389550341
Short name T506
Test name
Test status
Simulation time 1771384650 ps
CPU time 7.02 seconds
Started Feb 09 06:26:48 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 208860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389550341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.rstmgr_reset.3389550341
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/43.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1526372743
Short name T460
Test name
Test status
Simulation time 104993651 ps
CPU time 0.99 seconds
Started Feb 09 06:26:48 AM UTC 25
Finished Feb 09 06:26:50 AM UTC 25
Peak memory 207688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526372743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1526372743
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.3988584320
Short name T456
Test name
Test status
Simulation time 191029306 ps
CPU time 1.43 seconds
Started Feb 09 06:26:47 AM UTC 25
Finished Feb 09 06:26:50 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988584320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.rstmgr_smoke.3988584320
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/43.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.984704796
Short name T541
Test name
Test status
Simulation time 5384238675 ps
CPU time 17.9 seconds
Started Feb 09 06:26:48 AM UTC 25
Finished Feb 09 06:27:07 AM UTC 25
Peak memory 217896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984704796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.984704796
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/43.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.810131204
Short name T465
Test name
Test status
Simulation time 354038312 ps
CPU time 2.06 seconds
Started Feb 09 06:26:48 AM UTC 25
Finished Feb 09 06:26:51 AM UTC 25
Peak memory 208792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810131204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.rstmgr_sw_rst.810131204
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.3616370498
Short name T459
Test name
Test status
Simulation time 105529875 ps
CPU time 0.99 seconds
Started Feb 09 06:26:48 AM UTC 25
Finished Feb 09 06:26:50 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616370498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3616370498
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.2446990514
Short name T477
Test name
Test status
Simulation time 71496179 ps
CPU time 0.87 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:26:53 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446990514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2446990514
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/44.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.2273651724
Short name T524
Test name
Test status
Simulation time 2372135926 ps
CPU time 7.6 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:27:00 AM UTC 25
Peak memory 242128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273651724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2273651724
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2694556981
Short name T480
Test name
Test status
Simulation time 244401729 ps
CPU time 1.15 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:26:53 AM UTC 25
Peak memory 236868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694556981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2694556981
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.94377250
Short name T469
Test name
Test status
Simulation time 226500064 ps
CPU time 1.25 seconds
Started Feb 09 06:26:49 AM UTC 25
Finished Feb 09 06:26:52 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94377250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_
stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 44.rstmgr_por_stretcher.94377250
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.548098901
Short name T493
Test name
Test status
Simulation time 1138708415 ps
CPU time 4.46 seconds
Started Feb 09 06:26:49 AM UTC 25
Finished Feb 09 06:26:55 AM UTC 25
Peak memory 208924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548098901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.rstmgr_reset.548098901
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/44.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3547800681
Short name T479
Test name
Test status
Simulation time 98909862 ps
CPU time 1.11 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:26:53 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547800681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3547800681
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.2511542872
Short name T471
Test name
Test status
Simulation time 224499275 ps
CPU time 1.56 seconds
Started Feb 09 06:26:49 AM UTC 25
Finished Feb 09 06:26:52 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511542872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.rstmgr_smoke.2511542872
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/44.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.937968542
Short name T537
Test name
Test status
Simulation time 3241726185 ps
CPU time 12.22 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:27:04 AM UTC 25
Peak memory 209024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937968542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.937968542
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/44.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.998615469
Short name T475
Test name
Test status
Simulation time 449402406 ps
CPU time 2.16 seconds
Started Feb 09 06:26:49 AM UTC 25
Finished Feb 09 06:26:53 AM UTC 25
Peak memory 208664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998615469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.rstmgr_sw_rst.998615469
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.3384405510
Short name T468
Test name
Test status
Simulation time 109785656 ps
CPU time 1.03 seconds
Started Feb 09 06:26:49 AM UTC 25
Finished Feb 09 06:26:52 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384405510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3384405510
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.1635567140
Short name T484
Test name
Test status
Simulation time 72947134 ps
CPU time 0.91 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:26:53 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635567140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1635567140
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/45.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.2462423136
Short name T526
Test name
Test status
Simulation time 2367586054 ps
CPU time 7.83 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:27:00 AM UTC 25
Peak memory 241456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462423136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2462423136
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1963431807
Short name T485
Test name
Test status
Simulation time 245619679 ps
CPU time 1.18 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:26:54 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963431807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1963431807
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.2082264661
Short name T486
Test name
Test status
Simulation time 239985829 ps
CPU time 1.36 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:26:54 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082264661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2082264661
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.910508197
Short name T496
Test name
Test status
Simulation time 664072730 ps
CPU time 3.37 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 208800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910508197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.rstmgr_reset.910508197
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/45.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2706948440
Short name T483
Test name
Test status
Simulation time 149236052 ps
CPU time 1.08 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:26:53 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706948440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2706948440
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.3668063794
Short name T481
Test name
Test status
Simulation time 116987145 ps
CPU time 1.15 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:26:53 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668063794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 45.rstmgr_smoke.3668063794
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/45.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.634346
Short name T540
Test name
Test status
Simulation time 3380025968 ps
CPU time 14.05 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:27:06 AM UTC 25
Peak memory 217764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.634346
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/45.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.3374703681
Short name T492
Test name
Test status
Simulation time 387821237 ps
CPU time 2.48 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:26:55 AM UTC 25
Peak memory 208724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374703681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 45.rstmgr_sw_rst.3374703681
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.636661587
Short name T482
Test name
Test status
Simulation time 150534177 ps
CPU time 1.14 seconds
Started Feb 09 06:26:51 AM UTC 25
Finished Feb 09 06:26:53 AM UTC 25
Peak memory 207604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636661587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.636661587
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.3171869020
Short name T498
Test name
Test status
Simulation time 82700734 ps
CPU time 0.91 seconds
Started Feb 09 06:26:53 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171869020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3171869020
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/46.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.2921968481
Short name T523
Test name
Test status
Simulation time 1227701629 ps
CPU time 5.41 seconds
Started Feb 09 06:26:52 AM UTC 25
Finished Feb 09 06:26:59 AM UTC 25
Peak memory 242100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921968481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2921968481
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1201641933
Short name T489
Test name
Test status
Simulation time 243579949 ps
CPU time 1.02 seconds
Started Feb 09 06:26:52 AM UTC 25
Finished Feb 09 06:26:55 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201641933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1201641933
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.1100787066
Short name T490
Test name
Test status
Simulation time 178986402 ps
CPU time 1.19 seconds
Started Feb 09 06:26:52 AM UTC 25
Finished Feb 09 06:26:55 AM UTC 25
Peak memory 207600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100787066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1100787066
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.2635092081
Short name T529
Test name
Test status
Simulation time 1656297860 ps
CPU time 7.13 seconds
Started Feb 09 06:26:52 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 208796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635092081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 46.rstmgr_reset.2635092081
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/46.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.221488470
Short name T488
Test name
Test status
Simulation time 183074044 ps
CPU time 1.1 seconds
Started Feb 09 06:26:52 AM UTC 25
Finished Feb 09 06:26:55 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221488470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec
_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.221488470
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.979220752
Short name T491
Test name
Test status
Simulation time 190331917 ps
CPU time 1.29 seconds
Started Feb 09 06:26:52 AM UTC 25
Finished Feb 09 06:26:55 AM UTC 25
Peak memory 207624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979220752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.rstmgr_smoke.979220752
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/46.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.1866202026
Short name T547
Test name
Test status
Simulation time 11764455078 ps
CPU time 36.2 seconds
Started Feb 09 06:26:52 AM UTC 25
Finished Feb 09 06:27:30 AM UTC 25
Peak memory 217892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866202026 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1866202026
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/46.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.848750452
Short name T494
Test name
Test status
Simulation time 130067421 ps
CPU time 1.52 seconds
Started Feb 09 06:26:52 AM UTC 25
Finished Feb 09 06:26:55 AM UTC 25
Peak memory 207684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848750452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 46.rstmgr_sw_rst.848750452
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.4020560953
Short name T487
Test name
Test status
Simulation time 130905751 ps
CPU time 1.11 seconds
Started Feb 09 06:26:52 AM UTC 25
Finished Feb 09 06:26:55 AM UTC 25
Peak memory 207716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020560953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4020560953
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.2468588269
Short name T509
Test name
Test status
Simulation time 60563204 ps
CPU time 1 seconds
Started Feb 09 06:26:55 AM UTC 25
Finished Feb 09 06:26:57 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468588269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2468588269
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/47.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.1620987552
Short name T536
Test name
Test status
Simulation time 2361085436 ps
CPU time 8.41 seconds
Started Feb 09 06:26:54 AM UTC 25
Finished Feb 09 06:27:04 AM UTC 25
Peak memory 241512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620987552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1620987552
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2377112901
Short name T501
Test name
Test status
Simulation time 244314928 ps
CPU time 1.09 seconds
Started Feb 09 06:26:54 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 236612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377112901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2377112901
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.2078671163
Short name T497
Test name
Test status
Simulation time 116998489 ps
CPU time 0.83 seconds
Started Feb 09 06:26:54 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078671163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2078671163
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.147283510
Short name T530
Test name
Test status
Simulation time 1729003097 ps
CPU time 6.06 seconds
Started Feb 09 06:26:54 AM UTC 25
Finished Feb 09 06:27:01 AM UTC 25
Peak memory 208796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147283510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.rstmgr_reset.147283510
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/47.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3047061490
Short name T505
Test name
Test status
Simulation time 170899563 ps
CPU time 1.23 seconds
Started Feb 09 06:26:54 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047061490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3047061490
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.40042893
Short name T503
Test name
Test status
Simulation time 126152857 ps
CPU time 1.24 seconds
Started Feb 09 06:26:54 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40042893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.rstmgr_smoke.40042893
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/47.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.3869026516
Short name T514
Test name
Test status
Simulation time 554584004 ps
CPU time 2.39 seconds
Started Feb 09 06:26:54 AM UTC 25
Finished Feb 09 06:26:58 AM UTC 25
Peak memory 209044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869026516 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3869026516
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/47.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.2553103667
Short name T507
Test name
Test status
Simulation time 142871097 ps
CPU time 1.56 seconds
Started Feb 09 06:26:54 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 207744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553103667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 47.rstmgr_sw_rst.2553103667
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.1805920104
Short name T502
Test name
Test status
Simulation time 211282521 ps
CPU time 1.25 seconds
Started Feb 09 06:26:54 AM UTC 25
Finished Feb 09 06:26:56 AM UTC 25
Peak memory 207068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805920104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1805920104
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.442582384
Short name T516
Test name
Test status
Simulation time 73657756 ps
CPU time 1.04 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:26:59 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442582384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.442582384
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/48.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.401459352
Short name T535
Test name
Test status
Simulation time 1225716687 ps
CPU time 5.87 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:27:03 AM UTC 25
Peak memory 242124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401459352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.401459352
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2108172620
Short name T517
Test name
Test status
Simulation time 243834064 ps
CPU time 1.2 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:26:59 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108172620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2108172620
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.2864411821
Short name T508
Test name
Test status
Simulation time 110207166 ps
CPU time 0.8 seconds
Started Feb 09 06:26:55 AM UTC 25
Finished Feb 09 06:26:57 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864411821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2864411821
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.2379225982
Short name T478
Test name
Test status
Simulation time 1852423455 ps
CPU time 6.68 seconds
Started Feb 09 06:26:55 AM UTC 25
Finished Feb 09 06:27:03 AM UTC 25
Peak memory 208800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379225982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.rstmgr_reset.2379225982
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/48.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.939708193
Short name T512
Test name
Test status
Simulation time 100661844 ps
CPU time 1.04 seconds
Started Feb 09 06:26:55 AM UTC 25
Finished Feb 09 06:26:57 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939708193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec
_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.939708193
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.577647402
Short name T513
Test name
Test status
Simulation time 114120951 ps
CPU time 1.29 seconds
Started Feb 09 06:26:55 AM UTC 25
Finished Feb 09 06:26:57 AM UTC 25
Peak memory 207688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577647402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.rstmgr_smoke.577647402
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/48.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.2519061947
Short name T546
Test name
Test status
Simulation time 10324270560 ps
CPU time 31.13 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:27:29 AM UTC 25
Peak memory 208916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519061947 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2519061947
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/48.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.16839041
Short name T515
Test name
Test status
Simulation time 127815059 ps
CPU time 1.42 seconds
Started Feb 09 06:26:55 AM UTC 25
Finished Feb 09 06:26:58 AM UTC 25
Peak memory 216456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16839041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_r
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.rstmgr_sw_rst.16839041
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.2843470524
Short name T511
Test name
Test status
Simulation time 68661827 ps
CPU time 1 seconds
Started Feb 09 06:26:55 AM UTC 25
Finished Feb 09 06:26:57 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843470524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2843470524
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.1689496348
Short name T525
Test name
Test status
Simulation time 84580937 ps
CPU time 0.82 seconds
Started Feb 09 06:26:58 AM UTC 25
Finished Feb 09 06:27:00 AM UTC 25
Peak memory 207788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689496348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1689496348
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/49.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.235049969
Short name T534
Test name
Test status
Simulation time 1227745420 ps
CPU time 5.01 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:27:03 AM UTC 25
Peak memory 241996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235049969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.235049969
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1468929714
Short name T522
Test name
Test status
Simulation time 244582757 ps
CPU time 1.16 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:26:59 AM UTC 25
Peak memory 236868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468929714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1468929714
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.3357732718
Short name T519
Test name
Test status
Simulation time 167193491 ps
CPU time 1.03 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:26:59 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357732718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3357732718
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.1946474465
Short name T533
Test name
Test status
Simulation time 1016464133 ps
CPU time 4.33 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:27:02 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946474465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.rstmgr_reset.1946474465
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/49.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2071741280
Short name T521
Test name
Test status
Simulation time 106870385 ps
CPU time 1.06 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:26:59 AM UTC 25
Peak memory 207720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071741280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2071741280
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.50766939
Short name T520
Test name
Test status
Simulation time 111361167 ps
CPU time 1.21 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:26:59 AM UTC 25
Peak memory 207684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50766939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.rstmgr_smoke.50766939
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/49.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.2112336149
Short name T539
Test name
Test status
Simulation time 2436303425 ps
CPU time 7.7 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:27:06 AM UTC 25
Peak memory 217704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112336149 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2112336149
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/49.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.2311615427
Short name T527
Test name
Test status
Simulation time 381238567 ps
CPU time 2.52 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:27:00 AM UTC 25
Peak memory 208788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311615427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.rstmgr_sw_rst.2311615427
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.3981903280
Short name T518
Test name
Test status
Simulation time 142916804 ps
CPU time 1.04 seconds
Started Feb 09 06:26:56 AM UTC 25
Finished Feb 09 06:26:59 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981903280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3981903280
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.875208923
Short name T81
Test name
Test status
Simulation time 64146865 ps
CPU time 1.16 seconds
Started Feb 09 06:25:10 AM UTC 25
Finished Feb 09 06:25:12 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875208923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_tes
t +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.875208923
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.2692422959
Short name T43
Test name
Test status
Simulation time 1229626875 ps
CPU time 8.54 seconds
Started Feb 09 06:25:08 AM UTC 25
Finished Feb 09 06:25:18 AM UTC 25
Peak memory 240836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692422959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2692422959
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2951850146
Short name T80
Test name
Test status
Simulation time 243950627 ps
CPU time 1.75 seconds
Started Feb 09 06:25:08 AM UTC 25
Finished Feb 09 06:25:11 AM UTC 25
Peak memory 236704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951850146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2951850146
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.575234236
Short name T17
Test name
Test status
Simulation time 222023885 ps
CPU time 1.7 seconds
Started Feb 09 06:25:04 AM UTC 25
Finished Feb 09 06:25:07 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575234236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por
_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.575234236
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.3188105783
Short name T99
Test name
Test status
Simulation time 1365334954 ps
CPU time 9.18 seconds
Started Feb 09 06:25:06 AM UTC 25
Finished Feb 09 06:25:16 AM UTC 25
Peak memory 208796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188105783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.rstmgr_reset.3188105783
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1357578231
Short name T78
Test name
Test status
Simulation time 151689627 ps
CPU time 1.74 seconds
Started Feb 09 06:25:07 AM UTC 25
Finished Feb 09 06:25:10 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357578231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1357578231
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.3168958822
Short name T86
Test name
Test status
Simulation time 250403299 ps
CPU time 1.67 seconds
Started Feb 09 06:25:02 AM UTC 25
Finished Feb 09 06:25:05 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168958822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.rstmgr_smoke.3168958822
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.949097758
Short name T79
Test name
Test status
Simulation time 135282791 ps
CPU time 2.42 seconds
Started Feb 09 06:25:07 AM UTC 25
Finished Feb 09 06:25:10 AM UTC 25
Peak memory 217644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949097758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.rstmgr_sw_rst.949097758
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.3686775542
Short name T77
Test name
Test status
Simulation time 251000540 ps
CPU time 2.21 seconds
Started Feb 09 06:25:06 AM UTC 25
Finished Feb 09 06:25:09 AM UTC 25
Peak memory 208584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686775542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3686775542
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1692377335
Short name T150
Test name
Test status
Simulation time 77657006 ps
CPU time 1.32 seconds
Started Feb 09 06:25:15 AM UTC 25
Finished Feb 09 06:25:17 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692377335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1692377335
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2205652110
Short name T151
Test name
Test status
Simulation time 244743392 ps
CPU time 1.91 seconds
Started Feb 09 06:25:15 AM UTC 25
Finished Feb 09 06:25:18 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205652110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2205652110
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.4150347100
Short name T18
Test name
Test status
Simulation time 192948419 ps
CPU time 1.47 seconds
Started Feb 09 06:25:11 AM UTC 25
Finished Feb 09 06:25:14 AM UTC 25
Peak memory 207600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150347100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.4150347100
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.3533079511
Short name T100
Test name
Test status
Simulation time 1369829605 ps
CPU time 7.94 seconds
Started Feb 09 06:25:11 AM UTC 25
Finished Feb 09 06:25:20 AM UTC 25
Peak memory 208844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533079511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.rstmgr_reset.3533079511
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.939609382
Short name T149
Test name
Test status
Simulation time 102456704 ps
CPU time 1.21 seconds
Started Feb 09 06:25:13 AM UTC 25
Finished Feb 09 06:25:16 AM UTC 25
Peak memory 207656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939609382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec
_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.939609382
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2092151241
Short name T82
Test name
Test status
Simulation time 116163218 ps
CPU time 1.65 seconds
Started Feb 09 06:25:10 AM UTC 25
Finished Feb 09 06:25:13 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092151241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.rstmgr_smoke.2092151241
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.3606795878
Short name T89
Test name
Test status
Simulation time 128154799 ps
CPU time 2.33 seconds
Started Feb 09 06:25:13 AM UTC 25
Finished Feb 09 06:25:17 AM UTC 25
Peak memory 217576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606795878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.rstmgr_sw_rst.3606795878
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.3952753946
Short name T145
Test name
Test status
Simulation time 247441059 ps
CPU time 1.77 seconds
Started Feb 09 06:25:11 AM UTC 25
Finished Feb 09 06:25:14 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952753946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3952753946
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2811495556
Short name T155
Test name
Test status
Simulation time 90230098 ps
CPU time 1.26 seconds
Started Feb 09 06:25:20 AM UTC 25
Finished Feb 09 06:25:23 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811495556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2811495556
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.649475393
Short name T44
Test name
Test status
Simulation time 1233200431 ps
CPU time 8.02 seconds
Started Feb 09 06:25:19 AM UTC 25
Finished Feb 09 06:25:28 AM UTC 25
Peak memory 242040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649475393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_lea
f_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.649475393
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3354907948
Short name T154
Test name
Test status
Simulation time 244910292 ps
CPU time 1.47 seconds
Started Feb 09 06:25:19 AM UTC 25
Finished Feb 09 06:25:22 AM UTC 25
Peak memory 236868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354907948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3354907948
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.1939696957
Short name T19
Test name
Test status
Simulation time 225073536 ps
CPU time 1.47 seconds
Started Feb 09 06:25:17 AM UTC 25
Finished Feb 09 06:25:19 AM UTC 25
Peak memory 207588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939696957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1939696957
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.181530696
Short name T102
Test name
Test status
Simulation time 893531653 ps
CPU time 7.28 seconds
Started Feb 09 06:25:18 AM UTC 25
Finished Feb 09 06:25:26 AM UTC 25
Peak memory 208792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181530696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.rstmgr_reset.181530696
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1845506521
Short name T140
Test name
Test status
Simulation time 105412634 ps
CPU time 1.16 seconds
Started Feb 09 06:25:19 AM UTC 25
Finished Feb 09 06:25:21 AM UTC 25
Peak memory 206900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845506521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1845506521
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.4150302466
Short name T152
Test name
Test status
Simulation time 127191987 ps
CPU time 1.32 seconds
Started Feb 09 06:25:17 AM UTC 25
Finished Feb 09 06:25:19 AM UTC 25
Peak memory 207496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150302466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.rstmgr_smoke.4150302466
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.426682601
Short name T170
Test name
Test status
Simulation time 2232624873 ps
CPU time 13.66 seconds
Started Feb 09 06:25:20 AM UTC 25
Finished Feb 09 06:25:35 AM UTC 25
Peak memory 208916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426682601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.426682601
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.3012615192
Short name T137
Test name
Test status
Simulation time 411245663 ps
CPU time 2.86 seconds
Started Feb 09 06:25:19 AM UTC 25
Finished Feb 09 06:25:23 AM UTC 25
Peak memory 208156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012615192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.rstmgr_sw_rst.3012615192
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.3734684481
Short name T153
Test name
Test status
Simulation time 103779482 ps
CPU time 1.46 seconds
Started Feb 09 06:25:18 AM UTC 25
Finished Feb 09 06:25:20 AM UTC 25
Peak memory 207636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734684481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3734684481
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.23060245
Short name T160
Test name
Test status
Simulation time 92067463 ps
CPU time 1.19 seconds
Started Feb 09 06:25:25 AM UTC 25
Finished Feb 09 06:25:27 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23060245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test
+UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.23060245
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1497366341
Short name T159
Test name
Test status
Simulation time 245281438 ps
CPU time 1.9 seconds
Started Feb 09 06:25:24 AM UTC 25
Finished Feb 09 06:25:27 AM UTC 25
Peak memory 236868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497366341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1497366341
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.3820867741
Short name T20
Test name
Test status
Simulation time 193739115 ps
CPU time 1.59 seconds
Started Feb 09 06:25:21 AM UTC 25
Finished Feb 09 06:25:24 AM UTC 25
Peak memory 207660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820867741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_po
r_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3820867741
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.817152182
Short name T103
Test name
Test status
Simulation time 802287939 ps
CPU time 6.47 seconds
Started Feb 09 06:25:21 AM UTC 25
Finished Feb 09 06:25:29 AM UTC 25
Peak memory 208984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817152182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.rstmgr_reset.817152182
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3406043731
Short name T158
Test name
Test status
Simulation time 185873201 ps
CPU time 1.87 seconds
Started Feb 09 06:25:23 AM UTC 25
Finished Feb 09 06:25:26 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406043731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3406043731
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.514383117
Short name T156
Test name
Test status
Simulation time 111784360 ps
CPU time 1.83 seconds
Started Feb 09 06:25:21 AM UTC 25
Finished Feb 09 06:25:24 AM UTC 25
Peak memory 207684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514383117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.rstmgr_smoke.514383117
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.2899610909
Short name T231
Test name
Test status
Simulation time 9506738272 ps
CPU time 37.84 seconds
Started Feb 09 06:25:24 AM UTC 25
Finished Feb 09 06:26:03 AM UTC 25
Peak memory 217704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899610909 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2899610909
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.1565514386
Short name T138
Test name
Test status
Simulation time 534823552 ps
CPU time 4.21 seconds
Started Feb 09 06:25:23 AM UTC 25
Finished Feb 09 06:25:28 AM UTC 25
Peak memory 208660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565514386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.rstmgr_sw_rst.1565514386
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.3180064277
Short name T157
Test name
Test status
Simulation time 128026668 ps
CPU time 1.63 seconds
Started Feb 09 06:25:23 AM UTC 25
Finished Feb 09 06:25:25 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180064277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3180064277
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.3227527744
Short name T164
Test name
Test status
Simulation time 65451409 ps
CPU time 1.18 seconds
Started Feb 09 06:25:30 AM UTC 25
Finished Feb 09 06:25:32 AM UTC 25
Peak memory 207792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227527744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_te
st +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3227527744
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.3357756688
Short name T45
Test name
Test status
Simulation time 1919462679 ps
CPU time 9.1 seconds
Started Feb 09 06:25:28 AM UTC 25
Finished Feb 09 06:25:39 AM UTC 25
Peak memory 241704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357756688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3357756688
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1722457024
Short name T163
Test name
Test status
Simulation time 243660129 ps
CPU time 1.96 seconds
Started Feb 09 06:25:28 AM UTC 25
Finished Feb 09 06:25:32 AM UTC 25
Peak memory 236928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722457024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_le
af_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1722457024
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.941373739
Short name T21
Test name
Test status
Simulation time 87536208 ps
CPU time 1.19 seconds
Started Feb 09 06:25:26 AM UTC 25
Finished Feb 09 06:25:28 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941373739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por
_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.941373739
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.1775356037
Short name T105
Test name
Test status
Simulation time 1075879612 ps
CPU time 8.22 seconds
Started Feb 09 06:25:26 AM UTC 25
Finished Feb 09 06:25:36 AM UTC 25
Peak memory 208856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775356037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.rstmgr_reset.1775356037
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3826508437
Short name T162
Test name
Test status
Simulation time 101898446 ps
CPU time 1.5 seconds
Started Feb 09 06:25:27 AM UTC 25
Finished Feb 09 06:25:30 AM UTC 25
Peak memory 207724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826508437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_se
c_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3826508437
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.2567894920
Short name T139
Test name
Test status
Simulation time 260400366 ps
CPU time 2.37 seconds
Started Feb 09 06:25:25 AM UTC 25
Finished Feb 09 06:25:29 AM UTC 25
Peak memory 208984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567894920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.rstmgr_smoke.2567894920
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.321323211
Short name T132
Test name
Test status
Simulation time 2590096458 ps
CPU time 13.57 seconds
Started Feb 09 06:25:28 AM UTC 25
Finished Feb 09 06:25:44 AM UTC 25
Peak memory 208920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321323211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_
test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.321323211
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.726810018
Short name T90
Test name
Test status
Simulation time 129614002 ps
CPU time 2.33 seconds
Started Feb 09 06:25:27 AM UTC 25
Finished Feb 09 06:25:31 AM UTC 25
Peak memory 217512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726810018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_
rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.rstmgr_sw_rst.726810018
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.3132958100
Short name T161
Test name
Test status
Simulation time 95743026 ps
CPU time 1.38 seconds
Started Feb 09 06:25:27 AM UTC 25
Finished Feb 09 06:25:30 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132958100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw
_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3132958100
Directory /workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest
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