RSTMGR_CNSTY_CHK Simulation Results

Wednesday February 14 2024 20:02:28 UTC

GitHub Revision: 93b7cb99d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53669536132820869698500732458181248593474076177124168900566436467251403141328

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 TOTAL 0 0 --
V2 TOTAL 0 0 --
V2S unexpected_child_reset_activity rstmgr_cnsty_chk_smoke 0 0 --
V2S child_reset_asserts_late child_reset_asserts_late 0 0 --
V2S child_reset_releases_late child_reset_releases_late 0 0 --
V2S parent_reset_asserts_late parent_reset_asserts_late 0 0 --
V2S parent_reset_releases_late parent_reset_releases_late 0 0 --
V2S TOTAL 0 0 --
V3 TOTAL 0 0 --
Unmapped tests rstmgr_cnsty_chk_test 0 10 0.00
TOTAL 0 10 0.00

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V2S 5 0 0 0.00

Failure Buckets

Past Results