RSTMGR_CNSTY_CHK Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 TOTAL 0 0 --
V2 TOTAL 0 0 --
V2S unexpected_child_reset_activity rstmgr_cnsty_chk_smoke 0 0 --
V2S child_reset_asserts_late child_reset_asserts_late 0 0 --
V2S child_reset_releases_late child_reset_releases_late 0 0 --
V2S parent_reset_asserts_late parent_reset_asserts_late 0 0 --
V2S parent_reset_releases_late parent_reset_releases_late 0 0 --
V2S TOTAL 0 0 --
V3 TOTAL 0 0 --
Unmapped tests rstmgr_cnsty_chk_test 3.040s 10.492ms 10 10 100.00
TOTAL 10 10 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V2S 5 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00

Past Results