RSTMGR_CNSTY_CHK Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 TOTAL 0 0 --
V2 TOTAL 0 0 --
V2S unexpected_child_reset_activity rstmgr_cnsty_chk_smoke 0 0 --
V2S child_reset_asserts_late child_reset_asserts_late 0 0 --
V2S child_reset_releases_late child_reset_releases_late 0 0 --
V2S parent_reset_asserts_late parent_reset_asserts_late 0 0 --
V2S parent_reset_releases_late parent_reset_releases_late 0 0 --
V2S TOTAL 0 0 --
V3 TOTAL 0 0 --
Unmapped tests rstmgr_cnsty_chk_test 5.890s 11.071ms 10 10 100.00
TOTAL 10 10 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V2S 5 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00

Past Results