548a3880d8| Build Mode | Flow Infos | Flow Warnings | Flow Errors | Lint Infos | Lint Warnings | Lint Errors |
|---|---|---|---|---|---|---|
| default | 0 | 0 | 0 | 173 | 1 | 1 |
'default'I FSM_DEFAULT_REQ: prim_sync_reqack.sv:253 Next state register 'gen_nrz_hs_protocol.src_fsm_ns' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: prim_sync_reqack.sv:297 Next state register 'gen_nrz_hs_protocol.dst_fsm_ns' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: prim_diff_decode.sv:158 Next state register 'gen_async.state_d' has no assignment in the default branch of the case statement for this finite state machine New
I NESTED_SUBPROG: tlul_pkg.sv:143 Function 'prim_mubi_pkg::mubi4_test_invalid' is called from within a function New
I CASE_INC: rstmgr_cnsty_chk.sv:158 Case statement tag not specified for value 'b000000 and many other values New
I CASE_INC: prim_alert_sender.sv:199 Case statement tag not specified for value 'b111 New
I CASE_INC: prim_diff_decode.sv:115 Case statement tag not specified for value 'b11 New
I CASE_INC: tlul_err.sv:62 Case statement tag not specified for value 'h3 New
I ONE_BIT_VEC: rstmgr.sv:80 Declaration range '[0:0]' of 'gen_rst_por_aon[0:1].por_scanmode' has a length of one New
I ONE_BIT_VEC: rstmgr.sv:248 Declaration range '[0:0]' of 'rst_ctrl_scanmode' has a length of one New
I ONE_BIT_VEC: rstmgr_crash_info.sv:50 Declaration range '[IdxWidth - SlotCntWidth - 1:0]' ([0:0]) of 'gen_tieoffs.unused_idx' has a length of one, instance 'rstmgr.u_cpu_info' of module 'rstmgr_crash_info' (CrashDumpWidth=225,CrashRemainder=1 ('CrashDumpWidth % RdWidth > 0 ? 1 : 0'),CrashStoreSlot=8 ('CrashDumpWidth / RdWidth + CrashRemainder'),IdxWidth=4,RdWidth=32,SlotCntWidth=3 ('$clog2(CrashStoreSlot)')) New
I ONE_BIT_VEC: rstmgr_ctrl.sv:26 Declaration range '[OffDomains - 1:0]' ([0:0]) of 'rst_pd_nd' has a length of one, instance 'rstmgr.u_lc_src' of module 'rstmgr_ctrl' (OffDomains=1 ('PowerDomains - 1'),PowerDomains=2) New
I ONE_BIT_VEC: prim_buf.sv:24 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'rstmgr.u_ctrl_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_buf.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'rstmgr.u_ctrl_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:22 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:27 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:28 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:19 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:26 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'rstmgr.u_ctrl_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'rstmgr.u_ctrl_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'inv' has a length of one, instance 'rstmgr.u_ctrl_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:9 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:13 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:9 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:15 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:18 Declaration range '[Width - 1:0]' ([0:0]) of 'd_o' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:19 Declaration range '[Width - 1:0]' ([0:0]) of 'intq' has a length of one, instance 'rstmgr.u_lc_src.u_aon_rst.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_mubi4_sync.sv:38 Declaration range '[NumCopies - 1:0]' ([0:0]) of 'mubi_o' has a length of one, instance 'rstmgr.u_ctrl_scanmode_sync' of module 'prim_mubi4_sync' (NumCopies=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'rstmgr.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'rstmgr.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_subreg.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'RESVAL' has a length of one, instance 'rstmgr.u_reg.u_reset_info_por' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'rstmgr.u_reg.u_reset_info_por' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:25 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'rstmgr.u_reg.u_reset_info_por' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:29 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'rstmgr.u_reg.u_reset_info_por' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:34 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'rstmgr.u_reg.u_reset_info_por' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:35 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'rstmgr.u_reg.u_reset_info_por' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:39 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'rstmgr.u_reg.u_reset_info_por' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:17 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'rstmgr.u_reg.u_reset_info_por.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'rstmgr.u_reg.u_reset_info_por.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:24 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'rstmgr.u_reg.u_reset_info_por.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:28 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'rstmgr.u_reg.u_reset_info_por.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:36 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_w.unused_q' has a length of one, instance 'rstmgr.u_reg.u_alert_info_ctrl_en.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:47 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_wd' has a length of one, instance 'rstmgr.u_reg.u_err_code_reg_intg_err.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:48 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_q' has a length of one, instance 'rstmgr.u_reg.u_err_code_reg_intg_err.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'rstmgr.u_reg.u_alert_test_fatal_fault' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:14 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'rstmgr.u_reg.u_alert_test_fatal_fault' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:19 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'rstmgr.u_reg.u_alert_test_fatal_fault' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:20 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'rstmgr.u_reg.u_alert_test_fatal_fault' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'rstmgr.u_reg.u_alert_test_fatal_fault' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'd_sink' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_t' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_pre' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_reg_d2h' has a length of one New
I EXPLICIT_BITLEN: prim_util_pkg.sv:85 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: tlul_err.sv:69 Bit length not specified for constant "'h1" New
I EXPLICIT_BITLEN: tlul_err.sv:77 Bit length not specified for constant "'h2" New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:26 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:30 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:36 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:41 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:44 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:50 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:53 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:59 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:62 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:67 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:72 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:75 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:78 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:83 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:89 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:93 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:97 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:104 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:110 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:114 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:119 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:125 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:129 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:134 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:138 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: rstmgr_reg_pkg.sv:142 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:85 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:111 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:217 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:243 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:349 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:375 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:481 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:507 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:25 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:29 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:21 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:24 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:14 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:19 Name 'q' is shorter than minimum length 2 New
I CONST_OUTPUT: rstmgr.sv:317 Output 'resets_o.rst_por_n[1]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:320 Output 'rst_en_o.por[1]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:351 Output 'resets_o.rst_por_io_n[1]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:354 Output 'rst_en_o.por_io[1]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:385 Output 'resets_o.rst_por_io_div2_n[1]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:388 Output 'rst_en_o.por_io_div2[1]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:419 Output 'resets_o.rst_por_io_div4_n[1]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:422 Output 'rst_en_o.por_io_div4[1]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:453 Output 'resets_o.rst_por_usb_n[1]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:456 Output 'rst_en_o.por_usb[1]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:587 Output 'resets_o.rst_lc_aon_n[1]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:590 Output 'rst_en_o.lc_aon[1]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:835 Output 'resets_o.rst_sys_n[0]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:838 Output 'rst_en_o.sys[0]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:893 Output 'resets_o.rst_sys_io_div4_n[1]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:896 Output 'rst_en_o.sys_io_div4[1]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:903 Output 'resets_o.rst_spi_device_n[0]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:906 Output 'rst_en_o.spi_device[0]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:937 Output 'resets_o.rst_spi_host0_n[0]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:940 Output 'rst_en_o.spi_host0[0]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:971 Output 'resets_o.rst_spi_host1_n[0]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:974 Output 'rst_en_o.spi_host1[0]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:1005 Output 'resets_o.rst_usb_n[0]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:1008 Output 'rst_en_o.usb[0]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:1039 Output 'resets_o.rst_usb_aon_n[0]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:1042 Output 'rst_en_o.usb_aon[0]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:1073 Output 'resets_o.rst_i2c0_n[0]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:1076 Output 'rst_en_o.i2c0[0]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:1107 Output 'resets_o.rst_i2c1_n[0]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:1110 Output 'rst_en_o.i2c1[0]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr.sv:1141 Output 'resets_o.rst_i2c2_n[0]' is driven by constant zero New
I CONST_OUTPUT: rstmgr.sv:1144 Output 'rst_en_o.i2c2[0]' is driven by constant 4'b0110 New
I CONST_OUTPUT: rstmgr_crash_info.sv:44 Output 'slots_cnt_o' is driven by constant 4'b1000 in module 'rstmgr_crash_info' (CrashDumpWidth=225) New
I CONST_OUTPUT: rstmgr_crash_info.sv:44 Output 'slots_cnt_o' is driven by constant 4'b1001 in module 'rstmgr_crash_info' (CrashDumpWidth=276) New
I CONST_OUTPUT: rstmgr_leaf_rst.sv:120 Output 'err_o' is driven by constant zero in module 'rstmgr_leaf_rst' (SecCheck=0,SwRstReq=1'h0) New
I CONST_OUTPUT: rstmgr_leaf_rst.sv:121 Output 'fsm_err_o' is driven by constant zero in module 'rstmgr_leaf_rst' (SecCheck=0,SwRstReq=1'h0) New
I CONST_OUTPUT: tlul_adapter_reg.sv:91 Output 'addr_o[1:0]' is driven by constant zeros in module 'tlul_adapter_reg' (RegAw=7) New
I CONST_OUTPUT: tlul_adapter_reg.sv:195 Output 'intg_error_o' is driven by constant zero in module 'tlul_adapter_reg' (RegAw=7) New
W STAR_PORT_CONN_USE: prim_flop_2sync.sv:35 '.*' wild card port connection encountered on instance 'gen_generic.u_impl_generic' New
E IFDEF_CODE: prim_generic_flop_2sync.sv:35 Assignment to 'unused_sig' contained within `else block at prim_generic_flop_2sync.sv:33 prim_generic_flop_2sync.sv:33 New