CHIP_EARLGREY_ASIC Lint Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: 83db9403d

Branch: os_regression

Tool: VERILATOR

Build Mode Flow Warnings Flow Errors Lint Warnings Lint Errors
default 0 2 107 0

Messages for Build Mode 'default'

Flow Errors

ERROR: %Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:112:5: Unsized numbers/parameters not allowed in concatenations.

ERROR: Failed to build lowrisc:systems:chip_earlgrey_asic:0.1 : '['make', '-j', '120', 'Vchip_earlgrey_asic.mk']' exited with an error: 2

Lint Warnings

%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:113:5: Unsized numbers/parameters not allowed in concatenations.

%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:114:5: Unsized numbers/parameters not allowed in concatenations.

%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:115:5: Unsized numbers/parameters not allowed in concatenations.

%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:116:5: Unsized numbers/parameters not allowed in concatenations.

%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:117:5: Unsized numbers/parameters not allowed in concatenations.

%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:118:5: Unsized numbers/parameters not allowed in concatenations.

%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:119:5: Unsized numbers/parameters not allowed in concatenations.

%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:121:5: Unsized numbers/parameters not allowed in concatenations.

%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:122:5: Unsized numbers/parameters not allowed in concatenations.

%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:123:5: Unsized numbers/parameters not allowed in concatenations.

%Warning-WIDTH: ../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv:31:17: Operator VAR 'SecLcCtrlVolatileRawUnlockEn' expects 1 bits on the Initial value, but Initial value's VARREF 'SecVolatileRawUnlockEn' generates 32 bits.

%Warning-WIDTH: ../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv:51:17: Operator VAR 'SecPinmuxAonVolatileRawUnlockEn' expects 1 bits on the Initial value, but Initial value's VARREF 'SecVolatileRawUnlockEn' generates 32 bits.

%Warning-WIDTH: ../src/lowrisc_systems_flash_ctrl_pkg_0.1/rtl/autogen/flash_ctrl_pkg.sv:311:18: Operator PATMEMBER expects 10 bits on the Pattern value, but Pattern value's MUL generates 32 bits.

%Warning-WIDTH: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv:87:41: Operator VAR 'RomBaseAddr' expects 12 bits on the Initial value, but Initial value's VARREF 'HaltAddress' generates 64 bits.

%Warning-WIDTH: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv:90:41: Operator VAR 'RomEndAddr' expects 12 bits on the Initial value, but Initial value's ADD generates 64 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv:65:55: Operator LT expects 32 bits on the LHS, but LHS's VARREF 'curr_incr_cnt' generates 2 bits.

%Warning-WIDTH: ../src/lowrisc_ip_aes_1.0/rtl/aes_prng_masking.sv:85:37: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's EXTEND generates 2 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv:153:36: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv:213:26: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv:230:17: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:251:66: Operator LTE expects 32 bits on the LHS, but LHS's VARREF 'host_outstanding' generates 2 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:430:65: Operator EQ expects 2 bits on the RHS, but RHS's CONST '1'h1' generates 1 bits.

%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv:346:41: Operator SUB expects 32 bits on the RHS, but RHS's VARREF 'acq_fifo_depth_i' generates 7 bits.

%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv:346:29: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits.

%Warning-WIDTH: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv:282:47: Operator SUB expects 32 bits on the LHS, but LHS's VARREF 'DataCount' generates 4 bits.

%Warning-WIDTH: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv:277:47: Operator SUB expects 32 bits on the LHS, but LHS's SEL generates 10 bits.

%Warning-WIDTH: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv:277:47: Operator SUB expects 32 bits on the RHS, but RHS's SEL generates 10 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv:737:24: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS's VARREF 'MaxBeatCnt' generates 32 bits.

%Warning-WIDTH: ../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv:77:36: Operator GTE expects 32 bits on the LHS, but LHS's VARREF 'reseed_cnt_q' generates 5 bits.

%Warning-WIDTH: ../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_region_cfg.sv:116:47: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's MUL generates 32 bits.

%Warning-WIDTH: ../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv:131:58: Operator GTE expects 32 bits on the LHS, but LHS's SEL generates 7 bits.

%Warning-WIDTH: ../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv:132:57: Operator SUB expects 32 bits on the LHS, but LHS's SEL generates 7 bits.

%Warning-WIDTH: ../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv:131:70: Operator COND expects 32 bits on the Conditional False, but Conditional False's SEL generates 7 bits.

%Warning-WIDTH: ../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv:131:23: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's COND generates 32 bits.

%Warning-WIDTH: ../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_lpg_ctrl.sv:84:11: Logical operator LOGNOT expects 1 bit on the LHS, but LHS's VARREF 'lpg_used' generates 24 bits.

%Warning-WIDTH: ../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv:158:37: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '2'h0' generates 2 bits.

%Warning-WIDTH: ../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv:393:28: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's CONST '6'h0' generates 6 bits.

%Warning-WIDTH: ../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv:254:22: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits.

%Warning-UNUSED: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:706:23: Bits of signal are not used: 'ast_pwst'[3]

%Warning-UNUSED: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:707:23: Bits of signal are not used: 'ast_pwst_h'[3:0]

%Warning-UNUSED: ../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv:279:16: Bits of signal are not used: 'cio_otp_ctrl_test_d2p'[7:1]

%Warning-UNUSED: ../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv:280:16: Bits of signal are not used: 'cio_otp_ctrl_test_en_d2p'[7:1]

%Warning-UNUSED: ../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv:70:16: Signal is not used: 'csb_i'

%Warning-UNUSED: ../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv:137:27: Parameter is not used: 'TpmRegisterSize'

%Warning-UNUSED: ../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv:307:13: Bits of signal are not used: 'sys_clk_tpm_cfg'[4]

%Warning-UNUSED: ../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv:377:16: Bits of signal are not used: 'addr'[1:0]

%Warning-UNUSED: ../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv:383:15: Bits of signal are not used: 'wrdata_q'[7]

%Warning-UNUSED: ../src/lowrisc_systems_ast_0.1/rtl/aon_osc.sv:75:12: Signal is not used: 'en_osc'

%Warning-UNUSED: ../src/lowrisc_systems_ast_0.1/rtl/io_osc.sv:77:12: Signal is not used: 'en_osc'

%Warning-UNUSED: ../src/lowrisc_systems_ast_0.1/rtl/sys_osc.sv:104:12: Signal is not used: 'en_osc'

%Warning-UNUSED: ../src/lowrisc_systems_ast_0.1/rtl/usb_osc.sv:129:12: Signal is not used: 'en_osc'

%Warning-VARHIDDEN: ../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_pmp.sv:55:68: Declaration of signal hides declaration in upper scope: 'csr_pmp_cfg'

%Warning-VARHIDDEN: ../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_pmp.sv:69:64: Declaration of signal hides declaration in upper scope: 'csr_pmp_cfg'

%Warning-NOLATCH: ../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv:21:3: No latches detected in always_latch block

%Warning-UNOPTFLAT: ../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv:228:12: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_sram_ctrl_main.u_tlul_lc_gate.tl_d2h_error'

%Warning-UNOPTFLAT: ../src/lowrisc_prim_reg_we_check_0/rtl/prim_reg_we_check.sv:20:34: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pwrmgr_aon.u_reg.u_prim_reg_we_check.err_o'

%Warning-UNOPTFLAT: ../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv:56:39: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.gen_normal_case.gnt_tree[0]'

%Warning-UNOPTFLAT: ../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv:66:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_reg_core.reg_we_err'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv:260:26: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_keymgr.err_code'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:406:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.flash_rd_req'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv:61:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_keymgr.u_reg.reg_we_err'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv:318:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_kmac.u_errchk.err'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv:291:38: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_kmac.kmac_cmd'

%Warning-UNOPTFLAT: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv:42:24: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_rv_dm.__Vcellout__dap__td_o'

%Warning-UNOPTFLAT: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv:43:24: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_rv_dm.__Vcellout__dap__tdo_oe_o'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv:105:22: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_spi_device.sram_clk_muxed'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv:50:42: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_otp_ctrl.__Vcellout__u_otp_ctrl_dai__otp_req_o'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv:51:39: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_otp_ctrl.__Vcellout__gen_partitions[0].gen_unbuffered.u_part_unbuf__otp_req_o'

%Warning-UNOPTFLAT: ../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv:26:19: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_sram_ctrl_main.u_tlul_lc_gate.tl_d2h_o'

%Warning-UNOPTFLAT: ../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_id_stage.sv:286:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.id_stage_i.lsu_req'

%Warning-UNOPTFLAT: ../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_core.sv:212:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.lsu_load_resp_intg_err'

%Warning-UNOPTFLAT: ../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_core.sv:213:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.lsu_store_resp_intg_err'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:313:33: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.dio_oe'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:313:24: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.dio_out'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:312:24: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.mio_out'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:107:19: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.reg2hw'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:399:42: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.mio_oe_retreg_q'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:153:51: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.dio_pad_attr_q'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv:101:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_i2c1.i2c_core.u_i2c_fsm.sda_q'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv:51:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_i2c0.reg2hw'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv:100:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_i2c0.i2c_core.u_i2c_fsm.scl_q'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv:42:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_gpio.cio_gpio_en_q'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:154:51: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.mio_pad_attr_q'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_spi_host_1.0/rtl/spi_host_fsm.sv:93:21: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_spi_host1.u_spi_core.u_fsm.csb_q'

%Warning-UNOPTFLAT: ../src/lowrisc_prim_count_0/rtl/prim_count.sv:56:40: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr.cnt_q'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:62:38: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.host_gnt_err_o'

%Warning-UNOPTFLAT: ../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv:135:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_host_arb.err_q'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:194:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.ctrl_fsm_idle'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:111:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.ctrl_rsp_vld'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv:667:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_rd.intg_err_pre'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv:405:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_rd.data_err'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv:124:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.data_invalid_q'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv:282:13: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_rd.rd_attrs'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:54:38: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.ecc_single_err_o'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_spi_host_1.0/rtl/spi_host_core.sv:59:15: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_spi_host1.u_spi_core.speed'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_spi_host_1.0/rtl/spi_host_fsm.sv:65:34: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_spi_host1.u_spi_core.u_fsm.cmd_wr_en_q'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv:46:21: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_spi_host1.reg2hw'

%Warning-UNOPTFLAT: ../src/lowrisc_prim_count_0/rtl/prim_count.sv:103:23: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr.gen_cnts[0].cnt_unforced_q'

%Warning-UNOPTFLAT: ../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv:30:21: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.state_raw'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:138:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.rd_stage_data_valid'

%Warning-UNOPTFLAT: ../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv:38:36: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_otp_ctrl.u_prim_lc_sync_dft_en.lc_en'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv:20:36: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.__Vcellout__u_pinmux_strap_sampling__out_padring_o'

%Warning-UNOPTFLAT: ../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv:300:15: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.flash_phy_rsp'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv:19:36: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.__Vcellout__u_pinmux_strap_sampling__attr_padring_o'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv:21:36: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.__Vcellout__u_pinmux_strap_sampling__oe_padring_o'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv:121:44: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_otp_ctrl.hw2reg'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv:139:17: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_kmac.hw2reg'

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