CHIP_EARLGREY_ASIC Lint Results
Saturday August 17 2024 23:02:17 UTC
Branch: os_regression
Tool: VERILATOR
| Build Mode |
Flow Infos |
Flow Warnings |
Flow Errors |
Lint Infos |
Lint Warnings |
Lint Errors |
| default |
0 |
0 |
2 |
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160 |
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Messages for Build Mode 'default'
Flow Errors
ERROR: %Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:112:5: Unsized numbers/parameters not allowed in concatenations.
ERROR: Failed to build lowrisc:systems:chip_earlgrey_asic:0.1 : '['make', 'Vchip_earlgrey_asic.mk']' exited with an error: 2
Lint Warnings
%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:113:5: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:114:5: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:115:5: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:116:5: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:117:5: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:118:5: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:119:5: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:121:5: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:122:5: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:123:5: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTH: ../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv:36:17: Operator VAR 'SecLcCtrlVolatileRawUnlockEn' expects 1 bits on the Initial value, but Initial value's VARREF 'SecVolatileRawUnlockEn' generates 32 bits.
%Warning-WIDTH: ../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv:56:17: Operator VAR 'SecPinmuxAonVolatileRawUnlockEn' expects 1 bits on the Initial value, but Initial value's VARREF 'SecVolatileRawUnlockEn' generates 32 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_pkg_0.1/rtl/flash_ctrl_pkg.sv:296:18: Operator PATMEMBER expects 10 bits on the Pattern value, but Pattern value's MUL generates 32 bits.
%Warning-WIDTHCONCAT: ../src/lowrisc_prim_count_0/rtl/prim_count.sv:69:85: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv:65:55: Operator LT expects 32 bits on the LHS, but LHS's VARREF 'curr_incr_cnt' generates 2 bits.
%Warning-WIDTH: ../src/lowrisc_ip_aes_1.0/rtl/aes_prng_masking.sv:68:37: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's EXTEND generates 2 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv:153:36: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv:213:26: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv:230:17: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:248:66: Operator LTE expects 32 bits on the LHS, but LHS's VARREF 'host_outstanding' generates 2 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:428:65: Operator EQ expects 2 bits on the RHS, but RHS's CONST '1'h1' generates 1 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:133:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:133:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tsu_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:267:44: Operator SUB expects 32 bits on the RHS, but RHS's VARREF 'acq_fifo_depth_i' generates 9 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:267:29: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:416:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:508:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:718:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:757:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:808:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:856:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:883:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:903:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:946:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:969:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:124:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:124:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tsu_sta_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:125:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_f_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:125:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'thd_sta_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:127:46: Operator SUB expects 16 bits on the LHS, but LHS's VARREF 'tlow_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:127:46: Operator SUB expects 16 bits on the RHS, but RHS's VARREF 'thd_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:128:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:128:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'thigh_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:130:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_f_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:130:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'thd_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:131:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_f_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:131:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tlow_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:131:59: Operator SUB expects 16 bits on the RHS, but RHS's VARREF 'thd_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:132:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:132:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tsu_sto_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:393:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:489:41: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:671:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:679:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:687:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:695:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:715:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:725:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:740:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:756:24: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:765:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:779:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:794:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:803:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:819:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:834:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:842:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:863:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:878:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_region_cfg.sv:110:47: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's MUL generates 32 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv:743:24: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS's VARREF 'MaxBeatCnt' generates 32 bits.
%Warning-WIDTH: ../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv:77:36: Operator GTE expects 32 bits on the LHS, but LHS's VARREF 'reseed_cnt_q' generates 5 bits.
%Warning-WIDTH: ../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv:134:58: Operator GTE expects 32 bits on the LHS, but LHS's SEL generates 7 bits.
%Warning-WIDTH: ../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv:135:57: Operator SUB expects 32 bits on the LHS, but LHS's SEL generates 7 bits.
%Warning-WIDTH: ../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv:134:70: Operator COND expects 32 bits on the Conditional False, but Conditional False's SEL generates 7 bits.
%Warning-WIDTH: ../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv:134:23: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's COND generates 32 bits.
%Warning-WIDTH: ../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv:279:61: Operator SHIFTL expects 4 bits on the LHS, but LHS's EXTEND generates 2 bits.
%Warning-WIDTH: ../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_lpg_ctrl.sv:84:11: Logical operator LOGNOT expects 1 bit on the LHS, but LHS's VARREF 'lpg_used' generates 24 bits.
%Warning-WIDTH: ../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv:78:75: Operator ADD expects 8 bits on the RHS, but RHS's LOGNOT generates 1 bits.
%Warning-WIDTH: ../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv:314:26: Operator GTE expects 32 bits on the LHS, but LHS's VARREF 'uart_fifo_txilvl' generates 3 bits.
%Warning-WIDTH: ../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv:341:35: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'uart_fifo_rxilvl' generates 3 bits.
%Warning-WIDTH: ../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv:337:26: Operator GT expects 32 bits on the LHS, but LHS's VARREF 'uart_fifo_rxilvl' generates 3 bits.
%Warning-WIDTH: ../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv:352:22: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits.
%Warning-WIDTH: ../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv:296:24: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS's CONST '3'h0' generates 3 bits.
%Warning-WIDTH: ../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv:298:24: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS's CONST '3'h0' generates 3 bits.
%Warning-WIDTH: ../src/lowrisc_systems_ast_0.1/rtl/ast_dft.sv:39:20: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS's CONST '10'h0' generates 10 bits.
%Warning-WIDTH: ../src/lowrisc_systems_ast_0.1/rtl/ast_dft.sv:40:20: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS's CONST '10'h0' generates 10 bits.
%Warning-WIDTH: ../src/lowrisc_systems_ast_0.1/rtl/ast_dft.sv:41:20: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's CONST '5'h0' generates 5 bits.
%Warning-WIDTH: ../src/lowrisc_systems_ast_0.1/rtl/ast_dft.sv:42:20: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's CONST '5'h0' generates 5 bits.
%Warning-WIDTH: ../src/lowrisc_systems_ast_0.1/rtl/ast_dft.sv:43:20: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's CONST '5'h0' generates 5 bits.
%Warning-WIDTH: ../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv:553:57: Operator SHIFTR expects 32 or 7 bits on the LHS, but LHS's VARREF 'hmac_fifo_wdata_sel' generates 4 bits.
%Warning-UNUSED: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:767:23: Bits of signal are not used: 'ast_pwst'[3]
%Warning-UNUSED: ../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv:768:23: Bits of signal are not used: 'ast_pwst_h'[3:0]
%Warning-UNUSED: ../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv:287:16: Bits of signal are not used: 'cio_otp_ctrl_test_d2p'[7:1]
%Warning-UNUSED: ../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv:288:16: Bits of signal are not used: 'cio_otp_ctrl_test_en_d2p'[7:1]
%Warning-UNUSED: ../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv:68:16: Signal is not used: 'csb_i'
%Warning-UNUSED: ../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv:142:27: Parameter is not used: 'TpmRegisterSize'
%Warning-UNUSED: ../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv:332:13: Bits of signal are not used: 'sys_clk_tpm_cfg'[4]
%Warning-UNUSED: ../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv:406:16: Bits of signal are not used: 'addr'[1:0]
%Warning-UNUSED: ../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv:412:15: Bits of signal are not used: 'wrdata_q'[7]
%Warning-UNUSED: ../src/lowrisc_systems_ast_0.1/rtl/aon_osc.sv:75:12: Signal is not used: 'en_osc'
%Warning-UNUSED: ../src/lowrisc_systems_ast_0.1/rtl/io_osc.sv:77:12: Signal is not used: 'en_osc'
%Warning-UNUSED: ../src/lowrisc_systems_ast_0.1/rtl/sys_osc.sv:104:12: Signal is not used: 'en_osc'
%Warning-UNUSED: ../src/lowrisc_systems_ast_0.1/rtl/usb_osc.sv:129:12: Signal is not used: 'en_osc'
%Warning-NOLATCH: ../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv:21:3: No latches detected in always_latch block
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv:156:11: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_flash_hw_if.rma_ack_d'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_pwrmgr_reg_0.1/rtl/pwrmgr_reg_top.sv:56:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pwrmgr_aon.u_reg.reg_we_err'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv:234:36: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_i2c0.i2c_core.u_fifos.ram_arb_gnt'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv:98:28: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_i2c0.i2c_core.u_fifos.u_rx_fifo_sram_adapter.oup_buf_wvalid'
%Warning-UNOPTFLAT: ../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv:56:39: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.gen_normal_case.gnt_tree[0]'
%Warning-UNOPTFLAT: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv:43:24: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_rv_dm.__Vcellout__dap__td_o'
%Warning-UNOPTFLAT: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv:44:24: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_rv_dm.__Vcellout__dap__tdo_oe_o'
%Warning-UNOPTFLAT: ../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv:57:39: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_otp_ctrl.u_otp_ctrl_dai.u_part_sel_idx.gen_normal_case.idx_tree[23:20]'
%Warning-UNOPTFLAT: ../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv:58:39: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_otp_ctrl.u_otp_ctrl_dai.u_part_sel_idx.gen_normal_case.data_tree[191:160]'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_reg_0.1/rtl/flash_ctrl_core_reg_top.sv:63:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_reg_core.reg_we_err'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv:263:26: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_keymgr.err_code'
%Warning-UNOPTFLAT: ../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv:101:11: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_sram_ctrl_ret_aon.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.rdback_wait'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv:58:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_keymgr.u_reg.reg_we_err'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv:320:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_kmac.u_errchk.err'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:404:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.flash_rd_req'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv:289:38: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_kmac.kmac_cmd'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv:122:44: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_otp_ctrl.hw2reg'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv:50:42: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_otp_ctrl.__Vcellout__u_otp_ctrl_dai__otp_req_o'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv:51:39: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_otp_ctrl.__Vcellout__gen_partitions[0].gen_unbuffered.u_part_unbuf__otp_req_o'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv:27:36: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.__Vcellout__u_pinmux_strap_sampling__in_core_o'
%Warning-UNOPTFLAT: ../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_id_stage.sv:289:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.id_stage_i.lsu_req'
%Warning-UNOPTFLAT: ../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_core.sv:217:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.lsu_load_resp_intg_err'
%Warning-UNOPTFLAT: ../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_core.sv:218:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.lsu_store_resp_intg_err'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:326:33: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.dio_oe'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:326:24: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.dio_out'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:325:24: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.mio_out'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:113:19: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.reg2hw'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:413:42: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.mio_oe_retreg_q'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:158:51: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.dio_pad_attr_q'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv:80:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_i2c1.i2c_core.sda_out_fsm'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv:53:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_i2c0.reg2hw'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv:79:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_i2c0.i2c_core.scl_out_fsm'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv:42:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_gpio.cio_gpio_en_q'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv:159:51: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.mio_pad_attr_q'
%Warning-UNOPTFLAT: ../src/lowrisc_prim_count_0/rtl/prim_count.sv:145:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr.err_q'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:60:38: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.host_gnt_err_o'
%Warning-UNOPTFLAT: ../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv:135:16: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_host_arb.err_q'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:191:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.ctrl_fsm_idle'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:109:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.ctrl_rsp_vld'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv:766:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_rd.intg_err_pre'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv:417:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_rd.data_err'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv:124:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.data_invalid_q'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv:283:13: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_rd.rd_attrs'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:52:38: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.ecc_single_err_o'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv:92:28: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_spi_host1.sd_en_core'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv:46:21: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_spi_host1.reg2hw'
%Warning-UNOPTFLAT: ../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv:30:21: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.state_raw'
%Warning-UNOPTFLAT: ../src/lowrisc_prim_count_0/rtl/prim_count.sv:72:57: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_host_outstanding_cnt.cnt_q'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:136:9: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.u_eflash.gen_flash_cores[0].u_core.rd_stage_data_valid'
%Warning-UNOPTFLAT: ../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv:38:36: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_otp_ctrl.u_prim_lc_sync_dft_en.lc_en'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv:20:36: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.__Vcellout__u_pinmux_strap_sampling__out_padring_o'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl.sv:290:15: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_flash_ctrl.flash_phy_rsp'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv:19:36: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.__Vcellout__u_pinmux_strap_sampling__attr_padring_o'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv:21:36: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_pinmux_aon.__Vcellout__u_pinmux_strap_sampling__oe_padring_o'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv:139:17: Signal unoptimizable: Feedback to clock or circular logic: 'chip_earlgrey_asic.top_earlgrey.u_kmac.hw2reg'
Past Results