CHIP_EARLGREY_ASIC Synthesis Results

Sunday May 08 2022 23:33:37 UTC

GitHub Revision: 796ea2a54
Foundry Revision: 03361cc

Branch: HEAD

Synthesis Tool: DC

Build Mode Flow Warnings Flow Errors Analyze Warnings Analyze Errors Elab Warnings Elab Errors Compile Warnings Compile Errors
default 108979 0 322 0 706 0 103 0

Circuit Complexity in [kGE]

Instance Comb Buf/Inv Regs Logic Macros Total Logic [%] Macro [%] Total [%]
chip_earlgrey_asic 1083.5 100.7 1076.2 2159.7 5398.5 7558.2 -- -- --
top_earlgrey 1076.0 -- 1066.0 2142.1 4852.1 6994.2 99.2 % 89.9 % 92.5 %
top_earlgrey/u_adc_ctrl_aon 6.7 -- 9.6 16.4 0.00 16.4 0.8 % 0.0 % 0.2 %
top_earlgrey/u_aes 67.5 -- 43.0 110.5 0.00 110.5 5.1 % 0.0 % 1.5 %
top_earlgrey/u_alert_handler 39.7 -- 40.6 80.3 0.00 80.3 3.7 % 0.0 % 1.1 %
top_earlgrey/u_aon_timer_aon 2.9 -- 3.7 6.6 0.00 6.6 0.3 % 0.0 % 0.1 %
top_earlgrey/u_clkmgr_aon 5.5 -- 7.9 13.5 0.00 13.5 0.6 % 0.0 % 0.2 %
top_earlgrey/u_csrng 37.8 -- 92.5 130.3 0.00 130.3 6.0 % 0.0 % 1.7 %
top_earlgrey/u_edn0 8.2 -- 16.9 25.2 0.00 25.2 1.2 % 0.0 % 0.3 %
top_earlgrey/u_edn1 5.7 -- 11.5 17.2 0.00 17.2 0.8 % 0.0 % 0.2 %
top_earlgrey/u_entropy_src 52.2 -- 60.2 112.4 0.00 112.4 5.2 % 0.0 % 1.5 %
top_earlgrey/u_flash_ctrl 78.0 -- 72.9 150.9 3495.4 3646.3 7.0 % 64.7 % 48.2 %
top_earlgrey/u_gpio 3.4 -- 4.8 8.2 0.00 8.2 0.4 % 0.0 % 0.1 %
top_earlgrey/u_hmac 16.4 -- 16.2 32.6 0.00 32.6 1.5 % 0.0 % 0.4 %
top_earlgrey/u_i2c0 8.8 -- 21.9 30.7 0.00 30.7 1.4 % 0.0 % 0.4 %
top_earlgrey/u_i2c1 8.8 -- 21.9 30.7 0.00 30.7 1.4 % 0.0 % 0.4 %
top_earlgrey/u_i2c2 8.8 -- 21.9 30.7 0.00 30.7 1.4 % 0.0 % 0.4 %
top_earlgrey/u_keymgr 51.7 -- 34.6 86.3 0.00 86.3 4.0 % 0.0 % 1.1 %
top_earlgrey/u_kmac 116.8 -- 72.1 188.9 0.00 188.9 8.7 % 0.0 % 2.5 %
top_earlgrey/u_lc_ctrl 14.1 -- 15.6 29.7 0.00 29.7 1.4 % 0.0 % 0.4 %
top_earlgrey/u_otbn 162.6 -- 107.7 270.3 91.6 361.9 12.5 % 1.7 % 4.8 %
top_earlgrey/u_otp_ctrl 63.8 -- 47.2 111.1 284.7 395.7 5.1 % 5.3 % 5.2 %
top_earlgrey/u_pattgen 2.6 -- 4.3 6.9 0.00 6.9 0.3 % 0.0 % 0.1 %
top_earlgrey/u_pinmux_aon 29.7 -- 18.4 48.2 0.00 48.2 2.2 % 0.0 % 0.6 %
top_earlgrey/u_pwm_aon 12.1 -- 12.1 24.2 0.00 24.2 1.1 % 0.0 % 0.3 %
top_earlgrey/u_pwrmgr_aon 2.4 -- 2.6 5.0 0.00 5.0 0.2 % 0.0 % 0.1 %
top_earlgrey/u_rom_ctrl 9.0 -- 6.6 15.7 48.1 63.8 0.7 % 0.9 % 0.8 %
top_earlgrey/u_rstmgr_aon 6.7 -- 10.0 16.7 0.00 16.7 0.8 % 0.0 % 0.2 %
top_earlgrey/u_rv_core_ibex 111.8 -- 71.0 182.8 69.8 252.6 8.5 % 1.3 % 3.3 %
top_earlgrey/u_rv_dm 7.9 -- 8.9 16.8 0.00 16.8 0.8 % 0.0 % 0.2 %
top_earlgrey/u_rv_plic 12.7 -- 10.8 23.5 0.00 23.5 1.1 % 0.0 % 0.3 %
top_earlgrey/u_rv_timer 2.0 -- 1.6 3.6 0.00 3.6 0.2 % 0.0 % 0.0 %
top_earlgrey/u_sensor_ctrl 1.6 -- 1.4 3.0 0.00 3.0 0.1 % 0.0 % 0.0 %
top_earlgrey/u_spi_device 21.2 -- 24.1 45.3 69.9 115.3 2.1 % 1.3 % 1.5 %
top_earlgrey/u_spi_host0 9.8 -- 35.7 45.5 0.00 45.5 2.1 % 0.0 % 0.6 %
top_earlgrey/u_spi_host1 9.8 -- 35.7 45.5 0.00 45.5 2.1 % 0.0 % 0.6 %
top_earlgrey/u_sram_ctrl_main 9.0 -- 5.5 14.6 724.3 738.9 0.7 % 13.4 % 9.8 %
top_earlgrey/u_sram_ctrl_ret_aon 8.5 -- 5.0 13.5 28.4 41.9 0.6 % 0.5 % 0.6 %
top_earlgrey/u_sysrst_ctrl_aon 8.8 -- 11.5 20.3 0.00 20.3 0.9 % 0.0 % 0.3 %
top_earlgrey/u_uart0 2.9 -- 5.8 8.6 0.00 8.6 0.4 % 0.0 % 0.1 %
top_earlgrey/u_uart1 2.9 -- 5.8 8.6 0.00 8.6 0.4 % 0.0 % 0.1 %
top_earlgrey/u_uart2 2.9 -- 5.8 8.6 0.00 8.6 0.4 % 0.0 % 0.1 %
top_earlgrey/u_uart3 2.9 -- 5.8 8.6 0.00 8.6 0.4 % 0.0 % 0.1 %
top_earlgrey/u_usbdev 7.6 -- 9.8 17.4 39.9 57.3 0.8 % 0.7 % 0.8 %
top_earlgrey/u_xbar_main 26.7 -- 44.8 71.5 0.00 71.5 3.3 % 0.0 % 0.9 %
top_earlgrey/u_xbar_peri 5.2 -- 0.15 5.3 0.00 5.3 0.2 % 0.0 % 0.1 %
u_ast 6.5 -- 10.2 16.6 0.00 16.6 0.8 % 0.0 % 0.2 %
u_padring 0.96 -- 0.00 0.96 546.4 547.3 0.0 % 10.1 % 7.2 %
u_prim_usb_diff_rx 0.01 -- 0.00 0.01 0.00 0.01 0.0 % 0.0 % 0.0 %

Timing in [ns]

Path Group Period WNS TNS
AON_CLK 4750.0 0.00 0.00
IO_CLK 9.9 0.00 0.00
JTAG_TCK 47.5 0.00 0.00
MAIN_CLK 8.5 0.00 0.00
SPI_CSB_CLK 16.0 0.00 0.00
SPI_DEV_CLK 16.0 0.00 0.00
SPI_DEV_IN_CLK 16.0 0.00 0.00
SPI_DEV_OUT_CLK 16.0 0.00 0.00
SPI_DEV_PASSTHRU_CLK 25.0 0.00 0.00
SPI_DEV_PASSTHRU_CSB_CLK 25.0 0.00 0.00
SPI_DEV_PASSTHRU_IN_CLK 25.0 0.00 0.00
SPI_DEV_PASSTHRU_OUT_CLK 25.0 0.00 0.00
SPI_HOST_CLK 19.8 0.00 0.00
SPI_HOST_INT_CLK 19.8 0.00 0.00
SPI_HOST_PASSTHRU_CLK 25.0 0.00 0.00
USB_CLK 19.8 0.00 0.00
default -- -0.37 -0.37

Power Estimates in [mW]

Network Internal Leakage Total
2.8 / 56.1 % 1.8 / 36.9 % 0.35 / 7.0 % 5

Past Results