CHIP_EARLGREY_ASIC Synthesis Results

Thursday January 25 2024 08:06:34 UTC

GitHub Revision: eba675279e
Foundry Revision: 5fc983b

Branch: cs_regression

Synthesis Tool: DC

Build Mode Flow Warnings Flow Errors Analyze Warnings Analyze Errors Elab Warnings Elab Errors Compile Warnings Compile Errors
default 141560 6 327 0 635 1 6087 5

Circuit Complexity in [kGE]

Instance Comb Buf/Inv Regs Logic Macros Total Logic [%] Macro [%] Total [%]
chip_earlgrey_asic 1101.7 79.6 1088.6 2190.3 1863.2 4053.5 -- -- --
top_earlgrey 1094.9 -- 1076.7 2171.7 1316.8 3488.5 99.1 % 70.7 % 86.1 %
top_earlgrey/u_adc_ctrl_aon 6.5 -- 10.1 16.6 0.00 16.6 0.8 % 0.0 % 0.4 %
top_earlgrey/u_aes 67.6 -- 43.0 110.6 0.00 110.6 5.0 % 0.0 % 2.7 %
top_earlgrey/u_alert_handler 36.1 -- 42.1 78.2 0.00 78.2 3.6 % 0.0 % 1.9 %
top_earlgrey/u_aon_timer_aon 3.4 -- 4.3 7.6 0.00 7.6 0.3 % 0.0 % 0.2 %
top_earlgrey/u_clkmgr_aon 5.6 -- 9.5 15.2 0.00 15.2 0.7 % 0.0 % 0.4 %
top_earlgrey/u_csrng 37.6 -- 91.8 129.4 0.00 129.4 5.9 % 0.0 % 3.2 %
top_earlgrey/u_edn0 8.8 -- 19.8 28.6 0.00 28.6 1.3 % 0.0 % 0.7 %
top_earlgrey/u_edn1 6.3 -- 14.4 20.7 0.00 20.7 0.9 % 0.0 % 0.5 %
top_earlgrey/u_entropy_src 50.0 -- 60.3 110.3 0.00 110.3 5.0 % 0.0 % 2.7 %
top_earlgrey/u_flash_ctrl 63.7 -- 44.8 108.5 0.00 108.5 5.0 % 0.0 % 2.7 %
top_earlgrey/u_gpio 3.1 -- 4.8 7.9 0.00 7.9 0.4 % 0.0 % 0.2 %
top_earlgrey/u_hmac 16.5 -- 16.2 32.7 0.00 32.7 1.5 % 0.0 % 0.8 %
top_earlgrey/u_i2c0 8.3 -- 21.8 30.1 0.00 30.1 1.4 % 0.0 % 0.7 %
top_earlgrey/u_i2c1 8.3 -- 21.8 30.1 0.00 30.1 1.4 % 0.0 % 0.7 %
top_earlgrey/u_i2c2 8.3 -- 21.8 30.1 0.00 30.1 1.4 % 0.0 % 0.7 %
top_earlgrey/u_keymgr 52.7 -- 34.5 87.2 0.00 87.2 4.0 % 0.0 % 2.2 %
top_earlgrey/u_kmac 116.6 -- 72.4 189.0 0.00 189.0 8.6 % 0.0 % 4.7 %
top_earlgrey/u_lc_ctrl 14.0 -- 14.0 28.0 0.00 28.0 1.3 % 0.0 % 0.7 %
top_earlgrey/u_otbn 192.1 -- 108.7 300.8 91.6 392.5 13.7 % 4.9 % 9.7 %
top_earlgrey/u_otp_ctrl 63.9 -- 48.0 111.9 284.7 396.5 5.1 % 15.3 % 9.8 %
top_earlgrey/u_pattgen 2.3 -- 4.3 6.6 0.00 6.6 0.3 % 0.0 % 0.2 %
top_earlgrey/u_pinmux_aon 28.8 -- 18.6 47.4 0.00 47.4 2.2 % 0.0 % 1.2 %
top_earlgrey/u_pwm_aon 11.4 -- 12.2 23.6 0.00 23.6 1.1 % 0.0 % 0.6 %
top_earlgrey/u_pwrmgr_aon 2.2 -- 2.7 4.9 0.00 4.9 0.2 % 0.0 % 0.1 %
top_earlgrey/u_rom_ctrl 8.3 -- 6.7 15.0 48.1 63.1 0.7 % 2.6 % 1.6 %
top_earlgrey/u_rstmgr_aon 6.8 -- 10.3 17.1 0.00 17.1 0.8 % 0.0 % 0.4 %
top_earlgrey/u_rv_core_ibex 121.2 -- 73.0 194.2 69.8 264.1 8.9 % 3.7 % 6.5 %
top_earlgrey/u_rv_dm 7.6 -- 7.4 15.0 0.00 15.0 0.7 % 0.0 % 0.4 %
top_earlgrey/u_rv_plic 10.2 -- 10.5 20.6 0.00 20.6 0.9 % 0.0 % 0.5 %
top_earlgrey/u_rv_timer 1.8 -- 1.6 3.4 0.00 3.4 0.2 % 0.0 % 0.1 %
top_earlgrey/u_sensor_ctrl_aon 1.4 -- 1.3 2.7 0.00 2.7 0.1 % 0.0 % 0.1 %
top_earlgrey/u_spi_device 18.5 -- 28.5 47.1 69.9 117.0 2.1 % 3.8 % 2.9 %
top_earlgrey/u_spi_host0 9.7 -- 35.6 45.3 0.00 45.3 2.1 % 0.0 % 1.1 %
top_earlgrey/u_spi_host1 9.7 -- 35.6 45.3 0.00 45.3 2.1 % 0.0 % 1.1 %
top_earlgrey/u_sram_ctrl_main 9.8 -- 5.9 15.8 724.3 740.1 0.7 % 38.9 % 18.3 %
top_earlgrey/u_sram_ctrl_ret_aon 8.2 -- 5.2 13.4 28.4 41.8 0.6 % 1.5 % 1.0 %
top_earlgrey/u_sysrst_ctrl_aon 10.6 -- 15.5 26.2 0.00 26.2 1.2 % 0.0 % 0.6 %
top_earlgrey/u_uart0 5.0 -- 16.8 21.8 0.00 21.8 1.0 % 0.0 % 0.5 %
top_earlgrey/u_uart1 5.0 -- 16.8 21.8 0.00 21.8 1.0 % 0.0 % 0.5 %
top_earlgrey/u_uart2 5.0 -- 16.8 21.8 0.00 21.8 1.0 % 0.0 % 0.5 %
top_earlgrey/u_uart3 5.0 -- 16.8 21.8 0.00 21.8 1.0 % 0.0 % 0.5 %
top_earlgrey/u_usbdev 6.2 -- 7.4 13.6 0.00 13.6 0.6 % 0.0 % 0.3 %
top_earlgrey/u_xbar_main 25.8 -- 23.0 48.7 0.00 48.7 2.2 % 0.0 % 1.2 %
top_earlgrey/u_xbar_peri 5.1 -- 0.15 5.2 0.00 5.2 0.2 % 0.0 % 0.1 %
u_ast 5.8 -- 11.9 17.7 0.00 17.7 0.8 % 0.0 % 0.4 %
u_padring 0.93 -- 0.00 0.93 546.4 547.3 0.0 % 29.3 % 13.5 %
u_prim_usb_diff_rx 0.01 -- 0.00 0.01 0.00 0.01 0.0 % 0.0 % 0.0 %

Timing in [ns]

Path Group Period WNS TNS
AON_CLK 4750.0 0.00 0.00
AST_EXT_CLK 19.8 0.00 0.00
IO_CLK 9.9 0.00 0.00
IO_DIV2_CLK 19.8 0.00 0.00
IO_DIV4_CLK 39.6 0.00 0.00
JTAG_TCK 31.6 0.00 0.00
LC_JTAG_TCK 31.6 0.00 0.00
MAIN_CLK 8.5 0.00 0.00
RV_JTAG_TCK 31.6 0.00 0.00
SPI_DEV_CLK 20.0 0.00 0.00
SPI_DEV_CSB_CLK 40.0 0.00 0.00
SPI_DEV_IN_CLK 20.0 0.00 0.00
SPI_DEV_OUT_CLK 20.0 0.00 0.00
SPI_DEV_PASS_CLK 30.0 0.00 0.00
SPI_DEV_PASS_CSB_CLK 60.0 0.00 0.00
SPI_DEV_PASS_IN_CLK 30.0 0.00 0.00
SPI_DEV_PASS_OUT_CLK 30.0 0.00 0.00
SPI_HOST_CLK 19.8 0.00 0.00
SPI_HOST_PASS_CLK 30.0 0.00 0.00
SPI_TPM_CLK 40.0 0.00 0.00
SPI_TPM_IN_CLK 40.0 0.00 0.00
SPI_TPM_OUT_CLK 40.0 0.00 0.00
USB_CLK 19.8 0.00 0.00
default -- -0.43 -0.43

Power Estimates in [mW]

Network Internal Leakage Total
28.2 / 89.3 % 3.4 / 10.7 % 0.03 / 0.1 % 31.6

Past Results