CHIP_EARLGREY_ASIC Synthesis Results

Wednesday March 06 2024 08:02:41 UTC

GitHub Revision: 051b3a54d5
Foundry Revision: 5fc983b

Branch: cs_regression

Synthesis Tool: DC

Build Mode Flow Warnings Flow Errors Analyze Warnings Analyze Errors Elab Warnings Elab Errors Compile Warnings Compile Errors
default 143587 14 311 0 586 1 6168 5

Circuit Complexity in [kGE]

Instance Comb Buf/Inv Regs Logic Macros Total Logic [%] Macro [%] Total [%]
chip_earlgrey_asic 1409.6 89.9 1128.0 2537.5 1866.7 4404.3 -- -- --
top_earlgrey 1402.8 -- 1116.1 2518.9 1316.8 3835.7 99.3 % 70.5 % 87.1 %
top_earlgrey/u_adc_ctrl_aon 6.5 -- 10.1 16.6 0.00 16.6 0.7 % 0.0 % 0.4 %
top_earlgrey/u_aes 70.5 -- 43.1 113.5 0.00 113.5 4.5 % 0.0 % 2.6 %
top_earlgrey/u_alert_handler 36.2 -- 42.1 78.2 0.00 78.2 3.1 % 0.0 % 1.8 %
top_earlgrey/u_aon_timer_aon 4.4 -- 5.5 9.9 0.00 9.9 0.4 % 0.0 % 0.2 %
top_earlgrey/u_clkmgr_aon 5.7 -- 9.5 15.2 0.00 15.2 0.6 % 0.0 % 0.3 %
top_earlgrey/u_csrng 37.5 -- 91.8 129.3 0.00 129.3 5.1 % 0.0 % 2.9 %
top_earlgrey/u_edn0 8.1 -- 17.0 25.1 0.00 25.1 1.0 % 0.0 % 0.6 %
top_earlgrey/u_edn1 5.7 -- 11.6 17.3 0.00 17.3 0.7 % 0.0 % 0.4 %
top_earlgrey/u_entropy_src 50.3 -- 60.4 110.8 0.00 110.8 4.4 % 0.0 % 2.5 %
top_earlgrey/u_flash_ctrl 64.9 -- 44.8 109.7 0.00 109.7 4.3 % 0.0 % 2.5 %
top_earlgrey/u_gpio 3.1 -- 4.8 7.9 0.00 7.9 0.3 % 0.0 % 0.2 %
top_earlgrey/u_hmac 16.5 -- 16.2 32.8 0.00 32.8 1.3 % 0.0 % 0.7 %
top_earlgrey/u_i2c0 11.3 -- 36.5 47.8 0.00 47.8 1.9 % 0.0 % 1.1 %
top_earlgrey/u_i2c1 11.3 -- 36.5 47.8 0.00 47.8 1.9 % 0.0 % 1.1 %
top_earlgrey/u_i2c2 11.3 -- 36.5 47.8 0.00 47.8 1.9 % 0.0 % 1.1 %
top_earlgrey/u_keymgr 52.9 -- 34.5 87.4 0.00 87.4 3.4 % 0.0 % 2.0 %
top_earlgrey/u_kmac 404.4 -- 74.5 478.8 0.00 478.8 18.9 % 0.0 % 10.9 %
top_earlgrey/u_lc_ctrl 13.4 -- 14.0 27.4 0.00 27.4 1.1 % 0.0 % 0.6 %
top_earlgrey/u_otbn 192.8 -- 109.6 302.4 91.6 394.0 11.9 % 4.9 % 8.9 %
top_earlgrey/u_otp_ctrl 68.0 -- 50.1 118.1 284.7 402.8 4.7 % 15.2 % 9.1 %
top_earlgrey/u_pattgen 2.3 -- 4.3 6.6 0.00 6.6 0.3 % 0.0 % 0.2 %
top_earlgrey/u_pinmux_aon 28.8 -- 18.6 47.4 0.00 47.4 1.9 % 0.0 % 1.1 %
top_earlgrey/u_pwm_aon 11.4 -- 12.2 23.6 0.00 23.6 0.9 % 0.0 % 0.5 %
top_earlgrey/u_pwrmgr_aon 2.2 -- 2.7 4.9 0.00 4.9 0.2 % 0.0 % 0.1 %
top_earlgrey/u_rom_ctrl 8.2 -- 6.7 14.9 48.1 63.1 0.6 % 2.6 % 1.4 %
top_earlgrey/u_rstmgr_aon 6.8 -- 10.3 17.1 0.00 17.1 0.7 % 0.0 % 0.4 %
top_earlgrey/u_rv_core_ibex 121.2 -- 73.1 194.2 69.8 264.0 7.7 % 3.7 % 6.0 %
top_earlgrey/u_rv_dm 7.6 -- 7.4 15.0 0.00 15.0 0.6 % 0.0 % 0.3 %
top_earlgrey/u_rv_plic 10.1 -- 10.6 20.7 0.00 20.7 0.8 % 0.0 % 0.5 %
top_earlgrey/u_rv_timer 1.8 -- 1.6 3.4 0.00 3.4 0.1 % 0.0 % 0.1 %
top_earlgrey/u_sensor_ctrl_aon 1.4 -- 1.3 2.7 0.00 2.7 0.1 % 0.0 % 0.1 %
top_earlgrey/u_spi_device 19.3 -- 22.3 41.6 69.9 111.5 1.6 % 3.7 % 2.5 %
top_earlgrey/u_spi_host0 9.7 -- 35.6 45.3 0.00 45.3 1.8 % 0.0 % 1.0 %
top_earlgrey/u_spi_host1 9.7 -- 35.6 45.3 0.00 45.3 1.8 % 0.0 % 1.0 %
top_earlgrey/u_sram_ctrl_main 10.6 -- 5.9 16.6 724.3 740.9 0.7 % 38.8 % 16.8 %
top_earlgrey/u_sram_ctrl_ret_aon 8.2 -- 5.2 13.4 28.4 41.8 0.5 % 1.5 % 0.9 %
top_earlgrey/u_sysrst_ctrl_aon 10.6 -- 15.5 26.2 0.00 26.2 1.0 % 0.0 % 0.6 %
top_earlgrey/u_uart0 5.0 -- 16.8 21.8 0.00 21.8 0.9 % 0.0 % 0.5 %
top_earlgrey/u_uart1 5.0 -- 16.8 21.8 0.00 21.8 0.9 % 0.0 % 0.5 %
top_earlgrey/u_uart2 5.0 -- 16.8 21.8 0.00 21.8 0.9 % 0.0 % 0.5 %
top_earlgrey/u_uart3 5.0 -- 16.8 21.8 0.00 21.8 0.9 % 0.0 % 0.5 %
top_earlgrey/u_usbdev 6.4 -- 7.6 14.1 0.00 14.1 0.6 % 0.0 % 0.3 %
top_earlgrey/u_xbar_main 26.6 -- 23.0 49.6 0.00 49.6 2.0 % 0.0 % 1.1 %
top_earlgrey/u_xbar_peri 5.1 -- 0.15 5.2 0.00 5.2 0.2 % 0.0 % 0.1 %
u_ast 5.8 -- 11.9 17.7 0.00 17.7 0.7 % 0.0 % 0.4 %
u_padring 0.95 -- 0.00 0.95 549.9 550.8 0.0 % 29.5 % 12.5 %
u_prim_usb_diff_rx 0.01 -- 0.00 0.01 0.00 0.01 0.0 % 0.0 % 0.0 %

Timing in [ns]

Path Group Period WNS TNS
AON_CLK 4750.0 0.00 0.00
AST_EXT_CLK 19.8 0.00 0.00
IO_CLK 9.9 0.00 0.00
IO_DIV2_CLK 19.8 0.00 0.00
IO_DIV4_CLK 39.6 0.00 0.00
JTAG_TCK 31.6 0.00 0.00
LC_JTAG_TCK 31.6 0.00 0.00
MAIN_CLK 8.5 -321.91 -321.91
RV_JTAG_TCK 31.6 0.00 0.00
SPI_DEV_FAST_PASS_CLK 25.0 0.00 0.00
SPI_DEV_FAST_PASS_CSB_CLK 50.0 0.00 0.00
SPI_DEV_FAST_PASS_IN_CLK 25.0 0.00 0.00
SPI_DEV_FAST_PASS_OUT_CLK 25.0 0.00 0.00
SPI_DEV_HC_CLK 40.0 0.00 0.00
SPI_DEV_HC_CSB_CLK 80.0 0.00 0.00
SPI_DEV_HC_IN_CLK 40.0 0.00 0.00
SPI_DEV_HC_OUT_CLK 40.0 0.00 0.00
SPI_DEV_SLOW_PASS_CLK 40.0 0.00 0.00
SPI_DEV_SLOW_PASS_CSB_CLK 80.0 0.00 0.00
SPI_DEV_SLOW_PASS_IN_CLK 40.0 0.00 0.00
SPI_DEV_SLOW_PASS_OUT_CLK 40.0 0.00 0.00
SPI_HOST_CLK 19.8 0.00 0.00
SPI_HOST_FAST_PASS_CLK 25.0 0.00 0.00
SPI_HOST_SLOW_PASS_CLK 40.0 0.00 0.00
SPI_TPM_CLK 40.0 0.00 0.00
SPI_TPM_IN_CLK 40.0 0.00 0.00
SPI_TPM_OUT_CLK 40.0 0.00 0.00
USB_CLK 19.8 0.00 0.00
default -- -0.43 -0.43

Power Estimates in [mW]

Network Internal Leakage Total
79.8 / 96.0 % 3.3 / 4.0 % 0.03 / 0.0 % 83.1

Past Results