CHIP_EARLGREY_ASIC Synthesis Results

Thursday October 14 2021 10:31:07 UTC

GitHub Revision: 1982463c9
Foundry Revision: e95c38d

Branch: master

Synthesis Tool: DC

Build Mode Flow Warnings Flow Errors Analyze Warnings Analyze Errors Elab Warnings Elab Errors Compile Warnings Compile Errors
default 99703 0 326 0 636 0 80 0

Circuit Complexity in [kGE]

Instance Comb Buf/Inv Regs Logic Macros Total Logic [%] Macro [%] Total [%]
chip_earlgrey_asic 929.6 83.3 1025 1954.7 5346.5 7301.1 -- -- --
top_earlgrey 922.9 -- 1015.3 1938.1 4830.7 6768.8 99.2 % 90.4 % 92.7 %
top_earlgrey/u_adc_ctrl_aon 6.3 -- 9.6 15.9 0 15.9 0.8 % 0.0 % 0.2 %
top_earlgrey/u_aes 66.2 -- 47.4 113.5 0 113.5 5.8 % 0.0 % 1.6 %
top_earlgrey/u_alert_handler 36.5 -- 39.9 76.4 0 76.4 3.9 % 0.0 % 1.0 %
top_earlgrey/u_aon_timer_aon 2.7 -- 3.7 6.4 0 6.4 0.3 % 0.0 % 0.1 %
top_earlgrey/u_clkmgr_aon 3.2 -- 4.6 7.8 0 7.8 0.4 % 0.0 % 0.1 %
top_earlgrey/u_csrng 35.4 -- 90.6 126.1 0 126.1 6.4 % 0.0 % 1.7 %
top_earlgrey/u_edn0 6.5 -- 15 21.4 0 21.4 1.1 % 0.0 % 0.3 %
top_earlgrey/u_edn1 4.4 -- 10.4 14.8 0 14.8 0.8 % 0.0 % 0.2 %
top_earlgrey/u_entropy_src 38.5 -- 52.6 91.1 0 91.1 4.7 % 0.0 % 1.2 %
top_earlgrey/u_flash_ctrl 90.3 -- 81.8 172.1 3495.4 3667.5 8.8 % 65.4 % 50.2 %
top_earlgrey/u_gpio 3.2 -- 4.4 7.6 0 7.6 0.4 % 0.0 % 0.1 %
top_earlgrey/u_hmac 17.2 -- 16.2 33.4 0 33.4 1.7 % 0.0 % 0.5 %
top_earlgrey/u_i2c0 8.7 -- 22 30.7 0 30.7 1.6 % 0.0 % 0.4 %
top_earlgrey/u_i2c1 8.7 -- 22 30.7 0 30.7 1.6 % 0.0 % 0.4 %
top_earlgrey/u_i2c2 8.7 -- 22 30.7 0 30.7 1.6 % 0.0 % 0.4 %
top_earlgrey/u_keymgr 28.6 -- 28.1 56.8 0 56.8 2.9 % 0.0 % 0.8 %
top_earlgrey/u_kmac 102.9 -- 66.5 169.4 0 169.4 8.7 % 0.0 % 2.3 %
top_earlgrey/u_lc_ctrl 12.8 -- 15.5 28.3 0 28.3 1.4 % 0.0 % 0.4 %
top_earlgrey/u_otbn 127.2 -- 102.4 229.6 91.6 321.2 11.7 % 1.7 % 4.4 %
top_earlgrey/u_otp_ctrl 52.7 -- 45.3 98 284.7 382.6 5.0 % 5.3 % 5.2 %
top_earlgrey/u_pattgen 2.5 -- 4.3 6.8 0 6.8 0.3 % 0.0 % 0.1 %
top_earlgrey/u_pinmux_aon 28.1 -- 19.1 47.2 0 47.2 2.4 % 0.0 % 0.6 %
top_earlgrey/u_pwm_aon 13.2 -- 12.3 25.5 0 25.5 1.3 % 0.0 % 0.3 %
top_earlgrey/u_pwrmgr_aon 2 -- 2.3 4.3 0 4.3 0.2 % 0.0 % 0.1 %
top_earlgrey/u_rom_ctrl 6.6 -- 5.7 12.3 26.7 39 0.6 % 0.5 % 0.5 %
top_earlgrey/u_rstmgr_aon 5.2 -- 8.8 14 0 14 0.7 % 0.0 % 0.2 %
top_earlgrey/u_rv_core_ibex 79.5 -- 60.6 140.1 69.8 209.9 7.2 % 1.3 % 2.9 %
top_earlgrey/u_rv_dm 6.5 -- 8.9 15.4 0 15.4 0.8 % 0.0 % 0.2 %
top_earlgrey/u_rv_plic 11.6 -- 10.5 22.1 0 22.1 1.1 % 0.0 % 0.3 %
top_earlgrey/u_rv_timer 2 -- 1.6 3.6 0 3.6 0.2 % 0.0 % 0.0 %
top_earlgrey/u_sensor_ctrl 1.5 -- 1.3 2.8 0 2.8 0.1 % 0.0 % 0.0 %
top_earlgrey/u_spi_device 18.2 -- 21.2 39.4 69.9 109.3 2.0 % 1.3 % 1.5 %
top_earlgrey/u_spi_host0 9.4 -- 35.4 44.8 0 44.8 2.3 % 0.0 % 0.6 %
top_earlgrey/u_spi_host1 9.4 -- 35.4 44.8 0 44.8 2.3 % 0.0 % 0.6 %
top_earlgrey/u_sram_ctrl_main 9 -- 5.5 14.5 724.3 738.8 0.7 % 13.5 % 10.1 %
top_earlgrey/u_sram_ctrl_ret_aon 8.1 -- 5 13.1 28.4 41.5 0.7 % 0.5 % 0.6 %
top_earlgrey/u_sysrst_ctrl_aon 7.9 -- 11.1 19 0 19 1.0 % 0.0 % 0.3 %
top_earlgrey/u_uart0 2.8 -- 5.8 8.6 0 8.6 0.4 % 0.0 % 0.1 %
top_earlgrey/u_uart1 2.8 -- 5.8 8.6 0 8.6 0.4 % 0.0 % 0.1 %
top_earlgrey/u_uart2 2.8 -- 5.8 8.6 0 8.6 0.4 % 0.0 % 0.1 %
top_earlgrey/u_uart3 2.8 -- 5.8 8.6 0 8.6 0.4 % 0.0 % 0.1 %
top_earlgrey/u_usbdev 6.2 -- 8.5 14.7 39.9 54.6 0.8 % 0.7 % 0.7 %
top_earlgrey/u_xbar_main 20.3 -- 34.6 54.9 0 54.9 2.8 % 0.0 % 0.8 %
top_earlgrey/u_xbar_peri 3.8 -- 0.15 4 0 4 0.2 % 0.0 % 0.1 %
u_ast 5.8 -- 9.8 15.6 0 15.6 0.8 % 0.0 % 0.2 %
u_padring 0.96 -- 0 0.96 515.8 516.8 0.0 % 9.6 % 7.1 %
u_prim_usb_diff_rx 0 -- 0 0 0 0 0.0 % 0.0 % 0.0 %

Timing in [ns]

Path Group Period WNS TNS
AON_CLK 4750.0 0.00 0.00
IO_CLK 9.9 0.00 0.00
IO_DIV2_CLK 19.8 0.00 0.00
IO_DIV4_CLK 39.6 0.00 0.00
JTAG_TCK 47.5 0.00 0.00
MAIN_CLK 8.5 0.00 0.00
SPI_DEV_CLK 16.0 0.00 0.00
SPI_DEV_IN_CLK 16.0 0.00 0.00
SPI_DEV_OUT_CLK 16.0 0.00 0.00
SPI_DEV_PASSTHRU_CLK 25.0 0.00 0.00
SPI_DEV_PASSTHRU_IN_CLK 25.0 0.00 0.00
SPI_DEV_PASSTHRU_OUT_CLK 25.0 0.00 0.00
SPI_HOST_CLK 19.8 0.00 0.00
SPI_HOST_INT_CLK 19.8 0.00 0.00
SPI_HOST_PASSTHRU_CLK 25.0 0.00 0.00
USB_CLK 19.8 0.00 0.00
default -- -0.52 -0.52

Power Estimates in [mW]

Network Internal Leakage Total
27.5 / 2.4 % 2.7 / 0.2 % 1140.0 / 97.4 % 1170.2

Past Results