Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.98 99.03 92.19 96.84 94.74 98.62 99.77 97.68


Total test records in report: 724
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html
T545 /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2094708604 May 11 03:24:44 PM PDT 24 May 11 03:44:40 PM PDT 24 150494733435 ps
T546 /workspace/coverage/default/12.edn_disable_auto_req_mode.392178427 May 11 03:24:40 PM PDT 24 May 11 03:24:42 PM PDT 24 89947038 ps
T547 /workspace/coverage/default/0.edn_intr.1245618009 May 11 03:24:13 PM PDT 24 May 11 03:24:15 PM PDT 24 18918219 ps
T548 /workspace/coverage/default/31.edn_stress_all.3091809399 May 11 03:25:25 PM PDT 24 May 11 03:25:29 PM PDT 24 618030262 ps
T549 /workspace/coverage/default/6.edn_genbits.1788361921 May 11 03:24:32 PM PDT 24 May 11 03:24:33 PM PDT 24 16951118 ps
T135 /workspace/coverage/default/1.edn_intr.1834856141 May 11 03:24:18 PM PDT 24 May 11 03:24:19 PM PDT 24 25847498 ps
T550 /workspace/coverage/default/23.edn_err.3438185057 May 11 03:25:11 PM PDT 24 May 11 03:25:13 PM PDT 24 56227303 ps
T551 /workspace/coverage/default/1.edn_disable_auto_req_mode.2483066385 May 11 03:24:17 PM PDT 24 May 11 03:24:19 PM PDT 24 20658938 ps
T207 /workspace/coverage/default/95.edn_err.804265981 May 11 03:26:32 PM PDT 24 May 11 03:26:34 PM PDT 24 20049740 ps
T552 /workspace/coverage/default/9.edn_disable_auto_req_mode.195329299 May 11 03:24:42 PM PDT 24 May 11 03:24:44 PM PDT 24 27088328 ps
T553 /workspace/coverage/default/49.edn_genbits.2613705348 May 11 03:26:04 PM PDT 24 May 11 03:26:05 PM PDT 24 92651542 ps
T554 /workspace/coverage/default/33.edn_disable_auto_req_mode.1725172320 May 11 03:25:29 PM PDT 24 May 11 03:25:30 PM PDT 24 24353979 ps
T555 /workspace/coverage/default/14.edn_smoke.802620180 May 11 03:24:44 PM PDT 24 May 11 03:24:46 PM PDT 24 37581246 ps
T556 /workspace/coverage/default/17.edn_intr.3990280888 May 11 03:24:50 PM PDT 24 May 11 03:24:51 PM PDT 24 53721861 ps
T557 /workspace/coverage/default/24.edn_disable_auto_req_mode.4196358495 May 11 03:25:07 PM PDT 24 May 11 03:25:08 PM PDT 24 18426098 ps
T296 /workspace/coverage/default/24.edn_alert.2732411976 May 11 03:25:11 PM PDT 24 May 11 03:25:13 PM PDT 24 43878017 ps
T558 /workspace/coverage/default/38.edn_smoke.1794736726 May 11 03:25:41 PM PDT 24 May 11 03:25:43 PM PDT 24 90389782 ps
T559 /workspace/coverage/default/91.edn_err.2550295696 May 11 03:26:32 PM PDT 24 May 11 03:26:34 PM PDT 24 72368473 ps
T282 /workspace/coverage/default/7.edn_disable_auto_req_mode.3287883377 May 11 03:24:34 PM PDT 24 May 11 03:24:35 PM PDT 24 21652862 ps
T560 /workspace/coverage/default/33.edn_alert_test.1846705512 May 11 03:25:29 PM PDT 24 May 11 03:25:31 PM PDT 24 27323406 ps
T561 /workspace/coverage/default/45.edn_alert.4041972485 May 11 03:25:57 PM PDT 24 May 11 03:25:59 PM PDT 24 55132763 ps
T287 /workspace/coverage/default/47.edn_disable_auto_req_mode.1789475562 May 11 03:26:00 PM PDT 24 May 11 03:26:01 PM PDT 24 25326593 ps
T562 /workspace/coverage/default/21.edn_disable_auto_req_mode.86953209 May 11 03:25:04 PM PDT 24 May 11 03:25:05 PM PDT 24 44105015 ps
T294 /workspace/coverage/default/9.edn_genbits.426193996 May 11 03:24:37 PM PDT 24 May 11 03:24:38 PM PDT 24 40140868 ps
T138 /workspace/coverage/default/43.edn_intr.314093020 May 11 03:25:54 PM PDT 24 May 11 03:25:56 PM PDT 24 28887610 ps
T563 /workspace/coverage/default/44.edn_stress_all_with_rand_reset.429693575 May 11 03:25:55 PM PDT 24 May 11 03:34:37 PM PDT 24 20992409668 ps
T564 /workspace/coverage/default/2.edn_regwen.3162714548 May 11 03:24:15 PM PDT 24 May 11 03:24:16 PM PDT 24 14258188 ps
T104 /workspace/coverage/default/18.edn_disable.4011941263 May 11 03:24:53 PM PDT 24 May 11 03:24:54 PM PDT 24 10943137 ps
T565 /workspace/coverage/default/32.edn_genbits.2819792722 May 11 03:25:24 PM PDT 24 May 11 03:25:25 PM PDT 24 69920218 ps
T231 /workspace/coverage/default/46.edn_stress_all_with_rand_reset.37643808 May 11 03:25:56 PM PDT 24 May 11 03:43:29 PM PDT 24 148950578071 ps
T566 /workspace/coverage/default/26.edn_stress_all.2227367185 May 11 03:25:18 PM PDT 24 May 11 03:25:22 PM PDT 24 216270581 ps
T567 /workspace/coverage/default/18.edn_intr.1949704424 May 11 03:24:57 PM PDT 24 May 11 03:24:59 PM PDT 24 34567610 ps
T568 /workspace/coverage/default/24.edn_alert_test.2002819205 May 11 03:25:09 PM PDT 24 May 11 03:25:11 PM PDT 24 18819173 ps
T569 /workspace/coverage/default/1.edn_disable.3076577630 May 11 03:24:19 PM PDT 24 May 11 03:24:20 PM PDT 24 65757586 ps
T570 /workspace/coverage/default/63.edn_err.155089364 May 11 03:26:14 PM PDT 24 May 11 03:26:15 PM PDT 24 22609337 ps
T571 /workspace/coverage/default/48.edn_intr.1508888804 May 11 03:26:07 PM PDT 24 May 11 03:26:09 PM PDT 24 20873844 ps
T204 /workspace/coverage/default/75.edn_err.3671000789 May 11 03:26:25 PM PDT 24 May 11 03:26:27 PM PDT 24 31117669 ps
T105 /workspace/coverage/default/4.edn_alert.2577778033 May 11 03:24:34 PM PDT 24 May 11 03:24:36 PM PDT 24 17446189 ps
T572 /workspace/coverage/default/22.edn_intr.3010146755 May 11 03:25:05 PM PDT 24 May 11 03:25:07 PM PDT 24 22134484 ps
T573 /workspace/coverage/default/10.edn_smoke.413892419 May 11 03:24:44 PM PDT 24 May 11 03:24:45 PM PDT 24 26808996 ps
T250 /workspace/coverage/default/25.edn_disable.3670560776 May 11 03:25:12 PM PDT 24 May 11 03:25:14 PM PDT 24 14876552 ps
T574 /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3442274188 May 11 03:25:54 PM PDT 24 May 11 03:49:54 PM PDT 24 68994109630 ps
T575 /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1954260511 May 11 03:26:07 PM PDT 24 May 11 03:45:07 PM PDT 24 85689713007 ps
T576 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.784141740 May 11 03:24:41 PM PDT 24 May 11 03:38:06 PM PDT 24 37024255319 ps
T577 /workspace/coverage/default/44.edn_smoke.2882164618 May 11 03:25:54 PM PDT 24 May 11 03:25:55 PM PDT 24 22048006 ps
T578 /workspace/coverage/default/4.edn_alert_test.544131122 May 11 03:24:33 PM PDT 24 May 11 03:24:35 PM PDT 24 13411928 ps
T133 /workspace/coverage/default/19.edn_genbits.37898870 May 11 03:24:57 PM PDT 24 May 11 03:24:58 PM PDT 24 394227601 ps
T579 /workspace/coverage/default/12.edn_intr.1815203662 May 11 03:24:41 PM PDT 24 May 11 03:24:42 PM PDT 24 93804773 ps
T580 /workspace/coverage/default/15.edn_disable_auto_req_mode.2769726576 May 11 03:24:45 PM PDT 24 May 11 03:24:47 PM PDT 24 31142816 ps
T581 /workspace/coverage/default/94.edn_err.3155361216 May 11 03:26:30 PM PDT 24 May 11 03:26:32 PM PDT 24 20901874 ps
T582 /workspace/coverage/default/7.edn_alert.2989513838 May 11 03:24:31 PM PDT 24 May 11 03:24:32 PM PDT 24 53514531 ps
T583 /workspace/coverage/default/27.edn_stress_all.1940398692 May 11 03:25:19 PM PDT 24 May 11 03:25:22 PM PDT 24 82362227 ps
T584 /workspace/coverage/default/37.edn_alert_test.1336002591 May 11 03:25:46 PM PDT 24 May 11 03:25:48 PM PDT 24 47104635 ps
T585 /workspace/coverage/default/28.edn_genbits.3779873765 May 11 03:25:13 PM PDT 24 May 11 03:25:15 PM PDT 24 17843194 ps
T53 /workspace/coverage/default/1.edn_sec_cm.1821808044 May 11 03:24:16 PM PDT 24 May 11 03:24:33 PM PDT 24 1049821213 ps
T586 /workspace/coverage/default/5.edn_disable_auto_req_mode.12697721 May 11 03:24:33 PM PDT 24 May 11 03:24:34 PM PDT 24 24834020 ps
T587 /workspace/coverage/default/39.edn_alert.2804559636 May 11 03:25:47 PM PDT 24 May 11 03:25:49 PM PDT 24 85702309 ps
T588 /workspace/coverage/default/20.edn_disable_auto_req_mode.1212016981 May 11 03:25:02 PM PDT 24 May 11 03:25:03 PM PDT 24 18964496 ps
T589 /workspace/coverage/default/44.edn_alert_test.2380353004 May 11 03:25:52 PM PDT 24 May 11 03:25:53 PM PDT 24 18865694 ps
T306 /workspace/coverage/default/8.edn_alert.2300538243 May 11 03:24:33 PM PDT 24 May 11 03:24:35 PM PDT 24 20945352 ps
T590 /workspace/coverage/default/15.edn_stress_all_with_rand_reset.730767187 May 11 03:24:45 PM PDT 24 May 11 03:32:06 PM PDT 24 75696365396 ps
T276 /workspace/coverage/default/42.edn_stress_all.2308791697 May 11 03:25:49 PM PDT 24 May 11 03:25:53 PM PDT 24 438630061 ps
T591 /workspace/coverage/default/10.edn_disable_auto_req_mode.4234986984 May 11 03:24:37 PM PDT 24 May 11 03:24:40 PM PDT 24 84928978 ps
T592 /workspace/coverage/default/4.edn_err.3933452665 May 11 03:24:27 PM PDT 24 May 11 03:24:28 PM PDT 24 37152641 ps
T593 /workspace/coverage/default/45.edn_smoke.2339108550 May 11 03:25:54 PM PDT 24 May 11 03:25:56 PM PDT 24 77486177 ps
T286 /workspace/coverage/default/38.edn_err.1725631484 May 11 03:25:43 PM PDT 24 May 11 03:25:45 PM PDT 24 46463540 ps
T594 /workspace/coverage/default/41.edn_genbits.939963099 May 11 03:25:48 PM PDT 24 May 11 03:25:50 PM PDT 24 36196306 ps
T184 /workspace/coverage/default/46.edn_err.2447148651 May 11 03:26:01 PM PDT 24 May 11 03:26:02 PM PDT 24 26551066 ps
T595 /workspace/coverage/default/41.edn_err.660756057 May 11 03:25:50 PM PDT 24 May 11 03:25:52 PM PDT 24 40755117 ps
T596 /workspace/coverage/default/0.edn_err.4165266669 May 11 03:24:14 PM PDT 24 May 11 03:24:16 PM PDT 24 42100793 ps
T262 /workspace/coverage/default/22.edn_err.1033444161 May 11 03:25:07 PM PDT 24 May 11 03:25:08 PM PDT 24 35911506 ps
T597 /workspace/coverage/default/13.edn_alert_test.3835995802 May 11 03:24:44 PM PDT 24 May 11 03:24:46 PM PDT 24 217974510 ps
T598 /workspace/coverage/default/18.edn_alert.570961374 May 11 03:24:55 PM PDT 24 May 11 03:24:57 PM PDT 24 70909999 ps
T599 /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2379776968 May 11 03:24:56 PM PDT 24 May 11 03:49:31 PM PDT 24 228296747141 ps
T600 /workspace/coverage/default/46.edn_alert.2296828321 May 11 03:25:56 PM PDT 24 May 11 03:25:58 PM PDT 24 86468808 ps
T601 /workspace/coverage/default/35.edn_alert_test.2716742036 May 11 03:25:33 PM PDT 24 May 11 03:25:35 PM PDT 24 33066696 ps
T602 /workspace/coverage/default/31.edn_smoke.3775522834 May 11 03:25:20 PM PDT 24 May 11 03:25:22 PM PDT 24 49843784 ps
T603 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3260168225 May 11 03:25:25 PM PDT 24 May 11 03:39:45 PM PDT 24 38712147703 ps
T604 /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1651685625 May 11 03:25:17 PM PDT 24 May 11 03:35:49 PM PDT 24 82170308535 ps
T605 /workspace/coverage/default/31.edn_intr.161462513 May 11 03:25:21 PM PDT 24 May 11 03:25:23 PM PDT 24 31042878 ps
T606 /workspace/coverage/default/13.edn_stress_all.84586991 May 11 03:24:41 PM PDT 24 May 11 03:24:45 PM PDT 24 177286310 ps
T607 /workspace/coverage/default/1.edn_genbits.3085173075 May 11 03:24:14 PM PDT 24 May 11 03:24:15 PM PDT 24 32056407 ps
T608 /workspace/coverage/default/34.edn_alert_test.2842168689 May 11 03:25:37 PM PDT 24 May 11 03:25:39 PM PDT 24 34871618 ps
T609 /workspace/coverage/default/9.edn_intr.3196562488 May 11 03:24:37 PM PDT 24 May 11 03:24:39 PM PDT 24 22313232 ps
T185 /workspace/coverage/default/39.edn_err.3811357823 May 11 03:25:43 PM PDT 24 May 11 03:25:44 PM PDT 24 47469409 ps
T610 /workspace/coverage/default/20.edn_err.1095232803 May 11 03:25:01 PM PDT 24 May 11 03:25:03 PM PDT 24 83173440 ps
T611 /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1513862717 May 11 03:24:29 PM PDT 24 May 11 03:46:34 PM PDT 24 117013517178 ps
T309 /workspace/coverage/default/8.edn_regwen.3554713695 May 11 03:24:33 PM PDT 24 May 11 03:24:35 PM PDT 24 63653875 ps
T612 /workspace/coverage/default/29.edn_smoke.506269571 May 11 03:25:14 PM PDT 24 May 11 03:25:15 PM PDT 24 23085860 ps
T613 /workspace/coverage/default/24.edn_err.846068258 May 11 03:25:12 PM PDT 24 May 11 03:25:14 PM PDT 24 81322057 ps
T106 /workspace/coverage/default/38.edn_disable_auto_req_mode.2221859453 May 11 03:25:43 PM PDT 24 May 11 03:25:45 PM PDT 24 76595020 ps
T614 /workspace/coverage/default/12.edn_smoke.93311749 May 11 03:24:42 PM PDT 24 May 11 03:24:43 PM PDT 24 72066410 ps
T177 /workspace/coverage/default/98.edn_err.366212668 May 11 03:26:33 PM PDT 24 May 11 03:26:35 PM PDT 24 133120142 ps
T615 /workspace/coverage/default/44.edn_genbits.3503501299 May 11 03:25:51 PM PDT 24 May 11 03:25:53 PM PDT 24 19369928 ps
T616 /workspace/coverage/default/13.edn_genbits.704027564 May 11 03:24:47 PM PDT 24 May 11 03:24:49 PM PDT 24 292998893 ps
T107 /workspace/coverage/default/37.edn_alert.2703530102 May 11 03:25:38 PM PDT 24 May 11 03:25:40 PM PDT 24 40962795 ps
T617 /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1528679996 May 11 03:24:13 PM PDT 24 May 11 03:35:18 PM PDT 24 31415097180 ps
T179 /workspace/coverage/default/60.edn_err.3768467922 May 11 03:26:13 PM PDT 24 May 11 03:26:15 PM PDT 24 20288245 ps
T618 /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2579602271 May 11 03:25:57 PM PDT 24 May 11 03:52:28 PM PDT 24 248719133824 ps
T619 /workspace/coverage/default/3.edn_alert_test.1443295133 May 11 03:24:24 PM PDT 24 May 11 03:24:25 PM PDT 24 59342787 ps
T620 /workspace/coverage/default/20.edn_genbits.2004588746 May 11 03:25:02 PM PDT 24 May 11 03:25:04 PM PDT 24 14866695 ps
T621 /workspace/coverage/default/41.edn_alert.1895611345 May 11 03:25:50 PM PDT 24 May 11 03:25:52 PM PDT 24 77116634 ps
T284 /workspace/coverage/default/39.edn_disable_auto_req_mode.196160605 May 11 03:25:50 PM PDT 24 May 11 03:25:52 PM PDT 24 22410595 ps
T622 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2931506887 May 11 03:24:40 PM PDT 24 May 11 04:00:16 PM PDT 24 321953329664 ps
T623 /workspace/coverage/default/42.edn_genbits.3707325681 May 11 03:25:49 PM PDT 24 May 11 03:25:51 PM PDT 24 344238666 ps
T624 /workspace/coverage/default/30.edn_alert.3149732939 May 11 03:25:30 PM PDT 24 May 11 03:25:31 PM PDT 24 235756234 ps
T625 /workspace/coverage/default/20.edn_smoke.1332434288 May 11 03:25:00 PM PDT 24 May 11 03:25:01 PM PDT 24 32504263 ps
T626 /workspace/coverage/default/20.edn_alert.3836411856 May 11 03:24:59 PM PDT 24 May 11 03:25:01 PM PDT 24 33459918 ps
T627 /workspace/coverage/default/4.edn_stress_all.2279516586 May 11 03:24:25 PM PDT 24 May 11 03:24:26 PM PDT 24 71352513 ps
T628 /workspace/coverage/default/5.edn_smoke.1727294515 May 11 03:24:26 PM PDT 24 May 11 03:24:27 PM PDT 24 23397346 ps
T629 /workspace/coverage/default/34.edn_smoke.88393080 May 11 03:25:30 PM PDT 24 May 11 03:25:32 PM PDT 24 13157343 ps
T630 /workspace/coverage/default/0.edn_stress_all.3595478469 May 11 03:24:12 PM PDT 24 May 11 03:24:14 PM PDT 24 171394001 ps
T108 /workspace/coverage/default/26.edn_genbits.2345308533 May 11 03:25:11 PM PDT 24 May 11 03:25:14 PM PDT 24 39243152 ps
T307 /workspace/coverage/default/25.edn_alert.720867083 May 11 03:25:11 PM PDT 24 May 11 03:25:13 PM PDT 24 48701170 ps
T631 /workspace/coverage/default/49.edn_alert_test.1518607474 May 11 03:26:07 PM PDT 24 May 11 03:26:09 PM PDT 24 41941791 ps
T632 /workspace/coverage/default/7.edn_genbits.767786737 May 11 03:24:37 PM PDT 24 May 11 03:24:38 PM PDT 24 26382015 ps
T54 /workspace/coverage/default/2.edn_sec_cm.2398467276 May 11 03:24:23 PM PDT 24 May 11 03:24:29 PM PDT 24 2504268149 ps
T633 /workspace/coverage/default/3.edn_smoke.861389668 May 11 03:24:20 PM PDT 24 May 11 03:24:22 PM PDT 24 15929938 ps
T634 /workspace/coverage/default/74.edn_err.3995674583 May 11 03:26:24 PM PDT 24 May 11 03:26:25 PM PDT 24 50935613 ps
T635 /workspace/coverage/default/46.edn_disable_auto_req_mode.2345236623 May 11 03:25:59 PM PDT 24 May 11 03:26:00 PM PDT 24 222999337 ps
T636 /workspace/coverage/default/9.edn_disable.2177143279 May 11 03:24:37 PM PDT 24 May 11 03:24:39 PM PDT 24 20198793 ps
T637 /workspace/coverage/default/12.edn_genbits.3122611652 May 11 03:24:43 PM PDT 24 May 11 03:24:45 PM PDT 24 18104006 ps
T638 /workspace/coverage/default/30.edn_smoke.3254224325 May 11 03:25:20 PM PDT 24 May 11 03:25:22 PM PDT 24 130678027 ps
T639 /workspace/coverage/default/0.edn_alert.3878934549 May 11 03:24:16 PM PDT 24 May 11 03:24:17 PM PDT 24 70444272 ps
T640 /workspace/coverage/default/28.edn_disable_auto_req_mode.3057462108 May 11 03:25:15 PM PDT 24 May 11 03:25:16 PM PDT 24 23128699 ps
T206 /workspace/coverage/default/18.edn_err.3465534719 May 11 03:24:52 PM PDT 24 May 11 03:24:53 PM PDT 24 45953624 ps
T641 /workspace/coverage/default/10.edn_stress_all_with_rand_reset.753692970 May 11 03:24:41 PM PDT 24 May 11 03:51:03 PM PDT 24 77179224933 ps
T642 /workspace/coverage/default/49.edn_disable.1662103981 May 11 03:26:05 PM PDT 24 May 11 03:26:06 PM PDT 24 14241144 ps
T643 /workspace/coverage/default/21.edn_stress_all.3373465946 May 11 03:25:00 PM PDT 24 May 11 03:25:05 PM PDT 24 1325177426 ps
T644 /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2156421946 May 11 03:24:25 PM PDT 24 May 11 03:30:08 PM PDT 24 66140952774 ps
T645 /workspace/coverage/default/42.edn_disable.2525178547 May 11 03:25:50 PM PDT 24 May 11 03:25:52 PM PDT 24 13158244 ps
T646 /workspace/coverage/default/32.edn_smoke.4137172046 May 11 03:25:24 PM PDT 24 May 11 03:25:25 PM PDT 24 33746561 ps
T247 /workspace/coverage/default/47.edn_disable.1395991171 May 11 03:25:59 PM PDT 24 May 11 03:26:00 PM PDT 24 14913251 ps
T647 /workspace/coverage/default/42.edn_smoke.364910903 May 11 03:25:49 PM PDT 24 May 11 03:25:51 PM PDT 24 30830417 ps
T648 /workspace/coverage/default/25.edn_genbits.353263018 May 11 03:25:11 PM PDT 24 May 11 03:25:13 PM PDT 24 47315867 ps
T649 /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2557003130 May 11 03:24:35 PM PDT 24 May 11 04:01:06 PM PDT 24 370393671001 ps
T650 /workspace/coverage/default/0.edn_alert_test.611027975 May 11 03:24:13 PM PDT 24 May 11 03:24:14 PM PDT 24 30353203 ps
T651 /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1570901848 May 11 03:25:25 PM PDT 24 May 11 03:44:29 PM PDT 24 240478212099 ps
T652 /workspace/coverage/default/29.edn_intr.2587143872 May 11 03:25:20 PM PDT 24 May 11 03:25:21 PM PDT 24 34687730 ps
T653 /workspace/coverage/default/41.edn_alert_test.1160401460 May 11 03:25:49 PM PDT 24 May 11 03:25:51 PM PDT 24 31261763 ps
T654 /workspace/coverage/default/38.edn_alert_test.1294316461 May 11 03:25:48 PM PDT 24 May 11 03:25:49 PM PDT 24 11608080 ps
T655 /workspace/coverage/default/2.edn_intr.3636783752 May 11 03:24:22 PM PDT 24 May 11 03:24:23 PM PDT 24 35002613 ps
T303 /workspace/coverage/default/7.edn_regwen.653291111 May 11 03:24:30 PM PDT 24 May 11 03:24:31 PM PDT 24 19112390 ps
T656 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2171838424 May 11 03:24:50 PM PDT 24 May 11 03:35:43 PM PDT 24 139331571292 ps
T657 /workspace/coverage/default/25.edn_smoke.2020487714 May 11 03:25:10 PM PDT 24 May 11 03:25:12 PM PDT 24 23461585 ps
T658 /workspace/coverage/default/37.edn_disable_auto_req_mode.3751525557 May 11 03:25:46 PM PDT 24 May 11 03:25:48 PM PDT 24 26506383 ps
T659 /workspace/coverage/default/1.edn_err.1990242543 May 11 03:24:19 PM PDT 24 May 11 03:24:20 PM PDT 24 23136072 ps
T660 /workspace/coverage/default/62.edn_err.2206183589 May 11 03:26:12 PM PDT 24 May 11 03:26:13 PM PDT 24 54373815 ps
T251 /workspace/coverage/default/13.edn_disable.4100518621 May 11 03:24:44 PM PDT 24 May 11 03:24:45 PM PDT 24 42246315 ps
T661 /workspace/coverage/default/46.edn_disable.3959763833 May 11 03:26:01 PM PDT 24 May 11 03:26:03 PM PDT 24 32859758 ps
T203 /workspace/coverage/default/6.edn_err.3709326392 May 11 03:24:31 PM PDT 24 May 11 03:24:33 PM PDT 24 19200012 ps
T662 /workspace/coverage/default/16.edn_smoke.1065655650 May 11 03:24:49 PM PDT 24 May 11 03:24:50 PM PDT 24 20468027 ps
T663 /workspace/coverage/default/22.edn_disable.2966743510 May 11 03:25:05 PM PDT 24 May 11 03:25:06 PM PDT 24 40516148 ps
T664 /workspace/coverage/default/42.edn_intr.1680245544 May 11 03:25:50 PM PDT 24 May 11 03:25:52 PM PDT 24 25579179 ps
T665 /workspace/coverage/default/12.edn_stress_all.519464708 May 11 03:24:41 PM PDT 24 May 11 03:24:46 PM PDT 24 199623276 ps
T666 /workspace/coverage/default/48.edn_stress_all.1710398091 May 11 03:26:03 PM PDT 24 May 11 03:26:05 PM PDT 24 358032128 ps
T667 /workspace/coverage/default/25.edn_intr.1227916883 May 11 03:25:19 PM PDT 24 May 11 03:25:20 PM PDT 24 40279640 ps
T668 /workspace/coverage/default/26.edn_alert_test.441533328 May 11 03:25:19 PM PDT 24 May 11 03:25:21 PM PDT 24 85580749 ps
T669 /workspace/coverage/default/32.edn_err.479128941 May 11 03:25:22 PM PDT 24 May 11 03:25:23 PM PDT 24 73842636 ps
T670 /workspace/coverage/default/36.edn_intr.2349214836 May 11 03:25:34 PM PDT 24 May 11 03:25:36 PM PDT 24 27239424 ps
T671 /workspace/coverage/default/33.edn_alert.2204749404 May 11 03:25:25 PM PDT 24 May 11 03:25:27 PM PDT 24 62711284 ps
T672 /workspace/coverage/default/23.edn_stress_all_with_rand_reset.22288488 May 11 03:25:09 PM PDT 24 May 11 03:44:51 PM PDT 24 50150345423 ps
T673 /workspace/coverage/default/17.edn_genbits.3013300876 May 11 03:24:50 PM PDT 24 May 11 03:24:52 PM PDT 24 165260074 ps
T674 /workspace/coverage/default/44.edn_err.4071669439 May 11 03:25:55 PM PDT 24 May 11 03:25:56 PM PDT 24 221130734 ps
T194 /workspace/coverage/default/31.edn_disable_auto_req_mode.2121335189 May 11 03:25:25 PM PDT 24 May 11 03:25:26 PM PDT 24 81462649 ps
T675 /workspace/coverage/default/27.edn_genbits.4281022014 May 11 03:25:18 PM PDT 24 May 11 03:25:19 PM PDT 24 20396402 ps
T196 /workspace/coverage/default/19.edn_err.4044459482 May 11 03:24:58 PM PDT 24 May 11 03:24:59 PM PDT 24 24529685 ps
T208 /workspace/coverage/default/81.edn_err.3049603309 May 11 03:26:31 PM PDT 24 May 11 03:26:32 PM PDT 24 24599205 ps
T676 /workspace/coverage/default/11.edn_alert_test.1594721595 May 11 03:24:41 PM PDT 24 May 11 03:24:42 PM PDT 24 119853882 ps
T677 /workspace/coverage/default/21.edn_smoke.35050301 May 11 03:25:02 PM PDT 24 May 11 03:25:04 PM PDT 24 46566197 ps
T678 /workspace/coverage/default/10.edn_alert_test.373266177 May 11 03:24:37 PM PDT 24 May 11 03:24:39 PM PDT 24 13816522 ps
T679 /workspace/coverage/default/26.edn_intr.3960173954 May 11 03:25:14 PM PDT 24 May 11 03:25:15 PM PDT 24 95898943 ps
T680 /workspace/coverage/default/29.edn_genbits.217314574 May 11 03:25:20 PM PDT 24 May 11 03:25:21 PM PDT 24 15721709 ps
T681 /workspace/coverage/default/31.edn_stress_all_with_rand_reset.987106068 May 11 03:25:23 PM PDT 24 May 11 03:32:21 PM PDT 24 19664731150 ps
T682 /workspace/coverage/default/11.edn_disable_auto_req_mode.1033438495 May 11 03:24:41 PM PDT 24 May 11 03:24:43 PM PDT 24 55830513 ps
T683 /workspace/coverage/default/3.edn_stress_all.3251293572 May 11 03:24:21 PM PDT 24 May 11 03:24:25 PM PDT 24 177561211 ps
T684 /workspace/coverage/default/35.edn_disable_auto_req_mode.2479569153 May 11 03:25:36 PM PDT 24 May 11 03:25:38 PM PDT 24 98113629 ps
T685 /workspace/coverage/default/44.edn_stress_all.3755015560 May 11 03:25:57 PM PDT 24 May 11 03:26:01 PM PDT 24 117294794 ps
T686 /workspace/coverage/default/25.edn_alert_test.2779978894 May 11 03:25:19 PM PDT 24 May 11 03:25:20 PM PDT 24 71389526 ps
T687 /workspace/coverage/default/33.edn_err.2459679375 May 11 03:25:28 PM PDT 24 May 11 03:25:30 PM PDT 24 27262596 ps
T688 /workspace/coverage/default/23.edn_stress_all.571176886 May 11 03:25:09 PM PDT 24 May 11 03:25:12 PM PDT 24 231484407 ps
T689 /workspace/coverage/default/32.edn_intr.3579447803 May 11 03:25:24 PM PDT 24 May 11 03:25:25 PM PDT 24 17895754 ps
T690 /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2506035509 May 11 03:25:20 PM PDT 24 May 11 03:37:24 PM PDT 24 31531832364 ps
T155 /workspace/coverage/default/37.edn_disable.4272276813 May 11 03:25:40 PM PDT 24 May 11 03:25:41 PM PDT 24 21874346 ps
T691 /workspace/coverage/default/13.edn_alert.2587151747 May 11 03:24:43 PM PDT 24 May 11 03:24:45 PM PDT 24 17801403 ps
T692 /workspace/coverage/default/78.edn_err.2657038729 May 11 03:26:27 PM PDT 24 May 11 03:26:28 PM PDT 24 60390777 ps
T244 /workspace/coverage/default/35.edn_disable.2299543467 May 11 03:25:34 PM PDT 24 May 11 03:25:35 PM PDT 24 15152946 ps
T693 /workspace/coverage/default/36.edn_err.3561240752 May 11 03:25:39 PM PDT 24 May 11 03:25:40 PM PDT 24 33428958 ps
T694 /workspace/coverage/default/40.edn_stress_all_with_rand_reset.226251678 May 11 03:25:44 PM PDT 24 May 11 03:41:00 PM PDT 24 41471845405 ps
T695 /workspace/coverage/default/6.edn_intr.267171343 May 11 03:24:36 PM PDT 24 May 11 03:24:38 PM PDT 24 30272866 ps
T696 /workspace/coverage/default/37.edn_err.499412276 May 11 03:25:46 PM PDT 24 May 11 03:25:47 PM PDT 24 30728904 ps
T697 /workspace/coverage/default/16.edn_alert_test.3384369520 May 11 03:24:49 PM PDT 24 May 11 03:24:50 PM PDT 24 22326625 ps
T698 /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2945243107 May 11 03:25:36 PM PDT 24 May 11 03:33:38 PM PDT 24 42347826039 ps
T699 /workspace/coverage/default/17.edn_disable.3031703683 May 11 03:24:53 PM PDT 24 May 11 03:24:54 PM PDT 24 16202031 ps
T261 /workspace/coverage/default/28.edn_err.1730243161 May 11 03:25:18 PM PDT 24 May 11 03:25:19 PM PDT 24 21671486 ps
T700 /workspace/coverage/default/27.edn_alert.1489551310 May 11 03:25:16 PM PDT 24 May 11 03:25:18 PM PDT 24 20288246 ps
T701 /workspace/coverage/default/1.edn_alert_test.2372986698 May 11 03:24:18 PM PDT 24 May 11 03:24:19 PM PDT 24 54875670 ps
T702 /workspace/coverage/default/24.edn_genbits.3519381834 May 11 03:25:09 PM PDT 24 May 11 03:25:11 PM PDT 24 38688723 ps
T703 /workspace/coverage/default/7.edn_stress_all.1706989554 May 11 03:24:36 PM PDT 24 May 11 03:24:39 PM PDT 24 94792650 ps
T704 /workspace/coverage/default/27.edn_disable.3140913228 May 11 03:25:17 PM PDT 24 May 11 03:25:18 PM PDT 24 13668141 ps
T705 /workspace/coverage/default/69.edn_err.2170271513 May 11 03:26:20 PM PDT 24 May 11 03:26:22 PM PDT 24 18943453 ps
T706 /workspace/coverage/default/41.edn_intr.838562320 May 11 03:25:52 PM PDT 24 May 11 03:25:53 PM PDT 24 18032673 ps
T277 /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2127448034 May 11 03:24:51 PM PDT 24 May 11 03:48:47 PM PDT 24 227181230804 ps
T707 /workspace/coverage/default/41.edn_smoke.2931996092 May 11 03:26:05 PM PDT 24 May 11 03:26:06 PM PDT 24 13429891 ps
T708 /workspace/coverage/default/11.edn_stress_all.648735033 May 11 03:24:39 PM PDT 24 May 11 03:24:42 PM PDT 24 423833372 ps
T709 /workspace/coverage/default/46.edn_intr.774864921 May 11 03:25:57 PM PDT 24 May 11 03:25:59 PM PDT 24 21048001 ps
T710 /workspace/coverage/default/15.edn_genbits.3459577134 May 11 03:24:48 PM PDT 24 May 11 03:24:50 PM PDT 24 73149077 ps
T711 /workspace/coverage/default/45.edn_intr.755857004 May 11 03:26:02 PM PDT 24 May 11 03:26:03 PM PDT 24 29772723 ps
T298 /workspace/coverage/default/22.edn_alert.1167101581 May 11 03:25:05 PM PDT 24 May 11 03:25:07 PM PDT 24 73194046 ps
T712 /workspace/coverage/default/44.edn_disable_auto_req_mode.2342195239 May 11 03:25:54 PM PDT 24 May 11 03:25:56 PM PDT 24 65386140 ps
T713 /workspace/coverage/default/47.edn_alert_test.509428576 May 11 03:26:01 PM PDT 24 May 11 03:26:02 PM PDT 24 55806728 ps
T252 /workspace/coverage/default/30.edn_disable_auto_req_mode.1489895114 May 11 03:25:23 PM PDT 24 May 11 03:25:24 PM PDT 24 57388371 ps
T258 /workspace/coverage/default/41.edn_disable.3968721582 May 11 03:25:48 PM PDT 24 May 11 03:25:50 PM PDT 24 20190441 ps
T714 /workspace/coverage/default/23.edn_alert.2090530469 May 11 03:25:06 PM PDT 24 May 11 03:25:07 PM PDT 24 17666271 ps
T715 /workspace/coverage/default/30.edn_intr.1876580163 May 11 03:25:21 PM PDT 24 May 11 03:25:22 PM PDT 24 25708287 ps
T716 /workspace/coverage/default/10.edn_stress_all.2089420638 May 11 03:24:37 PM PDT 24 May 11 03:24:40 PM PDT 24 178386422 ps
T717 /workspace/coverage/default/7.edn_intr.612626579 May 11 03:24:32 PM PDT 24 May 11 03:24:34 PM PDT 24 39405835 ps
T718 /workspace/coverage/default/43.edn_alert_test.1674415655 May 11 03:25:53 PM PDT 24 May 11 03:25:55 PM PDT 24 24125751 ps
T719 /workspace/coverage/default/10.edn_alert.2727617268 May 11 03:24:41 PM PDT 24 May 11 03:24:43 PM PDT 24 51144462 ps
T720 /workspace/coverage/default/13.edn_smoke.2287372492 May 11 03:24:41 PM PDT 24 May 11 03:24:43 PM PDT 24 70707391 ps
T721 /workspace/coverage/default/73.edn_err.1331872036 May 11 03:26:22 PM PDT 24 May 11 03:26:24 PM PDT 24 42733729 ps
T722 /workspace/coverage/default/24.edn_smoke.4225037789 May 11 03:25:08 PM PDT 24 May 11 03:25:09 PM PDT 24 12075873 ps
T723 /workspace/coverage/default/53.edn_err.3665607146 May 11 03:26:09 PM PDT 24 May 11 03:26:11 PM PDT 24 35960231 ps
T724 /workspace/coverage/default/47.edn_intr.1702983942 May 11 03:26:01 PM PDT 24 May 11 03:26:03 PM PDT 24 37672779 ps

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2401044027
Short name T20
Test name
Test status
Simulation time 37480497713 ps
CPU time 313.44 seconds
Started May 11 03:25:49 PM PDT 24
Finished May 11 03:31:04 PM PDT 24
Peak memory 215104 kb
Host smart-1bee96de-31ca-4ce0-b762-5559aef6d9bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401044027 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2401044027
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_genbits.1240106615
Short name T32
Test name
Test status
Simulation time 150154378 ps
CPU time 1.35 seconds
Started May 11 03:25:29 PM PDT 24
Finished May 11 03:25:30 PM PDT 24
Peak memory 205736 kb
Host smart-46cbfc50-c6b7-4555-8696-e5d15bfb85ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240106615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1240106615
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1712193565
Short name T5
Test name
Test status
Simulation time 71488479 ps
CPU time 0.99 seconds
Started May 11 03:26:14 PM PDT 24
Finished May 11 03:26:15 PM PDT 24
Peak memory 215352 kb
Host smart-09aea4bd-cdda-49e9-bdb9-6007075360b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712193565 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1712193565
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/3.edn_disable.1658569753
Short name T46
Test name
Test status
Simulation time 11797250 ps
CPU time 0.86 seconds
Started May 11 03:24:29 PM PDT 24
Finished May 11 03:24:30 PM PDT 24
Peak memory 214980 kb
Host smart-57030553-d0e1-4ee1-b75b-99c18a00f127
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658569753 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1658569753
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/0.edn_sec_cm.307150994
Short name T21
Test name
Test status
Simulation time 1202039492 ps
CPU time 3.81 seconds
Started May 11 03:24:11 PM PDT 24
Finished May 11 03:24:15 PM PDT 24
Peak memory 233924 kb
Host smart-ec3d2c81-1d3f-4eac-a7af-fd3e3b840f15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307150994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.307150994
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_alert.3742395990
Short name T15
Test name
Test status
Simulation time 18530257 ps
CPU time 1.03 seconds
Started May 11 03:24:24 PM PDT 24
Finished May 11 03:24:25 PM PDT 24
Peak memory 206592 kb
Host smart-b50bf19e-0a72-4568-b69d-cc35edb4155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742395990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3742395990
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.708595967
Short name T8
Test name
Test status
Simulation time 25175193 ps
CPU time 1.07 seconds
Started May 11 03:24:36 PM PDT 24
Finished May 11 03:24:37 PM PDT 24
Peak memory 215336 kb
Host smart-86420e7a-0154-42c5-976f-3c89edddecd8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708595967 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.708595967
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1597370511
Short name T85
Test name
Test status
Simulation time 356107183 ps
CPU time 1.11 seconds
Started May 11 03:26:06 PM PDT 24
Finished May 11 03:26:08 PM PDT 24
Peak memory 215284 kb
Host smart-bd2f7b1c-97c4-4c0a-924d-e87d2b15de32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597370511 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1597370511
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_regwen.3756853160
Short name T76
Test name
Test status
Simulation time 22663555 ps
CPU time 0.85 seconds
Started May 11 03:24:28 PM PDT 24
Finished May 11 03:24:29 PM PDT 24
Peak memory 205296 kb
Host smart-9703bc8a-1647-4b58-a980-0afb764fb4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756853160 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3756853160
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/32.edn_disable.581981815
Short name T120
Test name
Test status
Simulation time 42205960 ps
CPU time 0.89 seconds
Started May 11 03:25:23 PM PDT 24
Finished May 11 03:25:24 PM PDT 24
Peak memory 214952 kb
Host smart-fca0bc5f-a33d-45d1-b38d-1963143bc163
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581981815 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.581981815
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1462748428
Short name T363
Test name
Test status
Simulation time 184907786 ps
CPU time 2.61 seconds
Started May 11 03:50:00 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205720 kb
Host smart-a1f1cf5f-cdad-4f39-9c6a-62a2b6821666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462748428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1462748428
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/default/44.edn_disable.2251124044
Short name T40
Test name
Test status
Simulation time 17873661 ps
CPU time 0.87 seconds
Started May 11 03:25:56 PM PDT 24
Finished May 11 03:25:57 PM PDT 24
Peak memory 214948 kb
Host smart-fe14b2f7-546f-41be-af4e-61bd7e33fbe7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251124044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2251124044
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2322461334
Short name T29
Test name
Test status
Simulation time 84252132 ps
CPU time 1.06 seconds
Started May 11 03:25:14 PM PDT 24
Finished May 11 03:25:16 PM PDT 24
Peak memory 215144 kb
Host smart-e81e6fb8-e98d-436c-bdd0-50ddf6ed2b19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322461334 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2322461334
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_disable.558188009
Short name T131
Test name
Test status
Simulation time 39364306 ps
CPU time 0.85 seconds
Started May 11 03:24:45 PM PDT 24
Finished May 11 03:24:47 PM PDT 24
Peak memory 214984 kb
Host smart-3d845175-9d50-4cf4-9394-72b3414f1f19
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558188009 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.558188009
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable.4011941263
Short name T104
Test name
Test status
Simulation time 10943137 ps
CPU time 0.89 seconds
Started May 11 03:24:53 PM PDT 24
Finished May 11 03:24:54 PM PDT 24
Peak memory 214984 kb
Host smart-b63ceaf3-f72a-42dc-bfd6-18cc212e8783
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011941263 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.4011941263
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2221859453
Short name T106
Test name
Test status
Simulation time 76595020 ps
CPU time 1.04 seconds
Started May 11 03:25:43 PM PDT 24
Finished May 11 03:25:45 PM PDT 24
Peak memory 215184 kb
Host smart-88384ce3-bbbd-4d2f-8017-df8b51c61a0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221859453 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2221859453
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2203245224
Short name T4
Test name
Test status
Simulation time 29597548 ps
CPU time 1.36 seconds
Started May 11 03:25:30 PM PDT 24
Finished May 11 03:25:31 PM PDT 24
Peak memory 222712 kb
Host smart-c26b908c-acf6-44cd-9a58-fcb11439d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203245224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2203245224
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2078920625
Short name T221
Test name
Test status
Simulation time 61400366 ps
CPU time 0.82 seconds
Started May 11 03:49:56 PM PDT 24
Finished May 11 03:49:58 PM PDT 24
Peak memory 205612 kb
Host smart-aa621f83-600f-4359-a77c-8f7f907f3f77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078920625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2078920625
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2219097607
Short name T180
Test name
Test status
Simulation time 56279612 ps
CPU time 1.03 seconds
Started May 11 03:24:47 PM PDT 24
Finished May 11 03:24:49 PM PDT 24
Peak memory 215088 kb
Host smart-31a57c89-fd72-43ff-80c2-bd05b7cba7eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219097607 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2219097607
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_intr.1834856141
Short name T135
Test name
Test status
Simulation time 25847498 ps
CPU time 0.87 seconds
Started May 11 03:24:18 PM PDT 24
Finished May 11 03:24:19 PM PDT 24
Peak memory 215056 kb
Host smart-176848c0-e558-496f-9b8b-cf505323d5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834856141 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1834856141
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2702434070
Short name T157
Test name
Test status
Simulation time 161211395857 ps
CPU time 1540.26 seconds
Started May 11 03:25:44 PM PDT 24
Finished May 11 03:51:25 PM PDT 24
Peak memory 218940 kb
Host smart-ecf6b48e-f140-4e36-9087-9d36ff1cc98c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702434070 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2702434070
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_alert.1859240519
Short name T94
Test name
Test status
Simulation time 20461780 ps
CPU time 1.04 seconds
Started May 11 03:24:55 PM PDT 24
Finished May 11 03:24:56 PM PDT 24
Peak memory 205632 kb
Host smart-b21dcc03-8d48-40da-a082-7f1b1dc1f297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859240519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1859240519
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2483066385
Short name T551
Test name
Test status
Simulation time 20658938 ps
CPU time 1.11 seconds
Started May 11 03:24:17 PM PDT 24
Finished May 11 03:24:19 PM PDT 24
Peak memory 215280 kb
Host smart-e08ac630-f758-4205-b9a1-989ac412f990
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483066385 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2483066385
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_genbits.658125201
Short name T12
Test name
Test status
Simulation time 45940345 ps
CPU time 1.17 seconds
Started May 11 03:24:36 PM PDT 24
Finished May 11 03:24:38 PM PDT 24
Peak memory 206396 kb
Host smart-df826f90-577d-440a-a2e3-26c42065a99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658125201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.658125201
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1707894273
Short name T67
Test name
Test status
Simulation time 55219229 ps
CPU time 0.83 seconds
Started May 11 03:24:38 PM PDT 24
Finished May 11 03:24:39 PM PDT 24
Peak memory 215092 kb
Host smart-61838aba-f5a6-4e30-9dfb-4d71502331e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707894273 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1707894273
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/43.edn_genbits.848055406
Short name T275
Test name
Test status
Simulation time 206854477 ps
CPU time 1.02 seconds
Started May 11 03:25:53 PM PDT 24
Finished May 11 03:25:54 PM PDT 24
Peak memory 206216 kb
Host smart-a9fc2e60-bd4b-423e-ad61-4f1226ea408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848055406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.848055406
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_stress_all.1254072585
Short name T63
Test name
Test status
Simulation time 121026775 ps
CPU time 1.84 seconds
Started May 11 03:25:25 PM PDT 24
Finished May 11 03:25:27 PM PDT 24
Peak memory 205812 kb
Host smart-a555afd8-343e-43f9-864c-da511647af44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254072585 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1254072585
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_disable.1105766525
Short name T71
Test name
Test status
Simulation time 21792575 ps
CPU time 0.8 seconds
Started May 11 03:26:05 PM PDT 24
Finished May 11 03:26:06 PM PDT 24
Peak memory 214980 kb
Host smart-a9f51d23-8acf-4dbf-9123-88b1b26e51a7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105766525 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1105766525
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable.3158059434
Short name T146
Test name
Test status
Simulation time 34461402 ps
CPU time 0.86 seconds
Started May 11 03:24:13 PM PDT 24
Finished May 11 03:24:14 PM PDT 24
Peak memory 214992 kb
Host smart-15856d95-df34-44a9-86da-b0109bcc0247
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158059434 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3158059434
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable.3076577630
Short name T569
Test name
Test status
Simulation time 65757586 ps
CPU time 0.85 seconds
Started May 11 03:24:19 PM PDT 24
Finished May 11 03:24:20 PM PDT 24
Peak memory 214956 kb
Host smart-bba204f7-041e-4c5c-a749-ae72cd18e685
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076577630 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3076577630
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable.4100518621
Short name T251
Test name
Test status
Simulation time 42246315 ps
CPU time 0.81 seconds
Started May 11 03:24:44 PM PDT 24
Finished May 11 03:24:45 PM PDT 24
Peak memory 214976 kb
Host smart-9507cdf0-da71-44ed-a002-d6bce46134de
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100518621 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.4100518621
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable.3177757272
Short name T92
Test name
Test status
Simulation time 24382220 ps
CPU time 0.87 seconds
Started May 11 03:24:58 PM PDT 24
Finished May 11 03:24:59 PM PDT 24
Peak memory 214980 kb
Host smart-782a4525-275d-4fce-aa1f-d3429511d8f8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177757272 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3177757272
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable.1448033785
Short name T96
Test name
Test status
Simulation time 22391752 ps
CPU time 0.87 seconds
Started May 11 03:25:05 PM PDT 24
Finished May 11 03:25:06 PM PDT 24
Peak memory 214980 kb
Host smart-abce65c3-07b3-42be-b381-740dccd2a248
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448033785 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1448033785
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable.2299543467
Short name T244
Test name
Test status
Simulation time 15152946 ps
CPU time 0.83 seconds
Started May 11 03:25:34 PM PDT 24
Finished May 11 03:25:35 PM PDT 24
Peak memory 214976 kb
Host smart-6408f917-c222-4ce6-b5e6-11bec8e391c7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299543467 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2299543467
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable.1250181076
Short name T115
Test name
Test status
Simulation time 10796635 ps
CPU time 0.87 seconds
Started May 11 03:25:45 PM PDT 24
Finished May 11 03:25:46 PM PDT 24
Peak memory 214980 kb
Host smart-1c11d5fb-e318-475a-9562-5258c79db595
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250181076 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1250181076
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/12.edn_alert.1724455056
Short name T1
Test name
Test status
Simulation time 15583434 ps
CPU time 0.97 seconds
Started May 11 03:24:43 PM PDT 24
Finished May 11 03:24:44 PM PDT 24
Peak memory 205908 kb
Host smart-aeafc606-b116-4354-9edb-6d67e7b54f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724455056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1724455056
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert.1787238646
Short name T109
Test name
Test status
Simulation time 39056305 ps
CPU time 0.98 seconds
Started May 11 03:24:45 PM PDT 24
Finished May 11 03:24:47 PM PDT 24
Peak memory 206552 kb
Host smart-f291b963-5cef-4b78-9ff4-16b3ca57d2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787238646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1787238646
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/47.edn_genbits.319867590
Short name T78
Test name
Test status
Simulation time 87375039 ps
CPU time 1.24 seconds
Started May 11 03:26:01 PM PDT 24
Finished May 11 03:26:03 PM PDT 24
Peak memory 205852 kb
Host smart-cf6928af-4b16-4bcb-ae70-d22f58e238cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319867590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.319867590
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_regwen.3494428026
Short name T149
Test name
Test status
Simulation time 14649041 ps
CPU time 0.92 seconds
Started May 11 03:24:27 PM PDT 24
Finished May 11 03:24:28 PM PDT 24
Peak memory 205560 kb
Host smart-713d415c-cdf3-4951-86bf-0a4a87081492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494428026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3494428026
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/12.edn_alert_test.2485972541
Short name T74
Test name
Test status
Simulation time 14938645 ps
CPU time 0.9 seconds
Started May 11 03:24:47 PM PDT 24
Finished May 11 03:24:48 PM PDT 24
Peak memory 205780 kb
Host smart-44be354b-a7b3-4985-99a9-6e3962061920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485972541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2485972541
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_genbits.2330539592
Short name T93
Test name
Test status
Simulation time 47279676 ps
CPU time 1.1 seconds
Started May 11 03:24:55 PM PDT 24
Finished May 11 03:24:57 PM PDT 24
Peak memory 205720 kb
Host smart-bd6bdf3b-c62e-4585-bb89-c2fcd3e53818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330539592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2330539592
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_genbits.2782549013
Short name T37
Test name
Test status
Simulation time 29811262 ps
CPU time 0.92 seconds
Started May 11 03:25:42 PM PDT 24
Finished May 11 03:25:44 PM PDT 24
Peak memory 205584 kb
Host smart-5e17e63c-8087-4e26-b86a-31498d912783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782549013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2782549013
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.653291111
Short name T303
Test name
Test status
Simulation time 19112390 ps
CPU time 0.96 seconds
Started May 11 03:24:30 PM PDT 24
Finished May 11 03:24:31 PM PDT 24
Peak memory 205300 kb
Host smart-5d2d3242-b73c-4278-bcfc-a4d9f887fd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653291111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.653291111
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2594362298
Short name T95
Test name
Test status
Simulation time 28934300 ps
CPU time 1.12 seconds
Started May 11 03:24:24 PM PDT 24
Finished May 11 03:24:25 PM PDT 24
Peak memory 215232 kb
Host smart-865fa0d3-9c7d-4b6a-9259-7c3d35b4998a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594362298 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2594362298
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3315543616
Short name T280
Test name
Test status
Simulation time 79269691 ps
CPU time 2.36 seconds
Started May 11 03:49:22 PM PDT 24
Finished May 11 03:49:25 PM PDT 24
Peak memory 205728 kb
Host smart-c48730d4-d751-4116-8594-1caf97024e2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315543616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3315543616
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1554839300
Short name T83
Test name
Test status
Simulation time 27068491 ps
CPU time 0.93 seconds
Started May 11 03:24:14 PM PDT 24
Finished May 11 03:24:15 PM PDT 24
Peak memory 205536 kb
Host smart-86e727ab-f2e1-4e4b-b0ca-695f9d63faba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554839300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1554839300
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert.4264619580
Short name T301
Test name
Test status
Simulation time 82448374 ps
CPU time 0.99 seconds
Started May 11 03:24:18 PM PDT 24
Finished May 11 03:24:19 PM PDT 24
Peak memory 205860 kb
Host smart-9269646b-3bbf-4500-b443-88f930d7c73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264619580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.4264619580
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_regwen.345600997
Short name T297
Test name
Test status
Simulation time 11333974 ps
CPU time 0.89 seconds
Started May 11 03:24:12 PM PDT 24
Finished May 11 03:24:13 PM PDT 24
Peak memory 205504 kb
Host smart-72db9734-ee32-4c92-903a-fa140054bf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345600997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.345600997
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.4245697146
Short name T271
Test name
Test status
Simulation time 37137529770 ps
CPU time 412.33 seconds
Started May 11 03:24:13 PM PDT 24
Finished May 11 03:31:06 PM PDT 24
Peak memory 215464 kb
Host smart-401b1380-c754-46c9-bce1-765aa789b66a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245697146 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.4245697146
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_alert.382695642
Short name T100
Test name
Test status
Simulation time 226491994 ps
CPU time 0.93 seconds
Started May 11 03:24:44 PM PDT 24
Finished May 11 03:24:46 PM PDT 24
Peak memory 205668 kb
Host smart-bee11447-a857-4e01-bd33-5aaf560fae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382695642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.382695642
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_genbits.61521000
Short name T289
Test name
Test status
Simulation time 57893813 ps
CPU time 1 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:24:42 PM PDT 24
Peak memory 206060 kb
Host smart-e30ac493-c895-4c8a-ae57-aa9e4fb17368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61521000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.61521000
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_genbits.704027564
Short name T616
Test name
Test status
Simulation time 292998893 ps
CPU time 1.15 seconds
Started May 11 03:24:47 PM PDT 24
Finished May 11 03:24:49 PM PDT 24
Peak memory 205756 kb
Host smart-ccfd0b24-7ae9-4d39-96f3-67f70e45aac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704027564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.704027564
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2379776968
Short name T599
Test name
Test status
Simulation time 228296747141 ps
CPU time 1474.85 seconds
Started May 11 03:24:56 PM PDT 24
Finished May 11 03:49:31 PM PDT 24
Peak memory 221564 kb
Host smart-63f082e8-cae8-4ab8-ab58-169021e9dd84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379776968 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2379776968
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_genbits.2805639992
Short name T290
Test name
Test status
Simulation time 23539962 ps
CPU time 0.91 seconds
Started May 11 03:25:08 PM PDT 24
Finished May 11 03:25:09 PM PDT 24
Peak memory 205564 kb
Host smart-81fc8f47-f041-4793-9fb1-12cc6a176b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805639992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2805639992
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_genbits.3519381834
Short name T702
Test name
Test status
Simulation time 38688723 ps
CPU time 1.02 seconds
Started May 11 03:25:09 PM PDT 24
Finished May 11 03:25:11 PM PDT 24
Peak memory 205596 kb
Host smart-32055a17-1cf2-4d3d-adb3-d72e5ac2af83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519381834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3519381834
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_err.3068025421
Short name T134
Test name
Test status
Simulation time 46414029 ps
CPU time 0.97 seconds
Started May 11 03:26:01 PM PDT 24
Finished May 11 03:26:03 PM PDT 24
Peak memory 215312 kb
Host smart-bd186569-9385-4d8f-b765-4794935a72c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068025421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3068025421
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1642827254
Short name T79
Test name
Test status
Simulation time 33997309 ps
CPU time 1.08 seconds
Started May 11 03:24:34 PM PDT 24
Finished May 11 03:24:36 PM PDT 24
Peak memory 206204 kb
Host smart-77c3d6da-d6e5-43d2-8b84-63c01a934e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642827254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1642827254
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3169156078
Short name T214
Test name
Test status
Simulation time 22190634 ps
CPU time 1.11 seconds
Started May 11 03:49:49 PM PDT 24
Finished May 11 03:49:50 PM PDT 24
Peak memory 205724 kb
Host smart-e1759154-8351-41c2-9a90-4b0191cb2ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169156078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3169156078
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/39.edn_intr.1368392891
Short name T136
Test name
Test status
Simulation time 24500638 ps
CPU time 0.96 seconds
Started May 11 03:25:46 PM PDT 24
Finished May 11 03:25:48 PM PDT 24
Peak memory 226244 kb
Host smart-b87faed0-7a27-437f-8f10-e03b3508aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368392891 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1368392891
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/23.edn_intr.736783948
Short name T521
Test name
Test status
Simulation time 94479513 ps
CPU time 0.77 seconds
Started May 11 03:25:09 PM PDT 24
Finished May 11 03:25:10 PM PDT 24
Peak memory 215052 kb
Host smart-a62e2e3d-d4cf-4247-9b70-dd976942a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736783948 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.736783948
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.571156120
Short name T117
Test name
Test status
Simulation time 45077876 ps
CPU time 0.98 seconds
Started May 11 03:24:56 PM PDT 24
Finished May 11 03:24:58 PM PDT 24
Peak memory 215160 kb
Host smart-814b144c-8076-441d-b2ef-3983d9ac9211
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571156120 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.571156120
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_genbits.37898870
Short name T133
Test name
Test status
Simulation time 394227601 ps
CPU time 1.49 seconds
Started May 11 03:24:57 PM PDT 24
Finished May 11 03:24:58 PM PDT 24
Peak memory 205940 kb
Host smart-3436346e-c09f-489b-af7f-c222f9f86171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37898870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.37898870
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1277867327
Short name T354
Test name
Test status
Simulation time 25856285 ps
CPU time 1.11 seconds
Started May 11 03:49:24 PM PDT 24
Finished May 11 03:49:26 PM PDT 24
Peak memory 205808 kb
Host smart-411b6b70-b4ba-4e64-93b0-1fb6a8d2d835
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277867327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1277867327
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2628341416
Short name T382
Test name
Test status
Simulation time 689199947 ps
CPU time 5.14 seconds
Started May 11 03:49:23 PM PDT 24
Finished May 11 03:49:29 PM PDT 24
Peak memory 205856 kb
Host smart-aeef69bd-f1a5-42a8-95d9-170aa36773ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628341416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2628341416
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3620404744
Short name T227
Test name
Test status
Simulation time 15760196 ps
CPU time 0.95 seconds
Started May 11 03:49:23 PM PDT 24
Finished May 11 03:49:25 PM PDT 24
Peak memory 205696 kb
Host smart-3893d6df-4a05-4349-8199-0fa2634a5922
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620404744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3620404744
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3959780052
Short name T379
Test name
Test status
Simulation time 84307922 ps
CPU time 1.33 seconds
Started May 11 03:49:23 PM PDT 24
Finished May 11 03:49:25 PM PDT 24
Peak memory 214068 kb
Host smart-932a8b39-16d4-44d6-9f63-d89891e2db8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959780052 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3959780052
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.691441191
Short name T390
Test name
Test status
Simulation time 40476964 ps
CPU time 0.84 seconds
Started May 11 03:49:23 PM PDT 24
Finished May 11 03:49:24 PM PDT 24
Peak memory 205576 kb
Host smart-4d64b5fc-ef92-48ab-91de-95af119531ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691441191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.691441191
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1734576560
Short name T334
Test name
Test status
Simulation time 26362305 ps
CPU time 0.87 seconds
Started May 11 03:49:21 PM PDT 24
Finished May 11 03:49:22 PM PDT 24
Peak memory 205600 kb
Host smart-94be3c21-ca96-4174-8f40-7f233823b8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734576560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1734576560
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1290505630
Short name T454
Test name
Test status
Simulation time 67718891 ps
CPU time 1.46 seconds
Started May 11 03:49:23 PM PDT 24
Finished May 11 03:49:24 PM PDT 24
Peak memory 205796 kb
Host smart-26302624-d7e6-49c3-b2cb-773a74ce39c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290505630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1290505630
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3032307153
Short name T421
Test name
Test status
Simulation time 249409208 ps
CPU time 2.71 seconds
Started May 11 03:49:23 PM PDT 24
Finished May 11 03:49:27 PM PDT 24
Peak memory 214084 kb
Host smart-7b9521ba-8d1b-4332-8b6e-b4bc883db205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032307153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3032307153
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3618332036
Short name T224
Test name
Test status
Simulation time 35276758 ps
CPU time 1.05 seconds
Started May 11 03:49:24 PM PDT 24
Finished May 11 03:49:26 PM PDT 24
Peak memory 205784 kb
Host smart-e67b1f6b-407f-4587-a7b5-f65dbf0175f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618332036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3618332036
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2500591455
Short name T357
Test name
Test status
Simulation time 57146352 ps
CPU time 3.15 seconds
Started May 11 03:49:24 PM PDT 24
Finished May 11 03:49:28 PM PDT 24
Peak memory 205844 kb
Host smart-84d41f9e-110c-4f38-8068-bc126dea5f97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500591455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2500591455
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2418861725
Short name T397
Test name
Test status
Simulation time 56934269 ps
CPU time 0.89 seconds
Started May 11 03:49:25 PM PDT 24
Finished May 11 03:49:26 PM PDT 24
Peak memory 205752 kb
Host smart-cb7ce549-eff5-444a-8c63-19aefc80d73d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418861725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2418861725
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.870072180
Short name T438
Test name
Test status
Simulation time 14448494 ps
CPU time 0.93 seconds
Started May 11 03:49:28 PM PDT 24
Finished May 11 03:49:29 PM PDT 24
Peak memory 205748 kb
Host smart-2766e016-1201-4b60-a80c-a05de0863251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870072180 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.870072180
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1274162052
Short name T433
Test name
Test status
Simulation time 15136596 ps
CPU time 0.91 seconds
Started May 11 03:49:23 PM PDT 24
Finished May 11 03:49:24 PM PDT 24
Peak memory 205680 kb
Host smart-19281998-57ce-40f4-b1a9-1a1a23fd0c10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274162052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1274162052
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.722598306
Short name T447
Test name
Test status
Simulation time 13970257 ps
CPU time 0.85 seconds
Started May 11 03:49:23 PM PDT 24
Finished May 11 03:49:24 PM PDT 24
Peak memory 205624 kb
Host smart-2ed0ecc6-4f76-4520-ade1-b74437acb28f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722598306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.722598306
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1839744702
Short name T166
Test name
Test status
Simulation time 38448031 ps
CPU time 1.14 seconds
Started May 11 03:49:24 PM PDT 24
Finished May 11 03:49:26 PM PDT 24
Peak memory 205744 kb
Host smart-d12a4ec5-cf1a-428e-9587-a33fa1dc052f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839744702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1839744702
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.896382319
Short name T165
Test name
Test status
Simulation time 116304914 ps
CPU time 3.63 seconds
Started May 11 03:49:25 PM PDT 24
Finished May 11 03:49:29 PM PDT 24
Peak memory 214040 kb
Host smart-5781369d-503f-4ca6-85bd-ca692e45cb55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896382319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.896382319
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.349405648
Short name T418
Test name
Test status
Simulation time 50655090 ps
CPU time 1.57 seconds
Started May 11 03:49:22 PM PDT 24
Finished May 11 03:49:24 PM PDT 24
Peak memory 205688 kb
Host smart-2567e7eb-8756-48fd-95aa-68ec553a53df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349405648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.349405648
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1227732599
Short name T374
Test name
Test status
Simulation time 25279660 ps
CPU time 1.28 seconds
Started May 11 03:49:43 PM PDT 24
Finished May 11 03:49:45 PM PDT 24
Peak memory 214252 kb
Host smart-7ad4118c-fde5-41ab-acad-203db1e93ff1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227732599 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1227732599
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.924855062
Short name T416
Test name
Test status
Simulation time 15023024 ps
CPU time 0.81 seconds
Started May 11 03:49:44 PM PDT 24
Finished May 11 03:49:46 PM PDT 24
Peak memory 205692 kb
Host smart-be1d7cbf-94e8-4cbc-bf09-c0bd1e3bd0a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924855062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.924855062
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1215176237
Short name T430
Test name
Test status
Simulation time 19530439 ps
CPU time 0.86 seconds
Started May 11 03:49:47 PM PDT 24
Finished May 11 03:49:48 PM PDT 24
Peak memory 205548 kb
Host smart-d47e3127-477c-44c5-b4f2-75cf0115d25d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215176237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1215176237
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3388645820
Short name T389
Test name
Test status
Simulation time 59757628 ps
CPU time 1.3 seconds
Started May 11 03:49:44 PM PDT 24
Finished May 11 03:49:46 PM PDT 24
Peak memory 205800 kb
Host smart-f2b0fa13-b810-46fe-9249-dbf8d780ec23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388645820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3388645820
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1444193435
Short name T394
Test name
Test status
Simulation time 328585407 ps
CPU time 3.29 seconds
Started May 11 03:49:42 PM PDT 24
Finished May 11 03:49:46 PM PDT 24
Peak memory 213924 kb
Host smart-a0642f0c-a23a-4a19-8cae-04697d1f4b79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444193435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1444193435
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.723245216
Short name T281
Test name
Test status
Simulation time 2144887884 ps
CPU time 5.58 seconds
Started May 11 03:49:45 PM PDT 24
Finished May 11 03:49:51 PM PDT 24
Peak memory 205784 kb
Host smart-ee2d458b-0297-4123-9eb6-607cc334fdba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723245216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.723245216
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2782677727
Short name T428
Test name
Test status
Simulation time 46851248 ps
CPU time 0.95 seconds
Started May 11 03:49:50 PM PDT 24
Finished May 11 03:49:52 PM PDT 24
Peak memory 205692 kb
Host smart-4cf8cc7e-ebac-4d5b-aa77-3a6a307ea63d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782677727 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2782677727
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2338327555
Short name T223
Test name
Test status
Simulation time 27135667 ps
CPU time 0.91 seconds
Started May 11 03:49:43 PM PDT 24
Finished May 11 03:49:44 PM PDT 24
Peak memory 205652 kb
Host smart-73a36f36-82ea-40d8-92af-7588ba210549
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338327555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2338327555
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2057355117
Short name T426
Test name
Test status
Simulation time 12681521 ps
CPU time 0.86 seconds
Started May 11 03:49:41 PM PDT 24
Finished May 11 03:49:43 PM PDT 24
Peak memory 205648 kb
Host smart-e6a25d12-f521-4186-a4e4-62f78b70efde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057355117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2057355117
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2303462332
Short name T410
Test name
Test status
Simulation time 67868491 ps
CPU time 1.08 seconds
Started May 11 03:49:50 PM PDT 24
Finished May 11 03:49:51 PM PDT 24
Peak memory 205804 kb
Host smart-da963ee3-9278-4a11-983c-7093c3ad2f82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303462332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2303462332
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.4025983803
Short name T431
Test name
Test status
Simulation time 96869829 ps
CPU time 1.91 seconds
Started May 11 03:49:46 PM PDT 24
Finished May 11 03:49:48 PM PDT 24
Peak memory 214028 kb
Host smart-18d77b21-df67-407a-8ff9-411bb38f2cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025983803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.4025983803
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1412112721
Short name T279
Test name
Test status
Simulation time 85480135 ps
CPU time 1.63 seconds
Started May 11 03:49:45 PM PDT 24
Finished May 11 03:49:47 PM PDT 24
Peak memory 205756 kb
Host smart-070d3caa-0b10-4ca4-97bd-86d5ea9a76f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412112721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1412112721
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.71888050
Short name T398
Test name
Test status
Simulation time 20476392 ps
CPU time 1.39 seconds
Started May 11 03:49:51 PM PDT 24
Finished May 11 03:49:52 PM PDT 24
Peak memory 214116 kb
Host smart-d74d2810-fad3-40cd-924e-94381db98b35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71888050 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.71888050
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1843838302
Short name T370
Test name
Test status
Simulation time 16833816 ps
CPU time 0.95 seconds
Started May 11 03:49:49 PM PDT 24
Finished May 11 03:49:50 PM PDT 24
Peak memory 205672 kb
Host smart-1a1c1a88-99b1-4bd1-baed-5bf7e96653ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843838302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1843838302
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3828295510
Short name T355
Test name
Test status
Simulation time 13993038 ps
CPU time 0.84 seconds
Started May 11 03:49:49 PM PDT 24
Finished May 11 03:49:51 PM PDT 24
Peak memory 205640 kb
Host smart-313fbdc2-a3b4-43ce-a36a-0cf495ee8921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828295510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3828295510
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3242949853
Short name T375
Test name
Test status
Simulation time 14562282 ps
CPU time 0.98 seconds
Started May 11 03:49:53 PM PDT 24
Finished May 11 03:49:55 PM PDT 24
Peak memory 205776 kb
Host smart-2c8da080-9916-437d-b7bd-eafa74518d24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242949853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3242949853
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1731615116
Short name T446
Test name
Test status
Simulation time 96346288 ps
CPU time 1.69 seconds
Started May 11 03:49:49 PM PDT 24
Finished May 11 03:49:51 PM PDT 24
Peak memory 216120 kb
Host smart-7ff4bae2-b201-4ef8-8cc4-6f4b90aab4ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731615116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1731615116
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.604422608
Short name T237
Test name
Test status
Simulation time 125274196 ps
CPU time 1.36 seconds
Started May 11 03:49:54 PM PDT 24
Finished May 11 03:49:55 PM PDT 24
Peak memory 205784 kb
Host smart-8c888ae1-f686-4439-b6f6-36830d688a00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604422608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.604422608
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2963150002
Short name T385
Test name
Test status
Simulation time 53780437 ps
CPU time 1.1 seconds
Started May 11 03:49:50 PM PDT 24
Finished May 11 03:49:52 PM PDT 24
Peak memory 214048 kb
Host smart-f50769a5-693a-43c6-836a-043d103e99f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963150002 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2963150002
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1715438308
Short name T222
Test name
Test status
Simulation time 34385599 ps
CPU time 0.81 seconds
Started May 11 03:49:50 PM PDT 24
Finished May 11 03:49:51 PM PDT 24
Peak memory 205764 kb
Host smart-85ca7ddd-bac7-46a1-9f3b-699d492c1135
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715438308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1715438308
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1030987082
Short name T456
Test name
Test status
Simulation time 12464969 ps
CPU time 0.83 seconds
Started May 11 03:49:49 PM PDT 24
Finished May 11 03:49:50 PM PDT 24
Peak memory 205632 kb
Host smart-27ee7689-f738-48e3-811e-19cf247cb94f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030987082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1030987082
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3493591255
Short name T168
Test name
Test status
Simulation time 23575889 ps
CPU time 1.1 seconds
Started May 11 03:49:51 PM PDT 24
Finished May 11 03:49:52 PM PDT 24
Peak memory 205800 kb
Host smart-c1059967-3fce-458c-a907-1ba163e861f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493591255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3493591255
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4283425317
Short name T406
Test name
Test status
Simulation time 264776297 ps
CPU time 2.51 seconds
Started May 11 03:49:49 PM PDT 24
Finished May 11 03:49:52 PM PDT 24
Peak memory 214076 kb
Host smart-a86dd9c0-e49c-4dc9-afdf-dbca4b635144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283425317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4283425317
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1182773379
Short name T376
Test name
Test status
Simulation time 187629874 ps
CPU time 3.82 seconds
Started May 11 03:49:49 PM PDT 24
Finished May 11 03:49:54 PM PDT 24
Peak memory 205952 kb
Host smart-4434ca79-2695-41b6-973a-01fe27787177
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182773379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1182773379
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2454111535
Short name T450
Test name
Test status
Simulation time 332975640 ps
CPU time 1.14 seconds
Started May 11 03:49:49 PM PDT 24
Finished May 11 03:49:50 PM PDT 24
Peak memory 214052 kb
Host smart-77e53d76-1006-48a3-892b-858d5cfccfc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454111535 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2454111535
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1889095011
Short name T234
Test name
Test status
Simulation time 20780278 ps
CPU time 0.91 seconds
Started May 11 03:49:50 PM PDT 24
Finished May 11 03:49:51 PM PDT 24
Peak memory 205692 kb
Host smart-8d042553-f39e-48d1-bf04-50ad73ef1c9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889095011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1889095011
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.505105471
Short name T407
Test name
Test status
Simulation time 92358339 ps
CPU time 0.78 seconds
Started May 11 03:49:47 PM PDT 24
Finished May 11 03:49:48 PM PDT 24
Peak memory 205464 kb
Host smart-8c7f2864-035f-4c45-9ccb-477639fe884c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505105471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.505105471
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.520464344
Short name T435
Test name
Test status
Simulation time 148144325 ps
CPU time 2.57 seconds
Started May 11 03:49:48 PM PDT 24
Finished May 11 03:49:51 PM PDT 24
Peak memory 214044 kb
Host smart-85afe110-ccab-44dc-9125-2c53897f6aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520464344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.520464344
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.4118334755
Short name T268
Test name
Test status
Simulation time 111041584 ps
CPU time 2.12 seconds
Started May 11 03:49:54 PM PDT 24
Finished May 11 03:49:56 PM PDT 24
Peak memory 205784 kb
Host smart-3bd939f8-767e-4b3c-818d-b66f07ddecbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118334755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.4118334755
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.509683929
Short name T367
Test name
Test status
Simulation time 34039602 ps
CPU time 1.08 seconds
Started May 11 03:50:00 PM PDT 24
Finished May 11 03:50:02 PM PDT 24
Peak memory 205788 kb
Host smart-f2b0b033-b411-47c4-b909-b445578c78e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509683929 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.509683929
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2172299105
Short name T422
Test name
Test status
Simulation time 36217037 ps
CPU time 0.77 seconds
Started May 11 03:49:53 PM PDT 24
Finished May 11 03:49:55 PM PDT 24
Peak memory 205428 kb
Host smart-06615694-98ec-42f8-bdd7-8a10498e49e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172299105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2172299105
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1680190514
Short name T442
Test name
Test status
Simulation time 34618266 ps
CPU time 0.81 seconds
Started May 11 03:49:54 PM PDT 24
Finished May 11 03:49:56 PM PDT 24
Peak memory 205464 kb
Host smart-fc22d0cb-063f-49a2-b9b0-d5a15b2d3df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680190514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1680190514
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2438028337
Short name T239
Test name
Test status
Simulation time 14743437 ps
CPU time 1 seconds
Started May 11 03:50:01 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205792 kb
Host smart-d78f955e-52d0-4059-ac07-7ed934ab43a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438028337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2438028337
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3973729237
Short name T387
Test name
Test status
Simulation time 71601454 ps
CPU time 1.77 seconds
Started May 11 03:49:54 PM PDT 24
Finished May 11 03:49:56 PM PDT 24
Peak memory 213936 kb
Host smart-ffb44c84-b17d-487f-a17c-c31c582210c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973729237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3973729237
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1370882524
Short name T448
Test name
Test status
Simulation time 279294889 ps
CPU time 1.73 seconds
Started May 11 03:50:00 PM PDT 24
Finished May 11 03:50:02 PM PDT 24
Peak memory 205644 kb
Host smart-f4b0c091-3838-443d-991d-42022adb3080
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370882524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1370882524
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.483268772
Short name T437
Test name
Test status
Simulation time 13889137 ps
CPU time 0.93 seconds
Started May 11 03:49:52 PM PDT 24
Finished May 11 03:49:53 PM PDT 24
Peak memory 205760 kb
Host smart-0033c17a-a61b-4106-90f1-a80886e78ad9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483268772 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.483268772
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2213895191
Short name T405
Test name
Test status
Simulation time 21710861 ps
CPU time 0.91 seconds
Started May 11 03:49:55 PM PDT 24
Finished May 11 03:49:57 PM PDT 24
Peak memory 205744 kb
Host smart-654a5204-269e-4280-8796-d51b477665a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213895191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2213895191
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2060549603
Short name T359
Test name
Test status
Simulation time 47019442 ps
CPU time 0.84 seconds
Started May 11 03:49:59 PM PDT 24
Finished May 11 03:50:00 PM PDT 24
Peak memory 205600 kb
Host smart-9d454817-72b5-47f0-9819-d4abd4b66736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060549603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2060549603
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1119490056
Short name T167
Test name
Test status
Simulation time 36412182 ps
CPU time 1.48 seconds
Started May 11 03:49:56 PM PDT 24
Finished May 11 03:49:58 PM PDT 24
Peak memory 205744 kb
Host smart-439ce2ee-ecd2-4f48-bb80-67ccccad05a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119490056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1119490056
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.806233563
Short name T341
Test name
Test status
Simulation time 49897704 ps
CPU time 2.84 seconds
Started May 11 03:49:55 PM PDT 24
Finished May 11 03:49:59 PM PDT 24
Peak memory 214076 kb
Host smart-e6f40549-5fb9-4c12-9466-13882ac95fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806233563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.806233563
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1807742164
Short name T373
Test name
Test status
Simulation time 149449629 ps
CPU time 2.15 seconds
Started May 11 03:49:55 PM PDT 24
Finished May 11 03:49:58 PM PDT 24
Peak memory 205792 kb
Host smart-a4a337ce-e4c1-4ef5-8f16-cda5650eefe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807742164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1807742164
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2347469060
Short name T350
Test name
Test status
Simulation time 235645184 ps
CPU time 1.36 seconds
Started May 11 03:49:54 PM PDT 24
Finished May 11 03:49:56 PM PDT 24
Peak memory 217616 kb
Host smart-75d66312-a5ea-4d00-836f-134b6c0eb6b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347469060 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2347469060
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.69732923
Short name T401
Test name
Test status
Simulation time 14597544 ps
CPU time 0.89 seconds
Started May 11 03:51:03 PM PDT 24
Finished May 11 03:51:05 PM PDT 24
Peak memory 204228 kb
Host smart-a913222e-af73-4547-a2bf-5f9ad06447d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69732923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.69732923
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3735255727
Short name T380
Test name
Test status
Simulation time 273792374 ps
CPU time 1.17 seconds
Started May 11 03:50:00 PM PDT 24
Finished May 11 03:50:01 PM PDT 24
Peak memory 205800 kb
Host smart-ea417e7a-6550-43e7-946d-b79051fad3e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735255727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3735255727
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.229564205
Short name T445
Test name
Test status
Simulation time 102160710 ps
CPU time 2.15 seconds
Started May 11 03:49:54 PM PDT 24
Finished May 11 03:49:57 PM PDT 24
Peak memory 214020 kb
Host smart-7393cea7-1e2b-4981-8473-7318682141f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229564205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.229564205
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2215055078
Short name T378
Test name
Test status
Simulation time 111602020 ps
CPU time 2.39 seconds
Started May 11 03:49:54 PM PDT 24
Finished May 11 03:49:57 PM PDT 24
Peak memory 205764 kb
Host smart-4bc3e436-f719-425d-b216-99890c6189c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215055078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2215055078
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4185236319
Short name T451
Test name
Test status
Simulation time 19590109 ps
CPU time 1.11 seconds
Started May 11 03:49:55 PM PDT 24
Finished May 11 03:49:56 PM PDT 24
Peak memory 213996 kb
Host smart-35db42fc-e2fe-4a67-95fe-7124c4cfb9cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185236319 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.4185236319
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3096177435
Short name T420
Test name
Test status
Simulation time 16525677 ps
CPU time 0.8 seconds
Started May 11 03:49:56 PM PDT 24
Finished May 11 03:49:57 PM PDT 24
Peak memory 205528 kb
Host smart-a5b7a48d-b93f-4594-bee8-cf925c0e5aeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096177435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3096177435
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4234662125
Short name T419
Test name
Test status
Simulation time 14440851 ps
CPU time 0.88 seconds
Started May 11 03:49:55 PM PDT 24
Finished May 11 03:49:57 PM PDT 24
Peak memory 205608 kb
Host smart-af2de66e-11b6-4a00-92e0-15ca20ba6e0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234662125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4234662125
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.981738094
Short name T161
Test name
Test status
Simulation time 26189948 ps
CPU time 1.14 seconds
Started May 11 03:49:56 PM PDT 24
Finished May 11 03:49:57 PM PDT 24
Peak memory 205844 kb
Host smart-1021fda7-19e6-4477-a8f0-956d2a33814c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981738094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.981738094
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.35682119
Short name T344
Test name
Test status
Simulation time 106196317 ps
CPU time 2.04 seconds
Started May 11 03:49:55 PM PDT 24
Finished May 11 03:49:58 PM PDT 24
Peak memory 213992 kb
Host smart-2e6c4cc1-1ff5-4b2b-b68d-6d24d1eb0ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35682119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.35682119
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3482475882
Short name T424
Test name
Test status
Simulation time 68979090 ps
CPU time 1.13 seconds
Started May 11 03:49:54 PM PDT 24
Finished May 11 03:49:56 PM PDT 24
Peak memory 214096 kb
Host smart-b959c748-b4d8-4c95-af7f-87bc2bb8431f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482475882 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3482475882
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.235514627
Short name T229
Test name
Test status
Simulation time 29965142 ps
CPU time 0.96 seconds
Started May 11 03:49:56 PM PDT 24
Finished May 11 03:49:58 PM PDT 24
Peak memory 205788 kb
Host smart-a6302125-43c6-4bf6-b3de-24cf85c561fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235514627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.235514627
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2489243721
Short name T235
Test name
Test status
Simulation time 11986618 ps
CPU time 0.87 seconds
Started May 11 03:49:59 PM PDT 24
Finished May 11 03:50:00 PM PDT 24
Peak memory 205656 kb
Host smart-0d44a9e2-8747-4f99-9cea-dd98ab7efce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489243721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2489243721
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1898285815
Short name T402
Test name
Test status
Simulation time 72638077 ps
CPU time 1.4 seconds
Started May 11 03:49:56 PM PDT 24
Finished May 11 03:49:58 PM PDT 24
Peak memory 205784 kb
Host smart-d8cf8506-b152-4404-887d-3107f1bb9b30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898285815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1898285815
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1346987281
Short name T455
Test name
Test status
Simulation time 84000524 ps
CPU time 2.86 seconds
Started May 11 03:51:03 PM PDT 24
Finished May 11 03:51:07 PM PDT 24
Peak memory 215900 kb
Host smart-079e7b6a-a82e-4bd5-b84c-03b1dbd35354
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346987281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1346987281
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3680309329
Short name T452
Test name
Test status
Simulation time 428911170 ps
CPU time 1.56 seconds
Started May 11 03:49:59 PM PDT 24
Finished May 11 03:50:01 PM PDT 24
Peak memory 205724 kb
Host smart-11d79689-b1ff-4d84-a956-a6fd2bf4b512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680309329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3680309329
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.527904221
Short name T228
Test name
Test status
Simulation time 44123450 ps
CPU time 1.6 seconds
Started May 11 03:49:29 PM PDT 24
Finished May 11 03:49:31 PM PDT 24
Peak memory 205780 kb
Host smart-512a059b-1426-4d30-8d32-56cede063dd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527904221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.527904221
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1447093996
Short name T365
Test name
Test status
Simulation time 98149496 ps
CPU time 3 seconds
Started May 11 03:49:29 PM PDT 24
Finished May 11 03:49:32 PM PDT 24
Peak memory 205736 kb
Host smart-bb640147-03d5-4175-bb70-32c182147863
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447093996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1447093996
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1038274606
Short name T347
Test name
Test status
Simulation time 80379037 ps
CPU time 0.89 seconds
Started May 11 03:49:29 PM PDT 24
Finished May 11 03:49:30 PM PDT 24
Peak memory 205732 kb
Host smart-e4bd7673-ff42-4172-8602-af4a49b7ee7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038274606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1038274606
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.902013251
Short name T383
Test name
Test status
Simulation time 37725168 ps
CPU time 1.13 seconds
Started May 11 03:49:26 PM PDT 24
Finished May 11 03:49:28 PM PDT 24
Peak memory 213968 kb
Host smart-765a1285-2de1-480d-a123-0457f3f29e5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902013251 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.902013251
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.656025451
Short name T396
Test name
Test status
Simulation time 101758600 ps
CPU time 0.77 seconds
Started May 11 03:49:28 PM PDT 24
Finished May 11 03:49:29 PM PDT 24
Peak memory 205544 kb
Host smart-244f17c3-1314-4a5d-85fa-fb43b66eb6f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656025451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.656025451
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2834614248
Short name T400
Test name
Test status
Simulation time 123121169 ps
CPU time 0.87 seconds
Started May 11 03:49:27 PM PDT 24
Finished May 11 03:49:28 PM PDT 24
Peak memory 205600 kb
Host smart-dd340230-6ecd-4a0d-80ac-2bf430af5d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834614248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2834614248
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.368015736
Short name T240
Test name
Test status
Simulation time 27501726 ps
CPU time 0.94 seconds
Started May 11 03:49:27 PM PDT 24
Finished May 11 03:49:28 PM PDT 24
Peak memory 205764 kb
Host smart-760e653b-afa5-4ec6-b903-7c59d8913fa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368015736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.368015736
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1463929003
Short name T362
Test name
Test status
Simulation time 55636585 ps
CPU time 2.28 seconds
Started May 11 03:49:27 PM PDT 24
Finished May 11 03:49:29 PM PDT 24
Peak memory 213988 kb
Host smart-cce37bc8-db6a-425d-bc3b-31ac8cd36048
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463929003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1463929003
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.281379085
Short name T349
Test name
Test status
Simulation time 88364330 ps
CPU time 2.21 seconds
Started May 11 03:49:28 PM PDT 24
Finished May 11 03:49:30 PM PDT 24
Peak memory 205812 kb
Host smart-ea52d545-c39a-46c1-87d7-ee8e18059a74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281379085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.281379085
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3185070236
Short name T372
Test name
Test status
Simulation time 43408198 ps
CPU time 0.84 seconds
Started May 11 03:49:53 PM PDT 24
Finished May 11 03:49:55 PM PDT 24
Peak memory 205400 kb
Host smart-7152c03c-2f5a-4491-93c3-222b09fee563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185070236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3185070236
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2645771205
Short name T432
Test name
Test status
Simulation time 36851863 ps
CPU time 0.8 seconds
Started May 11 03:49:58 PM PDT 24
Finished May 11 03:50:00 PM PDT 24
Peak memory 205496 kb
Host smart-3a0f7143-acb7-4427-bb39-502c9587fb29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645771205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2645771205
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1739879232
Short name T386
Test name
Test status
Simulation time 45250423 ps
CPU time 0.84 seconds
Started May 11 03:49:59 PM PDT 24
Finished May 11 03:50:00 PM PDT 24
Peak memory 205612 kb
Host smart-12443c9f-84e0-4579-b1d1-1bc89a1e75b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739879232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1739879232
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1360070035
Short name T351
Test name
Test status
Simulation time 11471991 ps
CPU time 0.83 seconds
Started May 11 03:49:55 PM PDT 24
Finished May 11 03:49:56 PM PDT 24
Peak memory 205580 kb
Host smart-ba0274d6-fce8-4def-b7be-2029ba5de365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360070035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1360070035
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1299289913
Short name T412
Test name
Test status
Simulation time 23912526 ps
CPU time 0.84 seconds
Started May 11 03:49:54 PM PDT 24
Finished May 11 03:49:55 PM PDT 24
Peak memory 205732 kb
Host smart-19c975ee-5752-45ed-9309-0bffde0ca576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299289913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1299289913
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.875667219
Short name T345
Test name
Test status
Simulation time 24464361 ps
CPU time 0.86 seconds
Started May 11 03:50:02 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205612 kb
Host smart-786456e1-4b1e-4be0-ba30-825786150f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875667219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.875667219
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2667191318
Short name T411
Test name
Test status
Simulation time 22645694 ps
CPU time 0.85 seconds
Started May 11 03:50:01 PM PDT 24
Finished May 11 03:50:02 PM PDT 24
Peak memory 205620 kb
Host smart-3c236e27-cf9d-4079-a045-f68b5396ef16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667191318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2667191318
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3749477656
Short name T346
Test name
Test status
Simulation time 39161740 ps
CPU time 0.85 seconds
Started May 11 03:50:04 PM PDT 24
Finished May 11 03:50:05 PM PDT 24
Peak memory 205600 kb
Host smart-ddaa74af-01d6-451c-9d46-8bf934cdedbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749477656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3749477656
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.284234738
Short name T338
Test name
Test status
Simulation time 17272513 ps
CPU time 0.92 seconds
Started May 11 03:50:02 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205612 kb
Host smart-38588eed-7d8e-4d43-9aca-d0ef18ed1b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284234738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.284234738
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3800624235
Short name T360
Test name
Test status
Simulation time 27408693 ps
CPU time 0.87 seconds
Started May 11 03:50:03 PM PDT 24
Finished May 11 03:50:04 PM PDT 24
Peak memory 205608 kb
Host smart-0e10b675-af24-47db-9ab3-823fbe39dece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800624235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3800624235
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.23861388
Short name T225
Test name
Test status
Simulation time 38806800 ps
CPU time 1.13 seconds
Started May 11 03:49:28 PM PDT 24
Finished May 11 03:49:30 PM PDT 24
Peak memory 205740 kb
Host smart-54905a7e-3b57-4929-997e-59cdad731800
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23861388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.23861388
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3769482445
Short name T230
Test name
Test status
Simulation time 1399385707 ps
CPU time 6.95 seconds
Started May 11 03:49:28 PM PDT 24
Finished May 11 03:49:36 PM PDT 24
Peak memory 205816 kb
Host smart-cf194730-b0a3-4664-b4a3-c937dcd69c5a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769482445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3769482445
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.4234139664
Short name T358
Test name
Test status
Simulation time 45802514 ps
CPU time 0.9 seconds
Started May 11 03:49:31 PM PDT 24
Finished May 11 03:49:32 PM PDT 24
Peak memory 205760 kb
Host smart-f0e6fcd3-7595-47ba-8ac5-6dd6699c1417
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234139664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.4234139664
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1697539817
Short name T371
Test name
Test status
Simulation time 43297497 ps
CPU time 1.15 seconds
Started May 11 03:49:29 PM PDT 24
Finished May 11 03:49:31 PM PDT 24
Peak memory 214008 kb
Host smart-f5f58877-696a-4ce3-acbe-8b1aaadf611b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697539817 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1697539817
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3203143798
Short name T413
Test name
Test status
Simulation time 13200435 ps
CPU time 0.86 seconds
Started May 11 03:49:28 PM PDT 24
Finished May 11 03:49:29 PM PDT 24
Peak memory 205748 kb
Host smart-ac1131fa-7fef-429a-a30c-4e1b87df092a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203143798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3203143798
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2552794436
Short name T439
Test name
Test status
Simulation time 33926936 ps
CPU time 0.8 seconds
Started May 11 03:49:29 PM PDT 24
Finished May 11 03:49:30 PM PDT 24
Peak memory 205440 kb
Host smart-c9f0ed42-3faf-440d-abb3-1af1ec0e6367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552794436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2552794436
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2459019858
Short name T409
Test name
Test status
Simulation time 355253121 ps
CPU time 1.22 seconds
Started May 11 03:49:28 PM PDT 24
Finished May 11 03:49:30 PM PDT 24
Peak memory 205784 kb
Host smart-1d759e02-0d95-4a7d-8d7e-0113c3b01415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459019858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2459019858
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2008809151
Short name T384
Test name
Test status
Simulation time 69296418 ps
CPU time 2.23 seconds
Started May 11 03:49:31 PM PDT 24
Finished May 11 03:49:33 PM PDT 24
Peak memory 214032 kb
Host smart-65c0dcc4-77c7-4487-aa13-c5466d2e7f15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008809151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2008809151
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.281731310
Short name T391
Test name
Test status
Simulation time 84541899 ps
CPU time 1.64 seconds
Started May 11 03:49:30 PM PDT 24
Finished May 11 03:49:32 PM PDT 24
Peak memory 205724 kb
Host smart-266a33fd-94ae-4145-9a67-c210e25f04a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281731310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.281731310
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.149225922
Short name T342
Test name
Test status
Simulation time 17536299 ps
CPU time 0.78 seconds
Started May 11 03:50:01 PM PDT 24
Finished May 11 03:50:02 PM PDT 24
Peak memory 205440 kb
Host smart-c62fa0b3-35f0-43ec-b5aa-1ed31209ba65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149225922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.149225922
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2930819113
Short name T381
Test name
Test status
Simulation time 38773689 ps
CPU time 0.85 seconds
Started May 11 03:50:01 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205636 kb
Host smart-5fd3723a-e600-4793-93cc-9bee8e89a0ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930819113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2930819113
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2775954376
Short name T392
Test name
Test status
Simulation time 15144234 ps
CPU time 0.86 seconds
Started May 11 03:50:00 PM PDT 24
Finished May 11 03:50:01 PM PDT 24
Peak memory 205616 kb
Host smart-0873f952-6ef8-47bb-bef4-b32dc3953066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775954376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2775954376
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2752540494
Short name T434
Test name
Test status
Simulation time 13894211 ps
CPU time 0.85 seconds
Started May 11 03:49:59 PM PDT 24
Finished May 11 03:50:01 PM PDT 24
Peak memory 205624 kb
Host smart-3d63225c-3739-4107-9283-6edf4b037f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752540494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2752540494
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1824082927
Short name T217
Test name
Test status
Simulation time 19925060 ps
CPU time 0.87 seconds
Started May 11 03:50:01 PM PDT 24
Finished May 11 03:50:02 PM PDT 24
Peak memory 205644 kb
Host smart-e5cd461e-d9de-4248-be23-203bab43003c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824082927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1824082927
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2053502845
Short name T395
Test name
Test status
Simulation time 45041244 ps
CPU time 0.86 seconds
Started May 11 03:50:01 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205636 kb
Host smart-8cd5487b-30c8-4858-923d-0f081657112a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053502845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2053502845
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3399015819
Short name T427
Test name
Test status
Simulation time 14723871 ps
CPU time 0.92 seconds
Started May 11 03:50:01 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205644 kb
Host smart-7a5b06dc-6aa1-4759-b182-703bb063efa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399015819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3399015819
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1944447604
Short name T361
Test name
Test status
Simulation time 17361595 ps
CPU time 0.81 seconds
Started May 11 03:50:02 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205512 kb
Host smart-b1de4d81-c0c9-4aef-9cff-740e46cc3166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944447604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1944447604
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2416208930
Short name T339
Test name
Test status
Simulation time 42426884 ps
CPU time 0.88 seconds
Started May 11 03:50:03 PM PDT 24
Finished May 11 03:50:04 PM PDT 24
Peak memory 205636 kb
Host smart-3246b82d-d7fc-4f27-82bd-e8f98b7259b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416208930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2416208930
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3916248664
Short name T174
Test name
Test status
Simulation time 113589717 ps
CPU time 0.84 seconds
Started May 11 03:50:04 PM PDT 24
Finished May 11 03:50:05 PM PDT 24
Peak memory 205604 kb
Host smart-f1f75d1a-b825-4e2f-8ef8-0e5861fc2899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916248664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3916248664
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3575660512
Short name T220
Test name
Test status
Simulation time 112100320 ps
CPU time 1.38 seconds
Started May 11 03:49:33 PM PDT 24
Finished May 11 03:49:35 PM PDT 24
Peak memory 205808 kb
Host smart-c80e98c7-9e9d-4ff3-ae14-70013a89d018
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575660512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3575660512
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4246921882
Short name T408
Test name
Test status
Simulation time 132762843 ps
CPU time 2.05 seconds
Started May 11 03:49:33 PM PDT 24
Finished May 11 03:49:35 PM PDT 24
Peak memory 205744 kb
Host smart-86f61bab-ff5c-4153-8015-d3d3627e4e59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246921882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.4246921882
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1099980851
Short name T226
Test name
Test status
Simulation time 13035250 ps
CPU time 0.93 seconds
Started May 11 03:49:33 PM PDT 24
Finished May 11 03:49:34 PM PDT 24
Peak memory 205744 kb
Host smart-3a7b8fed-34a5-4590-adac-4c1dd33a2481
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099980851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1099980851
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3273310185
Short name T436
Test name
Test status
Simulation time 71567906 ps
CPU time 1.36 seconds
Started May 11 03:49:35 PM PDT 24
Finished May 11 03:49:37 PM PDT 24
Peak memory 214100 kb
Host smart-e6ffc981-d885-4ffc-8e1f-bd7fc11b2872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273310185 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3273310185
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3203712826
Short name T232
Test name
Test status
Simulation time 18161267 ps
CPU time 0.99 seconds
Started May 11 03:49:34 PM PDT 24
Finished May 11 03:49:35 PM PDT 24
Peak memory 205764 kb
Host smart-880fb447-fe8f-4396-a7e5-a51e960f62c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203712826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3203712826
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1549772869
Short name T356
Test name
Test status
Simulation time 24566567 ps
CPU time 0.85 seconds
Started May 11 03:49:33 PM PDT 24
Finished May 11 03:49:34 PM PDT 24
Peak memory 205612 kb
Host smart-c176c5f6-9646-42be-b2bd-7a6fbd6e8d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549772869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1549772869
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.536762289
Short name T164
Test name
Test status
Simulation time 22239737 ps
CPU time 1.01 seconds
Started May 11 03:49:33 PM PDT 24
Finished May 11 03:49:34 PM PDT 24
Peak memory 205804 kb
Host smart-1126e26a-249f-4a94-bbb2-f6be165e11e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536762289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.536762289
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3767986534
Short name T423
Test name
Test status
Simulation time 129158727 ps
CPU time 2 seconds
Started May 11 03:49:28 PM PDT 24
Finished May 11 03:49:30 PM PDT 24
Peak memory 214044 kb
Host smart-ce3abfcc-2f60-4e07-b6b6-7137490bf455
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767986534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3767986534
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3193455601
Short name T404
Test name
Test status
Simulation time 335451705 ps
CPU time 2.7 seconds
Started May 11 03:49:35 PM PDT 24
Finished May 11 03:49:38 PM PDT 24
Peak memory 205968 kb
Host smart-7c632e5a-b83a-4b55-aa82-a50e5995a364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193455601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3193455601
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.339368019
Short name T453
Test name
Test status
Simulation time 32176778 ps
CPU time 0.8 seconds
Started May 11 03:50:02 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205464 kb
Host smart-6de8b140-f39d-4bb2-a9ed-9af5ea9499da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339368019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.339368019
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.95475058
Short name T348
Test name
Test status
Simulation time 18647051 ps
CPU time 0.8 seconds
Started May 11 03:49:59 PM PDT 24
Finished May 11 03:50:00 PM PDT 24
Peak memory 205408 kb
Host smart-847ca6a5-ddca-4730-8114-87ca301d9f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95475058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.95475058
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2334962188
Short name T335
Test name
Test status
Simulation time 25285668 ps
CPU time 0.91 seconds
Started May 11 03:50:01 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205580 kb
Host smart-09c6b441-340e-464c-b9d7-5aa0f5477c6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334962188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2334962188
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2205782125
Short name T369
Test name
Test status
Simulation time 22260491 ps
CPU time 0.84 seconds
Started May 11 03:49:59 PM PDT 24
Finished May 11 03:50:00 PM PDT 24
Peak memory 205608 kb
Host smart-22e10fc1-309a-413d-9ab8-8252ba3b4e23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205782125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2205782125
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1368135893
Short name T336
Test name
Test status
Simulation time 48269850 ps
CPU time 0.87 seconds
Started May 11 03:49:58 PM PDT 24
Finished May 11 03:49:59 PM PDT 24
Peak memory 205632 kb
Host smart-71b0db3a-45d2-4ee8-9bb2-55808a5f2e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368135893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1368135893
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1301443505
Short name T364
Test name
Test status
Simulation time 11292973 ps
CPU time 0.83 seconds
Started May 11 03:50:04 PM PDT 24
Finished May 11 03:50:05 PM PDT 24
Peak memory 205600 kb
Host smart-2336fa59-7834-45d6-a817-72da11716e13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301443505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1301443505
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1084826902
Short name T441
Test name
Test status
Simulation time 39034460 ps
CPU time 0.83 seconds
Started May 11 03:50:02 PM PDT 24
Finished May 11 03:50:04 PM PDT 24
Peak memory 205672 kb
Host smart-54af56ec-b865-477b-859f-a01d334297f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084826902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1084826902
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.748159484
Short name T425
Test name
Test status
Simulation time 12547043 ps
CPU time 0.85 seconds
Started May 11 03:50:02 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205624 kb
Host smart-aa41bf16-803d-4868-8637-fa4f4061ba39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748159484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.748159484
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2848368905
Short name T343
Test name
Test status
Simulation time 11912024 ps
CPU time 0.87 seconds
Started May 11 03:50:01 PM PDT 24
Finished May 11 03:50:03 PM PDT 24
Peak memory 205608 kb
Host smart-fce5f008-5740-45d1-9633-eae06154c69d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848368905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2848368905
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3658270469
Short name T444
Test name
Test status
Simulation time 123239315 ps
CPU time 0.78 seconds
Started May 11 03:50:01 PM PDT 24
Finished May 11 03:50:02 PM PDT 24
Peak memory 205460 kb
Host smart-d445595f-d53c-41d2-ac48-61b2aacbed4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658270469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3658270469
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1121524046
Short name T218
Test name
Test status
Simulation time 36376096 ps
CPU time 1.09 seconds
Started May 11 03:49:36 PM PDT 24
Finished May 11 03:49:37 PM PDT 24
Peak memory 205864 kb
Host smart-f90920d8-7d0e-4aff-b0bb-7fc3e815b34c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121524046 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1121524046
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.436818495
Short name T417
Test name
Test status
Simulation time 64524938 ps
CPU time 0.84 seconds
Started May 11 03:49:35 PM PDT 24
Finished May 11 03:49:37 PM PDT 24
Peak memory 205740 kb
Host smart-8f73f795-bc67-4d1d-b7df-9d71db23666b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436818495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.436818495
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2939885601
Short name T340
Test name
Test status
Simulation time 21052826 ps
CPU time 0.81 seconds
Started May 11 03:49:35 PM PDT 24
Finished May 11 03:49:37 PM PDT 24
Peak memory 205612 kb
Host smart-bf27a39c-8c6d-490f-a1fe-c629f2a0b7a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939885601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2939885601
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1173982831
Short name T238
Test name
Test status
Simulation time 60971931 ps
CPU time 0.96 seconds
Started May 11 03:49:34 PM PDT 24
Finished May 11 03:49:35 PM PDT 24
Peak memory 205832 kb
Host smart-9b76e16b-a70c-41d9-8bd3-e526a53863cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173982831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1173982831
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.65369445
Short name T236
Test name
Test status
Simulation time 430336525 ps
CPU time 2.62 seconds
Started May 11 03:49:32 PM PDT 24
Finished May 11 03:49:35 PM PDT 24
Peak memory 214024 kb
Host smart-26dfa956-a1b7-4d79-8838-20a2ca4537c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65369445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.65369445
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1384780148
Short name T414
Test name
Test status
Simulation time 76207476 ps
CPU time 2.37 seconds
Started May 11 03:49:36 PM PDT 24
Finished May 11 03:49:39 PM PDT 24
Peak memory 205736 kb
Host smart-182f485e-0d80-4463-bf05-416d0a5fe2a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384780148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1384780148
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2963786377
Short name T393
Test name
Test status
Simulation time 50723723 ps
CPU time 1.78 seconds
Started May 11 03:49:38 PM PDT 24
Finished May 11 03:49:41 PM PDT 24
Peak memory 214068 kb
Host smart-8c67eb86-fffa-4741-baee-ab99de16b65c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963786377 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2963786377
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.4199155465
Short name T443
Test name
Test status
Simulation time 16597221 ps
CPU time 0.92 seconds
Started May 11 03:49:41 PM PDT 24
Finished May 11 03:49:42 PM PDT 24
Peak memory 205732 kb
Host smart-70df7e05-c348-46b8-87f6-95364bf72344
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199155465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.4199155465
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.459040619
Short name T337
Test name
Test status
Simulation time 40820333 ps
CPU time 0.76 seconds
Started May 11 03:49:38 PM PDT 24
Finished May 11 03:49:40 PM PDT 24
Peak memory 205476 kb
Host smart-816296be-6a44-44c8-9cd4-c49bef8a5dfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459040619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.459040619
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1212982280
Short name T415
Test name
Test status
Simulation time 33522129 ps
CPU time 1.41 seconds
Started May 11 03:49:44 PM PDT 24
Finished May 11 03:49:46 PM PDT 24
Peak memory 205752 kb
Host smart-e1e25b24-faf0-4f56-a494-ed1204818275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212982280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1212982280
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3531203374
Short name T377
Test name
Test status
Simulation time 76319227 ps
CPU time 1.97 seconds
Started May 11 03:49:34 PM PDT 24
Finished May 11 03:49:36 PM PDT 24
Peak memory 213936 kb
Host smart-c62dbae7-b9f3-41ec-a56e-8bf52ac32ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531203374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3531203374
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2860794285
Short name T278
Test name
Test status
Simulation time 196877057 ps
CPU time 2.56 seconds
Started May 11 03:49:40 PM PDT 24
Finished May 11 03:49:43 PM PDT 24
Peak memory 205812 kb
Host smart-28f5a318-29af-4122-a709-a6b978f1373b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860794285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2860794285
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2911480029
Short name T233
Test name
Test status
Simulation time 17003952 ps
CPU time 1.26 seconds
Started May 11 03:49:38 PM PDT 24
Finished May 11 03:49:40 PM PDT 24
Peak memory 214072 kb
Host smart-e0271e0c-629e-4fb1-8130-cf697c90838b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911480029 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2911480029
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3867471038
Short name T213
Test name
Test status
Simulation time 13305311 ps
CPU time 0.88 seconds
Started May 11 03:49:39 PM PDT 24
Finished May 11 03:49:41 PM PDT 24
Peak memory 205692 kb
Host smart-20f92fce-6a82-4120-b9ee-bd30c07b0702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867471038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3867471038
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3256879869
Short name T353
Test name
Test status
Simulation time 40745600 ps
CPU time 0.82 seconds
Started May 11 03:49:38 PM PDT 24
Finished May 11 03:49:39 PM PDT 24
Peak memory 205608 kb
Host smart-674f5a81-612e-4b6e-a772-8a9c0d73c528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256879869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3256879869
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2827051982
Short name T162
Test name
Test status
Simulation time 42632672 ps
CPU time 1.05 seconds
Started May 11 03:49:39 PM PDT 24
Finished May 11 03:49:40 PM PDT 24
Peak memory 205776 kb
Host smart-a736b4d5-e2a9-4b3d-90bc-2d1adf7b1e07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827051982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2827051982
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3322845092
Short name T215
Test name
Test status
Simulation time 46355053 ps
CPU time 1.5 seconds
Started May 11 03:49:39 PM PDT 24
Finished May 11 03:49:41 PM PDT 24
Peak memory 213988 kb
Host smart-502d1fcb-8df6-4b35-b51e-7e310b75c85a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322845092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3322845092
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2158332623
Short name T163
Test name
Test status
Simulation time 1220196244 ps
CPU time 2.37 seconds
Started May 11 03:49:38 PM PDT 24
Finished May 11 03:49:41 PM PDT 24
Peak memory 205812 kb
Host smart-7750563f-bae1-4ae3-bcab-374846c23d1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158332623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2158332623
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3233667617
Short name T429
Test name
Test status
Simulation time 74457937 ps
CPU time 1.24 seconds
Started May 11 03:49:40 PM PDT 24
Finished May 11 03:49:41 PM PDT 24
Peak memory 214132 kb
Host smart-80eabe05-bc41-4e5f-a0be-d0352ad84a43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233667617 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3233667617
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2332600281
Short name T399
Test name
Test status
Simulation time 15477304 ps
CPU time 0.94 seconds
Started May 11 03:49:40 PM PDT 24
Finished May 11 03:49:42 PM PDT 24
Peak memory 205696 kb
Host smart-6bdfccad-03e1-48c0-8c64-4bc116020200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332600281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2332600281
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.146881514
Short name T388
Test name
Test status
Simulation time 54262425 ps
CPU time 0.91 seconds
Started May 11 03:49:39 PM PDT 24
Finished May 11 03:49:40 PM PDT 24
Peak memory 205612 kb
Host smart-2c314c6d-4519-4efc-b94f-69ff027fd7b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146881514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.146881514
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1507555230
Short name T440
Test name
Test status
Simulation time 23606519 ps
CPU time 1.12 seconds
Started May 11 03:49:44 PM PDT 24
Finished May 11 03:49:46 PM PDT 24
Peak memory 205752 kb
Host smart-2173fec5-7c6a-4297-9562-352d3e238575
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507555230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1507555230
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.351526375
Short name T449
Test name
Test status
Simulation time 54808046 ps
CPU time 1.72 seconds
Started May 11 03:49:41 PM PDT 24
Finished May 11 03:49:43 PM PDT 24
Peak memory 214024 kb
Host smart-91986120-2255-4f24-ae1a-e0f0682e3f6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351526375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.351526375
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1397985067
Short name T403
Test name
Test status
Simulation time 232255863 ps
CPU time 2.1 seconds
Started May 11 03:49:38 PM PDT 24
Finished May 11 03:49:40 PM PDT 24
Peak memory 205804 kb
Host smart-397497ba-e362-4bc3-9929-f212fc27e790
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397985067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1397985067
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2761614951
Short name T219
Test name
Test status
Simulation time 13575056 ps
CPU time 0.99 seconds
Started May 11 03:49:43 PM PDT 24
Finished May 11 03:49:44 PM PDT 24
Peak memory 205796 kb
Host smart-b5aca1df-82b9-474f-b343-b80f95e06053
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761614951 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2761614951
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1490098565
Short name T368
Test name
Test status
Simulation time 14779743 ps
CPU time 0.92 seconds
Started May 11 03:49:44 PM PDT 24
Finished May 11 03:49:46 PM PDT 24
Peak memory 205748 kb
Host smart-45cf6206-2cb8-46ae-8211-34b6bcc8f9e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490098565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1490098565
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.528462329
Short name T366
Test name
Test status
Simulation time 59996473 ps
CPU time 0.89 seconds
Started May 11 03:49:47 PM PDT 24
Finished May 11 03:49:48 PM PDT 24
Peak memory 205504 kb
Host smart-676b1eca-af1a-476b-88a2-2ba640134068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528462329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.528462329
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.233388570
Short name T216
Test name
Test status
Simulation time 64446884 ps
CPU time 1.08 seconds
Started May 11 03:49:44 PM PDT 24
Finished May 11 03:49:46 PM PDT 24
Peak memory 205816 kb
Host smart-36d7d5fe-dd5c-42eb-8b67-9472b32c068b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233388570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.233388570
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2853115129
Short name T352
Test name
Test status
Simulation time 44909318 ps
CPU time 1.98 seconds
Started May 11 03:49:45 PM PDT 24
Finished May 11 03:49:48 PM PDT 24
Peak memory 214092 kb
Host smart-48198ded-2559-4f27-8334-0546e313a527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853115129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2853115129
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3360437028
Short name T170
Test name
Test status
Simulation time 175848615 ps
CPU time 1.65 seconds
Started May 11 03:49:45 PM PDT 24
Finished May 11 03:49:47 PM PDT 24
Peak memory 205800 kb
Host smart-2aa7eac9-1e83-4e23-ab12-12dc56ccdaee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360437028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3360437028
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3878934549
Short name T639
Test name
Test status
Simulation time 70444272 ps
CPU time 1.02 seconds
Started May 11 03:24:16 PM PDT 24
Finished May 11 03:24:17 PM PDT 24
Peak memory 205560 kb
Host smart-d00916eb-28fc-4ba0-85e9-d0f00d8e81e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878934549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3878934549
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.611027975
Short name T650
Test name
Test status
Simulation time 30353203 ps
CPU time 0.94 seconds
Started May 11 03:24:13 PM PDT 24
Finished May 11 03:24:14 PM PDT 24
Peak memory 205260 kb
Host smart-e59570ac-4150-41a1-b9ce-ff7ab216c1ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611027975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.611027975
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.4220888504
Short name T57
Test name
Test status
Simulation time 23237351 ps
CPU time 1.01 seconds
Started May 11 03:24:12 PM PDT 24
Finished May 11 03:24:13 PM PDT 24
Peak memory 215172 kb
Host smart-d950af15-cd4a-4172-86b2-59fdda5fffbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220888504 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.4220888504
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.4165266669
Short name T596
Test name
Test status
Simulation time 42100793 ps
CPU time 1.2 seconds
Started May 11 03:24:14 PM PDT 24
Finished May 11 03:24:16 PM PDT 24
Peak memory 222728 kb
Host smart-28423cd3-2c02-47d8-be9c-744e3107bf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165266669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.4165266669
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.1245618009
Short name T547
Test name
Test status
Simulation time 18918219 ps
CPU time 1.05 seconds
Started May 11 03:24:13 PM PDT 24
Finished May 11 03:24:15 PM PDT 24
Peak memory 215104 kb
Host smart-8723d23d-6db8-41ca-82e9-78a7803084f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245618009 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1245618009
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1922121838
Short name T304
Test name
Test status
Simulation time 41192182 ps
CPU time 0.86 seconds
Started May 11 03:24:12 PM PDT 24
Finished May 11 03:24:13 PM PDT 24
Peak memory 205392 kb
Host smart-adae8bc8-b7e0-4dfc-a2a4-79e64eb58a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922121838 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1922121838
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.248187892
Short name T241
Test name
Test status
Simulation time 49953557 ps
CPU time 0.93 seconds
Started May 11 03:24:10 PM PDT 24
Finished May 11 03:24:11 PM PDT 24
Peak memory 205440 kb
Host smart-08decf35-2931-4cff-9453-a09884d07aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248187892 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.248187892
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3595478469
Short name T630
Test name
Test status
Simulation time 171394001 ps
CPU time 2.12 seconds
Started May 11 03:24:12 PM PDT 24
Finished May 11 03:24:14 PM PDT 24
Peak memory 206660 kb
Host smart-b1c7c43c-e606-4a52-8552-7ff5eeb208b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595478469 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3595478469
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1528679996
Short name T617
Test name
Test status
Simulation time 31415097180 ps
CPU time 664.1 seconds
Started May 11 03:24:13 PM PDT 24
Finished May 11 03:35:18 PM PDT 24
Peak memory 216656 kb
Host smart-ef68c85a-64d8-4257-8771-65149007bbf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528679996 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1528679996
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.2372986698
Short name T701
Test name
Test status
Simulation time 54875670 ps
CPU time 0.86 seconds
Started May 11 03:24:18 PM PDT 24
Finished May 11 03:24:19 PM PDT 24
Peak memory 206220 kb
Host smart-504117b9-a63f-4c29-a520-23b1b6367dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372986698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2372986698
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.1990242543
Short name T659
Test name
Test status
Simulation time 23136072 ps
CPU time 1.29 seconds
Started May 11 03:24:19 PM PDT 24
Finished May 11 03:24:20 PM PDT 24
Peak memory 229712 kb
Host smart-1508787e-1841-4db3-8b01-615330eb158c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990242543 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1990242543
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3085173075
Short name T607
Test name
Test status
Simulation time 32056407 ps
CPU time 1.04 seconds
Started May 11 03:24:14 PM PDT 24
Finished May 11 03:24:15 PM PDT 24
Peak memory 205676 kb
Host smart-8dceed45-3174-4d43-96e4-57ea6b744903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085173075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3085173075
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1821808044
Short name T53
Test name
Test status
Simulation time 1049821213 ps
CPU time 16.45 seconds
Started May 11 03:24:16 PM PDT 24
Finished May 11 03:24:33 PM PDT 24
Peak memory 233304 kb
Host smart-54bcb44d-a64e-4437-856d-64511e21f178
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821808044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1821808044
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3004724760
Short name T482
Test name
Test status
Simulation time 15277825 ps
CPU time 0.91 seconds
Started May 11 03:24:16 PM PDT 24
Finished May 11 03:24:17 PM PDT 24
Peak memory 205080 kb
Host smart-dde1dcc8-485b-4791-88a6-7f95cd9539e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004724760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3004724760
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.921777213
Short name T77
Test name
Test status
Simulation time 164423913 ps
CPU time 3.45 seconds
Started May 11 03:24:13 PM PDT 24
Finished May 11 03:24:17 PM PDT 24
Peak memory 206288 kb
Host smart-7a1bca94-010f-4187-bb41-02922009527f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921777213 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.921777213
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.2727617268
Short name T719
Test name
Test status
Simulation time 51144462 ps
CPU time 0.95 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:24:43 PM PDT 24
Peak memory 206612 kb
Host smart-6707e850-8dce-4155-99fb-436fd75f9201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727617268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2727617268
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.373266177
Short name T678
Test name
Test status
Simulation time 13816522 ps
CPU time 0.92 seconds
Started May 11 03:24:37 PM PDT 24
Finished May 11 03:24:39 PM PDT 24
Peak memory 206104 kb
Host smart-1926def5-e0a7-4675-ab01-8f8d0f0df85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373266177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.373266177
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.368883756
Short name T197
Test name
Test status
Simulation time 17510171 ps
CPU time 0.88 seconds
Started May 11 03:24:44 PM PDT 24
Finished May 11 03:24:46 PM PDT 24
Peak memory 214980 kb
Host smart-0d87da94-be83-41c2-b414-3bc5b5bc0925
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368883756 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.368883756
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.4234986984
Short name T591
Test name
Test status
Simulation time 84928978 ps
CPU time 1.17 seconds
Started May 11 03:24:37 PM PDT 24
Finished May 11 03:24:40 PM PDT 24
Peak memory 215264 kb
Host smart-29467446-eafd-4f71-8a58-db70b31e97bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234986984 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.4234986984
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3566857301
Short name T195
Test name
Test status
Simulation time 44627996 ps
CPU time 0.88 seconds
Started May 11 03:24:45 PM PDT 24
Finished May 11 03:24:46 PM PDT 24
Peak memory 221940 kb
Host smart-b8c947ae-a3bd-4001-86d9-99c64e0b621e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566857301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3566857301
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_smoke.413892419
Short name T573
Test name
Test status
Simulation time 26808996 ps
CPU time 0.88 seconds
Started May 11 03:24:44 PM PDT 24
Finished May 11 03:24:45 PM PDT 24
Peak memory 205640 kb
Host smart-4f13d469-238b-4104-9c92-77c5d18172b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413892419 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.413892419
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2089420638
Short name T716
Test name
Test status
Simulation time 178386422 ps
CPU time 1.44 seconds
Started May 11 03:24:37 PM PDT 24
Finished May 11 03:24:40 PM PDT 24
Peak memory 205836 kb
Host smart-e25bbaeb-c34f-43f2-9e6b-f698b4279d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089420638 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2089420638
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.753692970
Short name T641
Test name
Test status
Simulation time 77179224933 ps
CPU time 1581.01 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:51:03 PM PDT 24
Peak memory 218392 kb
Host smart-e00247da-4d76-4002-8a19-50f7804733ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753692970 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.753692970
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_alert_test.1594721595
Short name T676
Test name
Test status
Simulation time 119853882 ps
CPU time 0.82 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:24:42 PM PDT 24
Peak memory 205624 kb
Host smart-a4832ac8-70f0-4f14-9537-8b049a8805c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594721595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1594721595
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.507992119
Short name T18
Test name
Test status
Simulation time 14818018 ps
CPU time 0.89 seconds
Started May 11 03:24:42 PM PDT 24
Finished May 11 03:24:43 PM PDT 24
Peak memory 215184 kb
Host smart-c6996054-078e-4440-93f1-df8798466d20
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507992119 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.507992119
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1033438495
Short name T682
Test name
Test status
Simulation time 55830513 ps
CPU time 0.98 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:24:43 PM PDT 24
Peak memory 215100 kb
Host smart-cd0c6b47-e530-4e47-8a46-62983594f484
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033438495 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1033438495
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1532680350
Short name T49
Test name
Test status
Simulation time 55344352 ps
CPU time 1.01 seconds
Started May 11 03:24:39 PM PDT 24
Finished May 11 03:24:40 PM PDT 24
Peak memory 229256 kb
Host smart-3158484c-6d66-44ee-ac42-e965c2731e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532680350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1532680350
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.164495149
Short name T328
Test name
Test status
Simulation time 21036889 ps
CPU time 1.16 seconds
Started May 11 03:24:42 PM PDT 24
Finished May 11 03:24:44 PM PDT 24
Peak memory 222260 kb
Host smart-bee5272c-9c42-4271-9877-885276333bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164495149 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.164495149
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.608016171
Short name T484
Test name
Test status
Simulation time 16754278 ps
CPU time 0.87 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:24:43 PM PDT 24
Peak memory 205472 kb
Host smart-f9cc9d6a-69ad-4a76-84a1-5c6b7f37005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608016171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.608016171
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.648735033
Short name T708
Test name
Test status
Simulation time 423833372 ps
CPU time 2.86 seconds
Started May 11 03:24:39 PM PDT 24
Finished May 11 03:24:42 PM PDT 24
Peak memory 206284 kb
Host smart-a326207e-6e83-43fc-b1da-06a3f73a95f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648735033 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.648735033
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.784141740
Short name T576
Test name
Test status
Simulation time 37024255319 ps
CPU time 804.05 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:38:06 PM PDT 24
Peak memory 215520 kb
Host smart-6611742a-96be-489d-813e-eb33d0360d08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784141740 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.784141740
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_disable.1212520740
Short name T91
Test name
Test status
Simulation time 30955274 ps
CPU time 0.85 seconds
Started May 11 03:24:44 PM PDT 24
Finished May 11 03:24:46 PM PDT 24
Peak memory 214912 kb
Host smart-c6c55da7-880c-4515-bf63-e55769c4a603
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212520740 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1212520740
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.392178427
Short name T546
Test name
Test status
Simulation time 89947038 ps
CPU time 0.97 seconds
Started May 11 03:24:40 PM PDT 24
Finished May 11 03:24:42 PM PDT 24
Peak memory 215188 kb
Host smart-99ee321e-5899-4a4a-90e3-99903e654c6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392178427 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.392178427
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.662421880
Short name T178
Test name
Test status
Simulation time 26287928 ps
CPU time 1.22 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:24:43 PM PDT 24
Peak memory 215304 kb
Host smart-fd34a053-0ba1-4442-b9e9-a2770fa50a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662421880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.662421880
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3122611652
Short name T637
Test name
Test status
Simulation time 18104006 ps
CPU time 1.02 seconds
Started May 11 03:24:43 PM PDT 24
Finished May 11 03:24:45 PM PDT 24
Peak memory 205668 kb
Host smart-c5588f5b-2dd2-4394-9e45-44ccf093a8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122611652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3122611652
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1815203662
Short name T579
Test name
Test status
Simulation time 93804773 ps
CPU time 0.91 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:24:42 PM PDT 24
Peak memory 221180 kb
Host smart-a93909df-2ca0-42fe-954b-85a3d59131d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815203662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1815203662
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.93311749
Short name T614
Test name
Test status
Simulation time 72066410 ps
CPU time 0.84 seconds
Started May 11 03:24:42 PM PDT 24
Finished May 11 03:24:43 PM PDT 24
Peak memory 205208 kb
Host smart-bbd36f9f-13ec-4326-9c50-d4041771993b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93311749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.93311749
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.519464708
Short name T665
Test name
Test status
Simulation time 199623276 ps
CPU time 4.22 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:24:46 PM PDT 24
Peak memory 206548 kb
Host smart-6314ab9c-a767-40a3-9405-30101a3c1e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519464708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.519464708
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3252674239
Short name T506
Test name
Test status
Simulation time 114573781835 ps
CPU time 1317.18 seconds
Started May 11 03:24:40 PM PDT 24
Finished May 11 03:46:37 PM PDT 24
Peak memory 219220 kb
Host smart-f877e8dc-1501-49e9-ab9b-5902e733dcf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252674239 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3252674239
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.edn_alert.2587151747
Short name T691
Test name
Test status
Simulation time 17801403 ps
CPU time 0.95 seconds
Started May 11 03:24:43 PM PDT 24
Finished May 11 03:24:45 PM PDT 24
Peak memory 205748 kb
Host smart-19861660-3422-42b7-b517-5d199f2a0e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587151747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2587151747
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3835995802
Short name T597
Test name
Test status
Simulation time 217974510 ps
CPU time 0.9 seconds
Started May 11 03:24:44 PM PDT 24
Finished May 11 03:24:46 PM PDT 24
Peak memory 205184 kb
Host smart-4abc199b-e7fb-4d2c-a09e-d2d207f77317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835995802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3835995802
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3095056160
Short name T494
Test name
Test status
Simulation time 44476455 ps
CPU time 0.92 seconds
Started May 11 03:24:43 PM PDT 24
Finished May 11 03:24:44 PM PDT 24
Peak memory 215080 kb
Host smart-e57ab1f6-9d11-4cfe-bca7-01afb6ac59f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095056160 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3095056160
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1301190222
Short name T542
Test name
Test status
Simulation time 20764379 ps
CPU time 1.06 seconds
Started May 11 03:24:47 PM PDT 24
Finished May 11 03:24:49 PM PDT 24
Peak memory 216696 kb
Host smart-84644080-dedc-4891-9081-07c8daf0c1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301190222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1301190222
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.3755834373
Short name T527
Test name
Test status
Simulation time 33046216 ps
CPU time 0.86 seconds
Started May 11 03:24:43 PM PDT 24
Finished May 11 03:24:44 PM PDT 24
Peak memory 214824 kb
Host smart-f81fac0d-6cd7-45fa-aa90-ef67623ef30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755834373 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3755834373
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2287372492
Short name T720
Test name
Test status
Simulation time 70707391 ps
CPU time 0.91 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:24:43 PM PDT 24
Peak memory 205104 kb
Host smart-e5a513bb-0037-4521-a89e-dff76b0154a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287372492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2287372492
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.84586991
Short name T606
Test name
Test status
Simulation time 177286310 ps
CPU time 3.58 seconds
Started May 11 03:24:41 PM PDT 24
Finished May 11 03:24:45 PM PDT 24
Peak memory 206360 kb
Host smart-ecaf6857-ffdd-49f3-9bbd-44e74d9f7e30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84586991 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.84586991
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1631862414
Short name T495
Test name
Test status
Simulation time 24405473517 ps
CPU time 511.62 seconds
Started May 11 03:24:45 PM PDT 24
Finished May 11 03:33:17 PM PDT 24
Peak memory 216552 kb
Host smart-19377854-95db-42b4-bcea-25e15e6210ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631862414 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1631862414
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_alert.3555856497
Short name T308
Test name
Test status
Simulation time 105321217 ps
CPU time 0.89 seconds
Started May 11 03:24:43 PM PDT 24
Finished May 11 03:24:44 PM PDT 24
Peak memory 206472 kb
Host smart-1a41b34f-6d55-420d-98a5-d47db0dd5824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555856497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3555856497
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.761465747
Short name T310
Test name
Test status
Simulation time 65563998 ps
CPU time 0.85 seconds
Started May 11 03:24:45 PM PDT 24
Finished May 11 03:24:47 PM PDT 24
Peak memory 205076 kb
Host smart-f754a820-a28c-4018-a8d1-30b9cdefd90c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761465747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.761465747
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_err.4012134155
Short name T516
Test name
Test status
Simulation time 31984066 ps
CPU time 0.89 seconds
Started May 11 03:24:48 PM PDT 24
Finished May 11 03:24:49 PM PDT 24
Peak memory 216380 kb
Host smart-04f27b2d-3528-46f9-8578-481babb77761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012134155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4012134155
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3569396120
Short name T480
Test name
Test status
Simulation time 28639906 ps
CPU time 0.86 seconds
Started May 11 03:24:44 PM PDT 24
Finished May 11 03:24:46 PM PDT 24
Peak memory 205572 kb
Host smart-3e8dc16b-e803-4056-a369-079564ebbc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569396120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3569396120
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1019639544
Short name T35
Test name
Test status
Simulation time 35720265 ps
CPU time 0.96 seconds
Started May 11 03:24:43 PM PDT 24
Finished May 11 03:24:45 PM PDT 24
Peak memory 221916 kb
Host smart-d4cd3a6f-5e77-48f4-8bcb-5a91363d9cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019639544 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1019639544
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.802620180
Short name T555
Test name
Test status
Simulation time 37581246 ps
CPU time 0.84 seconds
Started May 11 03:24:44 PM PDT 24
Finished May 11 03:24:46 PM PDT 24
Peak memory 205288 kb
Host smart-f8c925f1-cc9f-4183-b1a8-7a372a9d6fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802620180 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.802620180
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1918211540
Short name T324
Test name
Test status
Simulation time 1121874521 ps
CPU time 3.74 seconds
Started May 11 03:24:42 PM PDT 24
Finished May 11 03:24:46 PM PDT 24
Peak memory 206696 kb
Host smart-95b28446-dc40-483f-a2d9-903a4abd0ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918211540 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1918211540
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2094708604
Short name T545
Test name
Test status
Simulation time 150494733435 ps
CPU time 1195.18 seconds
Started May 11 03:24:44 PM PDT 24
Finished May 11 03:44:40 PM PDT 24
Peak memory 220800 kb
Host smart-08b4352d-60d0-43e7-8f21-ee2de772e471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094708604 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2094708604
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.edn_alert_test.2624441314
Short name T463
Test name
Test status
Simulation time 49120440 ps
CPU time 0.87 seconds
Started May 11 03:24:50 PM PDT 24
Finished May 11 03:24:51 PM PDT 24
Peak memory 205600 kb
Host smart-aefd4523-a2ea-4c4d-9c86-4638966e79a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624441314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2624441314
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.437476627
Short name T42
Test name
Test status
Simulation time 18123936 ps
CPU time 0.81 seconds
Started May 11 03:24:46 PM PDT 24
Finished May 11 03:24:47 PM PDT 24
Peak memory 214988 kb
Host smart-41a1f328-5c83-47d0-893d-54ce4ac7a1ac
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437476627 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.437476627
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2769726576
Short name T580
Test name
Test status
Simulation time 31142816 ps
CPU time 0.99 seconds
Started May 11 03:24:45 PM PDT 24
Finished May 11 03:24:47 PM PDT 24
Peak memory 215204 kb
Host smart-fdf25ad7-b795-4de0-bf80-b330f311053b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769726576 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2769726576
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3003262317
Short name T59
Test name
Test status
Simulation time 19097572 ps
CPU time 1 seconds
Started May 11 03:24:46 PM PDT 24
Finished May 11 03:24:47 PM PDT 24
Peak memory 216400 kb
Host smart-b4ff08a0-f70e-4fa0-a507-7a92600922af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003262317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3003262317
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3459577134
Short name T710
Test name
Test status
Simulation time 73149077 ps
CPU time 1.34 seconds
Started May 11 03:24:48 PM PDT 24
Finished May 11 03:24:50 PM PDT 24
Peak memory 206348 kb
Host smart-9336861d-8af7-4b5d-92c4-db7a0efb28b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459577134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3459577134
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1953933227
Short name T461
Test name
Test status
Simulation time 23850221 ps
CPU time 1.08 seconds
Started May 11 03:24:48 PM PDT 24
Finished May 11 03:24:50 PM PDT 24
Peak memory 215124 kb
Host smart-77502f1c-8517-42b0-bac3-81ac8a158805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953933227 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1953933227
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.4264227200
Short name T531
Test name
Test status
Simulation time 14667858 ps
CPU time 0.93 seconds
Started May 11 03:24:46 PM PDT 24
Finished May 11 03:24:48 PM PDT 24
Peak memory 205380 kb
Host smart-c3768a94-082d-4f68-80ce-9b889cd468d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264227200 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.4264227200
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1140212087
Short name T36
Test name
Test status
Simulation time 975587897 ps
CPU time 4.08 seconds
Started May 11 03:24:46 PM PDT 24
Finished May 11 03:24:51 PM PDT 24
Peak memory 206488 kb
Host smart-05410ac9-475e-4c0e-bbab-c534bac316e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140212087 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1140212087
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.730767187
Short name T590
Test name
Test status
Simulation time 75696365396 ps
CPU time 440.85 seconds
Started May 11 03:24:45 PM PDT 24
Finished May 11 03:32:06 PM PDT 24
Peak memory 216376 kb
Host smart-373caca1-d65a-41c4-82b3-79061252b5d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730767187 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.730767187
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_alert.2315200983
Short name T82
Test name
Test status
Simulation time 18791506 ps
CPU time 1.07 seconds
Started May 11 03:24:50 PM PDT 24
Finished May 11 03:24:52 PM PDT 24
Peak memory 206656 kb
Host smart-25160ac4-3d33-4234-ad52-a181284d51df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315200983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2315200983
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3384369520
Short name T697
Test name
Test status
Simulation time 22326625 ps
CPU time 0.98 seconds
Started May 11 03:24:49 PM PDT 24
Finished May 11 03:24:50 PM PDT 24
Peak memory 205296 kb
Host smart-b5b86ef9-8f12-4f6a-b474-e918294ed995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384369520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3384369520
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2745769294
Short name T152
Test name
Test status
Simulation time 28588556 ps
CPU time 0.84 seconds
Started May 11 03:24:49 PM PDT 24
Finished May 11 03:24:50 PM PDT 24
Peak memory 215008 kb
Host smart-9fa1e921-5b28-4669-8024-5fa982d7d644
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745769294 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2745769294
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.566007413
Short name T507
Test name
Test status
Simulation time 32137972 ps
CPU time 1.01 seconds
Started May 11 03:24:50 PM PDT 24
Finished May 11 03:24:51 PM PDT 24
Peak memory 215196 kb
Host smart-726c35e5-3f48-484b-a2aa-f3b719290e8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566007413 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.566007413
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3895025470
Short name T259
Test name
Test status
Simulation time 36814342 ps
CPU time 1.2 seconds
Started May 11 03:24:49 PM PDT 24
Finished May 11 03:24:51 PM PDT 24
Peak memory 217596 kb
Host smart-fa9bac4e-8b3c-4547-99d1-c5287a45082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895025470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3895025470
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1838478563
Short name T47
Test name
Test status
Simulation time 39612730 ps
CPU time 1.01 seconds
Started May 11 03:24:47 PM PDT 24
Finished May 11 03:24:49 PM PDT 24
Peak memory 205948 kb
Host smart-fe156d8b-4275-4f0e-8638-a0b90540d5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838478563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1838478563
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3787869557
Short name T51
Test name
Test status
Simulation time 41890012 ps
CPU time 1.02 seconds
Started May 11 03:24:52 PM PDT 24
Finished May 11 03:24:54 PM PDT 24
Peak memory 222024 kb
Host smart-4f6c4aa3-1a67-4ff7-b9d5-7aedfa529381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787869557 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3787869557
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1065655650
Short name T662
Test name
Test status
Simulation time 20468027 ps
CPU time 0.91 seconds
Started May 11 03:24:49 PM PDT 24
Finished May 11 03:24:50 PM PDT 24
Peak memory 205232 kb
Host smart-0c244100-7fcb-4e57-9ad5-d0284946c9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065655650 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1065655650
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1785339900
Short name T171
Test name
Test status
Simulation time 550877878 ps
CPU time 3.12 seconds
Started May 11 03:24:49 PM PDT 24
Finished May 11 03:24:53 PM PDT 24
Peak memory 206124 kb
Host smart-e443869d-593e-4520-813b-74fb75af258d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785339900 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1785339900
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2171838424
Short name T656
Test name
Test status
Simulation time 139331571292 ps
CPU time 652.19 seconds
Started May 11 03:24:50 PM PDT 24
Finished May 11 03:35:43 PM PDT 24
Peak memory 215448 kb
Host smart-c28f81ac-e86e-402d-8823-82c9bd04db4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171838424 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2171838424
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_alert.2467291150
Short name T517
Test name
Test status
Simulation time 16579875 ps
CPU time 0.98 seconds
Started May 11 03:24:52 PM PDT 24
Finished May 11 03:24:54 PM PDT 24
Peak memory 206636 kb
Host smart-e4dac83c-c920-4009-a1c6-f239f1b30dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467291150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2467291150
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2574765255
Short name T460
Test name
Test status
Simulation time 12162206 ps
CPU time 0.86 seconds
Started May 11 03:24:51 PM PDT 24
Finished May 11 03:24:53 PM PDT 24
Peak memory 204920 kb
Host smart-1e4c4ed4-a9ac-4337-8761-8b4f3985ff15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574765255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2574765255
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3031703683
Short name T699
Test name
Test status
Simulation time 16202031 ps
CPU time 0.84 seconds
Started May 11 03:24:53 PM PDT 24
Finished May 11 03:24:54 PM PDT 24
Peak memory 214976 kb
Host smart-12c1a0da-91c3-4ee1-ba59-b21c6d024292
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031703683 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3031703683
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1418496878
Short name T97
Test name
Test status
Simulation time 50268775 ps
CPU time 1.03 seconds
Started May 11 03:24:53 PM PDT 24
Finished May 11 03:24:54 PM PDT 24
Peak memory 215248 kb
Host smart-8ed69ea5-d1e6-4502-a19b-fc565a3cfa6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418496878 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1418496878
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3774220382
Short name T202
Test name
Test status
Simulation time 18313096 ps
CPU time 1.14 seconds
Started May 11 03:24:52 PM PDT 24
Finished May 11 03:24:54 PM PDT 24
Peak memory 222212 kb
Host smart-7430b375-9e3c-460f-9130-7511d20a9760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774220382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3774220382
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3013300876
Short name T673
Test name
Test status
Simulation time 165260074 ps
CPU time 1.07 seconds
Started May 11 03:24:50 PM PDT 24
Finished May 11 03:24:52 PM PDT 24
Peak memory 205548 kb
Host smart-81d55b40-9efb-4dc9-8247-a6177b83b16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013300876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3013300876
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3990280888
Short name T556
Test name
Test status
Simulation time 53721861 ps
CPU time 0.93 seconds
Started May 11 03:24:50 PM PDT 24
Finished May 11 03:24:51 PM PDT 24
Peak memory 214952 kb
Host smart-8d0d0ff3-93a1-4cfe-98d2-88ced8e63714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990280888 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3990280888
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3966892441
Short name T330
Test name
Test status
Simulation time 14459781 ps
CPU time 0.91 seconds
Started May 11 03:24:47 PM PDT 24
Finished May 11 03:24:48 PM PDT 24
Peak memory 205232 kb
Host smart-f929125c-6421-4cdf-a80b-185e63fdea28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966892441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3966892441
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2358362073
Short name T459
Test name
Test status
Simulation time 76680648 ps
CPU time 2.07 seconds
Started May 11 03:24:48 PM PDT 24
Finished May 11 03:24:50 PM PDT 24
Peak memory 206256 kb
Host smart-0967166e-3b35-4d40-8c91-222a620ea081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358362073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2358362073
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2762312818
Short name T497
Test name
Test status
Simulation time 251673981582 ps
CPU time 2826.72 seconds
Started May 11 03:24:50 PM PDT 24
Finished May 11 04:11:57 PM PDT 24
Peak memory 225720 kb
Host smart-7a62c16f-cda0-4cc0-b0bf-035067bbd14f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762312818 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2762312818
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_alert.570961374
Short name T598
Test name
Test status
Simulation time 70909999 ps
CPU time 1 seconds
Started May 11 03:24:55 PM PDT 24
Finished May 11 03:24:57 PM PDT 24
Peak memory 205800 kb
Host smart-a33e70e3-0530-4422-a38b-46c3b4fdd8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570961374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.570961374
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3886179263
Short name T465
Test name
Test status
Simulation time 27076248 ps
CPU time 1.05 seconds
Started May 11 03:24:56 PM PDT 24
Finished May 11 03:24:57 PM PDT 24
Peak memory 205264 kb
Host smart-f7c01aab-6086-47f2-bebf-cd6bdabe66a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886179263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3886179263
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_err.3465534719
Short name T206
Test name
Test status
Simulation time 45953624 ps
CPU time 0.83 seconds
Started May 11 03:24:52 PM PDT 24
Finished May 11 03:24:53 PM PDT 24
Peak memory 216216 kb
Host smart-5dff3ea2-8c50-471e-bac2-e68d0879d11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465534719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3465534719
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.1949704424
Short name T567
Test name
Test status
Simulation time 34567610 ps
CPU time 0.89 seconds
Started May 11 03:24:57 PM PDT 24
Finished May 11 03:24:59 PM PDT 24
Peak memory 214968 kb
Host smart-f6a90b38-e6d4-450c-9419-1937e74408af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949704424 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1949704424
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.55707124
Short name T52
Test name
Test status
Simulation time 14847752 ps
CPU time 0.92 seconds
Started May 11 03:24:56 PM PDT 24
Finished May 11 03:24:57 PM PDT 24
Peak memory 205548 kb
Host smart-5e0f5b41-8cf3-4785-9276-85be6a36f57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55707124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.55707124
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.409451445
Short name T272
Test name
Test status
Simulation time 391557675 ps
CPU time 3.89 seconds
Started May 11 03:24:53 PM PDT 24
Finished May 11 03:24:57 PM PDT 24
Peak memory 206408 kb
Host smart-ed1135b9-f896-47ba-ba2b-2d65c8f57b65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409451445 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.409451445
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2127448034
Short name T277
Test name
Test status
Simulation time 227181230804 ps
CPU time 1435.36 seconds
Started May 11 03:24:51 PM PDT 24
Finished May 11 03:48:47 PM PDT 24
Peak memory 220604 kb
Host smart-5f4859c6-caa5-48ff-bd62-6bd0a202060b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127448034 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2127448034
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_alert_test.3087193417
Short name T312
Test name
Test status
Simulation time 13595161 ps
CPU time 0.91 seconds
Started May 11 03:25:03 PM PDT 24
Finished May 11 03:25:05 PM PDT 24
Peak memory 206128 kb
Host smart-33d05e2a-2161-4448-a90e-f9c668ed8dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087193417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3087193417
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2082995687
Short name T151
Test name
Test status
Simulation time 21865890 ps
CPU time 0.9 seconds
Started May 11 03:24:57 PM PDT 24
Finished May 11 03:24:59 PM PDT 24
Peak memory 215036 kb
Host smart-61261962-78f9-4b02-92ab-c7a522b11f6c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082995687 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2082995687
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1902490957
Short name T81
Test name
Test status
Simulation time 26981541 ps
CPU time 1.06 seconds
Started May 11 03:24:55 PM PDT 24
Finished May 11 03:24:56 PM PDT 24
Peak memory 215256 kb
Host smart-f117e4e2-344d-4efc-a544-1dcff30ac181
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902490957 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1902490957
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.4044459482
Short name T196
Test name
Test status
Simulation time 24529685 ps
CPU time 0.93 seconds
Started May 11 03:24:58 PM PDT 24
Finished May 11 03:24:59 PM PDT 24
Peak memory 216528 kb
Host smart-29d51394-94c4-472e-a173-37a2d3a93370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044459482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.4044459482
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_intr.1037031969
Short name T69
Test name
Test status
Simulation time 22737463 ps
CPU time 1.07 seconds
Started May 11 03:24:57 PM PDT 24
Finished May 11 03:24:59 PM PDT 24
Peak memory 215140 kb
Host smart-e1b6b625-7c41-46ae-8830-0390068002c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037031969 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1037031969
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2383759192
Short name T88
Test name
Test status
Simulation time 22074995 ps
CPU time 0.91 seconds
Started May 11 03:24:55 PM PDT 24
Finished May 11 03:24:56 PM PDT 24
Peak memory 205352 kb
Host smart-28746121-b618-46a5-b4e2-0dd39c6b530d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383759192 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2383759192
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3835835259
Short name T536
Test name
Test status
Simulation time 39525050 ps
CPU time 1.42 seconds
Started May 11 03:24:57 PM PDT 24
Finished May 11 03:24:59 PM PDT 24
Peak memory 205796 kb
Host smart-a1bc70a1-29b6-4b3c-a816-6f96192eba1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835835259 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3835835259
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_alert_test.818424773
Short name T493
Test name
Test status
Simulation time 47426780 ps
CPU time 0.84 seconds
Started May 11 03:24:21 PM PDT 24
Finished May 11 03:24:22 PM PDT 24
Peak memory 205788 kb
Host smart-7c09b886-5117-4460-ae11-2f6cd8b25480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818424773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.818424773
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2754818124
Short name T84
Test name
Test status
Simulation time 35537274 ps
CPU time 0.86 seconds
Started May 11 03:24:21 PM PDT 24
Finished May 11 03:24:23 PM PDT 24
Peak memory 215020 kb
Host smart-c57eba44-eb95-43c2-b6a3-8582e7fc2aec
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754818124 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2754818124
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.92429917
Short name T7
Test name
Test status
Simulation time 23887693 ps
CPU time 1.09 seconds
Started May 11 03:24:22 PM PDT 24
Finished May 11 03:24:23 PM PDT 24
Peak memory 229476 kb
Host smart-ec63acef-3218-40a8-a6e5-16771eb12a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92429917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.92429917
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2254785647
Short name T291
Test name
Test status
Simulation time 22393710 ps
CPU time 0.91 seconds
Started May 11 03:24:19 PM PDT 24
Finished May 11 03:24:20 PM PDT 24
Peak memory 205696 kb
Host smart-6b0a96e9-1b60-481b-ba3d-47fb9cb35083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254785647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2254785647
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3636783752
Short name T655
Test name
Test status
Simulation time 35002613 ps
CPU time 0.87 seconds
Started May 11 03:24:22 PM PDT 24
Finished May 11 03:24:23 PM PDT 24
Peak memory 214864 kb
Host smart-d4adad32-1f1c-4390-b241-a24117e77514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636783752 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3636783752
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3162714548
Short name T564
Test name
Test status
Simulation time 14258188 ps
CPU time 0.89 seconds
Started May 11 03:24:15 PM PDT 24
Finished May 11 03:24:16 PM PDT 24
Peak memory 205440 kb
Host smart-1860ca64-5f67-49d5-9b77-eabe5d96cb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162714548 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3162714548
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2398467276
Short name T54
Test name
Test status
Simulation time 2504268149 ps
CPU time 6.32 seconds
Started May 11 03:24:23 PM PDT 24
Finished May 11 03:24:29 PM PDT 24
Peak memory 235072 kb
Host smart-784a4221-6686-467d-b4aa-3d7742035df7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398467276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2398467276
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3773587972
Short name T55
Test name
Test status
Simulation time 70011927 ps
CPU time 0.88 seconds
Started May 11 03:24:16 PM PDT 24
Finished May 11 03:24:17 PM PDT 24
Peak memory 205472 kb
Host smart-cc2e6c3f-3a88-4835-a3cf-a9f38be5d00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773587972 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3773587972
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.582003640
Short name T535
Test name
Test status
Simulation time 249636198 ps
CPU time 2.76 seconds
Started May 11 03:24:17 PM PDT 24
Finished May 11 03:24:20 PM PDT 24
Peak memory 206224 kb
Host smart-dfb8123c-d3eb-4444-b8c5-7c2b45a127af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582003640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.582003640
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1999094883
Short name T159
Test name
Test status
Simulation time 104920214746 ps
CPU time 1312.6 seconds
Started May 11 03:24:17 PM PDT 24
Finished May 11 03:46:10 PM PDT 24
Peak memory 221068 kb
Host smart-f8812d47-fd47-4f59-ad5e-bec7b4192fa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999094883 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1999094883
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3836411856
Short name T626
Test name
Test status
Simulation time 33459918 ps
CPU time 0.98 seconds
Started May 11 03:24:59 PM PDT 24
Finished May 11 03:25:01 PM PDT 24
Peak memory 206592 kb
Host smart-e0f75ee1-1fe2-4c95-b96a-394566394109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836411856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3836411856
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1630663472
Short name T471
Test name
Test status
Simulation time 42128234 ps
CPU time 0.94 seconds
Started May 11 03:24:59 PM PDT 24
Finished May 11 03:25:00 PM PDT 24
Peak memory 205248 kb
Host smart-8d3cdeff-2e83-4a6c-94e1-74e48061c299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630663472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1630663472
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1212016981
Short name T588
Test name
Test status
Simulation time 18964496 ps
CPU time 1.02 seconds
Started May 11 03:25:02 PM PDT 24
Finished May 11 03:25:03 PM PDT 24
Peak memory 215232 kb
Host smart-a1fd0876-9acb-45d7-b095-e6818a143c67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212016981 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1212016981
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1095232803
Short name T610
Test name
Test status
Simulation time 83173440 ps
CPU time 1.04 seconds
Started May 11 03:25:01 PM PDT 24
Finished May 11 03:25:03 PM PDT 24
Peak memory 217828 kb
Host smart-5db5ebb1-39e8-4dc0-b4a2-35f5194213f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095232803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1095232803
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2004588746
Short name T620
Test name
Test status
Simulation time 14866695 ps
CPU time 1.1 seconds
Started May 11 03:25:02 PM PDT 24
Finished May 11 03:25:04 PM PDT 24
Peak memory 205872 kb
Host smart-ce5f1b55-fec0-43e3-83ad-2b19295eb1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004588746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2004588746
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.16223854
Short name T154
Test name
Test status
Simulation time 20511531 ps
CPU time 1.19 seconds
Started May 11 03:25:00 PM PDT 24
Finished May 11 03:25:02 PM PDT 24
Peak memory 222200 kb
Host smart-3f782899-9f92-4cdd-aa04-0732e402bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16223854 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.16223854
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1332434288
Short name T625
Test name
Test status
Simulation time 32504263 ps
CPU time 0.83 seconds
Started May 11 03:25:00 PM PDT 24
Finished May 11 03:25:01 PM PDT 24
Peak memory 205536 kb
Host smart-c6850d2c-c472-43d8-9fd9-c344ce53b22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332434288 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1332434288
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3819102208
Short name T86
Test name
Test status
Simulation time 72510030 ps
CPU time 0.9 seconds
Started May 11 03:25:00 PM PDT 24
Finished May 11 03:25:02 PM PDT 24
Peak memory 204900 kb
Host smart-44692df8-b176-49a9-be17-a9159290d483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819102208 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3819102208
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2258541224
Short name T522
Test name
Test status
Simulation time 35640297963 ps
CPU time 858.96 seconds
Started May 11 03:25:01 PM PDT 24
Finished May 11 03:39:20 PM PDT 24
Peak memory 215092 kb
Host smart-50036603-d37a-4bd3-859a-b283707ad6fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258541224 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2258541224
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.edn_alert.4060283224
Short name T75
Test name
Test status
Simulation time 18451974 ps
CPU time 0.96 seconds
Started May 11 03:25:06 PM PDT 24
Finished May 11 03:25:08 PM PDT 24
Peak memory 205816 kb
Host smart-c4222925-9621-42cf-b67a-49e5331e9e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060283224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.4060283224
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2745357232
Short name T319
Test name
Test status
Simulation time 78580257 ps
CPU time 0.94 seconds
Started May 11 03:25:04 PM PDT 24
Finished May 11 03:25:06 PM PDT 24
Peak memory 205784 kb
Host smart-3669eca3-a4ad-4540-a539-70cf3d44d9b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745357232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2745357232
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.86953209
Short name T562
Test name
Test status
Simulation time 44105015 ps
CPU time 1.04 seconds
Started May 11 03:25:04 PM PDT 24
Finished May 11 03:25:05 PM PDT 24
Peak memory 215188 kb
Host smart-de6972dd-b45e-4d35-8b08-bcc14502e76a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86953209 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_dis
able_auto_req_mode.86953209
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.926371345
Short name T329
Test name
Test status
Simulation time 19120715 ps
CPU time 1.45 seconds
Started May 11 03:25:08 PM PDT 24
Finished May 11 03:25:10 PM PDT 24
Peak memory 215156 kb
Host smart-e30f34d2-3317-4f8a-be67-ae38e45b0fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926371345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.926371345
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.912941501
Short name T288
Test name
Test status
Simulation time 17437015 ps
CPU time 0.94 seconds
Started May 11 03:25:02 PM PDT 24
Finished May 11 03:25:04 PM PDT 24
Peak memory 205384 kb
Host smart-60146685-298b-4cc1-bbf2-c8ec362940d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912941501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.912941501
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3067439105
Short name T33
Test name
Test status
Simulation time 23345752 ps
CPU time 0.87 seconds
Started May 11 03:25:04 PM PDT 24
Finished May 11 03:25:06 PM PDT 24
Peak memory 215232 kb
Host smart-0f481104-ad7e-4645-9117-38516a28b243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067439105 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3067439105
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.35050301
Short name T677
Test name
Test status
Simulation time 46566197 ps
CPU time 0.91 seconds
Started May 11 03:25:02 PM PDT 24
Finished May 11 03:25:04 PM PDT 24
Peak memory 205580 kb
Host smart-60ab2a55-f911-41b0-8a8b-7c0aedd94065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35050301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.35050301
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3373465946
Short name T643
Test name
Test status
Simulation time 1325177426 ps
CPU time 4.07 seconds
Started May 11 03:25:00 PM PDT 24
Finished May 11 03:25:05 PM PDT 24
Peak memory 206644 kb
Host smart-4b5f9569-e65d-4880-9ac0-424eb6879c48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373465946 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3373465946
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3994660891
Short name T477
Test name
Test status
Simulation time 72911744567 ps
CPU time 1789.27 seconds
Started May 11 03:25:01 PM PDT 24
Finished May 11 03:54:51 PM PDT 24
Peak memory 223336 kb
Host smart-838b6a6e-19c8-4f67-ae1a-ff37e7005ae6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994660891 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3994660891
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.edn_alert.1167101581
Short name T298
Test name
Test status
Simulation time 73194046 ps
CPU time 1.01 seconds
Started May 11 03:25:05 PM PDT 24
Finished May 11 03:25:07 PM PDT 24
Peak memory 206620 kb
Host smart-599266ef-200e-464d-be4d-d9ad391c81f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167101581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1167101581
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1754215998
Short name T502
Test name
Test status
Simulation time 57165874 ps
CPU time 0.93 seconds
Started May 11 03:25:08 PM PDT 24
Finished May 11 03:25:09 PM PDT 24
Peak memory 205252 kb
Host smart-dcbaf1bd-5c6a-4082-8428-02778e6504f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754215998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1754215998
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2966743510
Short name T663
Test name
Test status
Simulation time 40516148 ps
CPU time 0.86 seconds
Started May 11 03:25:05 PM PDT 24
Finished May 11 03:25:06 PM PDT 24
Peak memory 214936 kb
Host smart-6edf9702-468c-4d32-aed4-d9d4dceabbaa
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966743510 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2966743510
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.647385681
Short name T147
Test name
Test status
Simulation time 88347194 ps
CPU time 1.12 seconds
Started May 11 03:25:06 PM PDT 24
Finished May 11 03:25:07 PM PDT 24
Peak memory 215264 kb
Host smart-7002e83d-5b58-4c26-81cd-16f51f33c7c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647385681 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.647385681
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1033444161
Short name T262
Test name
Test status
Simulation time 35911506 ps
CPU time 0.95 seconds
Started May 11 03:25:07 PM PDT 24
Finished May 11 03:25:08 PM PDT 24
Peak memory 215336 kb
Host smart-7d6a854b-1f8f-47d7-9952-ff67618ee003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033444161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1033444161
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.500773787
Short name T487
Test name
Test status
Simulation time 15676825 ps
CPU time 1.02 seconds
Started May 11 03:25:08 PM PDT 24
Finished May 11 03:25:10 PM PDT 24
Peak memory 205556 kb
Host smart-74d28a0b-add3-47d4-a0d3-05d2b2fbdf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500773787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.500773787
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3010146755
Short name T572
Test name
Test status
Simulation time 22134484 ps
CPU time 0.93 seconds
Started May 11 03:25:05 PM PDT 24
Finished May 11 03:25:07 PM PDT 24
Peak memory 215172 kb
Host smart-a9bec14c-c32f-4963-a670-ceb633f730de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010146755 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3010146755
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.4024995277
Short name T544
Test name
Test status
Simulation time 46753607 ps
CPU time 0.95 seconds
Started May 11 03:25:05 PM PDT 24
Finished May 11 03:25:06 PM PDT 24
Peak memory 205508 kb
Host smart-fb198c77-8d01-4750-b861-ee6df15bd3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024995277 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.4024995277
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1197581554
Short name T89
Test name
Test status
Simulation time 52037985 ps
CPU time 1.18 seconds
Started May 11 03:25:07 PM PDT 24
Finished May 11 03:25:09 PM PDT 24
Peak memory 205756 kb
Host smart-1f1383f0-7736-4035-98b9-2800c8f7e20a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197581554 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1197581554
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3151115059
Short name T510
Test name
Test status
Simulation time 55266635221 ps
CPU time 1427.35 seconds
Started May 11 03:25:05 PM PDT 24
Finished May 11 03:48:52 PM PDT 24
Peak memory 218512 kb
Host smart-1d0c143c-37f7-45b1-9a12-12ceec9639f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151115059 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3151115059
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_alert.2090530469
Short name T714
Test name
Test status
Simulation time 17666271 ps
CPU time 0.98 seconds
Started May 11 03:25:06 PM PDT 24
Finished May 11 03:25:07 PM PDT 24
Peak memory 205744 kb
Host smart-e3ee7ca8-e37f-440b-98e7-24122a36d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090530469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2090530469
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3982626201
Short name T458
Test name
Test status
Simulation time 17131266 ps
CPU time 0.96 seconds
Started May 11 03:25:08 PM PDT 24
Finished May 11 03:25:09 PM PDT 24
Peak memory 205808 kb
Host smart-3d11ae3e-39f1-4807-a178-48171ea8a1ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982626201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3982626201
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2724105417
Short name T44
Test name
Test status
Simulation time 13658868 ps
CPU time 0.89 seconds
Started May 11 03:25:09 PM PDT 24
Finished May 11 03:25:10 PM PDT 24
Peak memory 215164 kb
Host smart-f3d930b4-e684-44fb-a9de-620c9e7cf2cf
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724105417 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2724105417
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1814539046
Short name T73
Test name
Test status
Simulation time 214748358 ps
CPU time 1.09 seconds
Started May 11 03:25:08 PM PDT 24
Finished May 11 03:25:10 PM PDT 24
Peak memory 215168 kb
Host smart-ec207c64-baad-4b34-a868-e4f432a6f4d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814539046 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1814539046
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3438185057
Short name T550
Test name
Test status
Simulation time 56227303 ps
CPU time 1.01 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:25:13 PM PDT 24
Peak memory 216624 kb
Host smart-b6f99b3a-4fd1-4beb-bdfc-3c7bf02fa9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438185057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3438185057
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_smoke.1182480781
Short name T500
Test name
Test status
Simulation time 32135753 ps
CPU time 0.82 seconds
Started May 11 03:25:05 PM PDT 24
Finished May 11 03:25:06 PM PDT 24
Peak memory 205100 kb
Host smart-114e59e8-2ed2-4e38-8041-8c9c7e98b238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182480781 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1182480781
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.571176886
Short name T688
Test name
Test status
Simulation time 231484407 ps
CPU time 2.95 seconds
Started May 11 03:25:09 PM PDT 24
Finished May 11 03:25:12 PM PDT 24
Peak memory 206632 kb
Host smart-72df78ed-5229-4413-a793-485eb1ed1402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571176886 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.571176886
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.22288488
Short name T672
Test name
Test status
Simulation time 50150345423 ps
CPU time 1181.12 seconds
Started May 11 03:25:09 PM PDT 24
Finished May 11 03:44:51 PM PDT 24
Peak memory 216372 kb
Host smart-7df7d1cd-7ce2-481c-a8f9-ca283b57366b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22288488 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.22288488
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.edn_alert.2732411976
Short name T296
Test name
Test status
Simulation time 43878017 ps
CPU time 1.05 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:25:13 PM PDT 24
Peak memory 205848 kb
Host smart-16839f33-ad50-4df9-be8f-9c6931d08107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732411976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2732411976
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2002819205
Short name T568
Test name
Test status
Simulation time 18819173 ps
CPU time 1.04 seconds
Started May 11 03:25:09 PM PDT 24
Finished May 11 03:25:11 PM PDT 24
Peak memory 205464 kb
Host smart-c76fa272-66fe-4b32-a345-af3d057b7069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002819205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2002819205
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1241713349
Short name T17
Test name
Test status
Simulation time 10727475 ps
CPU time 0.87 seconds
Started May 11 03:25:09 PM PDT 24
Finished May 11 03:25:11 PM PDT 24
Peak memory 206772 kb
Host smart-4ce59258-6509-4ee2-8e55-16cf5c0e3984
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241713349 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1241713349
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.4196358495
Short name T557
Test name
Test status
Simulation time 18426098 ps
CPU time 0.93 seconds
Started May 11 03:25:07 PM PDT 24
Finished May 11 03:25:08 PM PDT 24
Peak memory 215088 kb
Host smart-731cec19-b519-4660-b2d5-2a14fad6b992
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196358495 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.4196358495
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.846068258
Short name T613
Test name
Test status
Simulation time 81322057 ps
CPU time 0.8 seconds
Started May 11 03:25:12 PM PDT 24
Finished May 11 03:25:14 PM PDT 24
Peak memory 214848 kb
Host smart-68b2a50c-32f5-47b4-b35a-359c450b99ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846068258 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.846068258
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.1860712872
Short name T139
Test name
Test status
Simulation time 41426736 ps
CPU time 0.85 seconds
Started May 11 03:25:10 PM PDT 24
Finished May 11 03:25:12 PM PDT 24
Peak memory 215084 kb
Host smart-b7977bf4-11cf-4918-9d70-a1c98fc47d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860712872 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1860712872
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4225037789
Short name T722
Test name
Test status
Simulation time 12075873 ps
CPU time 0.88 seconds
Started May 11 03:25:08 PM PDT 24
Finished May 11 03:25:09 PM PDT 24
Peak memory 205276 kb
Host smart-7dbce27c-9aa9-49ed-9837-b84f8364aacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225037789 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4225037789
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1683134427
Short name T526
Test name
Test status
Simulation time 102671563 ps
CPU time 1.22 seconds
Started May 11 03:25:07 PM PDT 24
Finished May 11 03:25:09 PM PDT 24
Peak memory 205556 kb
Host smart-c756168b-7325-4565-9d24-54fe447dc5ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683134427 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1683134427
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3082695601
Short name T61
Test name
Test status
Simulation time 922039963562 ps
CPU time 2938.88 seconds
Started May 11 03:25:10 PM PDT 24
Finished May 11 04:14:10 PM PDT 24
Peak memory 224464 kb
Host smart-71b4260d-8172-49bc-9835-52c6175fdc59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082695601 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3082695601
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.edn_alert.720867083
Short name T307
Test name
Test status
Simulation time 48701170 ps
CPU time 0.98 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:25:13 PM PDT 24
Peak memory 206576 kb
Host smart-46cd9076-b4f4-4d80-9894-85a127db3a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720867083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.720867083
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2779978894
Short name T686
Test name
Test status
Simulation time 71389526 ps
CPU time 0.84 seconds
Started May 11 03:25:19 PM PDT 24
Finished May 11 03:25:20 PM PDT 24
Peak memory 204932 kb
Host smart-c6a1f58d-23a9-4ed6-a052-ed91e22e5741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779978894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2779978894
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3670560776
Short name T250
Test name
Test status
Simulation time 14876552 ps
CPU time 0.87 seconds
Started May 11 03:25:12 PM PDT 24
Finished May 11 03:25:14 PM PDT 24
Peak memory 214972 kb
Host smart-0445587a-a80b-401c-88ab-203305a145a1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670560776 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3670560776
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2279190293
Short name T191
Test name
Test status
Simulation time 20243406 ps
CPU time 1.06 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:25:13 PM PDT 24
Peak memory 215304 kb
Host smart-f5826fb1-bf07-4f97-82f1-57231c013071
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279190293 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2279190293
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1104172048
Short name T321
Test name
Test status
Simulation time 51413218 ps
CPU time 0.83 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:25:13 PM PDT 24
Peak memory 216104 kb
Host smart-32164966-9e41-41b8-a819-21302ec89dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104172048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1104172048
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.353263018
Short name T648
Test name
Test status
Simulation time 47315867 ps
CPU time 0.9 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:25:13 PM PDT 24
Peak memory 206280 kb
Host smart-f446c1cf-5577-44b7-a083-5653b2eb679b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353263018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.353263018
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1227916883
Short name T667
Test name
Test status
Simulation time 40279640 ps
CPU time 0.83 seconds
Started May 11 03:25:19 PM PDT 24
Finished May 11 03:25:20 PM PDT 24
Peak memory 214684 kb
Host smart-6413031d-e0ca-452a-ac3f-f2f873caeb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227916883 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1227916883
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2020487714
Short name T657
Test name
Test status
Simulation time 23461585 ps
CPU time 0.87 seconds
Started May 11 03:25:10 PM PDT 24
Finished May 11 03:25:12 PM PDT 24
Peak memory 205248 kb
Host smart-e4852cc4-f341-4d48-9384-929ba1423077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020487714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2020487714
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.718722418
Short name T126
Test name
Test status
Simulation time 19057320 ps
CPU time 0.97 seconds
Started May 11 03:25:10 PM PDT 24
Finished May 11 03:25:12 PM PDT 24
Peak memory 205468 kb
Host smart-fc61db82-f73c-46f1-8728-746364a05247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718722418 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.718722418
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.720594551
Short name T479
Test name
Test status
Simulation time 60263597031 ps
CPU time 552.34 seconds
Started May 11 03:25:09 PM PDT 24
Finished May 11 03:34:22 PM PDT 24
Peak memory 215128 kb
Host smart-55b0cb12-279c-42b0-8794-9be47fd5b0e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720594551 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.720594551
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_alert.1991103521
Short name T299
Test name
Test status
Simulation time 24508649 ps
CPU time 1 seconds
Started May 11 03:25:14 PM PDT 24
Finished May 11 03:25:16 PM PDT 24
Peak memory 206648 kb
Host smart-e3749971-40c2-4c18-a3b2-9fca85ac69d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991103521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1991103521
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.441533328
Short name T668
Test name
Test status
Simulation time 85580749 ps
CPU time 0.91 seconds
Started May 11 03:25:19 PM PDT 24
Finished May 11 03:25:21 PM PDT 24
Peak memory 206016 kb
Host smart-4a186bff-f27c-44f5-80e4-e0f1a010a686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441533328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.441533328
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.888347331
Short name T30
Test name
Test status
Simulation time 16412712 ps
CPU time 0.81 seconds
Started May 11 03:25:12 PM PDT 24
Finished May 11 03:25:14 PM PDT 24
Peak memory 215004 kb
Host smart-eeef7dcc-4c98-4924-a630-6c83b2f213a0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888347331 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.888347331
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1142530548
Short name T186
Test name
Test status
Simulation time 40102336 ps
CPU time 1 seconds
Started May 11 03:25:13 PM PDT 24
Finished May 11 03:25:15 PM PDT 24
Peak memory 215192 kb
Host smart-30c0fa5d-fac3-42c0-83fc-178e168e518d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142530548 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1142530548
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1670842619
Short name T254
Test name
Test status
Simulation time 32033307 ps
CPU time 0.84 seconds
Started May 11 03:25:12 PM PDT 24
Finished May 11 03:25:13 PM PDT 24
Peak memory 216256 kb
Host smart-2996ee03-15f9-423b-adbc-92103e2220dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670842619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1670842619
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2345308533
Short name T108
Test name
Test status
Simulation time 39243152 ps
CPU time 1.41 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:25:14 PM PDT 24
Peak memory 206232 kb
Host smart-46d29d20-349f-4015-8038-7bc62cd38e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345308533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2345308533
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3960173954
Short name T679
Test name
Test status
Simulation time 95898943 ps
CPU time 0.82 seconds
Started May 11 03:25:14 PM PDT 24
Finished May 11 03:25:15 PM PDT 24
Peak memory 215064 kb
Host smart-cd691635-5bdf-4bb2-92b6-d5f77f82f7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960173954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3960173954
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3118612972
Short name T464
Test name
Test status
Simulation time 39192251 ps
CPU time 0.82 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:25:13 PM PDT 24
Peak memory 205328 kb
Host smart-2ec13026-b087-4636-8a70-2802a3496bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118612972 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3118612972
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2227367185
Short name T566
Test name
Test status
Simulation time 216270581 ps
CPU time 2.64 seconds
Started May 11 03:25:18 PM PDT 24
Finished May 11 03:25:22 PM PDT 24
Peak memory 206356 kb
Host smart-f37a8127-e720-4339-b7be-d035ef968d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227367185 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2227367185
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.91495623
Short name T469
Test name
Test status
Simulation time 291044319195 ps
CPU time 796 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:38:28 PM PDT 24
Peak memory 216196 kb
Host smart-4afc78e4-de3a-48d4-8ec4-1ae8442f60b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91495623 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.91495623
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.edn_alert.1489551310
Short name T700
Test name
Test status
Simulation time 20288246 ps
CPU time 1.01 seconds
Started May 11 03:25:16 PM PDT 24
Finished May 11 03:25:18 PM PDT 24
Peak memory 206608 kb
Host smart-c0d1b16d-8c91-42c6-a99e-971f77095667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489551310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1489551310
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1797273778
Short name T505
Test name
Test status
Simulation time 17122031 ps
CPU time 0.97 seconds
Started May 11 03:25:16 PM PDT 24
Finished May 11 03:25:18 PM PDT 24
Peak memory 205240 kb
Host smart-9215500a-e8f7-44d2-8f1a-58b6b4c48ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797273778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1797273778
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3140913228
Short name T704
Test name
Test status
Simulation time 13668141 ps
CPU time 0.89 seconds
Started May 11 03:25:17 PM PDT 24
Finished May 11 03:25:18 PM PDT 24
Peak memory 215060 kb
Host smart-17c40dbe-aae5-46d0-b3b0-6776ba81841b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140913228 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3140913228
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.1013512588
Short name T200
Test name
Test status
Simulation time 19513103 ps
CPU time 1.04 seconds
Started May 11 03:25:15 PM PDT 24
Finished May 11 03:25:17 PM PDT 24
Peak memory 216636 kb
Host smart-69340ef3-5006-4be7-bbcd-26a8a0ec7aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013512588 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1013512588
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.4281022014
Short name T675
Test name
Test status
Simulation time 20396402 ps
CPU time 1.03 seconds
Started May 11 03:25:18 PM PDT 24
Finished May 11 03:25:19 PM PDT 24
Peak memory 205656 kb
Host smart-49098c95-b23f-4f5e-b0a4-c802786ca546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281022014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.4281022014
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1943460177
Short name T537
Test name
Test status
Simulation time 19621824 ps
CPU time 1.05 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:25:13 PM PDT 24
Peak memory 215308 kb
Host smart-5cdaa34c-5c20-44b3-a433-c3ebf9f7108a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943460177 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1943460177
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2094224144
Short name T314
Test name
Test status
Simulation time 23953510 ps
CPU time 0.84 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:25:13 PM PDT 24
Peak memory 205412 kb
Host smart-8e5761b9-4a9e-441c-8506-bcf06f5be07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094224144 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2094224144
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1940398692
Short name T583
Test name
Test status
Simulation time 82362227 ps
CPU time 2.2 seconds
Started May 11 03:25:19 PM PDT 24
Finished May 11 03:25:22 PM PDT 24
Peak memory 206328 kb
Host smart-2f038648-5e9e-43d8-a35c-0ae1d5e089f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940398692 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1940398692
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.94775546
Short name T24
Test name
Test status
Simulation time 38510934838 ps
CPU time 453.38 seconds
Started May 11 03:25:11 PM PDT 24
Finished May 11 03:32:46 PM PDT 24
Peak memory 215496 kb
Host smart-799bb19c-8c9d-4e16-bf43-f732675aed02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94775546 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.94775546
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_alert.3544406207
Short name T530
Test name
Test status
Simulation time 132447910 ps
CPU time 1 seconds
Started May 11 03:25:15 PM PDT 24
Finished May 11 03:25:17 PM PDT 24
Peak memory 205796 kb
Host smart-32b94f50-7955-4f60-83b6-dc892cdca980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544406207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3544406207
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3324599228
Short name T322
Test name
Test status
Simulation time 182435304 ps
CPU time 0.95 seconds
Started May 11 03:25:15 PM PDT 24
Finished May 11 03:25:16 PM PDT 24
Peak memory 206112 kb
Host smart-580c7c0a-24d4-4cca-a281-38217dc96e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324599228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3324599228
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.4113400668
Short name T121
Test name
Test status
Simulation time 21235978 ps
CPU time 0.86 seconds
Started May 11 03:25:20 PM PDT 24
Finished May 11 03:25:21 PM PDT 24
Peak memory 214968 kb
Host smart-5426d39a-798a-4930-9f0c-5fbd98dd0a95
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113400668 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4113400668
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3057462108
Short name T640
Test name
Test status
Simulation time 23128699 ps
CPU time 1.05 seconds
Started May 11 03:25:15 PM PDT 24
Finished May 11 03:25:16 PM PDT 24
Peak memory 215240 kb
Host smart-ddcb89cf-2e34-4005-ae3a-865d2db6dc4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057462108 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3057462108
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1730243161
Short name T261
Test name
Test status
Simulation time 21671486 ps
CPU time 0.93 seconds
Started May 11 03:25:18 PM PDT 24
Finished May 11 03:25:19 PM PDT 24
Peak memory 216492 kb
Host smart-4994d1c1-c9cc-4b4c-883c-7e3585004557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730243161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1730243161
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3779873765
Short name T585
Test name
Test status
Simulation time 17843194 ps
CPU time 0.89 seconds
Started May 11 03:25:13 PM PDT 24
Finished May 11 03:25:15 PM PDT 24
Peak memory 205452 kb
Host smart-04920855-156d-4538-9f5b-23eb8929a66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779873765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3779873765
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3384724925
Short name T2
Test name
Test status
Simulation time 25284896 ps
CPU time 0.99 seconds
Started May 11 03:25:17 PM PDT 24
Finished May 11 03:25:18 PM PDT 24
Peak memory 222152 kb
Host smart-79b65bf3-6c88-475e-808b-344b74914740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384724925 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3384724925
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2578995175
Short name T473
Test name
Test status
Simulation time 110844834 ps
CPU time 0.84 seconds
Started May 11 03:25:16 PM PDT 24
Finished May 11 03:25:18 PM PDT 24
Peak memory 205444 kb
Host smart-c31c296e-6686-48e4-a8a9-14f9fd409a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578995175 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2578995175
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.4130240927
Short name T504
Test name
Test status
Simulation time 158664170 ps
CPU time 3.43 seconds
Started May 11 03:25:17 PM PDT 24
Finished May 11 03:25:21 PM PDT 24
Peak memory 206736 kb
Host smart-c0b220d0-38af-43e5-9077-19a145c2f6d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130240927 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.4130240927
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1651685625
Short name T604
Test name
Test status
Simulation time 82170308535 ps
CPU time 632.43 seconds
Started May 11 03:25:17 PM PDT 24
Finished May 11 03:35:49 PM PDT 24
Peak memory 215168 kb
Host smart-894462df-ec85-49de-b9bf-62ba6f3c531b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651685625 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1651685625
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_alert.1053915590
Short name T144
Test name
Test status
Simulation time 59715108 ps
CPU time 0.97 seconds
Started May 11 03:25:18 PM PDT 24
Finished May 11 03:25:20 PM PDT 24
Peak memory 205796 kb
Host smart-9918e6ea-3036-4954-a068-26961b5cdce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053915590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1053915590
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2879581417
Short name T466
Test name
Test status
Simulation time 27049451 ps
CPU time 0.87 seconds
Started May 11 03:25:21 PM PDT 24
Finished May 11 03:25:23 PM PDT 24
Peak memory 205248 kb
Host smart-fc3f911d-4645-4002-a9a2-56161e00a764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879581417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2879581417
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1474444750
Short name T123
Test name
Test status
Simulation time 23939319 ps
CPU time 0.92 seconds
Started May 11 03:25:19 PM PDT 24
Finished May 11 03:25:20 PM PDT 24
Peak memory 215136 kb
Host smart-e5e01492-79d5-4501-a0f6-dc0b496ee836
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474444750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1474444750
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.234557506
Short name T43
Test name
Test status
Simulation time 21681893 ps
CPU time 0.98 seconds
Started May 11 03:25:25 PM PDT 24
Finished May 11 03:25:27 PM PDT 24
Peak memory 215176 kb
Host smart-999d96c2-58e2-439d-911d-262b15ea7250
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234557506 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.234557506
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2120187038
Short name T483
Test name
Test status
Simulation time 39721850 ps
CPU time 0.91 seconds
Started May 11 03:25:23 PM PDT 24
Finished May 11 03:25:24 PM PDT 24
Peak memory 216788 kb
Host smart-bcaca1e6-c658-4bde-ba51-ae27c834b253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120187038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2120187038
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.217314574
Short name T680
Test name
Test status
Simulation time 15721709 ps
CPU time 0.95 seconds
Started May 11 03:25:20 PM PDT 24
Finished May 11 03:25:21 PM PDT 24
Peak memory 205764 kb
Host smart-fc4387ff-b9a6-44bd-8e39-988c54a988b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217314574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.217314574
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2587143872
Short name T652
Test name
Test status
Simulation time 34687730 ps
CPU time 0.97 seconds
Started May 11 03:25:20 PM PDT 24
Finished May 11 03:25:21 PM PDT 24
Peak memory 222072 kb
Host smart-59b7e5bc-6a2a-4e18-b7ac-09d4edc53fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587143872 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2587143872
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.506269571
Short name T612
Test name
Test status
Simulation time 23085860 ps
CPU time 0.89 seconds
Started May 11 03:25:14 PM PDT 24
Finished May 11 03:25:15 PM PDT 24
Peak memory 205444 kb
Host smart-f74a0248-05bb-4b59-a365-029dcbd32f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506269571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.506269571
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1629272123
Short name T273
Test name
Test status
Simulation time 349512635 ps
CPU time 2.05 seconds
Started May 11 03:25:16 PM PDT 24
Finished May 11 03:25:19 PM PDT 24
Peak memory 206800 kb
Host smart-6be2857f-0f7f-479c-a352-aba4edc363d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629272123 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1629272123
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3286443182
Short name T160
Test name
Test status
Simulation time 78190727915 ps
CPU time 548.8 seconds
Started May 11 03:25:15 PM PDT 24
Finished May 11 03:34:25 PM PDT 24
Peak memory 215080 kb
Host smart-e2b6e89b-6e45-4ab7-a92c-fb1e386eb1b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286443182 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3286443182
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_alert.605159770
Short name T300
Test name
Test status
Simulation time 19095453 ps
CPU time 1.03 seconds
Started May 11 03:24:25 PM PDT 24
Finished May 11 03:24:26 PM PDT 24
Peak memory 206636 kb
Host smart-2ec4db11-d0a3-4450-b4f0-451a263c8dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605159770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.605159770
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1443295133
Short name T619
Test name
Test status
Simulation time 59342787 ps
CPU time 0.88 seconds
Started May 11 03:24:24 PM PDT 24
Finished May 11 03:24:25 PM PDT 24
Peak memory 205764 kb
Host smart-ab83c8da-168b-4fc7-9ca2-95e2324eb59e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443295133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1443295133
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3660416998
Short name T70
Test name
Test status
Simulation time 22222693 ps
CPU time 1.07 seconds
Started May 11 03:24:25 PM PDT 24
Finished May 11 03:24:27 PM PDT 24
Peak memory 215296 kb
Host smart-4b7b3484-ef6d-433b-9693-7e2860a8f1f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660416998 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3660416998
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2547928305
Short name T182
Test name
Test status
Simulation time 19106866 ps
CPU time 1.14 seconds
Started May 11 03:24:34 PM PDT 24
Finished May 11 03:24:36 PM PDT 24
Peak memory 215356 kb
Host smart-1ed43fda-0620-4d0b-a7d5-36447e51d507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547928305 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2547928305
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.168845336
Short name T492
Test name
Test status
Simulation time 22896183 ps
CPU time 0.89 seconds
Started May 11 03:24:20 PM PDT 24
Finished May 11 03:24:21 PM PDT 24
Peak memory 205564 kb
Host smart-fc226843-a965-4464-8157-e785cf0db133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168845336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.168845336
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.7262040
Short name T457
Test name
Test status
Simulation time 24887791 ps
CPU time 1.04 seconds
Started May 11 03:24:28 PM PDT 24
Finished May 11 03:24:30 PM PDT 24
Peak memory 222140 kb
Host smart-9a777024-20dc-4c0e-b9bc-a2ea80c7f043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7262040 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.7262040
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1122294757
Short name T295
Test name
Test status
Simulation time 22499106 ps
CPU time 0.91 seconds
Started May 11 03:24:20 PM PDT 24
Finished May 11 03:24:21 PM PDT 24
Peak memory 205376 kb
Host smart-f3f51954-c01f-4614-a08b-35402bb59070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122294757 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1122294757
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3931372171
Short name T23
Test name
Test status
Simulation time 1388660036 ps
CPU time 8.33 seconds
Started May 11 03:24:29 PM PDT 24
Finished May 11 03:24:38 PM PDT 24
Peak memory 234956 kb
Host smart-dfaf0c2f-c81a-4a93-a62d-dabf028fe4e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931372171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3931372171
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.861389668
Short name T633
Test name
Test status
Simulation time 15929938 ps
CPU time 0.93 seconds
Started May 11 03:24:20 PM PDT 24
Finished May 11 03:24:22 PM PDT 24
Peak memory 205524 kb
Host smart-546cca61-2269-4f73-9fab-44c526833071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861389668 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.861389668
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3251293572
Short name T683
Test name
Test status
Simulation time 177561211 ps
CPU time 3.89 seconds
Started May 11 03:24:21 PM PDT 24
Finished May 11 03:24:25 PM PDT 24
Peak memory 206456 kb
Host smart-47e06b9f-1baf-4250-9b2c-3d988b7dd00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251293572 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3251293572
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2156421946
Short name T644
Test name
Test status
Simulation time 66140952774 ps
CPU time 341.82 seconds
Started May 11 03:24:25 PM PDT 24
Finished May 11 03:30:08 PM PDT 24
Peak memory 216140 kb
Host smart-41af3a40-40c0-4841-8d04-3e47e23b777a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156421946 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2156421946
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3149732939
Short name T624
Test name
Test status
Simulation time 235756234 ps
CPU time 1.03 seconds
Started May 11 03:25:30 PM PDT 24
Finished May 11 03:25:31 PM PDT 24
Peak memory 205756 kb
Host smart-00a5db26-c01c-4967-97c0-ac3b6805bd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149732939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3149732939
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.707997212
Short name T317
Test name
Test status
Simulation time 22435110 ps
CPU time 0.82 seconds
Started May 11 03:25:25 PM PDT 24
Finished May 11 03:25:26 PM PDT 24
Peak memory 205608 kb
Host smart-917bd4ab-1377-4734-854f-f1e240b5a4c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707997212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.707997212
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1489895114
Short name T252
Test name
Test status
Simulation time 57388371 ps
CPU time 0.97 seconds
Started May 11 03:25:23 PM PDT 24
Finished May 11 03:25:24 PM PDT 24
Peak memory 215204 kb
Host smart-458b05cd-0792-429c-a4ac-881b8ffd6d16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489895114 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1489895114
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.570164983
Short name T255
Test name
Test status
Simulation time 19270712 ps
CPU time 1.05 seconds
Started May 11 03:25:20 PM PDT 24
Finished May 11 03:25:21 PM PDT 24
Peak memory 216500 kb
Host smart-49e3af0c-6bdb-414a-babb-a28075428254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570164983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.570164983
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3911971947
Short name T116
Test name
Test status
Simulation time 43697708 ps
CPU time 1.11 seconds
Started May 11 03:25:21 PM PDT 24
Finished May 11 03:25:23 PM PDT 24
Peak memory 205744 kb
Host smart-e7ba4ca7-b38e-47ec-8d55-2adac051e1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911971947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3911971947
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1876580163
Short name T715
Test name
Test status
Simulation time 25708287 ps
CPU time 0.97 seconds
Started May 11 03:25:21 PM PDT 24
Finished May 11 03:25:22 PM PDT 24
Peak memory 215092 kb
Host smart-bc73b756-b2ae-474b-a731-5a9235ea80eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876580163 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1876580163
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3254224325
Short name T638
Test name
Test status
Simulation time 130678027 ps
CPU time 0.89 seconds
Started May 11 03:25:20 PM PDT 24
Finished May 11 03:25:22 PM PDT 24
Peak memory 205240 kb
Host smart-0edca39b-9cef-492c-87ab-2c042957b34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254224325 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3254224325
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2506035509
Short name T690
Test name
Test status
Simulation time 31531832364 ps
CPU time 723.28 seconds
Started May 11 03:25:20 PM PDT 24
Finished May 11 03:37:24 PM PDT 24
Peak memory 215960 kb
Host smart-43f6c18e-6e9f-4d9f-9693-7d9c690c6c35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506035509 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2506035509
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2672019909
Short name T264
Test name
Test status
Simulation time 18835749 ps
CPU time 1.04 seconds
Started May 11 03:25:30 PM PDT 24
Finished May 11 03:25:31 PM PDT 24
Peak memory 205672 kb
Host smart-fa393c81-e80e-45af-ae6a-a2df0c56f440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672019909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2672019909
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2453733922
Short name T311
Test name
Test status
Simulation time 20721299 ps
CPU time 0.98 seconds
Started May 11 03:25:28 PM PDT 24
Finished May 11 03:25:29 PM PDT 24
Peak memory 205208 kb
Host smart-c4a35834-c5cf-4340-b0e1-0e20fda7e3e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453733922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2453733922
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1939841979
Short name T205
Test name
Test status
Simulation time 32328818 ps
CPU time 0.9 seconds
Started May 11 03:25:25 PM PDT 24
Finished May 11 03:25:27 PM PDT 24
Peak memory 214976 kb
Host smart-cd5bbde2-69f7-4b9d-bd64-916a00557d2d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939841979 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1939841979
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2121335189
Short name T194
Test name
Test status
Simulation time 81462649 ps
CPU time 0.99 seconds
Started May 11 03:25:25 PM PDT 24
Finished May 11 03:25:26 PM PDT 24
Peak memory 215308 kb
Host smart-30fd4021-2e94-4fd8-b55e-a9afd429cbdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121335189 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2121335189
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_genbits.15244543
Short name T10
Test name
Test status
Simulation time 30726355 ps
CPU time 1.04 seconds
Started May 11 03:25:30 PM PDT 24
Finished May 11 03:25:31 PM PDT 24
Peak memory 205580 kb
Host smart-8a71d525-3394-4cb3-a84d-d080f6b47909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15244543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.15244543
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.161462513
Short name T605
Test name
Test status
Simulation time 31042878 ps
CPU time 0.89 seconds
Started May 11 03:25:21 PM PDT 24
Finished May 11 03:25:23 PM PDT 24
Peak memory 215108 kb
Host smart-4bce5344-e0b1-4267-87d7-5d691c6bf53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161462513 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.161462513
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3775522834
Short name T602
Test name
Test status
Simulation time 49843784 ps
CPU time 0.9 seconds
Started May 11 03:25:20 PM PDT 24
Finished May 11 03:25:22 PM PDT 24
Peak memory 205372 kb
Host smart-9e6f40a8-ae51-4b49-94bd-b353547e2af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775522834 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3775522834
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3091809399
Short name T548
Test name
Test status
Simulation time 618030262 ps
CPU time 3.01 seconds
Started May 11 03:25:25 PM PDT 24
Finished May 11 03:25:29 PM PDT 24
Peak memory 206412 kb
Host smart-6df67c3e-b139-4885-b3f0-d53ec229bd85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091809399 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3091809399
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.987106068
Short name T681
Test name
Test status
Simulation time 19664731150 ps
CPU time 417.87 seconds
Started May 11 03:25:23 PM PDT 24
Finished May 11 03:32:21 PM PDT 24
Peak memory 216188 kb
Host smart-dfb5029b-c776-4ad3-a67c-467a62416640
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987106068 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.987106068
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.484349220
Short name T265
Test name
Test status
Simulation time 18951831 ps
CPU time 0.99 seconds
Started May 11 03:25:26 PM PDT 24
Finished May 11 03:25:27 PM PDT 24
Peak memory 206612 kb
Host smart-e6b18ae1-8c6a-45d7-9e70-2485fa4d16c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484349220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.484349220
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3459517355
Short name T318
Test name
Test status
Simulation time 17482070 ps
CPU time 0.99 seconds
Started May 11 03:25:27 PM PDT 24
Finished May 11 03:25:28 PM PDT 24
Peak memory 205780 kb
Host smart-a0ab5ba5-708f-42ef-a192-c80ae5f7e2e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459517355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3459517355
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3109030026
Short name T110
Test name
Test status
Simulation time 87954264 ps
CPU time 1.07 seconds
Started May 11 03:25:24 PM PDT 24
Finished May 11 03:25:25 PM PDT 24
Peak memory 215176 kb
Host smart-e8566f10-5b43-42ba-80a1-cd489390325b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109030026 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3109030026
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.479128941
Short name T669
Test name
Test status
Simulation time 73842636 ps
CPU time 1.16 seconds
Started May 11 03:25:22 PM PDT 24
Finished May 11 03:25:23 PM PDT 24
Peak memory 222628 kb
Host smart-01f325e2-0fd0-4f00-a608-85f795bfb19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479128941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.479128941
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2819792722
Short name T565
Test name
Test status
Simulation time 69920218 ps
CPU time 0.94 seconds
Started May 11 03:25:24 PM PDT 24
Finished May 11 03:25:25 PM PDT 24
Peak memory 205388 kb
Host smart-a3617c08-ab87-4cba-ba5f-36b2382fe594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819792722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2819792722
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3579447803
Short name T689
Test name
Test status
Simulation time 17895754 ps
CPU time 1.06 seconds
Started May 11 03:25:24 PM PDT 24
Finished May 11 03:25:25 PM PDT 24
Peak memory 215280 kb
Host smart-c2b3a702-41b4-426e-86cf-335fa546038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579447803 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3579447803
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.4137172046
Short name T646
Test name
Test status
Simulation time 33746561 ps
CPU time 0.88 seconds
Started May 11 03:25:24 PM PDT 24
Finished May 11 03:25:25 PM PDT 24
Peak memory 205464 kb
Host smart-ff54742a-d35a-4252-b51b-00aeb5383a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137172046 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.4137172046
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.272212625
Short name T499
Test name
Test status
Simulation time 570799424 ps
CPU time 3.33 seconds
Started May 11 03:25:23 PM PDT 24
Finished May 11 03:25:27 PM PDT 24
Peak memory 206220 kb
Host smart-29db2363-99cf-4495-9ea4-49700bcab1fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272212625 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.272212625
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1570901848
Short name T651
Test name
Test status
Simulation time 240478212099 ps
CPU time 1144.14 seconds
Started May 11 03:25:25 PM PDT 24
Finished May 11 03:44:29 PM PDT 24
Peak memory 217536 kb
Host smart-12ec7b63-7092-492a-94dc-f8a48a733646
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570901848 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1570901848
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2204749404
Short name T671
Test name
Test status
Simulation time 62711284 ps
CPU time 0.99 seconds
Started May 11 03:25:25 PM PDT 24
Finished May 11 03:25:27 PM PDT 24
Peak memory 205948 kb
Host smart-61a1daef-6a91-4418-8974-efc7845a8a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204749404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2204749404
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1846705512
Short name T560
Test name
Test status
Simulation time 27323406 ps
CPU time 0.85 seconds
Started May 11 03:25:29 PM PDT 24
Finished May 11 03:25:31 PM PDT 24
Peak memory 205116 kb
Host smart-47247c3b-35f7-4636-89d2-e7742429df50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846705512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1846705512
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1912216544
Short name T45
Test name
Test status
Simulation time 17662113 ps
CPU time 0.84 seconds
Started May 11 03:25:31 PM PDT 24
Finished May 11 03:25:32 PM PDT 24
Peak memory 206792 kb
Host smart-e96d3e53-884d-4fff-b9d9-761850d015e3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912216544 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1912216544
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1725172320
Short name T554
Test name
Test status
Simulation time 24353979 ps
CPU time 0.98 seconds
Started May 11 03:25:29 PM PDT 24
Finished May 11 03:25:30 PM PDT 24
Peak memory 215188 kb
Host smart-4594051b-dfe1-4810-b7ff-73629102fda2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725172320 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1725172320
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2459679375
Short name T687
Test name
Test status
Simulation time 27262596 ps
CPU time 1.23 seconds
Started May 11 03:25:28 PM PDT 24
Finished May 11 03:25:30 PM PDT 24
Peak memory 229388 kb
Host smart-09d73ea1-eb22-450c-b426-ab165289ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459679375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2459679375
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.238424998
Short name T39
Test name
Test status
Simulation time 92821196 ps
CPU time 1.16 seconds
Started May 11 03:25:25 PM PDT 24
Finished May 11 03:25:27 PM PDT 24
Peak memory 206244 kb
Host smart-a3ef6fd0-789c-4628-b210-e4d5629ae456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238424998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.238424998
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.783206662
Short name T316
Test name
Test status
Simulation time 21057368 ps
CPU time 1.15 seconds
Started May 11 03:25:23 PM PDT 24
Finished May 11 03:25:25 PM PDT 24
Peak memory 222164 kb
Host smart-c416e72b-a069-49f4-8f51-8279cea09669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783206662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.783206662
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3515707137
Short name T315
Test name
Test status
Simulation time 15218907 ps
CPU time 0.93 seconds
Started May 11 03:25:23 PM PDT 24
Finished May 11 03:25:25 PM PDT 24
Peak memory 205284 kb
Host smart-6b92ba1b-bb89-4d84-bf17-8d9385231388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515707137 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3515707137
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1132801901
Short name T172
Test name
Test status
Simulation time 116342934 ps
CPU time 1.61 seconds
Started May 11 03:25:25 PM PDT 24
Finished May 11 03:25:27 PM PDT 24
Peak memory 206144 kb
Host smart-5b699cae-c2d7-4126-8e7f-c6196678546d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132801901 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1132801901
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3260168225
Short name T603
Test name
Test status
Simulation time 38712147703 ps
CPU time 859.34 seconds
Started May 11 03:25:25 PM PDT 24
Finished May 11 03:39:45 PM PDT 24
Peak memory 215160 kb
Host smart-a617652c-7faa-4610-b3ee-35d93da7d777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260168225 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3260168225
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1502980347
Short name T128
Test name
Test status
Simulation time 31866148 ps
CPU time 0.99 seconds
Started May 11 03:25:28 PM PDT 24
Finished May 11 03:25:29 PM PDT 24
Peak memory 205796 kb
Host smart-2d029892-d34f-42f8-b95d-d3cff19838db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502980347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1502980347
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2842168689
Short name T608
Test name
Test status
Simulation time 34871618 ps
CPU time 0.82 seconds
Started May 11 03:25:37 PM PDT 24
Finished May 11 03:25:39 PM PDT 24
Peak memory 205616 kb
Host smart-48787668-3685-4ff0-83b3-d1c35a446dc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842168689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2842168689
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.246957847
Short name T114
Test name
Test status
Simulation time 12878415 ps
CPU time 0.88 seconds
Started May 11 03:25:31 PM PDT 24
Finished May 11 03:25:32 PM PDT 24
Peak memory 215180 kb
Host smart-6a9fff26-4c80-4879-a3a4-0a55927fae36
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246957847 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.246957847
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.4167140278
Short name T283
Test name
Test status
Simulation time 174198041 ps
CPU time 1.08 seconds
Started May 11 03:25:32 PM PDT 24
Finished May 11 03:25:33 PM PDT 24
Peak memory 215256 kb
Host smart-1c0229c8-17d0-4e7b-b3fd-b8cf74309e07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167140278 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.4167140278
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3177603751
Short name T187
Test name
Test status
Simulation time 31576515 ps
CPU time 1.03 seconds
Started May 11 03:25:30 PM PDT 24
Finished May 11 03:25:31 PM PDT 24
Peak memory 216532 kb
Host smart-370622b4-ae19-4a3d-8c74-2758b16539a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177603751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3177603751
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_intr.552107674
Short name T523
Test name
Test status
Simulation time 20885334 ps
CPU time 1.14 seconds
Started May 11 03:25:31 PM PDT 24
Finished May 11 03:25:32 PM PDT 24
Peak memory 222364 kb
Host smart-9ee673a7-a4c8-4f16-8d79-bc793c8a60fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552107674 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.552107674
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.88393080
Short name T629
Test name
Test status
Simulation time 13157343 ps
CPU time 0.87 seconds
Started May 11 03:25:30 PM PDT 24
Finished May 11 03:25:32 PM PDT 24
Peak memory 205280 kb
Host smart-79ecb961-7bd5-4469-893d-42f80ad38287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88393080 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.88393080
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.491774450
Short name T538
Test name
Test status
Simulation time 1114199042 ps
CPU time 3.76 seconds
Started May 11 03:25:28 PM PDT 24
Finished May 11 03:25:32 PM PDT 24
Peak memory 206664 kb
Host smart-46659ec8-9c0b-47ff-8ff4-9361ce7564d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491774450 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.491774450
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3213513965
Short name T25
Test name
Test status
Simulation time 30548694211 ps
CPU time 191.2 seconds
Started May 11 03:25:29 PM PDT 24
Finished May 11 03:28:40 PM PDT 24
Peak memory 215176 kb
Host smart-ca193acd-83d2-4dd3-b9a3-627e493d51ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213513965 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3213513965
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1160585233
Short name T267
Test name
Test status
Simulation time 36525923 ps
CPU time 1.03 seconds
Started May 11 03:25:37 PM PDT 24
Finished May 11 03:25:39 PM PDT 24
Peak memory 205836 kb
Host smart-5f8a8f5e-64b1-4dee-b1a8-ee1cc73c6271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160585233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1160585233
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2716742036
Short name T601
Test name
Test status
Simulation time 33066696 ps
CPU time 1.19 seconds
Started May 11 03:25:33 PM PDT 24
Finished May 11 03:25:35 PM PDT 24
Peak memory 205360 kb
Host smart-dab5bfad-3303-4268-8999-54e864173f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716742036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2716742036
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2479569153
Short name T684
Test name
Test status
Simulation time 98113629 ps
CPU time 1.08 seconds
Started May 11 03:25:36 PM PDT 24
Finished May 11 03:25:38 PM PDT 24
Peak memory 215248 kb
Host smart-482d5686-1c18-4107-97f5-7e5e62513f0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479569153 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2479569153
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3111924729
Short name T488
Test name
Test status
Simulation time 18287350 ps
CPU time 1.04 seconds
Started May 11 03:25:35 PM PDT 24
Finished May 11 03:25:37 PM PDT 24
Peak memory 216460 kb
Host smart-84f0f997-9755-4073-ba4d-6c15cf9dfb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111924729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3111924729
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2322549012
Short name T41
Test name
Test status
Simulation time 138296669 ps
CPU time 0.99 seconds
Started May 11 03:25:37 PM PDT 24
Finished May 11 03:25:39 PM PDT 24
Peak memory 205372 kb
Host smart-037c92eb-06d7-41af-acee-4651379c6a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322549012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2322549012
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2860076854
Short name T491
Test name
Test status
Simulation time 60116832 ps
CPU time 0.95 seconds
Started May 11 03:25:33 PM PDT 24
Finished May 11 03:25:35 PM PDT 24
Peak memory 221984 kb
Host smart-92954a44-b6b5-430e-bbb0-3da3416d121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860076854 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2860076854
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2958964958
Short name T509
Test name
Test status
Simulation time 112304593 ps
CPU time 0.91 seconds
Started May 11 03:25:33 PM PDT 24
Finished May 11 03:25:34 PM PDT 24
Peak memory 205352 kb
Host smart-6a5050f8-5d4f-415a-9347-ff80f2814262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958964958 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2958964958
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1128914211
Short name T211
Test name
Test status
Simulation time 45527849 ps
CPU time 1.54 seconds
Started May 11 03:25:36 PM PDT 24
Finished May 11 03:25:39 PM PDT 24
Peak memory 206268 kb
Host smart-f7b52028-d2ba-4e62-a8c2-2492a1eba052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128914211 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1128914211
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2945243107
Short name T698
Test name
Test status
Simulation time 42347826039 ps
CPU time 481.09 seconds
Started May 11 03:25:36 PM PDT 24
Finished May 11 03:33:38 PM PDT 24
Peak memory 215096 kb
Host smart-6c32821d-3707-49d3-9e6d-3cb9d1ab0c2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945243107 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2945243107
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1623755059
Short name T132
Test name
Test status
Simulation time 55139166 ps
CPU time 0.91 seconds
Started May 11 03:25:45 PM PDT 24
Finished May 11 03:25:46 PM PDT 24
Peak memory 205924 kb
Host smart-7b202e9d-c80b-484b-b50b-f10c9020e352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623755059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1623755059
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3320367958
Short name T313
Test name
Test status
Simulation time 21340069 ps
CPU time 1.03 seconds
Started May 11 03:25:37 PM PDT 24
Finished May 11 03:25:39 PM PDT 24
Peak memory 205280 kb
Host smart-956f789f-6153-4572-8632-31b3de62f823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320367958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3320367958
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1427443915
Short name T153
Test name
Test status
Simulation time 22829182 ps
CPU time 0.9 seconds
Started May 11 03:25:39 PM PDT 24
Finished May 11 03:25:41 PM PDT 24
Peak memory 215024 kb
Host smart-7e6539be-ca71-46ea-a23a-2b6e0501cf5e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427443915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1427443915
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.992912742
Short name T72
Test name
Test status
Simulation time 27521508 ps
CPU time 1.01 seconds
Started May 11 03:25:41 PM PDT 24
Finished May 11 03:25:43 PM PDT 24
Peak memory 215160 kb
Host smart-252f1045-c714-424d-ac80-7bbc2556c60f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992912742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.992912742
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3561240752
Short name T693
Test name
Test status
Simulation time 33428958 ps
CPU time 0.83 seconds
Started May 11 03:25:39 PM PDT 24
Finished May 11 03:25:40 PM PDT 24
Peak memory 216152 kb
Host smart-75a1aa7c-1f6f-4f30-80f3-747eb77d9fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561240752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3561240752
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3167519774
Short name T11
Test name
Test status
Simulation time 28608187 ps
CPU time 1.02 seconds
Started May 11 03:25:35 PM PDT 24
Finished May 11 03:25:36 PM PDT 24
Peak memory 205624 kb
Host smart-1e7dba4c-d1e3-4df8-8e4e-889db125a9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167519774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3167519774
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2349214836
Short name T670
Test name
Test status
Simulation time 27239424 ps
CPU time 1.02 seconds
Started May 11 03:25:34 PM PDT 24
Finished May 11 03:25:36 PM PDT 24
Peak memory 222192 kb
Host smart-43d75605-600b-4935-a3f0-9f4ca13b0fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349214836 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2349214836
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3059389933
Short name T58
Test name
Test status
Simulation time 13474171 ps
CPU time 0.88 seconds
Started May 11 03:25:36 PM PDT 24
Finished May 11 03:25:37 PM PDT 24
Peak memory 205464 kb
Host smart-56e7a0de-9777-484a-bac0-a8e4607cecbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059389933 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3059389933
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.348548146
Short name T169
Test name
Test status
Simulation time 164256093 ps
CPU time 3.32 seconds
Started May 11 03:25:35 PM PDT 24
Finished May 11 03:25:39 PM PDT 24
Peak memory 206232 kb
Host smart-a119ae06-5d11-4585-b310-face3663b12b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348548146 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.348548146
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.607855216
Short name T485
Test name
Test status
Simulation time 24903546945 ps
CPU time 640.57 seconds
Started May 11 03:25:34 PM PDT 24
Finished May 11 03:36:15 PM PDT 24
Peak memory 215848 kb
Host smart-dd9b85a9-8c09-42c7-9fbc-196e4529a51e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607855216 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.607855216
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2703530102
Short name T107
Test name
Test status
Simulation time 40962795 ps
CPU time 1.02 seconds
Started May 11 03:25:38 PM PDT 24
Finished May 11 03:25:40 PM PDT 24
Peak memory 206552 kb
Host smart-db024a8c-add3-42a6-bfea-dddf578e4502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703530102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2703530102
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1336002591
Short name T584
Test name
Test status
Simulation time 47104635 ps
CPU time 0.81 seconds
Started May 11 03:25:46 PM PDT 24
Finished May 11 03:25:48 PM PDT 24
Peak memory 205332 kb
Host smart-f879f439-6c55-418e-89a3-14e4754b4d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336002591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1336002591
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.4272276813
Short name T155
Test name
Test status
Simulation time 21874346 ps
CPU time 0.87 seconds
Started May 11 03:25:40 PM PDT 24
Finished May 11 03:25:41 PM PDT 24
Peak memory 215016 kb
Host smart-0754423d-a512-4a3c-b45a-84acd20f5c5c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272276813 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.4272276813
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3751525557
Short name T658
Test name
Test status
Simulation time 26506383 ps
CPU time 0.92 seconds
Started May 11 03:25:46 PM PDT 24
Finished May 11 03:25:48 PM PDT 24
Peak memory 215196 kb
Host smart-6095702a-6e18-41c4-889a-c383b9193353
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751525557 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3751525557
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.499412276
Short name T696
Test name
Test status
Simulation time 30728904 ps
CPU time 0.89 seconds
Started May 11 03:25:46 PM PDT 24
Finished May 11 03:25:47 PM PDT 24
Peak memory 216584 kb
Host smart-8ffd1ddb-4cc0-4159-a9fc-c24d3b419048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499412276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.499412276
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1828486783
Short name T292
Test name
Test status
Simulation time 39919302 ps
CPU time 0.86 seconds
Started May 11 03:25:46 PM PDT 24
Finished May 11 03:25:48 PM PDT 24
Peak memory 205512 kb
Host smart-d3cc799b-bd74-49c8-853a-ad5c413f5758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828486783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1828486783
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3708222792
Short name T27
Test name
Test status
Simulation time 22436790 ps
CPU time 1.12 seconds
Started May 11 03:25:37 PM PDT 24
Finished May 11 03:25:39 PM PDT 24
Peak memory 215276 kb
Host smart-ba83e3bf-a19e-4b53-9ac4-b159ab95fa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708222792 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3708222792
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2518103679
Short name T525
Test name
Test status
Simulation time 55622505 ps
CPU time 0.93 seconds
Started May 11 03:25:39 PM PDT 24
Finished May 11 03:25:41 PM PDT 24
Peak memory 205304 kb
Host smart-1b8fa55f-a132-4fd2-833d-5990e49432ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518103679 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2518103679
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1421112
Short name T270
Test name
Test status
Simulation time 194277901 ps
CPU time 2.44 seconds
Started May 11 03:25:42 PM PDT 24
Finished May 11 03:25:45 PM PDT 24
Peak memory 206700 kb
Host smart-56463786-d99a-4c7a-b463-574f3fecf57e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421112 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1421112
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.880278003
Short name T489
Test name
Test status
Simulation time 27412684672 ps
CPU time 739.47 seconds
Started May 11 03:25:38 PM PDT 24
Finished May 11 03:37:58 PM PDT 24
Peak memory 215332 kb
Host smart-aae6953c-4151-4ce3-b035-e43074fb584e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880278003 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.880278003
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.149291000
Short name T541
Test name
Test status
Simulation time 55955606 ps
CPU time 0.99 seconds
Started May 11 03:25:46 PM PDT 24
Finished May 11 03:25:48 PM PDT 24
Peak memory 206620 kb
Host smart-3993a4a6-a9ce-4c8f-80d8-658713bcf307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149291000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.149291000
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1294316461
Short name T654
Test name
Test status
Simulation time 11608080 ps
CPU time 0.86 seconds
Started May 11 03:25:48 PM PDT 24
Finished May 11 03:25:49 PM PDT 24
Peak memory 204936 kb
Host smart-e2f1e7ee-813d-4fa6-b8e5-57a22ec40095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294316461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1294316461
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_err.1725631484
Short name T286
Test name
Test status
Simulation time 46463540 ps
CPU time 1.16 seconds
Started May 11 03:25:43 PM PDT 24
Finished May 11 03:25:45 PM PDT 24
Peak memory 215348 kb
Host smart-fd3b689c-4fe3-4cd7-8ddb-2519e29289f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725631484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1725631484
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2709362386
Short name T498
Test name
Test status
Simulation time 42499201 ps
CPU time 0.95 seconds
Started May 11 03:25:39 PM PDT 24
Finished May 11 03:25:41 PM PDT 24
Peak memory 205664 kb
Host smart-0feda6b8-0053-49a8-b1bd-68b8c6a37482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709362386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2709362386
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1575110178
Short name T468
Test name
Test status
Simulation time 25303756 ps
CPU time 0.97 seconds
Started May 11 03:25:42 PM PDT 24
Finished May 11 03:25:44 PM PDT 24
Peak memory 215068 kb
Host smart-0daf0974-3dca-4eb4-ad2a-6c69597f13ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575110178 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1575110178
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1794736726
Short name T558
Test name
Test status
Simulation time 90389782 ps
CPU time 0.81 seconds
Started May 11 03:25:41 PM PDT 24
Finished May 11 03:25:43 PM PDT 24
Peak memory 205312 kb
Host smart-54ec3c6d-7c2d-401e-a3f1-c7ca70771102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794736726 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1794736726
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.848124711
Short name T124
Test name
Test status
Simulation time 57150972 ps
CPU time 1.68 seconds
Started May 11 03:25:44 PM PDT 24
Finished May 11 03:25:46 PM PDT 24
Peak memory 206012 kb
Host smart-46fcaef2-d5ab-4639-b227-d187729df419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848124711 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.848124711
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.424262748
Short name T503
Test name
Test status
Simulation time 466872261082 ps
CPU time 2883.21 seconds
Started May 11 03:25:43 PM PDT 24
Finished May 11 04:13:47 PM PDT 24
Peak memory 229840 kb
Host smart-f09a2d4c-f9a3-4008-9549-24cd8dd4107a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424262748 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.424262748
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2804559636
Short name T587
Test name
Test status
Simulation time 85702309 ps
CPU time 0.94 seconds
Started May 11 03:25:47 PM PDT 24
Finished May 11 03:25:49 PM PDT 24
Peak memory 206584 kb
Host smart-7e5c3416-407c-4e6b-8e45-f1c770b7198f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804559636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2804559636
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1997327268
Short name T323
Test name
Test status
Simulation time 108171951 ps
CPU time 0.85 seconds
Started May 11 03:25:49 PM PDT 24
Finished May 11 03:25:51 PM PDT 24
Peak memory 205608 kb
Host smart-4601f7e9-63e4-4577-9f56-775e0b8ce3a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997327268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1997327268
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3451420458
Short name T64
Test name
Test status
Simulation time 33494872 ps
CPU time 0.83 seconds
Started May 11 03:25:44 PM PDT 24
Finished May 11 03:25:46 PM PDT 24
Peak memory 214988 kb
Host smart-b0d4c9d7-7c70-434c-b23c-c75947bb1a85
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451420458 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3451420458
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.196160605
Short name T284
Test name
Test status
Simulation time 22410595 ps
CPU time 1.06 seconds
Started May 11 03:25:50 PM PDT 24
Finished May 11 03:25:52 PM PDT 24
Peak memory 215244 kb
Host smart-f1af9650-dc48-495a-9355-9b45eae34ee2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196160605 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.196160605
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3811357823
Short name T185
Test name
Test status
Simulation time 47469409 ps
CPU time 1.01 seconds
Started May 11 03:25:43 PM PDT 24
Finished May 11 03:25:44 PM PDT 24
Peak memory 215288 kb
Host smart-13dcbd79-1e16-4516-9683-788136df3cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811357823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3811357823
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.4126478043
Short name T293
Test name
Test status
Simulation time 117591188 ps
CPU time 0.99 seconds
Started May 11 03:25:44 PM PDT 24
Finished May 11 03:25:46 PM PDT 24
Peak memory 205624 kb
Host smart-b8c44e27-840c-4194-8e85-b5d0fc4c3493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126478043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4126478043
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_smoke.3191221411
Short name T519
Test name
Test status
Simulation time 26695448 ps
CPU time 0.92 seconds
Started May 11 03:25:42 PM PDT 24
Finished May 11 03:25:43 PM PDT 24
Peak memory 205164 kb
Host smart-4664f018-7276-458f-a65b-762d1e9237e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191221411 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3191221411
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1896842067
Short name T513
Test name
Test status
Simulation time 986992488 ps
CPU time 2.54 seconds
Started May 11 03:25:50 PM PDT 24
Finished May 11 03:25:53 PM PDT 24
Peak memory 206752 kb
Host smart-fcc1b666-d141-4331-a5fc-04494d9139c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896842067 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1896842067
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_alert.2577778033
Short name T105
Test name
Test status
Simulation time 17446189 ps
CPU time 0.98 seconds
Started May 11 03:24:34 PM PDT 24
Finished May 11 03:24:36 PM PDT 24
Peak memory 205644 kb
Host smart-80592aa0-2807-4b72-89e6-8f91499f494f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577778033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2577778033
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.544131122
Short name T578
Test name
Test status
Simulation time 13411928 ps
CPU time 0.87 seconds
Started May 11 03:24:33 PM PDT 24
Finished May 11 03:24:35 PM PDT 24
Peak memory 205100 kb
Host smart-94c984a2-5845-4378-aa97-d3e1f8e5798d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544131122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.544131122
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2200326205
Short name T103
Test name
Test status
Simulation time 25247217 ps
CPU time 0.93 seconds
Started May 11 03:24:27 PM PDT 24
Finished May 11 03:24:28 PM PDT 24
Peak memory 214988 kb
Host smart-7fd955e3-da01-4477-b5de-73e7d81ab674
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200326205 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2200326205
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2913219242
Short name T193
Test name
Test status
Simulation time 44995664 ps
CPU time 1.05 seconds
Started May 11 03:24:28 PM PDT 24
Finished May 11 03:24:29 PM PDT 24
Peak memory 215200 kb
Host smart-0fb0b927-8ac8-4541-82c2-eace69ea6bee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913219242 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2913219242
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3933452665
Short name T592
Test name
Test status
Simulation time 37152641 ps
CPU time 1.06 seconds
Started May 11 03:24:27 PM PDT 24
Finished May 11 03:24:28 PM PDT 24
Peak memory 216712 kb
Host smart-4a4d073b-1ee5-4a1d-9ec6-b2f66c32c58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933452665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3933452665
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2476670159
Short name T9
Test name
Test status
Simulation time 71302192 ps
CPU time 1.06 seconds
Started May 11 03:24:33 PM PDT 24
Finished May 11 03:24:35 PM PDT 24
Peak memory 205768 kb
Host smart-9fb0ccf6-0d59-4cce-bc68-d29606d6856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476670159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2476670159
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1294595189
Short name T125
Test name
Test status
Simulation time 31271901 ps
CPU time 0.82 seconds
Started May 11 03:24:32 PM PDT 24
Finished May 11 03:24:34 PM PDT 24
Peak memory 214952 kb
Host smart-541a2aed-b5ca-43f5-9670-402dbde61c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294595189 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1294595189
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2444889856
Short name T22
Test name
Test status
Simulation time 367632751 ps
CPU time 5.39 seconds
Started May 11 03:24:26 PM PDT 24
Finished May 11 03:24:32 PM PDT 24
Peak memory 234568 kb
Host smart-7d00aa46-5b25-48ff-9a3d-a58fcfd21f58
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444889856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2444889856
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.4246806598
Short name T511
Test name
Test status
Simulation time 27392582 ps
CPU time 0.91 seconds
Started May 11 03:24:30 PM PDT 24
Finished May 11 03:24:31 PM PDT 24
Peak memory 205364 kb
Host smart-08ba8bc7-9356-4584-8727-3927d3416774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246806598 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.4246806598
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2279516586
Short name T627
Test name
Test status
Simulation time 71352513 ps
CPU time 1.12 seconds
Started May 11 03:24:25 PM PDT 24
Finished May 11 03:24:26 PM PDT 24
Peak memory 205500 kb
Host smart-653828a6-c253-4827-808f-6fc8c2ba1651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279516586 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2279516586
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1513862717
Short name T611
Test name
Test status
Simulation time 117013517178 ps
CPU time 1324.68 seconds
Started May 11 03:24:29 PM PDT 24
Finished May 11 03:46:34 PM PDT 24
Peak memory 219152 kb
Host smart-9e9f85f2-4005-4be5-b110-c85d9a8a5f8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513862717 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1513862717
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.4246215013
Short name T98
Test name
Test status
Simulation time 38880149 ps
CPU time 0.96 seconds
Started May 11 03:25:49 PM PDT 24
Finished May 11 03:25:51 PM PDT 24
Peak memory 206548 kb
Host smart-2b11641b-626a-4ab2-ade5-7a706386484d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246215013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.4246215013
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2668988131
Short name T467
Test name
Test status
Simulation time 15799357 ps
CPU time 0.93 seconds
Started May 11 03:25:50 PM PDT 24
Finished May 11 03:25:52 PM PDT 24
Peak memory 205244 kb
Host smart-3627f7d7-02a0-4964-a857-37095fadb264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668988131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2668988131
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2288080325
Short name T113
Test name
Test status
Simulation time 86506325 ps
CPU time 0.98 seconds
Started May 11 03:25:49 PM PDT 24
Finished May 11 03:25:51 PM PDT 24
Peak memory 215208 kb
Host smart-630257c7-0c3a-4a43-82ea-465712ce9d1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288080325 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2288080325
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.141685728
Short name T210
Test name
Test status
Simulation time 19104162 ps
CPU time 1.39 seconds
Started May 11 03:25:50 PM PDT 24
Finished May 11 03:25:52 PM PDT 24
Peak memory 216524 kb
Host smart-1b00f9cc-b385-47fd-ad99-d6cf0b9a89a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141685728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.141685728
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_intr.4242746710
Short name T478
Test name
Test status
Simulation time 23542765 ps
CPU time 1.07 seconds
Started May 11 03:25:46 PM PDT 24
Finished May 11 03:25:48 PM PDT 24
Peak memory 215272 kb
Host smart-a50adb9b-b0a2-44bf-b4da-a19ffb91cfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242746710 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.4242746710
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2965060953
Short name T462
Test name
Test status
Simulation time 78061189 ps
CPU time 0.86 seconds
Started May 11 03:25:44 PM PDT 24
Finished May 11 03:25:46 PM PDT 24
Peak memory 205076 kb
Host smart-5c6c972f-2b18-470a-8b1c-a9ca9d4a58fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965060953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2965060953
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.465335576
Short name T476
Test name
Test status
Simulation time 1254158995 ps
CPU time 3.57 seconds
Started May 11 03:25:42 PM PDT 24
Finished May 11 03:25:46 PM PDT 24
Peak memory 206672 kb
Host smart-10f1f94e-d35c-478b-811a-9bfbcb68f93e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465335576 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.465335576
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.226251678
Short name T694
Test name
Test status
Simulation time 41471845405 ps
CPU time 914.94 seconds
Started May 11 03:25:44 PM PDT 24
Finished May 11 03:41:00 PM PDT 24
Peak memory 215948 kb
Host smart-1c08008b-06e1-4848-8875-e6c25b02220a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226251678 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.226251678
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1895611345
Short name T621
Test name
Test status
Simulation time 77116634 ps
CPU time 1.11 seconds
Started May 11 03:25:50 PM PDT 24
Finished May 11 03:25:52 PM PDT 24
Peak memory 206604 kb
Host smart-1dfd39e7-e634-47e0-a4fd-342cbdb22856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895611345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1895611345
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1160401460
Short name T653
Test name
Test status
Simulation time 31261763 ps
CPU time 0.9 seconds
Started May 11 03:25:49 PM PDT 24
Finished May 11 03:25:51 PM PDT 24
Peak memory 205244 kb
Host smart-ad0a9389-9576-4c65-9035-95ddc78a4fe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160401460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1160401460
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3968721582
Short name T258
Test name
Test status
Simulation time 20190441 ps
CPU time 0.84 seconds
Started May 11 03:25:48 PM PDT 24
Finished May 11 03:25:50 PM PDT 24
Peak memory 214976 kb
Host smart-294500ce-e820-4e6a-81aa-bf304e4fd09b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968721582 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3968721582
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.925956584
Short name T181
Test name
Test status
Simulation time 31108207 ps
CPU time 0.94 seconds
Started May 11 03:25:50 PM PDT 24
Finished May 11 03:25:52 PM PDT 24
Peak memory 215240 kb
Host smart-6065a83c-968c-4754-82a3-34c21af6370c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925956584 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.925956584
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.660756057
Short name T595
Test name
Test status
Simulation time 40755117 ps
CPU time 1.11 seconds
Started May 11 03:25:50 PM PDT 24
Finished May 11 03:25:52 PM PDT 24
Peak memory 217648 kb
Host smart-62a6ed15-9e4c-4575-a870-6cc2544893bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660756057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.660756057
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.939963099
Short name T594
Test name
Test status
Simulation time 36196306 ps
CPU time 0.94 seconds
Started May 11 03:25:48 PM PDT 24
Finished May 11 03:25:50 PM PDT 24
Peak memory 205644 kb
Host smart-8629248e-f7f5-49ee-bc8c-29c44009e8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939963099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.939963099
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.838562320
Short name T706
Test name
Test status
Simulation time 18032673 ps
CPU time 1.01 seconds
Started May 11 03:25:52 PM PDT 24
Finished May 11 03:25:53 PM PDT 24
Peak memory 215276 kb
Host smart-42a75923-8665-44aa-b92b-8aed743cdc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838562320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.838562320
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2931996092
Short name T707
Test name
Test status
Simulation time 13429891 ps
CPU time 0.9 seconds
Started May 11 03:26:05 PM PDT 24
Finished May 11 03:26:06 PM PDT 24
Peak memory 205272 kb
Host smart-1b35ec72-00e6-4948-8e9c-9116b05204ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931996092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2931996092
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.4037903142
Short name T142
Test name
Test status
Simulation time 152017617 ps
CPU time 3.31 seconds
Started May 11 03:25:47 PM PDT 24
Finished May 11 03:25:51 PM PDT 24
Peak memory 206736 kb
Host smart-5b27b9be-0a4c-441f-8217-34c67a9fbed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037903142 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.4037903142
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert.918835531
Short name T129
Test name
Test status
Simulation time 20923030 ps
CPU time 1.08 seconds
Started May 11 03:25:51 PM PDT 24
Finished May 11 03:25:52 PM PDT 24
Peak memory 206000 kb
Host smart-96ed7406-b956-4800-a65a-561408902769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918835531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.918835531
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2715456117
Short name T145
Test name
Test status
Simulation time 25928040 ps
CPU time 0.88 seconds
Started May 11 03:25:51 PM PDT 24
Finished May 11 03:25:53 PM PDT 24
Peak memory 205780 kb
Host smart-4f3786c7-7eda-405f-a357-1fdc8fea84c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715456117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2715456117
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2525178547
Short name T645
Test name
Test status
Simulation time 13158244 ps
CPU time 0.88 seconds
Started May 11 03:25:50 PM PDT 24
Finished May 11 03:25:52 PM PDT 24
Peak memory 215156 kb
Host smart-dcaef6cc-22da-4537-9561-7c3a6cc4dcc2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525178547 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2525178547
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2809494008
Short name T34
Test name
Test status
Simulation time 24821754 ps
CPU time 0.91 seconds
Started May 11 03:25:47 PM PDT 24
Finished May 11 03:25:49 PM PDT 24
Peak memory 215180 kb
Host smart-f185283b-3dda-4e14-9de9-778b436c1de4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809494008 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2809494008
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1660964704
Short name T48
Test name
Test status
Simulation time 25217034 ps
CPU time 1.07 seconds
Started May 11 03:25:49 PM PDT 24
Finished May 11 03:25:50 PM PDT 24
Peak memory 229292 kb
Host smart-e00b1d74-731d-48e3-9a5f-01921116bdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660964704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1660964704
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3707325681
Short name T623
Test name
Test status
Simulation time 344238666 ps
CPU time 1.09 seconds
Started May 11 03:25:49 PM PDT 24
Finished May 11 03:25:51 PM PDT 24
Peak memory 205596 kb
Host smart-057d8273-98b8-456a-9710-aca1563140fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707325681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3707325681
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1680245544
Short name T664
Test name
Test status
Simulation time 25579179 ps
CPU time 0.85 seconds
Started May 11 03:25:50 PM PDT 24
Finished May 11 03:25:52 PM PDT 24
Peak memory 215004 kb
Host smart-f33d913f-61c6-4559-927c-fb6c6a800603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680245544 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1680245544
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.364910903
Short name T647
Test name
Test status
Simulation time 30830417 ps
CPU time 0.88 seconds
Started May 11 03:25:49 PM PDT 24
Finished May 11 03:25:51 PM PDT 24
Peak memory 205620 kb
Host smart-4539ec6c-becf-47c9-949c-303696169262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364910903 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.364910903
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2308791697
Short name T276
Test name
Test status
Simulation time 438630061 ps
CPU time 3.02 seconds
Started May 11 03:25:49 PM PDT 24
Finished May 11 03:25:53 PM PDT 24
Peak memory 206392 kb
Host smart-67ea72e9-a9f2-4333-9484-5fbefbf9eccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308791697 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2308791697
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.2663451941
Short name T305
Test name
Test status
Simulation time 15621709 ps
CPU time 1.02 seconds
Started May 11 03:25:54 PM PDT 24
Finished May 11 03:25:56 PM PDT 24
Peak memory 206652 kb
Host smart-48669b01-b3b6-40ce-a682-32bc3b51c5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663451941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2663451941
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1674415655
Short name T718
Test name
Test status
Simulation time 24125751 ps
CPU time 0.86 seconds
Started May 11 03:25:53 PM PDT 24
Finished May 11 03:25:55 PM PDT 24
Peak memory 206156 kb
Host smart-946d9e99-2c55-4e6f-a6ab-1a1740b7659a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674415655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1674415655
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1564187308
Short name T285
Test name
Test status
Simulation time 17609330 ps
CPU time 0.9 seconds
Started May 11 03:25:53 PM PDT 24
Finished May 11 03:25:55 PM PDT 24
Peak memory 215180 kb
Host smart-82b1785f-94aa-4eaf-a8c7-44f3b9e2a281
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564187308 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1564187308
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.148170210
Short name T474
Test name
Test status
Simulation time 27992465 ps
CPU time 1.19 seconds
Started May 11 03:25:55 PM PDT 24
Finished May 11 03:25:57 PM PDT 24
Peak memory 217784 kb
Host smart-5fc1cdcf-b2bb-4192-8c0b-805a4f8b4c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148170210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.148170210
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_intr.314093020
Short name T138
Test name
Test status
Simulation time 28887610 ps
CPU time 1.04 seconds
Started May 11 03:25:54 PM PDT 24
Finished May 11 03:25:56 PM PDT 24
Peak memory 226248 kb
Host smart-25287c49-926a-4344-b409-7b8c249eee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314093020 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.314093020
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1803252631
Short name T331
Test name
Test status
Simulation time 14492532 ps
CPU time 0.93 seconds
Started May 11 03:25:49 PM PDT 24
Finished May 11 03:25:51 PM PDT 24
Peak memory 205364 kb
Host smart-44d9a310-296a-497f-93ea-2c996be4994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803252631 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1803252631
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1924578604
Short name T529
Test name
Test status
Simulation time 143666107 ps
CPU time 1.37 seconds
Started May 11 03:25:52 PM PDT 24
Finished May 11 03:25:54 PM PDT 24
Peak memory 205700 kb
Host smart-21ea575c-2c6c-4f6e-8dbf-4ea6eb237807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924578604 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1924578604
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2579602271
Short name T618
Test name
Test status
Simulation time 248719133824 ps
CPU time 1590.17 seconds
Started May 11 03:25:57 PM PDT 24
Finished May 11 03:52:28 PM PDT 24
Peak memory 222652 kb
Host smart-d9625d03-be81-42d8-b347-246c580422a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579602271 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2579602271
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.4262185390
Short name T130
Test name
Test status
Simulation time 33944009 ps
CPU time 1 seconds
Started May 11 03:25:56 PM PDT 24
Finished May 11 03:25:57 PM PDT 24
Peak memory 206580 kb
Host smart-6f1b477d-0d1d-4f94-aa74-b8eed9adc8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262185390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4262185390
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2380353004
Short name T589
Test name
Test status
Simulation time 18865694 ps
CPU time 1 seconds
Started May 11 03:25:52 PM PDT 24
Finished May 11 03:25:53 PM PDT 24
Peak memory 205252 kb
Host smart-9af15e82-e0ec-425d-b0ab-20b4c4b480c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380353004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2380353004
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2342195239
Short name T712
Test name
Test status
Simulation time 65386140 ps
CPU time 1 seconds
Started May 11 03:25:54 PM PDT 24
Finished May 11 03:25:56 PM PDT 24
Peak memory 215256 kb
Host smart-94825321-a292-4211-9e5c-89a43b0be2be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342195239 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2342195239
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.4071669439
Short name T674
Test name
Test status
Simulation time 221130734 ps
CPU time 0.98 seconds
Started May 11 03:25:55 PM PDT 24
Finished May 11 03:25:56 PM PDT 24
Peak memory 215312 kb
Host smart-76ee4f82-0793-4b38-881e-9caf1131d549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071669439 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4071669439
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3503501299
Short name T615
Test name
Test status
Simulation time 19369928 ps
CPU time 1.06 seconds
Started May 11 03:25:51 PM PDT 24
Finished May 11 03:25:53 PM PDT 24
Peak memory 205908 kb
Host smart-d407ea09-0ffc-447f-a3cd-dc618fdd3f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503501299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3503501299
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2020525502
Short name T141
Test name
Test status
Simulation time 24616689 ps
CPU time 0.91 seconds
Started May 11 03:25:55 PM PDT 24
Finished May 11 03:25:57 PM PDT 24
Peak memory 215348 kb
Host smart-3f124646-bc1b-441f-a254-985a516f7ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020525502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2020525502
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2882164618
Short name T577
Test name
Test status
Simulation time 22048006 ps
CPU time 0.9 seconds
Started May 11 03:25:54 PM PDT 24
Finished May 11 03:25:55 PM PDT 24
Peak memory 205476 kb
Host smart-cc968e5f-7b1b-4f96-9312-de484dcd86a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882164618 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2882164618
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3755015560
Short name T685
Test name
Test status
Simulation time 117294794 ps
CPU time 2.81 seconds
Started May 11 03:25:57 PM PDT 24
Finished May 11 03:26:01 PM PDT 24
Peak memory 206608 kb
Host smart-cfee5718-353b-4c78-9bc2-9bad1cdaa28c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755015560 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3755015560
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.429693575
Short name T563
Test name
Test status
Simulation time 20992409668 ps
CPU time 521.69 seconds
Started May 11 03:25:55 PM PDT 24
Finished May 11 03:34:37 PM PDT 24
Peak memory 215824 kb
Host smart-806485b6-aa1d-4e1d-81a9-f305db1ec8e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429693575 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.429693575
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.4041972485
Short name T561
Test name
Test status
Simulation time 55132763 ps
CPU time 0.95 seconds
Started May 11 03:25:57 PM PDT 24
Finished May 11 03:25:59 PM PDT 24
Peak memory 206588 kb
Host smart-a7d812a4-7ec2-464c-a6d9-e426777eaaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041972485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.4041972485
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.271679440
Short name T19
Test name
Test status
Simulation time 26289778 ps
CPU time 0.95 seconds
Started May 11 03:25:56 PM PDT 24
Finished May 11 03:25:58 PM PDT 24
Peak memory 205784 kb
Host smart-2cea6ed7-daed-4b0b-a703-393a96c7285f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271679440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.271679440
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1654344684
Short name T102
Test name
Test status
Simulation time 11188176 ps
CPU time 0.89 seconds
Started May 11 03:26:02 PM PDT 24
Finished May 11 03:26:03 PM PDT 24
Peak memory 214900 kb
Host smart-2fd9dd96-b7da-4b5b-9dbc-705380aacb67
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654344684 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1654344684
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.4219878204
Short name T112
Test name
Test status
Simulation time 84247560 ps
CPU time 0.99 seconds
Started May 11 03:25:58 PM PDT 24
Finished May 11 03:25:59 PM PDT 24
Peak memory 215248 kb
Host smart-f88f9aaf-3d0b-4f9a-84d1-8f232d1d3247
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219878204 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.4219878204
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3797812549
Short name T50
Test name
Test status
Simulation time 49476453 ps
CPU time 1.18 seconds
Started May 11 03:26:01 PM PDT 24
Finished May 11 03:26:02 PM PDT 24
Peak memory 222768 kb
Host smart-7cae9f41-c20e-49bc-a7cd-4097abbcde4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797812549 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3797812549
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2484057821
Short name T62
Test name
Test status
Simulation time 42131998 ps
CPU time 0.89 seconds
Started May 11 03:25:57 PM PDT 24
Finished May 11 03:25:59 PM PDT 24
Peak memory 205340 kb
Host smart-7474b171-442c-4d31-ae4d-553735de3657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484057821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2484057821
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.755857004
Short name T711
Test name
Test status
Simulation time 29772723 ps
CPU time 0.93 seconds
Started May 11 03:26:02 PM PDT 24
Finished May 11 03:26:03 PM PDT 24
Peak memory 214768 kb
Host smart-8ce50b9c-7e47-4dcb-ba1e-d49c623a3c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755857004 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.755857004
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2339108550
Short name T593
Test name
Test status
Simulation time 77486177 ps
CPU time 0.84 seconds
Started May 11 03:25:54 PM PDT 24
Finished May 11 03:25:56 PM PDT 24
Peak memory 205540 kb
Host smart-093f7441-deb8-4e04-9b6d-36fcf77fe7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339108550 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2339108550
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.4135423044
Short name T65
Test name
Test status
Simulation time 2067374096 ps
CPU time 3.09 seconds
Started May 11 03:25:54 PM PDT 24
Finished May 11 03:25:57 PM PDT 24
Peak memory 206408 kb
Host smart-c89a8e33-56fa-4745-9dad-b68be89a1d3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135423044 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.4135423044
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3442274188
Short name T574
Test name
Test status
Simulation time 68994109630 ps
CPU time 1440.06 seconds
Started May 11 03:25:54 PM PDT 24
Finished May 11 03:49:54 PM PDT 24
Peak memory 217200 kb
Host smart-fcdd7610-6100-42cc-b00f-fe9fc95fc1b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442274188 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3442274188
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2296828321
Short name T600
Test name
Test status
Simulation time 86468808 ps
CPU time 0.96 seconds
Started May 11 03:25:56 PM PDT 24
Finished May 11 03:25:58 PM PDT 24
Peak memory 205856 kb
Host smart-33f3e130-174f-4a9b-aee1-a03b9cbd0dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296828321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2296828321
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.44466506
Short name T518
Test name
Test status
Simulation time 43724194 ps
CPU time 0.81 seconds
Started May 11 03:26:07 PM PDT 24
Finished May 11 03:26:08 PM PDT 24
Peak memory 205200 kb
Host smart-2145e43c-516b-4258-a595-654d21421732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44466506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.44466506
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3959763833
Short name T661
Test name
Test status
Simulation time 32859758 ps
CPU time 0.83 seconds
Started May 11 03:26:01 PM PDT 24
Finished May 11 03:26:03 PM PDT 24
Peak memory 214968 kb
Host smart-818b229c-6893-4c51-a2b2-d8b73d0edc9d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959763833 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3959763833
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2345236623
Short name T635
Test name
Test status
Simulation time 222999337 ps
CPU time 1.1 seconds
Started May 11 03:25:59 PM PDT 24
Finished May 11 03:26:00 PM PDT 24
Peak memory 215212 kb
Host smart-a21120ed-b70b-40ce-a4d8-79414aa5a678
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345236623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2345236623
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2447148651
Short name T184
Test name
Test status
Simulation time 26551066 ps
CPU time 1.02 seconds
Started May 11 03:26:01 PM PDT 24
Finished May 11 03:26:02 PM PDT 24
Peak memory 229352 kb
Host smart-5ec625e8-eb20-4846-ae89-ba2172ad3af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447148651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2447148651
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1099113892
Short name T99
Test name
Test status
Simulation time 34303593 ps
CPU time 1.17 seconds
Started May 11 03:25:57 PM PDT 24
Finished May 11 03:25:59 PM PDT 24
Peak memory 205720 kb
Host smart-8984bb93-b903-42e7-800b-9dc3d1dfba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099113892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1099113892
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.774864921
Short name T709
Test name
Test status
Simulation time 21048001 ps
CPU time 1.05 seconds
Started May 11 03:25:57 PM PDT 24
Finished May 11 03:25:59 PM PDT 24
Peak memory 215144 kb
Host smart-9d701cc4-372b-4d32-8c51-97ead7a7050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774864921 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.774864921
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3460012232
Short name T520
Test name
Test status
Simulation time 38608072 ps
CPU time 1.02 seconds
Started May 11 03:25:58 PM PDT 24
Finished May 11 03:26:00 PM PDT 24
Peak memory 205968 kb
Host smart-709614d4-5f45-45de-8c9b-9a8274b09d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460012232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3460012232
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3030928032
Short name T501
Test name
Test status
Simulation time 582926585 ps
CPU time 3.49 seconds
Started May 11 03:25:59 PM PDT 24
Finished May 11 03:26:03 PM PDT 24
Peak memory 206232 kb
Host smart-ff8cc43d-98f2-452f-bfbe-879de11b5c61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030928032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3030928032
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.37643808
Short name T231
Test name
Test status
Simulation time 148950578071 ps
CPU time 1052.18 seconds
Started May 11 03:25:56 PM PDT 24
Finished May 11 03:43:29 PM PDT 24
Peak memory 219180 kb
Host smart-bdf0c111-f6df-45ac-ab13-6e7f798e78b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37643808 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.37643808
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2595742691
Short name T119
Test name
Test status
Simulation time 19683285 ps
CPU time 1.01 seconds
Started May 11 03:26:00 PM PDT 24
Finished May 11 03:26:01 PM PDT 24
Peak memory 206548 kb
Host smart-0a2ac368-2944-449c-9d21-0a5e0b06ec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595742691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2595742691
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.509428576
Short name T713
Test name
Test status
Simulation time 55806728 ps
CPU time 0.92 seconds
Started May 11 03:26:01 PM PDT 24
Finished May 11 03:26:02 PM PDT 24
Peak memory 205300 kb
Host smart-cc2d99a0-1032-48dd-af13-4603d978fc34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509428576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.509428576
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1395991171
Short name T247
Test name
Test status
Simulation time 14913251 ps
CPU time 0.87 seconds
Started May 11 03:25:59 PM PDT 24
Finished May 11 03:26:00 PM PDT 24
Peak memory 214980 kb
Host smart-62316ebe-d1bd-4c67-ae98-ab4b5e4ba7ae
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395991171 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1395991171
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1789475562
Short name T287
Test name
Test status
Simulation time 25326593 ps
CPU time 1.04 seconds
Started May 11 03:26:00 PM PDT 24
Finished May 11 03:26:01 PM PDT 24
Peak memory 215100 kb
Host smart-8e26c1b6-0fc3-4607-933e-be2608e81eac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789475562 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1789475562
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_intr.1702983942
Short name T724
Test name
Test status
Simulation time 37672779 ps
CPU time 1.01 seconds
Started May 11 03:26:01 PM PDT 24
Finished May 11 03:26:03 PM PDT 24
Peak memory 221920 kb
Host smart-c1713623-453d-430c-be81-347af6d940c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702983942 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1702983942
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2373141199
Short name T242
Test name
Test status
Simulation time 12147590 ps
CPU time 0.9 seconds
Started May 11 03:26:01 PM PDT 24
Finished May 11 03:26:02 PM PDT 24
Peak memory 205276 kb
Host smart-aab0c61a-8ca4-47a6-a09d-a5fb811cb218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373141199 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2373141199
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1184165978
Short name T212
Test name
Test status
Simulation time 282350586 ps
CPU time 2.74 seconds
Started May 11 03:26:02 PM PDT 24
Finished May 11 03:26:05 PM PDT 24
Peak memory 206176 kb
Host smart-aaa8620a-fea7-4950-bdca-16929d8f56a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184165978 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1184165978
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2589150818
Short name T490
Test name
Test status
Simulation time 71600451048 ps
CPU time 947.5 seconds
Started May 11 03:26:07 PM PDT 24
Finished May 11 03:41:55 PM PDT 24
Peak memory 216328 kb
Host smart-94cebf62-f857-42e1-8740-1f5284b5f491
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589150818 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2589150818
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1111485546
Short name T14
Test name
Test status
Simulation time 64501277 ps
CPU time 1.02 seconds
Started May 11 03:26:01 PM PDT 24
Finished May 11 03:26:03 PM PDT 24
Peak memory 206500 kb
Host smart-b59c9dff-78bf-48b9-8921-78081745cfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111485546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1111485546
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1389311853
Short name T470
Test name
Test status
Simulation time 162465446 ps
CPU time 0.94 seconds
Started May 11 03:26:04 PM PDT 24
Finished May 11 03:26:05 PM PDT 24
Peak memory 205292 kb
Host smart-b641b78a-12e4-4ebf-acd6-77b4ba3a198b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389311853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1389311853
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_err.1542882075
Short name T245
Test name
Test status
Simulation time 23630733 ps
CPU time 1.21 seconds
Started May 11 03:26:02 PM PDT 24
Finished May 11 03:26:03 PM PDT 24
Peak memory 216504 kb
Host smart-e530bbd7-da9c-4ea4-87e7-6da251e5130a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542882075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1542882075
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3166323601
Short name T122
Test name
Test status
Simulation time 43942006 ps
CPU time 0.91 seconds
Started May 11 03:26:07 PM PDT 24
Finished May 11 03:26:08 PM PDT 24
Peak memory 205688 kb
Host smart-d8c40fe4-af95-4bd7-84c9-c68adee57d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166323601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3166323601
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1508888804
Short name T571
Test name
Test status
Simulation time 20873844 ps
CPU time 1.14 seconds
Started May 11 03:26:07 PM PDT 24
Finished May 11 03:26:09 PM PDT 24
Peak memory 215104 kb
Host smart-f46cf82b-55ea-4a5d-a348-9af8a3fdeef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508888804 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1508888804
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.611703883
Short name T512
Test name
Test status
Simulation time 24067714 ps
CPU time 0.92 seconds
Started May 11 03:26:01 PM PDT 24
Finished May 11 03:26:03 PM PDT 24
Peak memory 205536 kb
Host smart-844667ca-58da-4044-ae26-63ba19982743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611703883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.611703883
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1710398091
Short name T666
Test name
Test status
Simulation time 358032128 ps
CPU time 2.31 seconds
Started May 11 03:26:03 PM PDT 24
Finished May 11 03:26:05 PM PDT 24
Peak memory 206536 kb
Host smart-b4c1cbe2-d826-42ba-b6ad-70bf88ff9fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710398091 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1710398091
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1954260511
Short name T575
Test name
Test status
Simulation time 85689713007 ps
CPU time 1140.23 seconds
Started May 11 03:26:07 PM PDT 24
Finished May 11 03:45:07 PM PDT 24
Peak memory 217284 kb
Host smart-7523fd54-9af0-40b8-bee6-cc28dd0a4814
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954260511 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1954260511
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2656695464
Short name T266
Test name
Test status
Simulation time 78969780 ps
CPU time 0.98 seconds
Started May 11 03:26:04 PM PDT 24
Finished May 11 03:26:05 PM PDT 24
Peak memory 206572 kb
Host smart-04e1461d-edda-4534-9d4e-b95da3223231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656695464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2656695464
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1518607474
Short name T631
Test name
Test status
Simulation time 41941791 ps
CPU time 0.98 seconds
Started May 11 03:26:07 PM PDT 24
Finished May 11 03:26:09 PM PDT 24
Peak memory 205056 kb
Host smart-a5320cae-b574-441f-baaf-d0762c70dc58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518607474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1518607474
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1662103981
Short name T642
Test name
Test status
Simulation time 14241144 ps
CPU time 0.93 seconds
Started May 11 03:26:05 PM PDT 24
Finished May 11 03:26:06 PM PDT 24
Peak memory 215176 kb
Host smart-7dad30ff-e478-43ad-a672-ba5f29e51389
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662103981 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1662103981
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.592174941
Short name T118
Test name
Test status
Simulation time 48026191 ps
CPU time 0.99 seconds
Started May 11 03:26:03 PM PDT 24
Finished May 11 03:26:05 PM PDT 24
Peak memory 216412 kb
Host smart-5517e550-c970-4272-8462-a024516f1e5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592174941 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.592174941
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1895214562
Short name T199
Test name
Test status
Simulation time 22735837 ps
CPU time 0.98 seconds
Started May 11 03:26:06 PM PDT 24
Finished May 11 03:26:07 PM PDT 24
Peak memory 222660 kb
Host smart-32e28023-d63e-41f7-8be4-9a4cc790743d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895214562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1895214562
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2613705348
Short name T553
Test name
Test status
Simulation time 92651542 ps
CPU time 0.9 seconds
Started May 11 03:26:04 PM PDT 24
Finished May 11 03:26:05 PM PDT 24
Peak memory 205788 kb
Host smart-de796520-b99d-4090-94c1-dc5fc713e074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613705348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2613705348
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3756417362
Short name T137
Test name
Test status
Simulation time 25344351 ps
CPU time 0.94 seconds
Started May 11 03:26:03 PM PDT 24
Finished May 11 03:26:04 PM PDT 24
Peak memory 226260 kb
Host smart-6aeab787-f144-460e-9ed7-9969f59a8a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756417362 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3756417362
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2570517071
Short name T496
Test name
Test status
Simulation time 25116636 ps
CPU time 0.9 seconds
Started May 11 03:26:06 PM PDT 24
Finished May 11 03:26:07 PM PDT 24
Peak memory 205572 kb
Host smart-39b2a3e4-968f-4d86-8c97-40bbfbea04d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570517071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2570517071
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1740405384
Short name T532
Test name
Test status
Simulation time 221789667 ps
CPU time 3.54 seconds
Started May 11 03:26:07 PM PDT 24
Finished May 11 03:26:11 PM PDT 24
Peak memory 206692 kb
Host smart-117ca4b2-2b24-44cb-85f3-fdc3cf48dddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740405384 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1740405384
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_alert.1832958932
Short name T66
Test name
Test status
Simulation time 57077787 ps
CPU time 0.97 seconds
Started May 11 03:24:25 PM PDT 24
Finished May 11 03:24:26 PM PDT 24
Peak memory 206592 kb
Host smart-e772632a-dd86-4a22-9ac5-4549d31f3a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832958932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1832958932
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2404965816
Short name T16
Test name
Test status
Simulation time 12467808 ps
CPU time 0.83 seconds
Started May 11 03:24:28 PM PDT 24
Finished May 11 03:24:29 PM PDT 24
Peak memory 204904 kb
Host smart-cb407ee8-6411-4d66-9aab-358992cbccca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404965816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2404965816
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.12697721
Short name T586
Test name
Test status
Simulation time 24834020 ps
CPU time 0.98 seconds
Started May 11 03:24:33 PM PDT 24
Finished May 11 03:24:34 PM PDT 24
Peak memory 215236 kb
Host smart-eeefb0f7-251f-41ad-ac93-0da6e2d0ff8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12697721 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disa
ble_auto_req_mode.12697721
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3120329245
Short name T325
Test name
Test status
Simulation time 24975607 ps
CPU time 1.14 seconds
Started May 11 03:24:24 PM PDT 24
Finished May 11 03:24:25 PM PDT 24
Peak memory 216540 kb
Host smart-2acff18b-6756-4d8b-8db4-423e1564f85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120329245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3120329245
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_intr.1856556474
Short name T140
Test name
Test status
Simulation time 20930018 ps
CPU time 0.94 seconds
Started May 11 03:24:25 PM PDT 24
Finished May 11 03:24:26 PM PDT 24
Peak memory 215236 kb
Host smart-b472d8fe-e27d-4807-bb08-40b0c79ace9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856556474 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1856556474
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.1727294515
Short name T628
Test name
Test status
Simulation time 23397346 ps
CPU time 0.87 seconds
Started May 11 03:24:26 PM PDT 24
Finished May 11 03:24:27 PM PDT 24
Peak memory 205224 kb
Host smart-44285c33-f470-44be-860f-816b03ab1db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727294515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1727294515
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2653168687
Short name T173
Test name
Test status
Simulation time 608823653 ps
CPU time 2.56 seconds
Started May 11 03:24:27 PM PDT 24
Finished May 11 03:24:30 PM PDT 24
Peak memory 206400 kb
Host smart-a848d0b5-c0c4-4700-a61e-442c15a4513b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653168687 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2653168687
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.4023228454
Short name T156
Test name
Test status
Simulation time 33368025380 ps
CPU time 406.79 seconds
Started May 11 03:24:34 PM PDT 24
Finished May 11 03:31:22 PM PDT 24
Peak memory 216388 kb
Host smart-4721489d-28b5-4225-825d-4f1a9330a4d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023228454 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4023228454
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2954979086
Short name T183
Test name
Test status
Simulation time 30993678 ps
CPU time 1.04 seconds
Started May 11 03:26:05 PM PDT 24
Finished May 11 03:26:07 PM PDT 24
Peak memory 215168 kb
Host smart-066621f1-f586-4db7-ad65-eb27ab2d561d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954979086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2954979086
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/51.edn_err.3843277701
Short name T198
Test name
Test status
Simulation time 42079916 ps
CPU time 1.2 seconds
Started May 11 03:26:05 PM PDT 24
Finished May 11 03:26:07 PM PDT 24
Peak memory 222636 kb
Host smart-be9c1a78-3c82-466e-93d9-011c6b6047d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843277701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3843277701
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/52.edn_err.729212938
Short name T528
Test name
Test status
Simulation time 29487499 ps
CPU time 0.97 seconds
Started May 11 03:26:09 PM PDT 24
Finished May 11 03:26:11 PM PDT 24
Peak memory 216552 kb
Host smart-cb191641-7d08-4176-aac0-5a55ff08d737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729212938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.729212938
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_err.3665607146
Short name T723
Test name
Test status
Simulation time 35960231 ps
CPU time 1.11 seconds
Started May 11 03:26:09 PM PDT 24
Finished May 11 03:26:11 PM PDT 24
Peak memory 216432 kb
Host smart-31c9e152-2fc9-43c5-9512-ede740ae02c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665607146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3665607146
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/54.edn_err.828534388
Short name T68
Test name
Test status
Simulation time 31854724 ps
CPU time 0.96 seconds
Started May 11 03:26:08 PM PDT 24
Finished May 11 03:26:10 PM PDT 24
Peak memory 216424 kb
Host smart-b56b72e1-4d2f-4ab2-a945-4202e666117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828534388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.828534388
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/55.edn_err.2171077655
Short name T481
Test name
Test status
Simulation time 53466136 ps
CPU time 1.01 seconds
Started May 11 03:26:09 PM PDT 24
Finished May 11 03:26:10 PM PDT 24
Peak memory 215260 kb
Host smart-e9d1c2a9-1a6c-4f73-8e64-f8094ecbca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171077655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2171077655
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/56.edn_err.3735178528
Short name T543
Test name
Test status
Simulation time 22095454 ps
CPU time 0.92 seconds
Started May 11 03:26:09 PM PDT 24
Finished May 11 03:26:10 PM PDT 24
Peak memory 216548 kb
Host smart-9a6429d3-d835-48ef-815b-1eb3aa13d049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735178528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3735178528
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_err.4136669497
Short name T263
Test name
Test status
Simulation time 19291980 ps
CPU time 1.09 seconds
Started May 11 03:26:09 PM PDT 24
Finished May 11 03:26:10 PM PDT 24
Peak memory 216732 kb
Host smart-46784bb6-2124-40b4-bb07-a4af924ba2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136669497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4136669497
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/58.edn_err.3137117579
Short name T26
Test name
Test status
Simulation time 51308519 ps
CPU time 0.96 seconds
Started May 11 03:26:13 PM PDT 24
Finished May 11 03:26:14 PM PDT 24
Peak memory 215356 kb
Host smart-c308c03b-ef77-44e5-a744-85cb77a8a3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137117579 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3137117579
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.2465064250
Short name T90
Test name
Test status
Simulation time 18295097 ps
CPU time 1.03 seconds
Started May 11 03:24:32 PM PDT 24
Finished May 11 03:24:34 PM PDT 24
Peak memory 206576 kb
Host smart-56073ccd-ff4b-40f4-b5e6-45c35629430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465064250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2465064250
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3299632970
Short name T327
Test name
Test status
Simulation time 46136323 ps
CPU time 0.91 seconds
Started May 11 03:24:32 PM PDT 24
Finished May 11 03:24:34 PM PDT 24
Peak memory 205760 kb
Host smart-4276e0f9-52dd-4c1b-a881-b26640e3df45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299632970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3299632970
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.643418720
Short name T111
Test name
Test status
Simulation time 44070908 ps
CPU time 0.84 seconds
Started May 11 03:24:29 PM PDT 24
Finished May 11 03:24:31 PM PDT 24
Peak memory 215024 kb
Host smart-deb7fcc7-2b78-46e5-9a7b-cfa262e7da22
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643418720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.643418720
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1137948653
Short name T31
Test name
Test status
Simulation time 221804837 ps
CPU time 1.06 seconds
Started May 11 03:24:29 PM PDT 24
Finished May 11 03:24:31 PM PDT 24
Peak memory 215244 kb
Host smart-5d33a396-fe22-440c-8d5d-c9fd11cdcf01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137948653 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1137948653
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3709326392
Short name T203
Test name
Test status
Simulation time 19200012 ps
CPU time 1.25 seconds
Started May 11 03:24:31 PM PDT 24
Finished May 11 03:24:33 PM PDT 24
Peak memory 222888 kb
Host smart-d91a08d2-4de4-410a-920c-64e7bc38a1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709326392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3709326392
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1788361921
Short name T549
Test name
Test status
Simulation time 16951118 ps
CPU time 0.96 seconds
Started May 11 03:24:32 PM PDT 24
Finished May 11 03:24:33 PM PDT 24
Peak memory 206284 kb
Host smart-9c716579-649e-4db4-a3d8-ba74b0149de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788361921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1788361921
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.267171343
Short name T695
Test name
Test status
Simulation time 30272866 ps
CPU time 0.97 seconds
Started May 11 03:24:36 PM PDT 24
Finished May 11 03:24:38 PM PDT 24
Peak memory 222112 kb
Host smart-c1ecfa86-9413-4b18-8ddc-5d8d25db1efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267171343 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.267171343
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.4039410182
Short name T302
Test name
Test status
Simulation time 93852067 ps
CPU time 0.86 seconds
Started May 11 03:24:31 PM PDT 24
Finished May 11 03:24:32 PM PDT 24
Peak memory 205196 kb
Host smart-d66461a9-91e6-4a2b-afae-f1c8113e4aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039410182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.4039410182
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.110160212
Short name T326
Test name
Test status
Simulation time 13879748 ps
CPU time 0.92 seconds
Started May 11 03:24:29 PM PDT 24
Finished May 11 03:24:30 PM PDT 24
Peak memory 205260 kb
Host smart-8617c079-c215-4d05-8ee2-c803562f84fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110160212 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.110160212
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3465749123
Short name T274
Test name
Test status
Simulation time 51912311 ps
CPU time 1.13 seconds
Started May 11 03:24:29 PM PDT 24
Finished May 11 03:24:31 PM PDT 24
Peak memory 205968 kb
Host smart-d3c47420-6a48-4b74-abc1-43ab47fd8b7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465749123 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3465749123
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2133296595
Short name T158
Test name
Test status
Simulation time 577764923484 ps
CPU time 1573.11 seconds
Started May 11 03:24:28 PM PDT 24
Finished May 11 03:50:42 PM PDT 24
Peak memory 218160 kb
Host smart-8bdd1aae-1900-48be-8dae-92b418a42339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133296595 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2133296595
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3768467922
Short name T179
Test name
Test status
Simulation time 20288245 ps
CPU time 1.22 seconds
Started May 11 03:26:13 PM PDT 24
Finished May 11 03:26:15 PM PDT 24
Peak memory 229396 kb
Host smart-67a63c9f-cc78-4a15-a931-0b9f60f9e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768467922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3768467922
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/61.edn_err.307729737
Short name T524
Test name
Test status
Simulation time 24036966 ps
CPU time 0.97 seconds
Started May 11 03:26:17 PM PDT 24
Finished May 11 03:26:18 PM PDT 24
Peak memory 216652 kb
Host smart-0a0f401f-97f6-46f1-918d-3f3d11de7ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307729737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.307729737
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_err.2206183589
Short name T660
Test name
Test status
Simulation time 54373815 ps
CPU time 0.95 seconds
Started May 11 03:26:12 PM PDT 24
Finished May 11 03:26:13 PM PDT 24
Peak memory 222132 kb
Host smart-76cdf52e-1d14-41c7-8c90-fdade07b1a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206183589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2206183589
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/63.edn_err.155089364
Short name T570
Test name
Test status
Simulation time 22609337 ps
CPU time 0.86 seconds
Started May 11 03:26:14 PM PDT 24
Finished May 11 03:26:15 PM PDT 24
Peak memory 216292 kb
Host smart-f339d893-c948-4122-bea1-05e07f456122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155089364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.155089364
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/64.edn_err.3575745627
Short name T190
Test name
Test status
Simulation time 62291299 ps
CPU time 0.98 seconds
Started May 11 03:26:15 PM PDT 24
Finished May 11 03:26:16 PM PDT 24
Peak memory 215136 kb
Host smart-14f5ebeb-5eea-4a03-ac15-13ca4050abfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575745627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3575745627
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.2544263870
Short name T13
Test name
Test status
Simulation time 104455886 ps
CPU time 1.17 seconds
Started May 11 03:26:17 PM PDT 24
Finished May 11 03:26:19 PM PDT 24
Peak memory 228208 kb
Host smart-7cb944ed-1d20-4668-b822-01ccfa21bd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544263870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2544263870
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/66.edn_err.3412560487
Short name T209
Test name
Test status
Simulation time 70241991 ps
CPU time 0.86 seconds
Started May 11 03:26:19 PM PDT 24
Finished May 11 03:26:20 PM PDT 24
Peak memory 216452 kb
Host smart-64f61265-1ba5-4175-8faa-e2d22e2a9ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412560487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3412560487
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/67.edn_err.262918171
Short name T6
Test name
Test status
Simulation time 33896808 ps
CPU time 1.06 seconds
Started May 11 03:26:19 PM PDT 24
Finished May 11 03:26:20 PM PDT 24
Peak memory 215336 kb
Host smart-3df040ff-b7b8-41e9-bba5-e1041961c4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262918171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.262918171
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.851101214
Short name T248
Test name
Test status
Simulation time 31867674 ps
CPU time 0.86 seconds
Started May 11 03:26:16 PM PDT 24
Finished May 11 03:26:18 PM PDT 24
Peak memory 216500 kb
Host smart-82cf38ba-d36f-4086-a588-5df667023d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851101214 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.851101214
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/69.edn_err.2170271513
Short name T705
Test name
Test status
Simulation time 18943453 ps
CPU time 1.23 seconds
Started May 11 03:26:20 PM PDT 24
Finished May 11 03:26:22 PM PDT 24
Peak memory 222652 kb
Host smart-4535ed68-8bc6-4d10-9be7-815464eb7c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170271513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2170271513
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.2989513838
Short name T582
Test name
Test status
Simulation time 53514531 ps
CPU time 0.89 seconds
Started May 11 03:24:31 PM PDT 24
Finished May 11 03:24:32 PM PDT 24
Peak memory 206564 kb
Host smart-4ed0a13a-a250-4c3e-a486-c1ebf25488fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989513838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2989513838
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4222634219
Short name T534
Test name
Test status
Simulation time 16350701 ps
CPU time 0.92 seconds
Started May 11 03:24:37 PM PDT 24
Finished May 11 03:24:39 PM PDT 24
Peak memory 205236 kb
Host smart-2102399a-35b2-4eac-a240-dd0daa7b1d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222634219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4222634219
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.813027467
Short name T87
Test name
Test status
Simulation time 16890873 ps
CPU time 0.82 seconds
Started May 11 03:24:36 PM PDT 24
Finished May 11 03:24:37 PM PDT 24
Peak memory 215004 kb
Host smart-feeff01d-9539-40a9-9bd2-7cf319ec2811
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813027467 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.813027467
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3287883377
Short name T282
Test name
Test status
Simulation time 21652862 ps
CPU time 1.01 seconds
Started May 11 03:24:34 PM PDT 24
Finished May 11 03:24:35 PM PDT 24
Peak memory 215228 kb
Host smart-d5dd0c2c-0f77-4351-943c-970c7522cae3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287883377 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3287883377
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3975183471
Short name T28
Test name
Test status
Simulation time 29522915 ps
CPU time 1.07 seconds
Started May 11 03:24:31 PM PDT 24
Finished May 11 03:24:32 PM PDT 24
Peak memory 216520 kb
Host smart-499d5d36-f957-4510-84a8-01d8ffb44fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975183471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3975183471
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.767786737
Short name T632
Test name
Test status
Simulation time 26382015 ps
CPU time 0.94 seconds
Started May 11 03:24:37 PM PDT 24
Finished May 11 03:24:38 PM PDT 24
Peak memory 206136 kb
Host smart-8e3346eb-eac8-4a00-85e9-04d4478fc900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767786737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.767786737
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.612626579
Short name T717
Test name
Test status
Simulation time 39405835 ps
CPU time 0.86 seconds
Started May 11 03:24:32 PM PDT 24
Finished May 11 03:24:34 PM PDT 24
Peak memory 214952 kb
Host smart-19cd3899-1b6c-450f-93c9-8fae7fc95c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612626579 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.612626579
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.520306981
Short name T243
Test name
Test status
Simulation time 53044966 ps
CPU time 0.91 seconds
Started May 11 03:24:32 PM PDT 24
Finished May 11 03:24:33 PM PDT 24
Peak memory 205292 kb
Host smart-e8ad0a13-62db-416b-8dd5-1d5ed9540cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520306981 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.520306981
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1706989554
Short name T703
Test name
Test status
Simulation time 94792650 ps
CPU time 2.52 seconds
Started May 11 03:24:36 PM PDT 24
Finished May 11 03:24:39 PM PDT 24
Peak memory 206452 kb
Host smart-c146247e-c35a-4562-be77-2ddf3f9dba8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706989554 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1706989554
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.706984750
Short name T143
Test name
Test status
Simulation time 119645786501 ps
CPU time 1621.78 seconds
Started May 11 03:24:30 PM PDT 24
Finished May 11 03:51:32 PM PDT 24
Peak memory 221260 kb
Host smart-497db0a4-f136-4649-bade-15fac52843b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706984750 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.706984750
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1125823686
Short name T188
Test name
Test status
Simulation time 22870868 ps
CPU time 1.22 seconds
Started May 11 03:26:19 PM PDT 24
Finished May 11 03:26:20 PM PDT 24
Peak memory 230900 kb
Host smart-108d5dac-7de1-4ddb-b91b-e37cb9840655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125823686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1125823686
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/71.edn_err.874030999
Short name T475
Test name
Test status
Simulation time 18966345 ps
CPU time 1.02 seconds
Started May 11 03:26:19 PM PDT 24
Finished May 11 03:26:20 PM PDT 24
Peak memory 216364 kb
Host smart-78142aeb-b9ff-4900-9f63-a47f96ec41b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874030999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.874030999
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/72.edn_err.3984609429
Short name T269
Test name
Test status
Simulation time 25564919 ps
CPU time 1.23 seconds
Started May 11 03:26:22 PM PDT 24
Finished May 11 03:26:23 PM PDT 24
Peak memory 215488 kb
Host smart-29cf6e3e-33de-4db3-bfa3-a04723e28159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984609429 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3984609429
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/73.edn_err.1331872036
Short name T721
Test name
Test status
Simulation time 42733729 ps
CPU time 1.25 seconds
Started May 11 03:26:22 PM PDT 24
Finished May 11 03:26:24 PM PDT 24
Peak memory 228396 kb
Host smart-12ca6aa7-b79a-45f3-9206-19326f1a1bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331872036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1331872036
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_err.3995674583
Short name T634
Test name
Test status
Simulation time 50935613 ps
CPU time 1.01 seconds
Started May 11 03:26:24 PM PDT 24
Finished May 11 03:26:25 PM PDT 24
Peak memory 217812 kb
Host smart-9011263f-e798-4bf3-846e-258ab93c830a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995674583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3995674583
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_err.3671000789
Short name T204
Test name
Test status
Simulation time 31117669 ps
CPU time 0.97 seconds
Started May 11 03:26:25 PM PDT 24
Finished May 11 03:26:27 PM PDT 24
Peak memory 221940 kb
Host smart-7e4dc55a-da47-4c7a-bcc0-25b9d27301a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671000789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3671000789
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/76.edn_err.1070042538
Short name T175
Test name
Test status
Simulation time 52963008 ps
CPU time 1.35 seconds
Started May 11 03:26:24 PM PDT 24
Finished May 11 03:26:26 PM PDT 24
Peak memory 228440 kb
Host smart-eb09d172-8e85-4d11-aa87-d227b2604e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070042538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1070042538
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/77.edn_err.2986301530
Short name T249
Test name
Test status
Simulation time 47313781 ps
CPU time 1.08 seconds
Started May 11 03:26:25 PM PDT 24
Finished May 11 03:26:26 PM PDT 24
Peak memory 217656 kb
Host smart-0da26d38-0205-4be3-bbdf-1fe88d1c8637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986301530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2986301530
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_err.2657038729
Short name T692
Test name
Test status
Simulation time 60390777 ps
CPU time 0.79 seconds
Started May 11 03:26:27 PM PDT 24
Finished May 11 03:26:28 PM PDT 24
Peak memory 216340 kb
Host smart-1003178c-cb89-49a2-b1d4-7d68c0385031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657038729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2657038729
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_err.3815727379
Short name T533
Test name
Test status
Simulation time 31029365 ps
CPU time 0.88 seconds
Started May 11 03:26:27 PM PDT 24
Finished May 11 03:26:28 PM PDT 24
Peak memory 215036 kb
Host smart-aa26f559-270a-43eb-af0a-650ad1fcc387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815727379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3815727379
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.2300538243
Short name T306
Test name
Test status
Simulation time 20945352 ps
CPU time 1.07 seconds
Started May 11 03:24:33 PM PDT 24
Finished May 11 03:24:35 PM PDT 24
Peak memory 206624 kb
Host smart-283ec289-7226-42b0-a186-fedef33fd598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300538243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2300538243
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.777454183
Short name T127
Test name
Test status
Simulation time 16743432 ps
CPU time 0.94 seconds
Started May 11 03:24:34 PM PDT 24
Finished May 11 03:24:35 PM PDT 24
Peak memory 205784 kb
Host smart-6370005c-665b-44c2-8b43-bb66a74d6cf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777454183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.777454183
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3216180330
Short name T101
Test name
Test status
Simulation time 18126138 ps
CPU time 0.88 seconds
Started May 11 03:24:34 PM PDT 24
Finished May 11 03:24:35 PM PDT 24
Peak memory 215004 kb
Host smart-0f19b315-78e3-49b4-9132-5c3f15ef1aac
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216180330 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3216180330
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.3698566186
Short name T257
Test name
Test status
Simulation time 19581766 ps
CPU time 1.05 seconds
Started May 11 03:24:36 PM PDT 24
Finished May 11 03:24:37 PM PDT 24
Peak memory 216720 kb
Host smart-41ea3318-b139-480d-b09f-74614fafd885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698566186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3698566186
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3487443032
Short name T38
Test name
Test status
Simulation time 43212977 ps
CPU time 1.2 seconds
Started May 11 03:24:33 PM PDT 24
Finished May 11 03:24:35 PM PDT 24
Peak memory 206144 kb
Host smart-9a71f567-f299-4b2e-89db-757d84d4b6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487443032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3487443032
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3355917693
Short name T332
Test name
Test status
Simulation time 53108396 ps
CPU time 1.17 seconds
Started May 11 03:24:36 PM PDT 24
Finished May 11 03:24:38 PM PDT 24
Peak memory 215224 kb
Host smart-9e00a251-9302-4f5b-bef3-bece1c432764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355917693 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3355917693
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3554713695
Short name T309
Test name
Test status
Simulation time 63653875 ps
CPU time 0.85 seconds
Started May 11 03:24:33 PM PDT 24
Finished May 11 03:24:35 PM PDT 24
Peak memory 205080 kb
Host smart-5cf81be1-3bc8-4c2b-b5e3-7691e016073b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554713695 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3554713695
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3373984524
Short name T56
Test name
Test status
Simulation time 34133435 ps
CPU time 0.87 seconds
Started May 11 03:24:34 PM PDT 24
Finished May 11 03:24:36 PM PDT 24
Peak memory 205256 kb
Host smart-86bf7c17-3791-4bbc-ab03-4a18ce9d9ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373984524 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3373984524
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.4061473586
Short name T486
Test name
Test status
Simulation time 80436735 ps
CPU time 2.17 seconds
Started May 11 03:24:36 PM PDT 24
Finished May 11 03:24:39 PM PDT 24
Peak memory 206236 kb
Host smart-38e000dc-4c08-422d-b2ca-2c12f6f94bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061473586 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.4061473586
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2557003130
Short name T649
Test name
Test status
Simulation time 370393671001 ps
CPU time 2190.28 seconds
Started May 11 03:24:35 PM PDT 24
Finished May 11 04:01:06 PM PDT 24
Peak memory 223004 kb
Host smart-f1810661-0aee-427f-8ef4-44c3ed82e897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557003130 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2557003130
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.1621675331
Short name T508
Test name
Test status
Simulation time 158939492 ps
CPU time 1.11 seconds
Started May 11 03:26:27 PM PDT 24
Finished May 11 03:26:28 PM PDT 24
Peak memory 222756 kb
Host smart-591313d1-c662-4363-b406-b36c476da1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621675331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1621675331
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/81.edn_err.3049603309
Short name T208
Test name
Test status
Simulation time 24599205 ps
CPU time 0.95 seconds
Started May 11 03:26:31 PM PDT 24
Finished May 11 03:26:32 PM PDT 24
Peak memory 216540 kb
Host smart-a093d8c2-230f-4c24-afb2-25fbcda8fc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049603309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3049603309
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.496822640
Short name T256
Test name
Test status
Simulation time 33202724 ps
CPU time 1.05 seconds
Started May 11 03:26:27 PM PDT 24
Finished May 11 03:26:29 PM PDT 24
Peak memory 216620 kb
Host smart-230b4003-c3e5-48d6-8bdd-97adf3633555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496822640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.496822640
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_err.2894908807
Short name T201
Test name
Test status
Simulation time 22487437 ps
CPU time 0.86 seconds
Started May 11 03:26:26 PM PDT 24
Finished May 11 03:26:27 PM PDT 24
Peak memory 216388 kb
Host smart-ea6bb969-8948-47ea-b64f-cfc0438df90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894908807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2894908807
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.1242261809
Short name T176
Test name
Test status
Simulation time 19643443 ps
CPU time 1.19 seconds
Started May 11 03:26:27 PM PDT 24
Finished May 11 03:26:29 PM PDT 24
Peak memory 229472 kb
Host smart-0cee1cf1-acfe-4233-b28b-cb9eff56244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242261809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1242261809
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/85.edn_err.1511648627
Short name T3
Test name
Test status
Simulation time 42232086 ps
CPU time 1.09 seconds
Started May 11 03:26:27 PM PDT 24
Finished May 11 03:26:29 PM PDT 24
Peak memory 217732 kb
Host smart-03f17e3c-c51b-4533-95b9-465f343c4950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511648627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1511648627
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_err.617182053
Short name T246
Test name
Test status
Simulation time 70115149 ps
CPU time 1.11 seconds
Started May 11 03:26:30 PM PDT 24
Finished May 11 03:26:31 PM PDT 24
Peak memory 217720 kb
Host smart-31e8ab3a-3160-45f5-9f3b-26682b82f8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617182053 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.617182053
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/87.edn_err.3283998046
Short name T320
Test name
Test status
Simulation time 44691804 ps
CPU time 1.06 seconds
Started May 11 03:26:32 PM PDT 24
Finished May 11 03:26:34 PM PDT 24
Peak memory 215412 kb
Host smart-510a8b2b-dcf8-44bc-88d8-9ddf7b03312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283998046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3283998046
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/88.edn_err.4067858145
Short name T192
Test name
Test status
Simulation time 22025783 ps
CPU time 1.08 seconds
Started May 11 03:26:33 PM PDT 24
Finished May 11 03:26:34 PM PDT 24
Peak memory 220724 kb
Host smart-e651cd6f-408d-4719-956e-92f006cb2351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067858145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.4067858145
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_err.881246736
Short name T253
Test name
Test status
Simulation time 59940661 ps
CPU time 0.95 seconds
Started May 11 03:26:26 PM PDT 24
Finished May 11 03:26:27 PM PDT 24
Peak memory 216680 kb
Host smart-25b8f0eb-7ab4-4017-a9c7-652309e02133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881246736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.881246736
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.4154875214
Short name T80
Test name
Test status
Simulation time 64878053 ps
CPU time 1 seconds
Started May 11 03:24:37 PM PDT 24
Finished May 11 03:24:39 PM PDT 24
Peak memory 206624 kb
Host smart-711dd192-e607-4cfe-8eea-105250cb0039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154875214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.4154875214
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4057125780
Short name T333
Test name
Test status
Simulation time 30472018 ps
CPU time 0.93 seconds
Started May 11 03:24:45 PM PDT 24
Finished May 11 03:24:47 PM PDT 24
Peak memory 205236 kb
Host smart-6fe840cc-7738-4d9b-819e-1d60cd064473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057125780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.4057125780
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2177143279
Short name T636
Test name
Test status
Simulation time 20198793 ps
CPU time 0.89 seconds
Started May 11 03:24:37 PM PDT 24
Finished May 11 03:24:39 PM PDT 24
Peak memory 215044 kb
Host smart-5faf3466-cbc5-470d-af57-32217e67bff5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177143279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2177143279
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.195329299
Short name T552
Test name
Test status
Simulation time 27088328 ps
CPU time 1.02 seconds
Started May 11 03:24:42 PM PDT 24
Finished May 11 03:24:44 PM PDT 24
Peak memory 215196 kb
Host smart-cd75ca32-2bb5-42d4-930f-3a9d0e4054d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195329299 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.195329299
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.626097014
Short name T514
Test name
Test status
Simulation time 30835848 ps
CPU time 1.05 seconds
Started May 11 03:24:37 PM PDT 24
Finished May 11 03:24:39 PM PDT 24
Peak memory 216524 kb
Host smart-e708e5e9-02a7-4a15-9fcf-a5e6b5a6bfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626097014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.626097014
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.426193996
Short name T294
Test name
Test status
Simulation time 40140868 ps
CPU time 1.03 seconds
Started May 11 03:24:37 PM PDT 24
Finished May 11 03:24:38 PM PDT 24
Peak memory 205920 kb
Host smart-696f22e9-e648-42d3-a214-14d88e3ce254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426193996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.426193996
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3196562488
Short name T609
Test name
Test status
Simulation time 22313232 ps
CPU time 0.9 seconds
Started May 11 03:24:37 PM PDT 24
Finished May 11 03:24:39 PM PDT 24
Peak memory 215268 kb
Host smart-08a480c4-fcd5-4aaf-8e4b-169722d5dafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196562488 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3196562488
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1261568947
Short name T148
Test name
Test status
Simulation time 20462903 ps
CPU time 0.87 seconds
Started May 11 03:24:34 PM PDT 24
Finished May 11 03:24:36 PM PDT 24
Peak memory 205228 kb
Host smart-0ad73bb5-ae89-47b9-8446-da9d48f07f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261568947 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1261568947
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.279517236
Short name T472
Test name
Test status
Simulation time 60293378 ps
CPU time 0.91 seconds
Started May 11 03:24:34 PM PDT 24
Finished May 11 03:24:36 PM PDT 24
Peak memory 205268 kb
Host smart-94982ebf-6217-4361-a172-9638d42b3e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279517236 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.279517236
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.394372010
Short name T539
Test name
Test status
Simulation time 1224172964 ps
CPU time 3.19 seconds
Started May 11 03:24:40 PM PDT 24
Finished May 11 03:24:43 PM PDT 24
Peak memory 206128 kb
Host smart-8973bb8e-1a82-49aa-90c0-9056e6650032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394372010 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.394372010
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2931506887
Short name T622
Test name
Test status
Simulation time 321953329664 ps
CPU time 2135.86 seconds
Started May 11 03:24:40 PM PDT 24
Finished May 11 04:00:16 PM PDT 24
Peak memory 225512 kb
Host smart-16a1fefc-f682-436d-8d20-995da8e6745c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931506887 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2931506887
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3254272413
Short name T60
Test name
Test status
Simulation time 33685675 ps
CPU time 0.96 seconds
Started May 11 03:26:33 PM PDT 24
Finished May 11 03:26:34 PM PDT 24
Peak memory 222520 kb
Host smart-141b734e-e55d-4385-8422-43728d2b667b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254272413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3254272413
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.2550295696
Short name T559
Test name
Test status
Simulation time 72368473 ps
CPU time 1.24 seconds
Started May 11 03:26:32 PM PDT 24
Finished May 11 03:26:34 PM PDT 24
Peak memory 222932 kb
Host smart-049b92bb-bcd4-4e48-811a-226aca4ab4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550295696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2550295696
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/92.edn_err.2403332050
Short name T515
Test name
Test status
Simulation time 23464233 ps
CPU time 1.12 seconds
Started May 11 03:26:31 PM PDT 24
Finished May 11 03:26:32 PM PDT 24
Peak memory 215424 kb
Host smart-5e7adada-3641-4443-a5c7-aa6e4047d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403332050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2403332050
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/93.edn_err.1896428655
Short name T260
Test name
Test status
Simulation time 33394000 ps
CPU time 0.93 seconds
Started May 11 03:26:34 PM PDT 24
Finished May 11 03:26:35 PM PDT 24
Peak memory 216464 kb
Host smart-7162fd03-c846-4743-bb15-1bb70a64f008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896428655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1896428655
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/94.edn_err.3155361216
Short name T581
Test name
Test status
Simulation time 20901874 ps
CPU time 1.36 seconds
Started May 11 03:26:30 PM PDT 24
Finished May 11 03:26:32 PM PDT 24
Peak memory 216652 kb
Host smart-85872877-c737-404a-9692-37fca68a7df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155361216 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3155361216
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/95.edn_err.804265981
Short name T207
Test name
Test status
Simulation time 20049740 ps
CPU time 1.15 seconds
Started May 11 03:26:32 PM PDT 24
Finished May 11 03:26:34 PM PDT 24
Peak memory 222740 kb
Host smart-895ebfcd-8112-46de-8e2a-e44c8ffdfac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804265981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.804265981
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/96.edn_err.3928943025
Short name T189
Test name
Test status
Simulation time 47593102 ps
CPU time 1.13 seconds
Started May 11 03:26:32 PM PDT 24
Finished May 11 03:26:34 PM PDT 24
Peak memory 222724 kb
Host smart-be74b416-9643-40e3-8b3c-79d66a03415a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928943025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3928943025
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_err.1277875352
Short name T540
Test name
Test status
Simulation time 114273807 ps
CPU time 1.28 seconds
Started May 11 03:26:32 PM PDT 24
Finished May 11 03:26:34 PM PDT 24
Peak memory 215464 kb
Host smart-15b11325-0b32-4ea3-b273-b6e759845e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277875352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1277875352
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_err.366212668
Short name T177
Test name
Test status
Simulation time 133120142 ps
CPU time 1.31 seconds
Started May 11 03:26:33 PM PDT 24
Finished May 11 03:26:35 PM PDT 24
Peak memory 228608 kb
Host smart-0625697b-6615-48ab-8aa1-105e334c0ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366212668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.366212668
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_err.1763029228
Short name T150
Test name
Test status
Simulation time 30499822 ps
CPU time 0.99 seconds
Started May 11 03:26:31 PM PDT 24
Finished May 11 03:26:32 PM PDT 24
Peak memory 215264 kb
Host smart-bb0e1f10-ebdc-4869-9f53-ddc1e8fd3bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763029228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1763029228
Directory /workspace/99.edn_err/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%