Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.79	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	77	253	76.67

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	58	222	79.29	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4451

1

T1

3

T2

11

T3

4

auto[1]

506

1

T4

1

T14

2

T26

5

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4451

1

T1

3

T2

11

T3

4

auto[1]

506

1

T4

1

T14

2

T26

5

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4449

1

T1

3

T2

11

T3

4

auto[1]

508

1

T4

2

T13

2

T14

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4449

1

T1

3

T2

11

T3

4

auto[1]

508

1

T4

2

T13

2

T14

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	393	1			T26	3		T70	1		T18	1
auto[OpGenId]	1048	1			T1	1		T3	1		T4	1
auto[OpGenSwOut]	1072	1			T3	1		T4	1		T5	2
auto[OpGenHwOut]	2381	1			T1	1		T2	11		T3	2
auto[OpDisable]	63	1			T1	1		T26	1		T42	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	393	1			T26	3		T70	1		T18	1
auto[OpGenId]	1048	1			T1	1		T3	1		T4	1
auto[OpGenSwOut]	1072	1			T3	1		T4	1		T5	2
auto[OpGenHwOut]	2381	1			T1	1		T2	11		T3	2
auto[OpDisable]	63	1			T1	1		T26	1		T42	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4414

1

T1

2

T2

10

T3

4

auto[1]

543

1

T1

1

T2

1

T4

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4414

1

T1

2

T2

10

T3

4

auto[1]

543

1

T1

1

T2

1

T4

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4691

1

T1

3

T2

11

T3

4

auto[1]

266

1

T108

4

T73

14

T120

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1684	1			T1	2		T2	2		T3	2
auto[1]	617	1			T2	1		T4	1		T5	2
auto[2]	682	1			T1	1		T2	2		T3	1
auto[3]	657	1			T2	2		T5	1		T13	1
auto[4]	313	1			T2	1		T15	1		T17	1
auto[5]	356	1			T75	1		T70	1		T71	1
auto[6]	304	1			T2	2		T5	1		T13	1
auto[7]	344	1			T2	1		T3	1		T26	5

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1317	1			T2	4		T3	1		T5	1
clear_one[1]	617	1			T2	1		T4	1		T5	2
clear_one[2]	682	1			T1	1		T2	2		T3	1
clear_one[3]	657	1			T2	2		T5	1		T13	1
clear_none	1684	1			T1	2		T2	2		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	942	1			T1	1		T2	3		T3	2
auto[StInit]	732	1			T2	1		T5	1		T14	1
auto[StCreatorRootKey]	498	1			T2	1		T3	1		T5	1
auto[StOwnerIntKey]	472	1			T2	1		T4	1		T5	1
auto[StOwnerKey]	432	1			T2	1		T5	1		T15	1
auto[StDisabled]	1729	1			T1	2		T2	4		T3	1
auto[StInvalid]	152	1			T47	3		T41	5		T48	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	942	1			T1	1		T2	3		T3	2
auto[StInit]	732	1			T2	1		T5	1		T14	1
auto[StCreatorRootKey]	498	1			T2	1		T3	1		T5	1
auto[StOwnerIntKey]	472	1			T2	1		T4	1		T5	1
auto[StOwnerKey]	432	1			T2	1		T5	1		T15	1
auto[StDisabled]	1729	1			T1	2		T2	4		T3	1
auto[StInvalid]	152	1			T47	3		T41	5		T48	1

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	58	222	79.29	58

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[6]]	[auto[StInvalid]]	[auto[OpAdvance] , auto[OpGenId]]	--	--	2
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T220	1		T221	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	163	1			T1	1		T26	1		T42	3
auto[0]	auto[StReset]	auto[OpGenSwOut]	157	1			T3	1		T13	1		T26	6
auto[0]	auto[StReset]	auto[OpGenHwOut]	242	1			T2	1		T3	1		T17	1
auto[0]	auto[StInit]	auto[OpAdvance]	48	1			T18	1		T42	1		T44	1
auto[0]	auto[StInit]	auto[OpGenId]	77	1			T17	1		T26	1		T42	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	105	1			T14	1		T42	1		T54	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	177	1			T2	1		T5	1		T15	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	23	1			T42	1		T126	1		T222	3
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	40	1			T75	1		T111	1		T223	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	50	1			T70	1		T42	2		T137	3
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	66	1			T15	1		T44	1		T121	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	16	1			T26	1		T108	1		T191	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	33	1			T4	1		T44	1		T122	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	26	1			T61	1		T7	2		T53	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T71	1		T44	1		T195	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T108	1		T224	1		T225	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	16	1			T226	1		T227	1		T228	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T222	1		T229	1		T230	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T74	1		T42	1		T44	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	17	1			T108	1		T44	1		T7	1
auto[0]	auto[StDisabled]	auto[OpGenId]	42	1			T42	1		T44	2		T182	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	64	1			T14	1		T26	1		T75	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	143	1			T1	1		T4	1		T26	2
auto[0]	auto[StDisabled]	auto[OpDisable]	16	1			T42	1		T231	1		T232	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	8	1			T233	1		T234	1		T235	1
auto[0]	auto[StInvalid]	auto[OpGenId]	13	1			T47	1		T189	1		T197	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T41	1		T192	1		T235	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T47	1		T41	1		T236	1
auto[1]	auto[StReset]	auto[OpGenId]	23	1			T26	1		T57	1		T237	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	23	1			T44	1		T122	1		T182	2
auto[1]	auto[StReset]	auto[OpGenHwOut]	29	1			T26	1		T71	2		T54	1
auto[1]	auto[StInit]	auto[OpAdvance]	6	1			T25	1		T238	1		T227	1
auto[1]	auto[StInit]	auto[OpGenId]	18	1			T49	1		T76	1		T239	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	13	1			T24	1		T240	1		T241	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	22	1			T26	1		T125	1		T242	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T53	1		T221	1		T243	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T26	1		T190	1		T224	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T182	1		T244	1		T224	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T26	1		T71	1		T42	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T220	1		T245	1		T246	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T244	1		T247	1		T248	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T5	1		T8	1		T249	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T250	1		T251	1		T252	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T253	1		-	-		-	-
auto[1]	auto[StOwnerKey]	auto[OpGenId]	15	1			T220	1		T249	1		T254	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T53	1		T220	1		T255	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T71	1		T256	1		T95	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	21	1			T42	1		T44	1		T73	1
auto[1]	auto[StDisabled]	auto[OpGenId]	42	1			T13	1		T73	2		T182	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T5	1		T126	1		T44	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T2	1		T4	1		T74	1
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T257	1		T8	1		T225	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	8	1			T85	1		T236	1		T235	1
auto[1]	auto[StInvalid]	auto[OpGenId]	6	1			T258	1		T194	1		T259	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T85	2		T193	1		T260	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T85	1		T261	1		T262	1
auto[2]	auto[StReset]	auto[OpGenId]	21	1			T53	1		T263	1		T264	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	11	1			T113	1		T88	1		T265	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	48	1			T2	2		T242	1		T199	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T92	1		T266	1		T267	1
auto[2]	auto[StInit]	auto[OpGenId]	20	1			T97	1		T92	1		T202	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	19	1			T268	1		T238	2		T227	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	32	1			T74	1		T71	1		T42	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T42	1		T28	1		T224	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T3	1		T42	1		T124	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T23	1		T182	1		T53	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T42	1		T269	1		T237	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T26	1		T270	1		T271	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T119	1		T255	1		T272	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T53	1		T224	1		T273	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	32	1			T121	1		T242	1		T274	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T120	1		T224	1		T225	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T42	1		T182	1		T273	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T44	1		T275	1		T276	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T15	1		T42	1		T242	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	23	1			T126	1		T7	2		T224	1
auto[2]	auto[StDisabled]	auto[OpGenId]	60	1			T26	2		T75	1		T70	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T4	1		T239	1		T198	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T5	1		T14	1		T15	3
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T1	1		T26	1		T277	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T48	1		T233	1		T234	1
auto[2]	auto[StInvalid]	auto[OpGenId]	4	1			T278	2		T279	1		T280	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T281	1		T282	1		T280	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T283	1		T284	1		T285	1
auto[3]	auto[StReset]	auto[OpGenId]	23	1			T108	1		T277	1		T202	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	14	1			T54	1		T204	1		T247	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	38	1			T74	3		T242	1		T199	1
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T198	1		T8	1		T270	2
auto[3]	auto[StInit]	auto[OpGenId]	18	1			T17	1		T54	1		T113	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	12	1			T44	1		T80	1		T241	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	27	1			T199	1		T25	1		T251	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T137	1		T100	1		T286	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T5	1		T220	1		T270	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T239	1		T53	1		T287	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T2	1		T74	1		T125	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T7	1		T266	1		T273	2
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T13	1		T42	1		T44	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T270	2		T224	1		T247	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T74	1		T26	1		T44	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T26	1		T137	1		T53	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	16	1			T126	1		T54	1		T288	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T44	1		T88	1		T289	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T42	2		T125	1		T72	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	22	1			T44	1		T122	1		T182	1
auto[3]	auto[StDisabled]	auto[OpGenId]	51	1			T75	1		T42	2		T223	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T26	3		T75	1		T42	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	145	1			T2	1		T74	2		T70	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T54	1		T44	1		T290	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	1	1			T291	1		-	-		-	-
auto[3]	auto[StInvalid]	auto[OpGenId]	5	1			T41	1		T260	1		T262	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T261	1		T292	1		T282	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T41	1		T192	1		T197	1
auto[4]	auto[StReset]	auto[OpGenId]	6	1			T57	1		T192	1		T213	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	10	1			T204	2		T267	1		T293	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	13	1			T294	1		T295	1		T296	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T297	1		T298	1		T299	1
auto[4]	auto[StInit]	auto[OpGenId]	7	1			T17	1		T19	1		T204	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	9	1			T42	1		T300	1		T78	2
auto[4]	auto[StInit]	auto[OpGenHwOut]	9	1			T44	1		T57	1		T263	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T297	1		T301	1		T302	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T204	1		T225	1		T215	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T268	1		T272	1		T303	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T96	1		T7	1		T250	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T288	1		T304	1		T81	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T224	1		T305	1		T306	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T63	1		T307	1		T64	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T108	1		T200	1		T62	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T220	1		T308	1		T309	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	3	1			T310	1		T308	1		T311	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T44	1		T224	1		T293	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T2	1		T121	1		T7	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	14	1			T70	1		T44	2		T220	1
auto[4]	auto[StDisabled]	auto[OpGenId]	24	1			T44	2		T182	1		T204	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T54	1		T44	1		T248	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T15	1		T74	1		T26	2
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T54	1		T182	1		T312	1
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T189	1		T233	1		T194	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T85	1		T235	1		T313	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T260	1		T314	1		T315	1
auto[5]	auto[StReset]	auto[OpGenId]	8	1			T239	1		T316	1		T317	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T70	1		T38	1		T182	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	24	1			T71	1		T242	1		T50	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T24	1		T318	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T86	1		T319	1		T320	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	11	1			T73	1		T92	1		T48	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	9	1			T44	1		T77	1		T296	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T73	1		-	-		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T73	1		T216	1		T321	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T44	1		T39	1		T224	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T46	1		T225	2		T322	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T44	1		T73	2		T19	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T75	1		T53	1		T64	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T54	1		T323	1		T53	2
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T199	1		T269	1		T324	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T10	1		T325	1		T326	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	5	1			T19	1		T8	1		T224	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T224	1		T327	1		T328	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	30	1			T73	3		T119	1		T190	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	18	1			T42	1		T73	2		T198	1
auto[5]	auto[StDisabled]	auto[OpGenId]	33	1			T42	2		T126	1		T54	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T44	1		T73	1		T256	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T125	1		T44	1		T73	2
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T67	1		T329	1		T330	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T236	1		T196	1		T260	1
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T331	1		T332	1		T333	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T192	1		T193	1		T283	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T234	1		T334	1		T315	1
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T42	1		T44	1		T57	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	14	1			T13	1		T239	1		T46	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	14	1			T71	1		T122	1		T239	1
auto[6]	auto[StInit]	auto[OpAdvance]	5	1			T204	1		T335	1		T336	1
auto[6]	auto[StInit]	auto[OpGenId]	9	1			T17	1		T337	1		T80	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	8	1			T24	1		T111	1		T337	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	10	1			T92	1		T338	1		T322	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T335	1		T339	1		T299	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T255	1		T340	1		T341	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T54	1		T225	1		T227	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T342	1		T343	1		T344	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T345	1		T302	2		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T26	1		T190	1		T346	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T28	1		T204	1		T247	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T2	1		T15	1		T70	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T243	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	9	1			T5	1		T26	1		T224	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T42	1		T57	1		T347	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T348	1		T252	1		T349	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	14	1			T108	2		T182	1		T239	1
auto[6]	auto[StDisabled]	auto[OpGenId]	27	1			T42	1		T195	1		T350	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	14	1			T26	1		T42	1		T120	3
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T2	1		T26	1		T71	1
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T244	1		T215	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T196	1		T351	1		T279	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T261	1		T285	1		-	-
auto[7]	auto[StReset]	auto[OpGenId]	13	1			T113	1		T92	1		T263	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	8	1			T352	1		T142	1		T353	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	19	1			T26	1		T54	1		T111	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T224	1		T77	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	11	1			T195	1		T7	1		T80	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	5	1			T42	1		T44	1		T354	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	14	1			T52	1		T355	1		T295	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T44	1		T204	1		T293	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T352	1		T308	1		T356	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T42	1		T224	1		T290	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T72	1		T357	1		T201	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T297	2		T358	1		T359	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T256	1		T58	1		T204	2
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T26	1		T42	1		T237	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T125	1		T360	1		T355	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T247	1		-	-		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T7	1		T8	1		T225	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T8	1		T243	1		T64	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T26	1		T357	1		T361	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	6	1			T53	1		T270	1		T362	1
auto[7]	auto[StDisabled]	auto[OpGenId]	25	1			T26	1		T42	1		T44	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T26	1		T61	1		T231	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T2	1		T3	1		T72	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T204	1		T363	1		T68	2
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T364	1		T283	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T292	1		T331	1		T365	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T41	1		T197	1		T258	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T47	1		T235	1		T280	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1317

1

T2

4

T3

1

T5

1

clear_one[1]

auto[0]

auto[0]

auto[0]

341

1

T5

2

T26

6

T71

4

clear_one[1]

auto[0]

auto[0]

auto[1]

119

1

T2

1

T74

1

T26

1

clear_one[1]

auto[0]

auto[1]

auto[0]

124

1

T13

1

T26

1

T44

1

clear_one[1]

auto[0]

auto[1]

auto[1]

33

1

T4

1

T366

1

T46

1

clear_one[2]

auto[0]

auto[0]

auto[0]

387

1

T1

1

T2

2

T3

1

clear_one[2]

auto[0]

auto[0]

auto[1]

135

1

T4

1

T15

4

T26

2

clear_one[2]

auto[1]

auto[0]

auto[0]

110

1

T14

1

T26

1

T42

1

clear_one[2]

auto[1]

auto[0]

auto[1]

50

1

T26

1

T42

2

T126

1

clear_one[3]

auto[0]

auto[0]

auto[0]

398

1

T2

2

T5

1

T17

1

clear_one[3]

auto[0]

auto[1]

auto[0]

118

1

T13

1

T26

2

T70

1

clear_one[3]

auto[1]

auto[0]

auto[0]

109

1

T26

2

T71

2

T42

2

clear_one[3]

auto[1]

auto[1]

auto[0]

32

1

T42

2

T44

1

T366

1

clear_none

auto[0]

auto[0]

auto[0]

1212

1

T1

1

T2

2

T3

2

clear_none

auto[0]

auto[0]

auto[1]

124

1

T1

1

T15

1

T74

1

clear_none

auto[0]

auto[1]

auto[0]

114

1

T26

1

T54

1

T44

2

clear_none

auto[0]

auto[1]

auto[1]

29

1

T26

1

T277

1

T7

3

clear_none

auto[1]

auto[0]

auto[0]

115

1

T70

1

T71

2

T42

1

clear_none

auto[1]

auto[0]

auto[1]

32

1

T97

1

T46

1

T367

2

clear_none

auto[1]

auto[1]

auto[0]

37

1

T14

1

T42

3

T44

2

clear_none

auto[1]

auto[1]

auto[1]

21

1

T4

1

T26

1

T230

9

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1228	1			T2	4		T3	1		T5	1
clear_all	auto[1]	89	1			T108	2		T73	12		T120	2
clear_one[1]	auto[0]	591	1			T2	1		T4	1		T5	2
clear_one[1]	auto[1]	26	1			T73	2		T366	3		T220	2
clear_one[2]	auto[0]	647	1			T1	1		T2	2		T3	1
clear_one[2]	auto[1]	35	1			T270	2		T268	1		T304	1
clear_one[3]	auto[0]	609	1			T2	2		T5	1		T13	1
clear_one[3]	auto[1]	48	1			T137	3		T220	1		T270	9
clear_none	auto[0]	1616	1			T1	2		T2	2		T3	2
clear_none	auto[1]	68	1			T108	2		T137	3		T222	6