Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11091

1

T1

4

T2

14

T3

13

auto[Attestation]

7705

1

T2

3

T3

5

T4

14

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2726	1			T1	2		T3	5		T4	6
auto[Aes]	3351	1			T3	5		T4	5		T5	1
auto[Kmac]	3412	1			T3	2		T4	1		T13	5
auto[Otbn]	3392	1			T1	1		T2	17		T3	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7525	1			T1	1		T2	8		T3	3
auto[OpGenId]	5915	1			T1	1		T3	4		T4	6
auto[OpGenSwOut]	5891	1			T3	6		T4	9		T5	2
auto[OpGenHwOut]	6990	1			T1	3		T2	17		T3	8
auto[OpDisable]	125	1			T1	1		T3	1		T26	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9707

1

T1

2

T2

8

T3

4

auto[OpDoneFail]

16739

1

T1

4

T2

17

T3

18

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6386	1			T1	3		T2	10		T3	12
auto[StInit]	4323	1			T1	2		T2	2		T3	4
auto[StCreatorRootKey]	2821	1			T2	2		T3	2		T4	1
auto[StOwnerIntKey]	2469	1			T2	2		T4	3		T5	2
auto[StOwnerKey]	2283	1			T2	2		T4	6		T5	2
auto[StDisabled]	7222	1			T1	1		T2	7		T3	4
auto[StInvalid]	942	1			T47	23		T41	21		T48	20

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	309	1			T3	1		T13	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	130	1			T30	1		T26	3		T51	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	63	1			T26	1		T42	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	54	1			T70	1		T42	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T4	1		T26	1		T42	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	205	1			T13	1		T26	2		T75	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	30	1			T41	2		T48	1		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	309	1			T3	2		T17	2		T26	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	123	1			T4	1		T14	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	72	1			T26	1		T42	1		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	62	1			T5	1		T26	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	58	1			T4	1		T26	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	202	1			T13	1		T26	2		T42	5
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	29	1			T41	1		T48	1		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	355	1			T3	2		T13	2		T26	6
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	122	1			T17	1		T26	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T70	1		T42	2		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	61	1			T14	1		T137	1		T190	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	57	1			T42	1		T54	1		T191	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	209	1			T26	1		T42	2		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	30	1			T47	1		T41	1		T189	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	319	1			T3	1		T13	1		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	129	1			T17	2		T42	5		T54	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	74	1			T42	1		T44	4		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	58	1			T14	1		T26	1		T44	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	56	1			T4	1		T26	2		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	185	1			T4	1		T26	4		T42	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	28	1			T47	1		T41	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	82	1			T26	5		T44	3		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	120	1			T26	1		T42	2		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	66	1			T42	2		T44	1		T185	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	59	1			T42	1		T57	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	49	1			T4	2		T14	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	181	1			T5	1		T26	5		T42	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	33	1			T47	2		T41	2		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	70	1			T42	1		T44	5		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	105	1			T17	2		T26	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	58	1			T51	1		T70	1		T44	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	63	1			T42	1		T44	2		T185	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	55	1			T26	1		T44	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	177	1			T4	1		T26	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	27	1			T47	1		T48	1		T85	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	100	1			T26	1		T42	1		T44	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	122	1			T30	1		T26	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	65	1			T30	1		T26	1		T42	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	62	1			T26	3		T42	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	51	1			T26	1		T70	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	211	1			T26	4		T75	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	17	1			T85	1		T193	1		T194	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	68	1			T26	1		T44	3		T182	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	140	1			T26	1		T35	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	71	1			T26	3		T42	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	79	1			T42	1		T44	4		T122	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	67	1			T26	1		T70	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	211	1			T4	1		T14	1		T26	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	21	1			T189	1		T85	1		T192	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	277	1			T1	1		T3	1		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	103	1			T1	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	72	1			T14	1		T30	1		T26	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	53	1			T14	1		T26	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	38	1			T54	1		T44	2		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	170	1			T3	1		T26	7		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	35	1			T189	2		T192	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	485	1			T3	2		T13	2		T17	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	115	1			T17	1		T26	2		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	87	1			T26	1		T70	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	88	1			T26	2		T35	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	81	1			T14	1		T26	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	256	1			T4	1		T26	4		T71	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	33	1			T41	2		T48	2		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	456	1			T16	1		T17	1		T26	5
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	127	1			T42	2		T44	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	97	1			T51	1		T18	1		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T13	1		T26	1		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	96	1			T26	1		T42	2		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	255	1			T4	1		T14	2		T26	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T47	1		T41	1		T189	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	422	1			T2	9		T3	1		T74	12
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	140	1			T2	1		T15	1		T74	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T2	1		T15	1		T74	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	99	1			T15	1		T74	1		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	85	1			T2	1		T15	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	261	1			T1	1		T2	2		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	19	1			T41	1		T85	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	55	1			T26	2		T44	4		T48	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T4	1		T5	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	59	1			T26	1		T44	3		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	44	1			T42	1		T124	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T26	1		T126	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	192	1			T3	1		T4	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	33	1			T41	2		T189	3		T85	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	51	1			T26	3		T44	4		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	173	1			T3	1		T30	1		T26	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	103	1			T42	1		T108	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	82	1			T199	1		T200	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	82	1			T35	1		T42	2		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	278	1			T4	1		T13	1		T26	6
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	27	1			T47	1		T48	1		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	51	1			T26	4		T44	2		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	151	1			T13	1		T26	2		T42	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T26	1		T35	1		T42	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T70	1		T121	1		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	70	1			T26	1		T57	1		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	246	1			T13	1		T26	5		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	18	1			T41	1		T48	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	61	1			T44	6		T49	2		T182	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	117	1			T17	1		T42	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T42	1		T44	3		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	96	1			T2	1		T26	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	85	1			T74	1		T26	3		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	253	1			T2	2		T4	3		T15	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	33	1			T189	1		T85	3		T192	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	163	1			T4	1		T26	2		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	686	1			T3	1		T13	2		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	176	1			T4	1		T5	1		T26	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	679	1			T3	2		T4	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	189	1			T14	1		T70	1		T42	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	719	1			T3	2		T13	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	180	1			T4	1		T14	1		T26	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	669	1			T3	1		T4	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	157	1			T4	2		T14	1		T42	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	433	1			T5	1		T26	11		T42	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	172	1			T26	1		T51	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	383	1			T4	1		T17	2		T26	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	167	1			T30	1		T26	5		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	461	1			T30	1		T26	6		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	199	1			T26	4		T70	1		T42	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	458	1			T4	1		T14	1		T26	5
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	152	1			T14	2		T30	1		T26	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	596	1			T1	2		T3	3		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	242	1			T14	1		T26	4		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	903	1			T3	2		T4	1		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	262	1			T13	1		T26	2		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	881	1			T4	1		T14	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	284	1			T2	2		T15	3		T74	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	855	1			T1	1		T2	12		T3	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	147	1			T26	2		T42	1		T124	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	392	1			T3	1		T4	2		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	251	1			T35	1		T42	3		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	545	1			T3	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	257	1			T26	2		T35	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	476	1			T13	2		T26	11		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	271	1			T2	1		T74	1		T26	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	476	1			T2	2		T4	3		T15	3