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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1516 1 T1 2 T3 4 T4 2
auto[1] 1614 1 T1 1 T3 1 T4 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 92 1 T17 1 T26 3 T42 1
auto[134217728:268435455] 90 1 T26 1 T42 2 T44 1
auto[268435456:402653183] 95 1 T17 1 T26 1 T42 1
auto[402653184:536870911] 90 1 T26 2 T18 1 T42 3
auto[536870912:671088639] 93 1 T3 1 T26 3 T54 1
auto[671088640:805306367] 95 1 T51 1 T42 4 T44 4
auto[805306368:939524095] 115 1 T4 1 T26 2 T42 1
auto[939524096:1073741823] 83 1 T42 2 T54 1 T23 2
auto[1073741824:1207959551] 89 1 T17 1 T70 2 T42 4
auto[1207959552:1342177279] 97 1 T26 1 T42 1 T44 1
auto[1342177280:1476395007] 94 1 T13 1 T26 2 T42 1
auto[1476395008:1610612735] 97 1 T3 1 T70 1 T42 1
auto[1610612736:1744830463] 78 1 T4 1 T42 1 T44 1
auto[1744830464:1879048191] 95 1 T13 1 T14 1 T26 1
auto[1879048192:2013265919] 116 1 T14 1 T42 5 T124 1
auto[2013265920:2147483647] 110 1 T14 2 T26 1 T42 2
auto[2147483648:2281701375] 105 1 T1 1 T42 3 T54 1
auto[2281701376:2415919103] 106 1 T17 1 T26 2 T42 1
auto[2415919104:2550136831] 89 1 T17 1 T26 1 T42 1
auto[2550136832:2684354559] 98 1 T14 1 T70 1 T42 2
auto[2684354560:2818572287] 103 1 T3 1 T4 2 T42 4
auto[2818572288:2952790015] 98 1 T1 1 T26 2 T70 1
auto[2952790016:3087007743] 101 1 T1 1 T26 1 T42 2
auto[3087007744:3221225471] 93 1 T3 1 T42 1 T44 3
auto[3221225472:3355443199] 91 1 T30 2 T26 1 T42 1
auto[3355443200:3489660927] 93 1 T26 1 T44 6 T277 1
auto[3489660928:3623878655] 103 1 T17 1 T30 1 T26 1
auto[3623878656:3758096383] 97 1 T42 2 T44 3 T49 1
auto[3758096384:3892314111] 106 1 T26 4 T42 2 T44 2
auto[3892314112:4026531839] 109 1 T16 1 T17 1 T18 1
auto[4026531840:4160749567] 108 1 T3 1 T26 2 T70 1
auto[4160749568:4294967295] 101 1 T26 1 T51 1 T42 4


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 47 1 T17 1 T26 3 T23 1
auto[0:134217727] auto[1] 45 1 T42 1 T120 1 T191 1
auto[134217728:268435455] auto[0] 39 1 T26 1 T42 1 T44 1
auto[134217728:268435455] auto[1] 51 1 T42 1 T50 1 T41 1
auto[268435456:402653183] auto[0] 48 1 T23 1 T44 1 T182 1
auto[268435456:402653183] auto[1] 47 1 T17 1 T26 1 T42 1
auto[402653184:536870911] auto[0] 40 1 T18 1 T42 1 T54 1
auto[402653184:536870911] auto[1] 50 1 T26 2 T42 2 T44 1
auto[536870912:671088639] auto[0] 51 1 T3 1 T26 1 T54 1
auto[536870912:671088639] auto[1] 42 1 T26 2 T366 1 T310 1
auto[671088640:805306367] auto[0] 41 1 T42 2 T44 1 T24 1
auto[671088640:805306367] auto[1] 54 1 T51 1 T42 2 T44 3
auto[805306368:939524095] auto[0] 57 1 T26 1 T42 1 T54 1
auto[805306368:939524095] auto[1] 58 1 T4 1 T26 1 T108 1
auto[939524096:1073741823] auto[0] 42 1 T42 1 T54 1 T23 1
auto[939524096:1073741823] auto[1] 41 1 T42 1 T23 1 T44 1
auto[1073741824:1207959551] auto[0] 47 1 T17 1 T70 2 T42 1
auto[1073741824:1207959551] auto[1] 42 1 T42 3 T124 2 T44 1
auto[1207959552:1342177279] auto[0] 43 1 T122 1 T24 1 T182 1
auto[1207959552:1342177279] auto[1] 54 1 T26 1 T42 1 T44 1
auto[1342177280:1476395007] auto[0] 47 1 T26 1 T46 1 T222 1
auto[1342177280:1476395007] auto[1] 47 1 T13 1 T26 1 T42 1
auto[1476395008:1610612735] auto[0] 45 1 T70 1 T198 1 T113 1
auto[1476395008:1610612735] auto[1] 52 1 T3 1 T42 1 T124 1
auto[1610612736:1744830463] auto[0] 39 1 T4 1 T42 1 T44 1
auto[1610612736:1744830463] auto[1] 39 1 T119 1 T198 1 T189 1
auto[1744830464:1879048191] auto[0] 49 1 T13 1 T14 1 T42 1
auto[1744830464:1879048191] auto[1] 46 1 T26 1 T42 1 T44 1
auto[1879048192:2013265919] auto[0] 59 1 T14 1 T42 2 T44 1
auto[1879048192:2013265919] auto[1] 57 1 T42 3 T124 1 T54 2
auto[2013265920:2147483647] auto[0] 62 1 T14 2 T42 1 T44 1
auto[2013265920:2147483647] auto[1] 48 1 T26 1 T42 1 T44 1
auto[2147483648:2281701375] auto[0] 40 1 T1 1 T42 1 T57 1
auto[2147483648:2281701375] auto[1] 65 1 T42 2 T54 1 T44 1
auto[2281701376:2415919103] auto[0] 46 1 T17 1 T26 2 T42 1
auto[2281701376:2415919103] auto[1] 60 1 T126 1 T44 2 T182 3
auto[2415919104:2550136831] auto[0] 46 1 T17 1 T26 1 T42 1
auto[2415919104:2550136831] auto[1] 43 1 T126 1 T198 1 T87 1
auto[2550136832:2684354559] auto[0] 51 1 T14 1 T70 1 T108 1
auto[2550136832:2684354559] auto[1] 47 1 T42 2 T122 1 T41 1
auto[2684354560:2818572287] auto[0] 51 1 T3 1 T4 1 T42 2
auto[2684354560:2818572287] auto[1] 52 1 T4 1 T42 2 T124 1
auto[2818572288:2952790015] auto[0] 46 1 T1 1 T191 1 T232 1
auto[2818572288:2952790015] auto[1] 52 1 T26 2 T70 1 T108 1
auto[2952790016:3087007743] auto[0] 48 1 T42 1 T54 1 T44 2
auto[2952790016:3087007743] auto[1] 53 1 T1 1 T26 1 T42 1
auto[3087007744:3221225471] auto[0] 47 1 T3 1 T42 1 T44 1
auto[3087007744:3221225471] auto[1] 46 1 T44 2 T182 1 T87 1
auto[3221225472:3355443199] auto[0] 46 1 T30 1 T42 1 T126 1
auto[3221225472:3355443199] auto[1] 45 1 T30 1 T26 1 T23 1
auto[3355443200:3489660927] auto[0] 41 1 T44 2 T277 1 T38 1
auto[3355443200:3489660927] auto[1] 52 1 T26 1 T44 4 T182 1
auto[3489660928:3623878655] auto[0] 45 1 T17 1 T30 1 T44 1
auto[3489660928:3623878655] auto[1] 58 1 T26 1 T31 1 T73 1
auto[3623878656:3758096383] auto[0] 50 1 T44 3 T24 1 T232 1
auto[3623878656:3758096383] auto[1] 47 1 T42 2 T49 1 T239 1
auto[3758096384:3892314111] auto[0] 47 1 T26 1 T42 2 T44 2
auto[3758096384:3892314111] auto[1] 59 1 T26 3 T97 1 T41 1
auto[3892314112:4026531839] auto[0] 54 1 T17 1 T18 1 T42 1
auto[3892314112:4026531839] auto[1] 55 1 T16 1 T44 1 T277 1
auto[4026531840:4160749567] auto[0] 55 1 T3 1 T26 1 T44 2
auto[4026531840:4160749567] auto[1] 53 1 T26 1 T70 1 T42 1
auto[4160749568:4294967295] auto[0] 47 1 T26 1 T42 1 T44 1
auto[4160749568:4294967295] auto[1] 54 1 T51 1 T42 3 T137 1

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