Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6444

1

T1

6

T3

9

T4

7

auto[1]

301

1

T108

4

T73

17

T120

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2753	1			T1	3		T3	4		T4	2
auto[134217728:268435455]	173	1			T4	1		T14	1		T30	1
auto[268435456:402653183]	148	1			T4	1		T26	2		T18	1
auto[402653184:536870911]	135	1			T17	1		T42	2		T108	1
auto[536870912:671088639]	128	1			T54	1		T23	2		T44	1
auto[671088640:805306367]	140	1			T26	2		T108	1		T124	1
auto[805306368:939524095]	114	1			T1	1		T26	2		T70	2
auto[939524096:1073741823]	128	1			T17	1		T26	1		T42	1
auto[1073741824:1207959551]	117	1			T26	2		T42	2		T54	1
auto[1207959552:1342177279]	124	1			T42	1		T124	1		T54	1
auto[1342177280:1476395007]	125	1			T17	1		T42	2		T108	1
auto[1476395008:1610612735]	129	1			T14	1		T42	2		T126	1
auto[1610612736:1744830463]	124	1			T3	1		T4	1		T26	2
auto[1744830464:1879048191]	108	1			T70	1		T42	4		T44	2
auto[1879048192:2013265919]	103	1			T4	1		T26	1		T70	1
auto[2013265920:2147483647]	129	1			T3	1		T17	1		T26	2
auto[2147483648:2281701375]	126	1			T14	1		T26	1		T42	3
auto[2281701376:2415919103]	128	1			T13	1		T14	1		T26	1
auto[2415919104:2550136831]	134	1			T26	1		T42	2		T44	2
auto[2550136832:2684354559]	121	1			T17	2		T42	1		T124	1
auto[2684354560:2818572287]	132	1			T3	1		T14	1		T17	1
auto[2818572288:2952790015]	118	1			T3	1		T16	1		T17	2
auto[2952790016:3087007743]	121	1			T14	2		T26	2		T51	1
auto[3087007744:3221225471]	114	1			T14	1		T26	1		T70	2
auto[3221225472:3355443199]	149	1			T1	2		T26	3		T42	2
auto[3355443200:3489660927]	108	1			T3	1		T26	1		T42	2
auto[3489660928:3623878655]	145	1			T17	1		T42	3		T108	3
auto[3623878656:3758096383]	124	1			T4	1		T42	3		T124	1
auto[3758096384:3892314111]	144	1			T26	1		T42	1		T124	2
auto[3892314112:4026531839]	134	1			T18	1		T42	3		T124	2
auto[4026531840:4160749567]	136	1			T26	2		T42	3		T108	1
auto[4160749568:4294967295]	133	1			T30	1		T26	4		T42	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2741	1			T1	3		T3	4		T4	2
auto[0:134217727]	auto[1]	12	1			T73	1		T120	1		T137	3
auto[134217728:268435455]	auto[0]	165	1			T4	1		T14	1		T30	1
auto[134217728:268435455]	auto[1]	8	1			T220	2		T271	1		T388	1
auto[268435456:402653183]	auto[0]	142	1			T4	1		T26	2		T18	1
auto[268435456:402653183]	auto[1]	6	1			T73	1		T376	1		T392	1
auto[402653184:536870911]	auto[0]	125	1			T17	1		T42	2		T54	1
auto[402653184:536870911]	auto[1]	10	1			T108	1		T137	1		T222	2
auto[536870912:671088639]	auto[0]	119	1			T54	1		T23	2		T44	1
auto[536870912:671088639]	auto[1]	9	1			T222	1		T230	1		T270	1
auto[671088640:805306367]	auto[0]	131	1			T26	2		T124	1		T44	6
auto[671088640:805306367]	auto[1]	9	1			T108	1		T120	1		T222	2
auto[805306368:939524095]	auto[0]	109	1			T1	1		T26	2		T70	2
auto[805306368:939524095]	auto[1]	5	1			T381	1		T393	2		T297	1
auto[939524096:1073741823]	auto[0]	119	1			T17	1		T26	1		T42	1
auto[939524096:1073741823]	auto[1]	9	1			T229	1		T376	2		T383	1
auto[1073741824:1207959551]	auto[0]	105	1			T26	2		T42	2		T54	1
auto[1073741824:1207959551]	auto[1]	12	1			T73	2		T120	1		T137	1
auto[1207959552:1342177279]	auto[0]	112	1			T42	1		T124	1		T54	1
auto[1207959552:1342177279]	auto[1]	12	1			T222	2		T230	1		T345	1
auto[1342177280:1476395007]	auto[0]	118	1			T17	1		T42	2		T108	1
auto[1342177280:1476395007]	auto[1]	7	1			T222	1		T248	1		T385	1
auto[1476395008:1610612735]	auto[0]	119	1			T14	1		T42	2		T126	1
auto[1476395008:1610612735]	auto[1]	10	1			T73	2		T367	1		T304	1
auto[1610612736:1744830463]	auto[0]	113	1			T3	1		T4	1		T26	2
auto[1610612736:1744830463]	auto[1]	11	1			T120	1		T304	3		T383	1
auto[1744830464:1879048191]	auto[0]	98	1			T70	1		T42	4		T44	2
auto[1744830464:1879048191]	auto[1]	10	1			T222	1		T345	1		T394	1
auto[1879048192:2013265919]	auto[0]	96	1			T4	1		T26	1		T70	1
auto[1879048192:2013265919]	auto[1]	7	1			T230	1		T221	1		T381	1
auto[2013265920:2147483647]	auto[0]	117	1			T3	1		T17	1		T26	2
auto[2013265920:2147483647]	auto[1]	12	1			T366	1		T270	1		T388	1
auto[2147483648:2281701375]	auto[0]	118	1			T14	1		T26	1		T42	3
auto[2147483648:2281701375]	auto[1]	8	1			T366	1		T317	1		T271	2
auto[2281701376:2415919103]	auto[0]	122	1			T13	1		T14	1		T26	1
auto[2281701376:2415919103]	auto[1]	6	1			T270	1		T345	1		T385	1
auto[2415919104:2550136831]	auto[0]	120	1			T26	1		T42	2		T44	2
auto[2415919104:2550136831]	auto[1]	14	1			T73	2		T222	1		T304	1
auto[2550136832:2684354559]	auto[0]	112	1			T17	2		T42	1		T124	1
auto[2550136832:2684354559]	auto[1]	9	1			T73	2		T120	1		T376	1
auto[2684354560:2818572287]	auto[0]	121	1			T3	1		T14	1		T17	1
auto[2684354560:2818572287]	auto[1]	11	1			T73	2		T376	1		T220	1
auto[2818572288:2952790015]	auto[0]	108	1			T3	1		T16	1		T17	2
auto[2818572288:2952790015]	auto[1]	10	1			T137	1		T230	1		T270	1
auto[2952790016:3087007743]	auto[0]	106	1			T14	2		T26	2		T51	1
auto[2952790016:3087007743]	auto[1]	15	1			T366	1		T230	3		T367	2
auto[3087007744:3221225471]	auto[0]	106	1			T14	1		T26	1		T70	2
auto[3087007744:3221225471]	auto[1]	8	1			T230	1		T345	1		T383	2
auto[3221225472:3355443199]	auto[0]	134	1			T1	2		T26	3		T42	2
auto[3221225472:3355443199]	auto[1]	15	1			T73	1		T230	1		T382	1
auto[3355443200:3489660927]	auto[0]	102	1			T3	1		T26	1		T42	2
auto[3355443200:3489660927]	auto[1]	6	1			T366	1		T248	1		T271	1
auto[3489660928:3623878655]	auto[0]	133	1			T17	1		T42	3		T108	1
auto[3489660928:3623878655]	auto[1]	12	1			T108	2		T73	1		T222	1
auto[3623878656:3758096383]	auto[0]	120	1			T4	1		T42	3		T124	1
auto[3623878656:3758096383]	auto[1]	4	1			T304	1		T271	1		T245	1
auto[3758096384:3892314111]	auto[0]	135	1			T26	1		T42	1		T124	2
auto[3758096384:3892314111]	auto[1]	9	1			T73	2		T137	1		T304	1
auto[3892314112:4026531839]	auto[0]	126	1			T18	1		T42	3		T124	2
auto[3892314112:4026531839]	auto[1]	8	1			T73	1		T385	1		T307	2
auto[4026531840:4160749567]	auto[0]	129	1			T26	2		T42	3		T108	1
auto[4026531840:4160749567]	auto[1]	7	1			T120	1		T230	1		T387	1
auto[4160749568:4294967295]	auto[0]	123	1			T30	1		T26	4		T42	2
auto[4160749568:4294967295]	auto[1]	10	1			T120	1		T137	1		T248	1