Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.83 99.10 98.07 98.58 100.00 99.11 98.41 91.58


Total test records in report: 1056
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T1009 /workspace/coverage/default/39.keymgr_sync_async_fault_cross.199876762 Jan 22 05:04:43 PM PST 24 Jan 22 05:04:47 PM PST 24 86438024 ps
T1010 /workspace/coverage/default/6.keymgr_sw_invalid_input.2022662588 Jan 22 04:59:35 PM PST 24 Jan 22 04:59:40 PM PST 24 386556779 ps
T1011 /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3975442317 Jan 22 05:05:23 PM PST 24 Jan 22 05:05:28 PM PST 24 668814057 ps
T1012 /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1201879821 Jan 22 04:59:51 PM PST 24 Jan 22 04:59:55 PM PST 24 74453433 ps
T1013 /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3182196967 Jan 22 05:02:02 PM PST 24 Jan 22 05:02:16 PM PST 24 1524006537 ps
T351 /workspace/coverage/default/43.keymgr_kmac_rsp_err.1417835915 Jan 22 05:05:26 PM PST 24 Jan 22 05:05:31 PM PST 24 69859784 ps
T278 /workspace/coverage/default/27.keymgr_kmac_rsp_err.3710359378 Jan 22 05:03:00 PM PST 24 Jan 22 05:03:07 PM PST 24 1486181286 ps
T1014 /workspace/coverage/default/27.keymgr_custom_cm.3610713803 Jan 22 05:02:42 PM PST 24 Jan 22 05:02:54 PM PST 24 1421904985 ps
T1015 /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3613830192 Jan 22 05:03:44 PM PST 24 Jan 22 05:03:49 PM PST 24 227506294 ps
T1016 /workspace/coverage/default/9.keymgr_sideload_aes.1349069079 Jan 22 05:00:04 PM PST 24 Jan 22 05:00:11 PM PST 24 166741288 ps
T1017 /workspace/coverage/default/14.keymgr_cfg_regwen.2948764096 Jan 22 05:00:42 PM PST 24 Jan 22 05:01:06 PM PST 24 694149125 ps
T1018 /workspace/coverage/default/27.keymgr_smoke.3662201770 Jan 22 05:53:13 PM PST 24 Jan 22 05:53:23 PM PST 24 43047217 ps
T1019 /workspace/coverage/default/34.keymgr_sideload_aes.2942718708 Jan 22 05:03:57 PM PST 24 Jan 22 05:04:02 PM PST 24 337956576 ps
T1020 /workspace/coverage/default/31.keymgr_alert_test.4005728347 Jan 22 05:36:07 PM PST 24 Jan 22 05:36:19 PM PST 24 33150017 ps
T1021 /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3682939943 Jan 22 05:00:05 PM PST 24 Jan 22 05:00:12 PM PST 24 138098946 ps
T1022 /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2559486494 Jan 22 05:03:46 PM PST 24 Jan 22 05:03:52 PM PST 24 516549582 ps
T1023 /workspace/coverage/default/14.keymgr_random.3434660659 Jan 22 05:00:42 PM PST 24 Jan 22 05:00:53 PM PST 24 176579288 ps
T1024 /workspace/coverage/default/19.keymgr_alert_test.3908893491 Jan 22 05:01:40 PM PST 24 Jan 22 05:01:41 PM PST 24 13659985 ps
T1025 /workspace/coverage/default/31.keymgr_sideload_aes.3347580740 Jan 22 05:03:09 PM PST 24 Jan 22 05:03:18 PM PST 24 414362144 ps
T1026 /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3657789696 Jan 22 04:59:29 PM PST 24 Jan 22 04:59:47 PM PST 24 1725008106 ps
T1027 /workspace/coverage/default/21.keymgr_stress_all.1395130152 Jan 22 05:01:48 PM PST 24 Jan 22 05:03:35 PM PST 24 14787640207 ps
T1028 /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1282851546 Jan 22 05:05:26 PM PST 24 Jan 22 05:05:30 PM PST 24 124706135 ps
T1029 /workspace/coverage/default/29.keymgr_sw_invalid_input.1005241481 Jan 22 05:02:53 PM PST 24 Jan 22 05:03:02 PM PST 24 106048312 ps
T1030 /workspace/coverage/default/41.keymgr_alert_test.2603914590 Jan 22 05:05:11 PM PST 24 Jan 22 05:05:14 PM PST 24 55042109 ps
T1031 /workspace/coverage/default/2.keymgr_random.3465748246 Jan 22 04:59:05 PM PST 24 Jan 22 04:59:10 PM PST 24 438691130 ps
T22 /workspace/coverage/default/42.keymgr_custom_cm.1198537542 Jan 22 05:05:15 PM PST 24 Jan 22 05:05:20 PM PST 24 70706216 ps
T1032 /workspace/coverage/default/41.keymgr_random.2338186064 Jan 22 05:04:54 PM PST 24 Jan 22 05:05:02 PM PST 24 294221931 ps
T1033 /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1322336806 Jan 22 05:02:59 PM PST 24 Jan 22 05:03:04 PM PST 24 357587112 ps
T1034 /workspace/coverage/default/32.keymgr_sideload_kmac.1498981035 Jan 22 05:42:22 PM PST 24 Jan 22 05:42:27 PM PST 24 187020414 ps
T1035 /workspace/coverage/default/4.keymgr_smoke.1065485357 Jan 22 04:59:29 PM PST 24 Jan 22 04:59:48 PM PST 24 763692245 ps
T1036 /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1436321997 Jan 22 04:59:43 PM PST 24 Jan 22 04:59:52 PM PST 24 317167461 ps
T1037 /workspace/coverage/default/41.keymgr_lc_disable.2216323672 Jan 22 05:05:05 PM PST 24 Jan 22 05:05:11 PM PST 24 345416337 ps
T279 /workspace/coverage/default/37.keymgr_kmac_rsp_err.4208169142 Jan 22 05:04:11 PM PST 24 Jan 22 05:04:16 PM PST 24 63207750 ps
T1038 /workspace/coverage/default/27.keymgr_sideload_protect.3571680534 Jan 22 05:02:59 PM PST 24 Jan 22 05:03:04 PM PST 24 83811322 ps
T1039 /workspace/coverage/default/48.keymgr_sideload_protect.50819376 Jan 22 05:06:07 PM PST 24 Jan 22 05:06:16 PM PST 24 120906033 ps
T1040 /workspace/coverage/default/0.keymgr_lc_disable.3402274907 Jan 22 04:58:19 PM PST 24 Jan 22 04:58:29 PM PST 24 171935094 ps
T1041 /workspace/coverage/default/41.keymgr_sync_async_fault_cross.402249301 Jan 22 05:05:01 PM PST 24 Jan 22 05:05:09 PM PST 24 1395314953 ps
T330 /workspace/coverage/default/47.keymgr_direct_to_disabled.820572152 Jan 22 05:05:49 PM PST 24 Jan 22 05:05:54 PM PST 24 151061965 ps
T368 /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1650517613 Jan 22 05:04:00 PM PST 24 Jan 22 05:04:07 PM PST 24 377122351 ps
T280 /workspace/coverage/default/25.keymgr_kmac_rsp_err.426224512 Jan 22 05:02:14 PM PST 24 Jan 22 05:02:52 PM PST 24 4805953206 ps
T1042 /workspace/coverage/default/43.keymgr_lc_disable.3233927090 Jan 22 05:05:23 PM PST 24 Jan 22 05:05:32 PM PST 24 145327457 ps
T1043 /workspace/coverage/default/30.keymgr_sideload.2518395418 Jan 22 05:02:59 PM PST 24 Jan 22 05:03:07 PM PST 24 1170292992 ps
T1044 /workspace/coverage/default/35.keymgr_sideload_protect.1312345923 Jan 22 05:04:07 PM PST 24 Jan 22 05:04:25 PM PST 24 686995549 ps
T1045 /workspace/coverage/default/15.keymgr_smoke.2188453173 Jan 22 05:15:22 PM PST 24 Jan 22 05:15:25 PM PST 24 70676187 ps
T1046 /workspace/coverage/default/13.keymgr_sideload.576082263 Jan 22 05:00:41 PM PST 24 Jan 22 05:00:45 PM PST 24 137045989 ps
T1047 /workspace/coverage/default/24.keymgr_sideload.3222838026 Jan 22 05:02:01 PM PST 24 Jan 22 05:02:30 PM PST 24 4174997712 ps
T1048 /workspace/coverage/default/33.keymgr_sw_invalid_input.1760001560 Jan 22 05:03:44 PM PST 24 Jan 22 05:03:48 PM PST 24 153927610 ps
T1049 /workspace/coverage/default/36.keymgr_sideload_aes.4262572178 Jan 22 05:03:53 PM PST 24 Jan 22 05:03:57 PM PST 24 60447831 ps
T1050 /workspace/coverage/default/29.keymgr_kmac_rsp_err.2129595655 Jan 22 05:02:53 PM PST 24 Jan 22 05:03:00 PM PST 24 515588820 ps
T1051 /workspace/coverage/default/28.keymgr_sw_invalid_input.3376674377 Jan 22 05:02:54 PM PST 24 Jan 22 05:03:00 PM PST 24 58171244 ps
T1052 /workspace/coverage/default/9.keymgr_random.3945118554 Jan 22 05:00:05 PM PST 24 Jan 22 05:01:15 PM PST 24 3988696807 ps
T1053 /workspace/coverage/default/16.keymgr_lc_disable.1807887906 Jan 22 05:11:23 PM PST 24 Jan 22 05:11:30 PM PST 24 331825201 ps
T1054 /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2208042106 Jan 22 05:47:13 PM PST 24 Jan 22 05:47:37 PM PST 24 5504561959 ps
T1055 /workspace/coverage/default/14.keymgr_alert_test.1656139585 Jan 22 05:00:43 PM PST 24 Jan 22 05:00:49 PM PST 24 42708919 ps
T1056 /workspace/coverage/default/24.keymgr_sw_invalid_input.3350301904 Jan 22 05:02:01 PM PST 24 Jan 22 05:02:04 PM PST 24 155748655 ps
T94 /workspace/coverage/default/3.keymgr_sec_cm.612546637 Jan 22 04:59:36 PM PST 24 Jan 22 05:00:04 PM PST 24 3445409738 ps

Test location /workspace/coverage/default/4.keymgr_random.2409113655
Short name T4
Test name
Test status
Simulation time 1213745055 ps
CPU time 9.7 seconds
Started Jan 22 04:59:33 PM PST 24
Finished Jan 22 04:59:44 PM PST 24
Peak memory 207952 kb
Host smart-25e5d481-42de-490b-9644-8ba8d4ca6d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409113655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2409113655
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.566282896
Short name T44
Test name
Test status
Simulation time 5353195474 ps
CPU time 120.16 seconds
Started Jan 22 05:03:48 PM PST 24
Finished Jan 22 05:05:54 PM PST 24
Peak memory 216176 kb
Host smart-6494b821-1484-48fd-99ad-7a6a74453798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566282896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.566282896
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2814901655
Short name T42
Test name
Test status
Simulation time 33899212772 ps
CPU time 53.61 seconds
Started Jan 22 05:04:01 PM PST 24
Finished Jan 22 05:04:55 PM PST 24
Peak memory 220608 kb
Host smart-7f449242-59c2-413e-9fab-7a577c9a9cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814901655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2814901655
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2963543934
Short name T6
Test name
Test status
Simulation time 1946163808 ps
CPU time 56.58 seconds
Started Jan 22 04:58:35 PM PST 24
Finished Jan 22 04:59:33 PM PST 24
Peak memory 237192 kb
Host smart-ba843c09-66e5-45d5-8a1b-3ee62f57a076
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963543934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2963543934
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.274852279
Short name T114
Test name
Test status
Simulation time 205900060 ps
CPU time 9.18 seconds
Started Jan 22 05:05:04 PM PST 24
Finished Jan 22 05:05:15 PM PST 24
Peak memory 222540 kb
Host smart-64a7fc07-f4f2-4705-9011-e77f3b260135
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274852279 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.274852279
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2926041585
Short name T108
Test name
Test status
Simulation time 116938499 ps
CPU time 4.1 seconds
Started Jan 22 05:02:52 PM PST 24
Finished Jan 22 05:03:00 PM PST 24
Peak memory 215144 kb
Host smart-415b86b5-faea-4f37-8258-ce9534764b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926041585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2926041585
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2936030172
Short name T13
Test name
Test status
Simulation time 305109161 ps
CPU time 4.27 seconds
Started Jan 22 04:58:53 PM PST 24
Finished Jan 22 04:58:58 PM PST 24
Peak memory 209720 kb
Host smart-b7e4cd49-96d2-4b8a-8950-0bae98a13fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936030172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2936030172
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3623559008
Short name T104
Test name
Test status
Simulation time 747691393 ps
CPU time 8.97 seconds
Started Jan 22 04:39:48 PM PST 24
Finished Jan 22 04:39:58 PM PST 24
Peak memory 213820 kb
Host smart-f1c57745-8e88-48af-8055-0113b12ed0cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623559008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3623559008
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3177681708
Short name T35
Test name
Test status
Simulation time 539359483 ps
CPU time 5.69 seconds
Started Jan 22 05:02:58 PM PST 24
Finished Jan 22 05:03:07 PM PST 24
Peak memory 210412 kb
Host smart-ff13ea8f-4885-41e6-b14b-a68efb95fb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177681708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3177681708
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.299966794
Short name T10
Test name
Test status
Simulation time 50570621 ps
CPU time 3.75 seconds
Started Jan 22 05:00:43 PM PST 24
Finished Jan 22 05:00:52 PM PST 24
Peak memory 222488 kb
Host smart-a774e798-a865-4eca-9d8c-a1f2f2de0be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299966794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.299966794
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3925911232
Short name T297
Test name
Test status
Simulation time 327153988 ps
CPU time 17.11 seconds
Started Jan 22 05:01:42 PM PST 24
Finished Jan 22 05:01:59 PM PST 24
Peak memory 215320 kb
Host smart-b20ebc92-5dd4-4568-9df3-360089342240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925911232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3925911232
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.922628968
Short name T26
Test name
Test status
Simulation time 1665906063 ps
CPU time 57.45 seconds
Started Jan 22 04:59:32 PM PST 24
Finished Jan 22 05:00:30 PM PST 24
Peak memory 215444 kb
Host smart-0a9ab685-de1a-4964-a020-482cca74d82d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922628968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.922628968
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.751455631
Short name T24
Test name
Test status
Simulation time 52095075 ps
CPU time 2.59 seconds
Started Jan 22 05:03:04 PM PST 24
Finished Jan 22 05:03:15 PM PST 24
Peak memory 209560 kb
Host smart-66084fc3-9287-4a23-9e6b-05adc2ad8159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751455631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.751455631
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3896731573
Short name T73
Test name
Test status
Simulation time 1130973480 ps
CPU time 63.68 seconds
Started Jan 22 04:59:31 PM PST 24
Finished Jan 22 05:00:35 PM PST 24
Peak memory 215644 kb
Host smart-d04cc577-1702-48f2-b599-04d3ca4273f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896731573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3896731573
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2462524954
Short name T224
Test name
Test status
Simulation time 1039075444 ps
CPU time 44.31 seconds
Started Jan 22 05:03:58 PM PST 24
Finished Jan 22 05:04:43 PM PST 24
Peak memory 214940 kb
Host smart-c474c682-12ee-43f5-a08d-ceafd9bcfae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462524954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2462524954
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3918855531
Short name T220
Test name
Test status
Simulation time 574765432 ps
CPU time 31.91 seconds
Started Jan 22 04:59:26 PM PST 24
Finished Jan 22 04:59:58 PM PST 24
Peak memory 214352 kb
Host smart-bd1c48dc-1b8e-4d1c-8757-69ba5c70c98f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918855531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3918855531
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3713154431
Short name T41
Test name
Test status
Simulation time 549833000 ps
CPU time 6.24 seconds
Started Jan 22 05:05:15 PM PST 24
Finished Jan 22 05:05:23 PM PST 24
Peak memory 222416 kb
Host smart-d396933a-5957-45de-9853-1b4abdd890d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713154431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3713154431
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.542299258
Short name T101
Test name
Test status
Simulation time 153938547 ps
CPU time 9.62 seconds
Started Jan 22 05:02:31 PM PST 24
Finished Jan 22 05:02:55 PM PST 24
Peak memory 220792 kb
Host smart-9e1a3681-380d-4a70-8c16-96007c2f463c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542299258 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.542299258
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.480194228
Short name T270
Test name
Test status
Simulation time 277072347 ps
CPU time 15.25 seconds
Started Jan 22 05:03:42 PM PST 24
Finished Jan 22 05:03:58 PM PST 24
Peak memory 222416 kb
Host smart-4653d0c8-b6bb-41f3-898e-f9dc4447f2fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480194228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.480194228
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3881030783
Short name T46
Test name
Test status
Simulation time 4033859945 ps
CPU time 42.69 seconds
Started Jan 22 05:02:01 PM PST 24
Finished Jan 22 05:02:44 PM PST 24
Peak memory 215232 kb
Host smart-3146ba61-ec1c-4153-bf58-0a447686963d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881030783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3881030783
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.507367752
Short name T38
Test name
Test status
Simulation time 709855590 ps
CPU time 13.75 seconds
Started Jan 22 05:26:09 PM PST 24
Finished Jan 22 05:26:31 PM PST 24
Peak memory 219884 kb
Host smart-4efae3e8-8376-4898-90e7-6ad275c0de52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507367752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.507367752
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.549383724
Short name T383
Test name
Test status
Simulation time 70838680 ps
CPU time 4.6 seconds
Started Jan 22 05:01:45 PM PST 24
Finished Jan 22 05:01:50 PM PST 24
Peak memory 214276 kb
Host smart-09951326-2493-472b-93f8-60e70eac5e9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549383724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.549383724
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2511644003
Short name T137
Test name
Test status
Simulation time 1306439548 ps
CPU time 18.75 seconds
Started Jan 22 05:02:52 PM PST 24
Finished Jan 22 05:03:15 PM PST 24
Peak memory 214312 kb
Host smart-18ff7cea-8e94-49c8-8161-3b1cdb246f29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511644003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2511644003
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.4098363773
Short name T81
Test name
Test status
Simulation time 96047755 ps
CPU time 4.3 seconds
Started Jan 22 05:00:36 PM PST 24
Finished Jan 22 05:00:42 PM PST 24
Peak memory 209532 kb
Host smart-5de75fbd-8570-4182-a6c9-8d9b9ad1582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098363773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4098363773
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3570266655
Short name T386
Test name
Test status
Simulation time 31234215791 ps
CPU time 105.44 seconds
Started Jan 22 05:00:26 PM PST 24
Finished Jan 22 05:02:13 PM PST 24
Peak memory 215476 kb
Host smart-589ac3a0-a3f9-4073-ad9d-57d5083aba1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570266655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3570266655
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.301599156
Short name T118
Test name
Test status
Simulation time 1234778317 ps
CPU time 6.46 seconds
Started Jan 22 04:39:44 PM PST 24
Finished Jan 22 04:39:51 PM PST 24
Peak memory 209044 kb
Host smart-adbf6a44-1382-42a1-bb48-3c8ebaee41ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301599156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.301599156
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.399725927
Short name T414
Test name
Test status
Simulation time 379483321 ps
CPU time 10.07 seconds
Started Jan 22 04:38:43 PM PST 24
Finished Jan 22 04:38:54 PM PST 24
Peak memory 213744 kb
Host smart-64d725af-dbd3-4ff8-ae67-19ccae5c4dc0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399725927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.399725927
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.916664759
Short name T31
Test name
Test status
Simulation time 158576144 ps
CPU time 1.7 seconds
Started Jan 22 05:02:48 PM PST 24
Finished Jan 22 05:02:56 PM PST 24
Peak memory 209808 kb
Host smart-3986035c-0f5c-4c77-970b-b021f8f6e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916664759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.916664759
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.651069013
Short name T204
Test name
Test status
Simulation time 1853533563 ps
CPU time 26.79 seconds
Started Jan 22 05:00:27 PM PST 24
Finished Jan 22 05:00:58 PM PST 24
Peak memory 215136 kb
Host smart-0afaf03a-1c69-4c7a-96a7-3141c054c670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651069013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.651069013
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2741874229
Short name T138
Test name
Test status
Simulation time 183425725 ps
CPU time 2.89 seconds
Started Jan 22 04:58:32 PM PST 24
Finished Jan 22 04:58:35 PM PST 24
Peak memory 222644 kb
Host smart-a514ff99-a5d1-41c9-8141-d12258518390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741874229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2741874229
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3380736804
Short name T64
Test name
Test status
Simulation time 10874182182 ps
CPU time 38.6 seconds
Started Jan 22 04:58:26 PM PST 24
Finished Jan 22 04:59:07 PM PST 24
Peak memory 222544 kb
Host smart-ec3ffc0e-5fc1-4a11-ac3a-07a4a63d1448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380736804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3380736804
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2586244072
Short name T85
Test name
Test status
Simulation time 258125713 ps
CPU time 7.4 seconds
Started Jan 22 05:04:39 PM PST 24
Finished Jan 22 05:04:47 PM PST 24
Peak memory 214168 kb
Host smart-166cc3fc-3afe-43fc-a058-0bdab5cf459f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586244072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2586244072
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1443862726
Short name T34
Test name
Test status
Simulation time 43626799 ps
CPU time 2.67 seconds
Started Jan 22 05:04:38 PM PST 24
Finished Jan 22 05:04:41 PM PST 24
Peak memory 214564 kb
Host smart-17f71b6b-c607-45ce-8db4-d3ac520eb069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443862726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1443862726
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.362471849
Short name T65
Test name
Test status
Simulation time 23124161193 ps
CPU time 244.55 seconds
Started Jan 22 04:59:30 PM PST 24
Finished Jan 22 05:03:35 PM PST 24
Peak memory 216484 kb
Host smart-42234d06-6c35-4005-8600-c96557e8b0e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362471849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.362471849
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3742954055
Short name T356
Test name
Test status
Simulation time 98269600 ps
CPU time 4.87 seconds
Started Jan 22 05:05:56 PM PST 24
Finished Jan 22 05:06:01 PM PST 24
Peak memory 214652 kb
Host smart-5ef2a9b5-1c38-402b-938a-06f9019b0584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742954055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3742954055
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2367092785
Short name T155
Test name
Test status
Simulation time 599794452 ps
CPU time 5.48 seconds
Started Jan 22 04:39:58 PM PST 24
Finished Jan 22 04:40:04 PM PST 24
Peak memory 217568 kb
Host smart-7b0ac251-6d81-425e-a86f-0332adb31745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367092785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2367092785
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3817968028
Short name T345
Test name
Test status
Simulation time 2025835008 ps
CPU time 61.2 seconds
Started Jan 22 05:05:44 PM PST 24
Finished Jan 22 05:06:46 PM PST 24
Peak memory 215832 kb
Host smart-af474dc1-1244-4074-954d-d17a0c828162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817968028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3817968028
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.148015189
Short name T90
Test name
Test status
Simulation time 68117335 ps
CPU time 0.75 seconds
Started Jan 22 05:00:32 PM PST 24
Finished Jan 22 05:00:34 PM PST 24
Peak memory 205944 kb
Host smart-0fb95e5d-5b73-4eea-8723-5c02687afd08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148015189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.148015189
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.178126491
Short name T53
Test name
Test status
Simulation time 9405059750 ps
CPU time 52.77 seconds
Started Jan 22 05:00:43 PM PST 24
Finished Jan 22 05:01:41 PM PST 24
Peak memory 222552 kb
Host smart-38b2eca3-a07e-4d66-a1c1-6ccb5a9fda07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178126491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.178126491
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2004708057
Short name T54
Test name
Test status
Simulation time 574830679 ps
CPU time 8.16 seconds
Started Jan 22 05:11:27 PM PST 24
Finished Jan 22 05:11:38 PM PST 24
Peak memory 214284 kb
Host smart-3bcbd685-451d-4742-92ed-9112cb830b0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004708057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2004708057
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2394062907
Short name T193
Test name
Test status
Simulation time 300367314 ps
CPU time 4.14 seconds
Started Jan 22 05:02:07 PM PST 24
Finished Jan 22 05:02:11 PM PST 24
Peak memory 211180 kb
Host smart-ee254fd1-9aa5-456c-92f0-c0fec45174b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394062907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2394062907
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2655426626
Short name T139
Test name
Test status
Simulation time 2409476345 ps
CPU time 37.83 seconds
Started Jan 22 05:03:06 PM PST 24
Finished Jan 22 05:03:52 PM PST 24
Peak memory 222728 kb
Host smart-b3fa7e25-0897-493a-88d3-387416537c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655426626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2655426626
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2706491298
Short name T380
Test name
Test status
Simulation time 78718868 ps
CPU time 4.34 seconds
Started Jan 22 04:59:36 PM PST 24
Finished Jan 22 04:59:41 PM PST 24
Peak memory 214136 kb
Host smart-ea558d65-1c5d-409f-8be4-2c9d1672f116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706491298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2706491298
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.611673843
Short name T150
Test name
Test status
Simulation time 211581079 ps
CPU time 3.25 seconds
Started Jan 22 04:39:43 PM PST 24
Finished Jan 22 04:39:46 PM PST 24
Peak memory 213532 kb
Host smart-c0f518c3-2c54-49d8-8ae3-e0fdea4481a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611673843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.611673843
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3937767394
Short name T315
Test name
Test status
Simulation time 341338189 ps
CPU time 7.23 seconds
Started Jan 22 04:59:52 PM PST 24
Finished Jan 22 04:59:59 PM PST 24
Peak memory 214224 kb
Host smart-1482fad8-4874-4c7b-a401-64f293cdafae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937767394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3937767394
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3937777006
Short name T142
Test name
Test status
Simulation time 91176749 ps
CPU time 5.43 seconds
Started Jan 22 04:58:56 PM PST 24
Finished Jan 22 04:59:02 PM PST 24
Peak memory 222556 kb
Host smart-03362c45-5218-4bcd-b091-3c970c06c110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937777006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3937777006
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3587368662
Short name T140
Test name
Test status
Simulation time 85590779 ps
CPU time 2.62 seconds
Started Jan 22 05:02:54 PM PST 24
Finished Jan 22 05:02:59 PM PST 24
Peak memory 217304 kb
Host smart-fa12bbee-0e32-4170-a1b6-cb7674053e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587368662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3587368662
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3861013785
Short name T141
Test name
Test status
Simulation time 211979070 ps
CPU time 4.24 seconds
Started Jan 22 05:05:16 PM PST 24
Finished Jan 22 05:05:22 PM PST 24
Peak memory 215536 kb
Host smart-24122751-c78a-4134-b396-8eafb7991d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861013785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3861013785
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2664470479
Short name T143
Test name
Test status
Simulation time 135032184 ps
CPU time 5.73 seconds
Started Jan 22 05:02:01 PM PST 24
Finished Jan 22 05:02:07 PM PST 24
Peak memory 218080 kb
Host smart-e9d3cc3a-a362-4820-9e03-ab6b5e2aee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664470479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2664470479
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.194501257
Short name T282
Test name
Test status
Simulation time 1110876924 ps
CPU time 9.26 seconds
Started Jan 22 05:52:45 PM PST 24
Finished Jan 22 05:52:56 PM PST 24
Peak memory 222344 kb
Host smart-90f1e14f-c04c-4eb7-a199-8a56cf8b3ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194501257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.194501257
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3272000671
Short name T7
Test name
Test status
Simulation time 13040963914 ps
CPU time 154.63 seconds
Started Jan 22 05:01:06 PM PST 24
Finished Jan 22 05:03:41 PM PST 24
Peak memory 222696 kb
Host smart-6ea05238-5bf1-478d-8c30-95bea0cf3be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272000671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3272000671
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.145262793
Short name T295
Test name
Test status
Simulation time 43833137 ps
CPU time 2.89 seconds
Started Jan 22 04:58:23 PM PST 24
Finished Jan 22 04:58:28 PM PST 24
Peak memory 208892 kb
Host smart-c7998fbd-18f3-4164-a625-3aa320d8b084
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145262793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.145262793
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.344557799
Short name T298
Test name
Test status
Simulation time 15219326960 ps
CPU time 85.02 seconds
Started Jan 22 05:00:41 PM PST 24
Finished Jan 22 05:02:07 PM PST 24
Peak memory 216736 kb
Host smart-69049bd4-548b-41cb-9b51-83958ac4402f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344557799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.344557799
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.909628863
Short name T573
Test name
Test status
Simulation time 4010641250 ps
CPU time 54.57 seconds
Started Jan 22 05:01:42 PM PST 24
Finished Jan 22 05:02:37 PM PST 24
Peak memory 209140 kb
Host smart-264ee400-d8fb-44eb-8eda-3bb70d0b5ee5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909628863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.909628863
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3670043970
Short name T196
Test name
Test status
Simulation time 413420870 ps
CPU time 6.9 seconds
Started Jan 22 05:02:53 PM PST 24
Finished Jan 22 05:03:03 PM PST 24
Peak memory 214168 kb
Host smart-0ba61562-8ab7-45f9-a3f8-8baf4b370f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670043970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3670043970
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1681646680
Short name T29
Test name
Test status
Simulation time 384130942 ps
CPU time 4.7 seconds
Started Jan 22 05:00:57 PM PST 24
Finished Jan 22 05:01:02 PM PST 24
Peak memory 210752 kb
Host smart-aeb205ac-5097-4952-b152-27405b85537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681646680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1681646680
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1198537542
Short name T22
Test name
Test status
Simulation time 70706216 ps
CPU time 2.76 seconds
Started Jan 22 05:05:15 PM PST 24
Finished Jan 22 05:05:20 PM PST 24
Peak memory 222732 kb
Host smart-c0da9562-e456-4d6e-a33e-1345a72542f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198537542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1198537542
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.222194060
Short name T37
Test name
Test status
Simulation time 164684319 ps
CPU time 3.41 seconds
Started Jan 22 04:59:50 PM PST 24
Finished Jan 22 04:59:54 PM PST 24
Peak memory 209948 kb
Host smart-b3922ff2-ae38-4f19-b203-4840aa01d217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222194060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.222194060
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.948224311
Short name T285
Test name
Test status
Simulation time 1082223432 ps
CPU time 25.03 seconds
Started Jan 22 04:58:19 PM PST 24
Finished Jan 22 04:58:44 PM PST 24
Peak memory 217132 kb
Host smart-b926abd1-6d68-40f4-b39f-57955cacf3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948224311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.948224311
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1309991729
Short name T255
Test name
Test status
Simulation time 1515724736 ps
CPU time 17.3 seconds
Started Jan 22 04:58:31 PM PST 24
Finished Jan 22 04:58:49 PM PST 24
Peak memory 222696 kb
Host smart-5b9037c8-8f99-4060-9a82-42cd480c577b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309991729 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1309991729
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1321182692
Short name T121
Test name
Test status
Simulation time 924171219 ps
CPU time 23.28 seconds
Started Jan 22 05:00:34 PM PST 24
Finished Jan 22 05:01:00 PM PST 24
Peak memory 208128 kb
Host smart-5259206e-1d4a-482b-a684-f868b5b4a02f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321182692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1321182692
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3344012469
Short name T331
Test name
Test status
Simulation time 1101519503 ps
CPU time 7.43 seconds
Started Jan 22 05:01:44 PM PST 24
Finished Jan 22 05:01:52 PM PST 24
Peak memory 211148 kb
Host smart-643ac13a-b2b8-4001-bf89-deab8d811e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344012469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3344012469
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1299172806
Short name T88
Test name
Test status
Simulation time 10895403933 ps
CPU time 51.24 seconds
Started Jan 22 05:02:06 PM PST 24
Finished Jan 22 05:02:57 PM PST 24
Peak memory 220380 kb
Host smart-5fe2cd1c-3c95-4e39-a0be-6421d1b5f2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299172806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1299172806
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.426224512
Short name T280
Test name
Test status
Simulation time 4805953206 ps
CPU time 36.86 seconds
Started Jan 22 05:02:14 PM PST 24
Finished Jan 22 05:02:52 PM PST 24
Peak memory 222448 kb
Host smart-c12dbf0f-02ce-4b4c-b230-30ad78d7bc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426224512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.426224512
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.289427075
Short name T311
Test name
Test status
Simulation time 568180563 ps
CPU time 12.57 seconds
Started Jan 22 05:03:46 PM PST 24
Finished Jan 22 05:04:00 PM PST 24
Peak memory 220328 kb
Host smart-752792a4-8070-4e66-8f25-49f58bde1862
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289427075 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.289427075
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1486599994
Short name T388
Test name
Test status
Simulation time 630695083 ps
CPU time 18.41 seconds
Started Jan 22 05:04:11 PM PST 24
Finished Jan 22 05:04:30 PM PST 24
Peak memory 214328 kb
Host smart-ee4d0587-c180-4cac-be52-0d5b59321970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486599994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1486599994
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2056057202
Short name T23
Test name
Test status
Simulation time 2431524027 ps
CPU time 22.39 seconds
Started Jan 22 05:04:10 PM PST 24
Finished Jan 22 05:04:33 PM PST 24
Peak memory 209624 kb
Host smart-e01e7696-75e3-44d3-bfe1-ec2970af64d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056057202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2056057202
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1545143730
Short name T338
Test name
Test status
Simulation time 259523278 ps
CPU time 3.54 seconds
Started Jan 22 05:04:12 PM PST 24
Finished Jan 22 05:04:16 PM PST 24
Peak memory 208476 kb
Host smart-80b0553c-6d3f-47bd-8c2e-effcd48cac84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545143730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1545143730
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.518472146
Short name T303
Test name
Test status
Simulation time 691125024 ps
CPU time 25.8 seconds
Started Jan 22 05:05:50 PM PST 24
Finished Jan 22 05:06:17 PM PST 24
Peak memory 218080 kb
Host smart-96e5cc2d-12ec-4ea0-9cf6-b611427e7e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518472146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.518472146
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3771639827
Short name T158
Test name
Test status
Simulation time 303378530 ps
CPU time 4.45 seconds
Started Jan 22 04:39:53 PM PST 24
Finished Jan 22 04:39:58 PM PST 24
Peak memory 213608 kb
Host smart-7b75cf8b-8e6a-4ec5-bf23-9e518ab79d38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771639827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3771639827
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1436164773
Short name T161
Test name
Test status
Simulation time 234794786 ps
CPU time 6.53 seconds
Started Jan 22 04:40:05 PM PST 24
Finished Jan 22 04:40:14 PM PST 24
Peak memory 209008 kb
Host smart-d221035f-9ce4-4613-a23a-c7f42c07ee37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436164773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1436164773
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1182289924
Short name T153
Test name
Test status
Simulation time 142960736 ps
CPU time 4.7 seconds
Started Jan 22 04:38:53 PM PST 24
Finished Jan 22 04:38:58 PM PST 24
Peak memory 213536 kb
Host smart-10edf9bb-1644-4a02-bbc5-90ec3b00064c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182289924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1182289924
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2831547038
Short name T152
Test name
Test status
Simulation time 1819881059 ps
CPU time 18 seconds
Started Jan 22 04:38:55 PM PST 24
Finished Jan 22 04:39:13 PM PST 24
Peak memory 208928 kb
Host smart-0368f38c-3251-4769-b810-b2a07a9d721e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831547038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2831547038
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.208125839
Short name T157
Test name
Test status
Simulation time 101208005 ps
CPU time 3.15 seconds
Started Jan 22 05:06:03 PM PST 24
Finished Jan 22 05:06:07 PM PST 24
Peak memory 209028 kb
Host smart-52ced0f9-6a61-4150-a203-86c047c8d2a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208125839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
208125839
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3769560677
Short name T146
Test name
Test status
Simulation time 341237688 ps
CPU time 2.54 seconds
Started Jan 22 05:00:32 PM PST 24
Finished Jan 22 05:00:36 PM PST 24
Peak memory 209688 kb
Host smart-d47a20b1-d093-4c3c-8c96-137fc2a74e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769560677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3769560677
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3649978825
Short name T359
Test name
Test status
Simulation time 465319757 ps
CPU time 5.28 seconds
Started Jan 22 04:58:19 PM PST 24
Finished Jan 22 04:58:29 PM PST 24
Peak memory 214372 kb
Host smart-7ffeb2b0-b574-47d0-8ca4-60b777e711c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649978825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3649978825
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2052572326
Short name T219
Test name
Test status
Simulation time 21326739737 ps
CPU time 135.11 seconds
Started Jan 22 04:58:57 PM PST 24
Finished Jan 22 05:01:13 PM PST 24
Peak memory 216956 kb
Host smart-7bb6d533-4d6f-4056-94c0-8e3f7ff4d6a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052572326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2052572326
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.970489072
Short name T112
Test name
Test status
Simulation time 893923755 ps
CPU time 11.1 seconds
Started Jan 22 04:58:54 PM PST 24
Finished Jan 22 04:59:06 PM PST 24
Peak memory 220012 kb
Host smart-5c971b34-7548-4114-8134-058cb398992e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970489072 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.970489072
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3119870563
Short name T245
Test name
Test status
Simulation time 2939744376 ps
CPU time 43.08 seconds
Started Jan 22 05:00:19 PM PST 24
Finished Jan 22 05:01:05 PM PST 24
Peak memory 215640 kb
Host smart-c46b5f77-badc-438f-8ef3-690151864f65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119870563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3119870563
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2141685099
Short name T233
Test name
Test status
Simulation time 3142710786 ps
CPU time 69.09 seconds
Started Jan 22 05:00:19 PM PST 24
Finished Jan 22 05:01:29 PM PST 24
Peak memory 230608 kb
Host smart-18db2000-ddbd-4424-bf33-b3eeb71bddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141685099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2141685099
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2502465852
Short name T67
Test name
Test status
Simulation time 724631603 ps
CPU time 4.11 seconds
Started Jan 22 05:00:23 PM PST 24
Finished Jan 22 05:00:28 PM PST 24
Peak memory 218468 kb
Host smart-884de742-8dd4-43ea-a981-3112039f9a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502465852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2502465852
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3637069147
Short name T344
Test name
Test status
Simulation time 201023847 ps
CPU time 3.64 seconds
Started Jan 22 05:00:22 PM PST 24
Finished Jan 22 05:00:27 PM PST 24
Peak memory 206840 kb
Host smart-e89f58e3-2141-40e1-b60a-c8e05460afd6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637069147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3637069147
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3570113477
Short name T318
Test name
Test status
Simulation time 110789107 ps
CPU time 4.76 seconds
Started Jan 22 05:00:44 PM PST 24
Finished Jan 22 05:00:53 PM PST 24
Peak memory 219064 kb
Host smart-8466ba24-9589-49c5-8843-a1c29cfeb3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570113477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3570113477
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1638030072
Short name T291
Test name
Test status
Simulation time 49685021 ps
CPU time 3.16 seconds
Started Jan 22 05:00:37 PM PST 24
Finished Jan 22 05:00:41 PM PST 24
Peak memory 211572 kb
Host smart-d1a37cfe-e536-4698-9d7a-79949e453dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638030072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1638030072
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3843140824
Short name T206
Test name
Test status
Simulation time 82783411 ps
CPU time 1.79 seconds
Started Jan 22 05:00:39 PM PST 24
Finished Jan 22 05:00:42 PM PST 24
Peak memory 208708 kb
Host smart-cddc794f-f232-4d2b-a738-f7b2ff877d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843140824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3843140824
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1128835231
Short name T229
Test name
Test status
Simulation time 4219813090 ps
CPU time 52.47 seconds
Started Jan 22 06:26:21 PM PST 24
Finished Jan 22 06:27:15 PM PST 24
Peak memory 215064 kb
Host smart-b13260a5-1f0c-463e-9bde-52b5821a6303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1128835231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1128835231
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.123805783
Short name T299
Test name
Test status
Simulation time 223049722 ps
CPU time 3.06 seconds
Started Jan 22 05:19:10 PM PST 24
Finished Jan 22 05:19:15 PM PST 24
Peak memory 209300 kb
Host smart-dc5d9da4-3838-43d1-ab4d-f6aab60e52f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123805783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.123805783
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3143014921
Short name T217
Test name
Test status
Simulation time 2747748901 ps
CPU time 28.52 seconds
Started Jan 22 05:01:16 PM PST 24
Finished Jan 22 05:01:45 PM PST 24
Peak memory 215928 kb
Host smart-41ec546c-3d85-4def-ab12-cc40c2acb7fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143014921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3143014921
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1784961782
Short name T364
Test name
Test status
Simulation time 168115260 ps
CPU time 3.98 seconds
Started Jan 22 05:01:57 PM PST 24
Finished Jan 22 05:02:02 PM PST 24
Peak memory 208936 kb
Host smart-1490200c-8896-438d-944f-d4448b0608c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784961782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1784961782
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1851548062
Short name T644
Test name
Test status
Simulation time 37628316 ps
CPU time 2.5 seconds
Started Jan 22 05:02:31 PM PST 24
Finished Jan 22 05:02:48 PM PST 24
Peak memory 208476 kb
Host smart-68901f42-87d4-45f7-8b31-1784d2aa9b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851548062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1851548062
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1280298044
Short name T49
Test name
Test status
Simulation time 254199196 ps
CPU time 7.48 seconds
Started Jan 22 05:03:03 PM PST 24
Finished Jan 22 05:03:12 PM PST 24
Peak memory 222572 kb
Host smart-11903295-7ea9-4f3c-b794-3c98284f27f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280298044 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1280298044
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.4238174721
Short name T243
Test name
Test status
Simulation time 1853225295 ps
CPU time 22.16 seconds
Started Jan 22 05:03:07 PM PST 24
Finished Jan 22 05:03:37 PM PST 24
Peak memory 215784 kb
Host smart-d433460e-8bd3-4921-94b6-64e8ed39308b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238174721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4238174721
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2567792444
Short name T247
Test name
Test status
Simulation time 770764397 ps
CPU time 10.31 seconds
Started Jan 22 05:04:08 PM PST 24
Finished Jan 22 05:04:19 PM PST 24
Peak memory 215876 kb
Host smart-f8b824ce-fb00-455a-acba-dc6615e21c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567792444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2567792444
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1650990267
Short name T215
Test name
Test status
Simulation time 1092571203 ps
CPU time 15.93 seconds
Started Jan 22 04:59:27 PM PST 24
Finished Jan 22 04:59:44 PM PST 24
Peak memory 222464 kb
Host smart-847ea522-1144-4408-9d53-3badea59a3b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650990267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1650990267
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.744570682
Short name T207
Test name
Test status
Simulation time 114240427 ps
CPU time 3.48 seconds
Started Jan 22 05:05:06 PM PST 24
Finished Jan 22 05:05:15 PM PST 24
Peak memory 208776 kb
Host smart-bfe2fbcc-b0e4-489f-9d89-4494299139d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744570682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.744570682
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1659524737
Short name T76
Test name
Test status
Simulation time 137496742 ps
CPU time 2.29 seconds
Started Jan 22 05:05:16 PM PST 24
Finished Jan 22 05:05:20 PM PST 24
Peak memory 208200 kb
Host smart-947ed3d0-3e10-490e-bb96-4f1835eac3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659524737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1659524737
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.676387936
Short name T253
Test name
Test status
Simulation time 93914264 ps
CPU time 4.59 seconds
Started Jan 22 05:05:49 PM PST 24
Finished Jan 22 05:05:54 PM PST 24
Peak memory 209568 kb
Host smart-990ca239-5d7c-432a-af4d-f730fdd2a5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676387936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.676387936
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2714442139
Short name T145
Test name
Test status
Simulation time 130596557 ps
CPU time 5.28 seconds
Started Jan 22 05:01:28 PM PST 24
Finished Jan 22 05:01:34 PM PST 24
Peak memory 217224 kb
Host smart-5d192331-c00d-44ff-b19a-25d66b00f2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714442139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2714442139
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2068004756
Short name T485
Test name
Test status
Simulation time 72667746 ps
CPU time 4.06 seconds
Started Jan 22 04:38:24 PM PST 24
Finished Jan 22 04:38:29 PM PST 24
Peak memory 205172 kb
Host smart-e469f734-2663-4cc0-ab7a-7eeab25cc5ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068004756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
068004756
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.110237192
Short name T442
Test name
Test status
Simulation time 130011132 ps
CPU time 7.83 seconds
Started Jan 22 04:38:28 PM PST 24
Finished Jan 22 04:38:36 PM PST 24
Peak memory 205100 kb
Host smart-2b1f7e49-f523-4233-a0d2-98b52ff03e16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110237192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.110237192
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1205585597
Short name T404
Test name
Test status
Simulation time 45334068 ps
CPU time 1.01 seconds
Started Jan 22 04:47:07 PM PST 24
Finished Jan 22 04:47:08 PM PST 24
Peak memory 205048 kb
Host smart-d66e5624-62c5-4049-9e43-6c38e346a26a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205585597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
205585597
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1095952381
Short name T420
Test name
Test status
Simulation time 100073722 ps
CPU time 1.12 seconds
Started Jan 22 04:38:42 PM PST 24
Finished Jan 22 04:38:44 PM PST 24
Peak memory 205312 kb
Host smart-22521f89-938a-4fa9-bbb6-b3e8ecbe336a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095952381 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1095952381
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1754067713
Short name T437
Test name
Test status
Simulation time 17129905 ps
CPU time 1.27 seconds
Started Jan 22 04:38:29 PM PST 24
Finished Jan 22 04:38:31 PM PST 24
Peak memory 205280 kb
Host smart-72c4a4da-63a8-4683-9a5e-8264ad456a9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754067713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1754067713
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.335728981
Short name T184
Test name
Test status
Simulation time 24348260 ps
CPU time 0.79 seconds
Started Jan 22 04:38:24 PM PST 24
Finished Jan 22 04:38:26 PM PST 24
Peak memory 205164 kb
Host smart-8c7f3d51-baef-4d5a-ab72-92aa2d8bdb77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335728981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.335728981
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2835110027
Short name T423
Test name
Test status
Simulation time 183426887 ps
CPU time 2.09 seconds
Started Jan 22 04:38:24 PM PST 24
Finished Jan 22 04:38:28 PM PST 24
Peak memory 205184 kb
Host smart-6134c624-6b83-4b0d-9e3c-d918f8210299
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835110027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2835110027
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1742172973
Short name T164
Test name
Test status
Simulation time 95373875 ps
CPU time 3.08 seconds
Started Jan 22 04:38:27 PM PST 24
Finished Jan 22 04:38:31 PM PST 24
Peak memory 213844 kb
Host smart-0caa5730-a879-4aed-b64c-cc5a10d74248
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742172973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1742172973
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.4172049059
Short name T411
Test name
Test status
Simulation time 140884421 ps
CPU time 3.63 seconds
Started Jan 22 04:38:28 PM PST 24
Finished Jan 22 04:38:32 PM PST 24
Peak memory 213632 kb
Host smart-23b2121d-1cfe-4ae5-919a-4e5453bb2f14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172049059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.4172049059
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3035496415
Short name T159
Test name
Test status
Simulation time 502268443 ps
CPU time 14.5 seconds
Started Jan 22 04:38:27 PM PST 24
Finished Jan 22 04:38:42 PM PST 24
Peak memory 213504 kb
Host smart-8efbb455-2253-47dd-8eb9-d958980953cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035496415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3035496415
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2454754842
Short name T434
Test name
Test status
Simulation time 372293521 ps
CPU time 5 seconds
Started Jan 22 04:38:38 PM PST 24
Finished Jan 22 04:38:44 PM PST 24
Peak memory 205292 kb
Host smart-86cccfcf-a1a6-4bee-b13e-8308862a8f24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454754842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
454754842
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.200344146
Short name T181
Test name
Test status
Simulation time 70557333 ps
CPU time 0.92 seconds
Started Jan 22 04:38:42 PM PST 24
Finished Jan 22 04:38:44 PM PST 24
Peak memory 205096 kb
Host smart-8b25dcb7-7d28-4172-b9ea-1684ac18b55f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200344146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.200344146
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.361840226
Short name T512
Test name
Test status
Simulation time 219953487 ps
CPU time 1.51 seconds
Started Jan 22 04:38:38 PM PST 24
Finished Jan 22 04:38:40 PM PST 24
Peak memory 213444 kb
Host smart-6bddffa6-59a6-41a2-924e-5cb7fd227215
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361840226 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.361840226
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1135392234
Short name T501
Test name
Test status
Simulation time 8229681 ps
CPU time 0.79 seconds
Started Jan 22 04:38:43 PM PST 24
Finished Jan 22 04:38:44 PM PST 24
Peak memory 205016 kb
Host smart-2334785d-4a6d-4933-b80b-6707537b1ba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135392234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1135392234
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3609949772
Short name T422
Test name
Test status
Simulation time 116512636 ps
CPU time 3.34 seconds
Started Jan 22 04:38:38 PM PST 24
Finished Jan 22 04:38:42 PM PST 24
Peak memory 213776 kb
Host smart-cb407cc3-171a-43c5-8024-c3a9268e2333
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609949772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3609949772
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.76975284
Short name T115
Test name
Test status
Simulation time 46794646 ps
CPU time 1.71 seconds
Started Jan 22 04:38:38 PM PST 24
Finished Jan 22 04:38:41 PM PST 24
Peak memory 213548 kb
Host smart-4b1ade5e-da20-4ba2-92a0-f30ff8e70a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76975284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.76975284
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1883631099
Short name T415
Test name
Test status
Simulation time 75163856 ps
CPU time 1.3 seconds
Started Jan 22 04:39:31 PM PST 24
Finished Jan 22 04:39:33 PM PST 24
Peak memory 205244 kb
Host smart-22f35ecf-50ed-4033-821c-9f9bf72f6aac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883631099 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1883631099
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1066794953
Short name T468
Test name
Test status
Simulation time 31138358 ps
CPU time 1.05 seconds
Started Jan 22 04:39:34 PM PST 24
Finished Jan 22 04:39:35 PM PST 24
Peak memory 205308 kb
Host smart-7badd3c4-c461-4e51-af58-2909a357c170
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066794953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1066794953
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.325887533
Short name T131
Test name
Test status
Simulation time 17050442 ps
CPU time 0.8 seconds
Started Jan 22 04:39:32 PM PST 24
Finished Jan 22 04:39:33 PM PST 24
Peak memory 205132 kb
Host smart-d515a231-c7a6-498c-b9c6-39d96cd95e7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325887533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.325887533
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3107037548
Short name T490
Test name
Test status
Simulation time 438164458 ps
CPU time 10.95 seconds
Started Jan 22 04:39:35 PM PST 24
Finished Jan 22 04:39:47 PM PST 24
Peak memory 213680 kb
Host smart-f66ba610-eb11-4206-9c79-f114913ea45b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107037548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3107037548
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3323209525
Short name T507
Test name
Test status
Simulation time 285422113 ps
CPU time 11.2 seconds
Started Jan 22 04:39:27 PM PST 24
Finished Jan 22 04:39:39 PM PST 24
Peak memory 219740 kb
Host smart-e16c21d3-bf21-4431-8290-e71b8b125f7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323209525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3323209525
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3333919875
Short name T116
Test name
Test status
Simulation time 48214811 ps
CPU time 2.25 seconds
Started Jan 22 05:52:49 PM PST 24
Finished Jan 22 05:52:52 PM PST 24
Peak memory 213504 kb
Host smart-6a8c8e34-a75d-42c7-8378-113c21291b44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333919875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3333919875
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3016300112
Short name T505
Test name
Test status
Simulation time 74722283 ps
CPU time 1.57 seconds
Started Jan 22 04:39:32 PM PST 24
Finished Jan 22 04:39:34 PM PST 24
Peak memory 205424 kb
Host smart-b4b8e9a0-f555-487a-a939-421e34db9b8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016300112 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3016300112
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4234993112
Short name T457
Test name
Test status
Simulation time 15303783 ps
CPU time 1.04 seconds
Started Jan 22 04:39:35 PM PST 24
Finished Jan 22 04:39:36 PM PST 24
Peak memory 205244 kb
Host smart-373c3ab1-684f-45e0-8621-8d02e4c7b705
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234993112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4234993112
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2112108864
Short name T403
Test name
Test status
Simulation time 8009108 ps
CPU time 0.81 seconds
Started Jan 22 04:39:35 PM PST 24
Finished Jan 22 04:39:36 PM PST 24
Peak memory 205076 kb
Host smart-74ce5cb5-c3aa-4764-a81b-c0f25a40f553
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112108864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2112108864
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1025905095
Short name T170
Test name
Test status
Simulation time 176737210 ps
CPU time 2.73 seconds
Started Jan 22 04:39:34 PM PST 24
Finished Jan 22 04:39:37 PM PST 24
Peak memory 213756 kb
Host smart-99e45557-e635-43bf-931f-967ba1cc64fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025905095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1025905095
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2135005114
Short name T134
Test name
Test status
Simulation time 374041409 ps
CPU time 8.16 seconds
Started Jan 22 04:39:36 PM PST 24
Finished Jan 22 04:39:44 PM PST 24
Peak memory 219768 kb
Host smart-f63410ba-8793-4847-8c46-d47650d85fa3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135005114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2135005114
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2127253789
Short name T475
Test name
Test status
Simulation time 25283607 ps
CPU time 1.59 seconds
Started Jan 22 04:39:34 PM PST 24
Finished Jan 22 04:39:36 PM PST 24
Peak memory 213572 kb
Host smart-d147190b-700e-4fbe-ac80-8998c1b37fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127253789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2127253789
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3956862872
Short name T154
Test name
Test status
Simulation time 2164747085 ps
CPU time 15.14 seconds
Started Jan 22 04:39:32 PM PST 24
Finished Jan 22 04:39:48 PM PST 24
Peak memory 208552 kb
Host smart-677b87c2-576c-4c83-81e0-033da83c8f6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956862872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3956862872
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2205632168
Short name T410
Test name
Test status
Simulation time 60294365 ps
CPU time 1.1 seconds
Started Jan 22 04:48:26 PM PST 24
Finished Jan 22 04:48:27 PM PST 24
Peak memory 205296 kb
Host smart-40eb48a1-0a61-41b2-a3da-46d6cb2e21b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205632168 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2205632168
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1872836879
Short name T456
Test name
Test status
Simulation time 25277297 ps
CPU time 1.55 seconds
Started Jan 22 04:39:42 PM PST 24
Finished Jan 22 04:39:44 PM PST 24
Peak memory 205120 kb
Host smart-787dff82-1ef8-4b80-b03c-d6fc17cbe269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872836879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1872836879
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2851415428
Short name T438
Test name
Test status
Simulation time 40842772 ps
CPU time 0.86 seconds
Started Jan 22 04:39:39 PM PST 24
Finished Jan 22 04:39:41 PM PST 24
Peak memory 205216 kb
Host smart-c64c26a3-fc2a-4011-a74d-db4192f6a2cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851415428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2851415428
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3026890077
Short name T439
Test name
Test status
Simulation time 33775137 ps
CPU time 1.91 seconds
Started Jan 22 04:39:35 PM PST 24
Finished Jan 22 04:39:37 PM PST 24
Peak memory 205328 kb
Host smart-9c4060aa-2227-4050-8221-b6b20bf2fde8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026890077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3026890077
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3510613931
Short name T406
Test name
Test status
Simulation time 89900130 ps
CPU time 2.97 seconds
Started Jan 22 04:55:42 PM PST 24
Finished Jan 22 04:55:45 PM PST 24
Peak memory 213860 kb
Host smart-9987b2ec-1693-42d9-8eb8-c19691570277
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510613931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3510613931
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.700499523
Short name T499
Test name
Test status
Simulation time 193489245 ps
CPU time 8.37 seconds
Started Jan 22 04:39:32 PM PST 24
Finished Jan 22 04:39:40 PM PST 24
Peak memory 213728 kb
Host smart-be038b25-95f3-4553-96cc-402cc9a1ef37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700499523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.700499523
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1312468423
Short name T477
Test name
Test status
Simulation time 1886959053 ps
CPU time 4.33 seconds
Started Jan 22 04:39:42 PM PST 24
Finished Jan 22 04:39:47 PM PST 24
Peak memory 216528 kb
Host smart-3d2f4532-796a-4b33-9d8e-d16a24d47ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312468423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1312468423
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4185885353
Short name T149
Test name
Test status
Simulation time 288325767 ps
CPU time 10.14 seconds
Started Jan 22 04:39:35 PM PST 24
Finished Jan 22 04:39:46 PM PST 24
Peak memory 213520 kb
Host smart-789a322d-c4c4-4b5b-96d7-0da7bbc69761
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185885353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.4185885353
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2344530314
Short name T459
Test name
Test status
Simulation time 40627829 ps
CPU time 1.74 seconds
Started Jan 22 04:39:36 PM PST 24
Finished Jan 22 04:39:38 PM PST 24
Peak memory 218404 kb
Host smart-a13bbf83-4ad8-424c-aa6f-8df821cd9d2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344530314 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2344530314
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1185726956
Short name T452
Test name
Test status
Simulation time 135640761 ps
CPU time 0.9 seconds
Started Jan 22 04:39:39 PM PST 24
Finished Jan 22 04:39:41 PM PST 24
Peak memory 205244 kb
Host smart-2a84ec4c-5988-440a-b6ae-c89d79f68f05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185726956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1185726956
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2417525854
Short name T430
Test name
Test status
Simulation time 8958870 ps
CPU time 0.69 seconds
Started Jan 22 04:39:39 PM PST 24
Finished Jan 22 04:39:40 PM PST 24
Peak memory 205208 kb
Host smart-7ffd2f05-5f71-48a8-ad5b-11a02222d4f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417525854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2417525854
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3921417363
Short name T486
Test name
Test status
Simulation time 90586644 ps
CPU time 1.66 seconds
Started Jan 22 05:09:54 PM PST 24
Finished Jan 22 05:09:57 PM PST 24
Peak memory 205248 kb
Host smart-f639d009-95b3-4229-a5bd-20097912c351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921417363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3921417363
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.330331226
Short name T109
Test name
Test status
Simulation time 455175308 ps
CPU time 4.71 seconds
Started Jan 22 04:39:39 PM PST 24
Finished Jan 22 04:39:44 PM PST 24
Peak memory 213800 kb
Host smart-694ac63b-f426-4715-bc03-e3d01631c0f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330331226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.330331226
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2208795194
Short name T102
Test name
Test status
Simulation time 103557807 ps
CPU time 4.89 seconds
Started Jan 22 04:39:31 PM PST 24
Finished Jan 22 04:39:36 PM PST 24
Peak memory 219904 kb
Host smart-733de693-317b-4ab6-a236-b65020e65b8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208795194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2208795194
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1665238458
Short name T117
Test name
Test status
Simulation time 57758346 ps
CPU time 1.89 seconds
Started Jan 22 04:39:35 PM PST 24
Finished Jan 22 04:39:37 PM PST 24
Peak memory 213480 kb
Host smart-10565edf-054f-475b-bec6-882e5c7c8eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665238458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1665238458
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1595891066
Short name T148
Test name
Test status
Simulation time 66571412 ps
CPU time 3.75 seconds
Started Jan 22 04:39:39 PM PST 24
Finished Jan 22 04:39:44 PM PST 24
Peak memory 213632 kb
Host smart-6dc22fc1-35b9-40b8-a959-abd69aec22d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595891066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1595891066
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3367029059
Short name T169
Test name
Test status
Simulation time 24108195 ps
CPU time 1.13 seconds
Started Jan 22 04:39:44 PM PST 24
Finished Jan 22 04:39:46 PM PST 24
Peak memory 205088 kb
Host smart-23fc5d8a-c013-44bb-8b51-bab5b4dccd87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367029059 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3367029059
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3083670435
Short name T511
Test name
Test status
Simulation time 28964204 ps
CPU time 0.73 seconds
Started Jan 22 04:39:42 PM PST 24
Finished Jan 22 04:39:43 PM PST 24
Peak memory 205144 kb
Host smart-e55c13cd-b605-4a12-9211-68b027c6eb5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083670435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3083670435
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4283855560
Short name T491
Test name
Test status
Simulation time 34743835 ps
CPU time 2.02 seconds
Started Jan 22 05:55:25 PM PST 24
Finished Jan 22 05:55:28 PM PST 24
Peak memory 205312 kb
Host smart-bc5faa5c-9afc-4dea-bf05-6f18f76148c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283855560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4283855560
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2797200323
Short name T187
Test name
Test status
Simulation time 95099589 ps
CPU time 3.36 seconds
Started Jan 22 04:48:21 PM PST 24
Finished Jan 22 04:48:25 PM PST 24
Peak memory 221980 kb
Host smart-1e978ceb-cf94-4e7a-95b2-30d288ca68a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797200323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2797200323
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.255266988
Short name T432
Test name
Test status
Simulation time 99721662 ps
CPU time 2.96 seconds
Started Jan 22 04:39:40 PM PST 24
Finished Jan 22 04:39:43 PM PST 24
Peak memory 213508 kb
Host smart-d73c47f6-397b-4f26-9b17-fc635b31f982
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255266988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.255266988
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1225182839
Short name T483
Test name
Test status
Simulation time 68006106 ps
CPU time 1.06 seconds
Started Jan 22 04:39:54 PM PST 24
Finished Jan 22 04:39:55 PM PST 24
Peak memory 205352 kb
Host smart-ce1fd51e-6c0f-439f-acc8-913fed7e74bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225182839 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1225182839
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2955613732
Short name T433
Test name
Test status
Simulation time 51080591 ps
CPU time 1.07 seconds
Started Jan 22 05:20:54 PM PST 24
Finished Jan 22 05:20:59 PM PST 24
Peak memory 205224 kb
Host smart-974de0e0-1ce5-4799-b976-9574db1030cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955613732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2955613732
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1806829245
Short name T178
Test name
Test status
Simulation time 12099694 ps
CPU time 0.87 seconds
Started Jan 22 04:39:43 PM PST 24
Finished Jan 22 04:39:44 PM PST 24
Peak memory 205056 kb
Host smart-bc56eac4-291f-4caf-a8f5-f070b5da8aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806829245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1806829245
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.250533989
Short name T127
Test name
Test status
Simulation time 192072571 ps
CPU time 2.44 seconds
Started Jan 22 04:39:49 PM PST 24
Finished Jan 22 04:39:52 PM PST 24
Peak memory 205192 kb
Host smart-8ab7d650-457b-4775-80cd-4ea761639e41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250533989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.250533989
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2343183861
Short name T106
Test name
Test status
Simulation time 433879992 ps
CPU time 3.92 seconds
Started Jan 22 04:39:44 PM PST 24
Finished Jan 22 04:39:49 PM PST 24
Peak memory 213528 kb
Host smart-1b7a0d17-dccb-4f7e-ae55-ae01500538d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343183861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2343183861
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2384730296
Short name T425
Test name
Test status
Simulation time 396316928 ps
CPU time 4.73 seconds
Started Jan 22 04:39:42 PM PST 24
Finished Jan 22 04:39:47 PM PST 24
Peak memory 221944 kb
Host smart-99aac36c-e036-49c8-9ceb-18a168a50ac0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384730296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2384730296
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.621884252
Short name T448
Test name
Test status
Simulation time 17709684 ps
CPU time 1.07 seconds
Started Jan 22 04:39:53 PM PST 24
Finished Jan 22 04:39:55 PM PST 24
Peak memory 205328 kb
Host smart-18c8c414-376c-45be-b238-254d679e1f7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621884252 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.621884252
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1293557981
Short name T128
Test name
Test status
Simulation time 44762026 ps
CPU time 1.05 seconds
Started Jan 22 04:39:49 PM PST 24
Finished Jan 22 04:39:51 PM PST 24
Peak memory 205168 kb
Host smart-40e51ee0-cf07-4784-aaa8-b584c84489b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293557981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1293557981
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1401034705
Short name T408
Test name
Test status
Simulation time 41635383 ps
CPU time 0.71 seconds
Started Jan 22 04:39:45 PM PST 24
Finished Jan 22 04:39:47 PM PST 24
Peak memory 205128 kb
Host smart-81421e36-0fd0-4635-b801-1083f572b59f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401034705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1401034705
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.208258269
Short name T492
Test name
Test status
Simulation time 36550025 ps
CPU time 1.87 seconds
Started Jan 22 04:39:52 PM PST 24
Finished Jan 22 04:39:55 PM PST 24
Peak memory 205292 kb
Host smart-da425aa2-603f-4ab4-969c-28e716ac3db9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208258269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.208258269
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1359591572
Short name T493
Test name
Test status
Simulation time 220360317 ps
CPU time 6.5 seconds
Started Jan 22 04:39:51 PM PST 24
Finished Jan 22 04:39:58 PM PST 24
Peak memory 213832 kb
Host smart-af34ac80-3143-4b51-bbb9-6d93e0ecf8a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359591572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1359591572
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3521960121
Short name T471
Test name
Test status
Simulation time 437479254 ps
CPU time 11.5 seconds
Started Jan 22 04:55:45 PM PST 24
Finished Jan 22 04:55:57 PM PST 24
Peak memory 213724 kb
Host smart-d8eaaf19-38bd-4695-8cd9-06568437a5b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521960121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3521960121
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.327086881
Short name T428
Test name
Test status
Simulation time 239069460 ps
CPU time 2.46 seconds
Started Jan 22 04:39:49 PM PST 24
Finished Jan 22 04:39:52 PM PST 24
Peak memory 216484 kb
Host smart-84544f96-4dbe-4d9a-a990-6dca3f6f12e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327086881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.327086881
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1888267033
Short name T435
Test name
Test status
Simulation time 306646103 ps
CPU time 1.66 seconds
Started Jan 22 04:39:57 PM PST 24
Finished Jan 22 04:40:01 PM PST 24
Peak memory 213392 kb
Host smart-9178e510-583c-44fe-b7e3-70ba985abb30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888267033 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1888267033
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1550171542
Short name T487
Test name
Test status
Simulation time 42928424 ps
CPU time 1.07 seconds
Started Jan 22 04:39:57 PM PST 24
Finished Jan 22 04:40:00 PM PST 24
Peak memory 205184 kb
Host smart-34b1f62e-e8eb-4908-9f90-3167c35d5eed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550171542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1550171542
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2304965431
Short name T465
Test name
Test status
Simulation time 19487656 ps
CPU time 0.97 seconds
Started Jan 22 04:39:59 PM PST 24
Finished Jan 22 04:40:01 PM PST 24
Peak memory 205188 kb
Host smart-59b3497d-645c-4537-a17a-7675ec4b7307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304965431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2304965431
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4277747882
Short name T496
Test name
Test status
Simulation time 150363568 ps
CPU time 2.03 seconds
Started Jan 22 04:40:04 PM PST 24
Finished Jan 22 04:40:09 PM PST 24
Peak memory 205284 kb
Host smart-eb9e7e14-80eb-4747-b228-aeed0485978e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277747882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.4277747882
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2735132312
Short name T107
Test name
Test status
Simulation time 343620892 ps
CPU time 3.09 seconds
Started Jan 22 04:39:48 PM PST 24
Finished Jan 22 04:39:51 PM PST 24
Peak memory 213740 kb
Host smart-073aaded-eb40-4fd8-b482-63b43d8c64af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735132312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2735132312
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1362628920
Short name T463
Test name
Test status
Simulation time 873494665 ps
CPU time 8.78 seconds
Started Jan 22 04:39:53 PM PST 24
Finished Jan 22 04:40:03 PM PST 24
Peak memory 213796 kb
Host smart-ff8525a8-bdda-4402-85e7-e18c68a25747
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362628920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1362628920
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1706204025
Short name T458
Test name
Test status
Simulation time 172438451 ps
CPU time 3.31 seconds
Started Jan 22 04:39:58 PM PST 24
Finished Jan 22 04:40:03 PM PST 24
Peak memory 213444 kb
Host smart-6be49e0b-c88d-48da-a5fe-acb30b265bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706204025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1706204025
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2590046027
Short name T494
Test name
Test status
Simulation time 114921351 ps
CPU time 1.65 seconds
Started Jan 22 04:40:03 PM PST 24
Finished Jan 22 04:40:09 PM PST 24
Peak memory 213488 kb
Host smart-cca12328-c9c9-49e4-8463-9d54419600b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590046027 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2590046027
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3192713752
Short name T135
Test name
Test status
Simulation time 28620418 ps
CPU time 1.55 seconds
Started Jan 22 04:40:04 PM PST 24
Finished Jan 22 04:40:09 PM PST 24
Peak memory 205296 kb
Host smart-3968e14b-afb6-4276-8e86-3d7992bf85cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192713752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3192713752
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2434316330
Short name T186
Test name
Test status
Simulation time 27861747 ps
CPU time 0.7 seconds
Started Jan 22 04:40:02 PM PST 24
Finished Jan 22 04:40:08 PM PST 24
Peak memory 205136 kb
Host smart-69b3df22-2c4e-47e0-a22b-40f9ba4cd396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434316330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2434316330
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3123577666
Short name T436
Test name
Test status
Simulation time 23777773 ps
CPU time 1.71 seconds
Started Jan 22 04:40:03 PM PST 24
Finished Jan 22 04:40:09 PM PST 24
Peak memory 205240 kb
Host smart-7cb02c26-8886-446e-b88a-974574f06908
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123577666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3123577666
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.456432731
Short name T163
Test name
Test status
Simulation time 423240102 ps
CPU time 3.06 seconds
Started Jan 22 04:39:57 PM PST 24
Finished Jan 22 04:40:02 PM PST 24
Peak memory 213776 kb
Host smart-005148bc-7a6c-44b0-8f59-591c48c36ded
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456432731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.456432731
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3064798699
Short name T500
Test name
Test status
Simulation time 173963430 ps
CPU time 4.96 seconds
Started Jan 22 04:39:56 PM PST 24
Finished Jan 22 04:40:04 PM PST 24
Peak memory 216524 kb
Host smart-c04050c2-b2ff-46ec-9576-8dcebfdf43eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064798699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3064798699
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3828699291
Short name T156
Test name
Test status
Simulation time 248467342 ps
CPU time 5.73 seconds
Started Jan 22 04:40:04 PM PST 24
Finished Jan 22 04:40:13 PM PST 24
Peak memory 208992 kb
Host smart-53e0afae-c759-4b36-85c4-6217db33d5aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828699291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3828699291
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2379247551
Short name T450
Test name
Test status
Simulation time 35573030 ps
CPU time 1.28 seconds
Started Jan 22 04:40:05 PM PST 24
Finished Jan 22 04:40:09 PM PST 24
Peak memory 213688 kb
Host smart-15e56a1d-890d-49fe-bfe8-0de5a5cbed50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379247551 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2379247551
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3671785626
Short name T508
Test name
Test status
Simulation time 18756522 ps
CPU time 0.84 seconds
Started Jan 22 04:40:04 PM PST 24
Finished Jan 22 04:40:08 PM PST 24
Peak memory 205144 kb
Host smart-4bb9b218-4d2b-43ec-b944-beab66dd20c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671785626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3671785626
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4012853574
Short name T446
Test name
Test status
Simulation time 102098317 ps
CPU time 1.7 seconds
Started Jan 22 04:40:02 PM PST 24
Finished Jan 22 04:40:09 PM PST 24
Peak memory 205212 kb
Host smart-4fc70fa2-2e47-43ec-8196-d52a62a2ea18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012853574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.4012853574
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3570190813
Short name T464
Test name
Test status
Simulation time 316247963 ps
CPU time 2.79 seconds
Started Jan 22 04:40:08 PM PST 24
Finished Jan 22 04:40:13 PM PST 24
Peak memory 221928 kb
Host smart-7cf4b780-f966-4195-8534-293a4ec2ce14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570190813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3570190813
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.4099949116
Short name T103
Test name
Test status
Simulation time 726067333 ps
CPU time 5.64 seconds
Started Jan 22 04:40:04 PM PST 24
Finished Jan 22 04:40:13 PM PST 24
Peak memory 213692 kb
Host smart-57137e81-e576-4b2c-927a-70970d6444a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099949116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.4099949116
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2745130398
Short name T168
Test name
Test status
Simulation time 222036766 ps
CPU time 2.59 seconds
Started Jan 22 04:40:07 PM PST 24
Finished Jan 22 04:40:12 PM PST 24
Peak memory 215756 kb
Host smart-cbc0c113-b0a0-4dc9-94bd-4476bacaf260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745130398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2745130398
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2144643479
Short name T466
Test name
Test status
Simulation time 767978695 ps
CPU time 13.65 seconds
Started Jan 22 04:38:40 PM PST 24
Finished Jan 22 04:38:54 PM PST 24
Peak memory 205272 kb
Host smart-5ef893f7-69f0-458a-96bc-5a09906d846c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144643479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
144643479
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1541838115
Short name T179
Test name
Test status
Simulation time 252730601 ps
CPU time 12.47 seconds
Started Jan 22 04:38:41 PM PST 24
Finished Jan 22 04:38:54 PM PST 24
Peak memory 205200 kb
Host smart-61b56cd9-ee10-4d26-a248-63253aabe0ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541838115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
541838115
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2544592261
Short name T176
Test name
Test status
Simulation time 60935670 ps
CPU time 1.47 seconds
Started Jan 22 04:38:41 PM PST 24
Finished Jan 22 04:38:43 PM PST 24
Peak memory 205248 kb
Host smart-543e6950-fd68-4290-a589-382addc2686b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544592261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
544592261
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.174025404
Short name T174
Test name
Test status
Simulation time 15122421 ps
CPU time 0.99 seconds
Started Jan 22 04:38:42 PM PST 24
Finished Jan 22 04:38:43 PM PST 24
Peak memory 205360 kb
Host smart-06e270be-9f7b-44d7-9d26-0e59ffb88956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174025404 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.174025404
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2201278915
Short name T412
Test name
Test status
Simulation time 12236284 ps
CPU time 0.71 seconds
Started Jan 22 04:38:43 PM PST 24
Finished Jan 22 04:38:44 PM PST 24
Peak memory 205136 kb
Host smart-b96a33f5-cf36-46c0-a437-b6b2b61abda0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201278915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2201278915
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1346772205
Short name T476
Test name
Test status
Simulation time 95715998 ps
CPU time 1.75 seconds
Started Jan 22 04:38:45 PM PST 24
Finished Jan 22 04:38:47 PM PST 24
Peak memory 213040 kb
Host smart-099c1799-c131-4732-a0c8-59d3a555963d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346772205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1346772205
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1388838733
Short name T497
Test name
Test status
Simulation time 74574892 ps
CPU time 2.71 seconds
Started Jan 22 04:38:40 PM PST 24
Finished Jan 22 04:38:44 PM PST 24
Peak memory 213892 kb
Host smart-717c86da-ee98-4df6-834a-6fc9e949fa5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388838733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1388838733
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2376387844
Short name T447
Test name
Test status
Simulation time 724795029 ps
CPU time 21.21 seconds
Started Jan 22 04:38:38 PM PST 24
Finished Jan 22 04:39:00 PM PST 24
Peak memory 213776 kb
Host smart-ff2c7186-e130-40aa-a3d4-a71aa26cadb9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376387844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2376387844
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1579759383
Short name T478
Test name
Test status
Simulation time 281300239 ps
CPU time 4.41 seconds
Started Jan 22 04:38:41 PM PST 24
Finished Jan 22 04:38:46 PM PST 24
Peak memory 213584 kb
Host smart-b1998f26-5b8c-46b9-b8d9-3c1f7c4f6880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579759383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1579759383
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3766636781
Short name T421
Test name
Test status
Simulation time 21752610 ps
CPU time 0.71 seconds
Started Jan 22 04:40:12 PM PST 24
Finished Jan 22 04:40:14 PM PST 24
Peak memory 205104 kb
Host smart-c5bd725d-a869-4c33-817c-e6563095f34f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766636781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3766636781
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1150551453
Short name T502
Test name
Test status
Simulation time 31518416 ps
CPU time 0.75 seconds
Started Jan 22 04:40:18 PM PST 24
Finished Jan 22 04:40:19 PM PST 24
Peak memory 205148 kb
Host smart-f23de97f-fd8d-4ba0-82f3-17e0563d77ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150551453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1150551453
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1457234858
Short name T495
Test name
Test status
Simulation time 25929963 ps
CPU time 0.91 seconds
Started Jan 22 04:40:16 PM PST 24
Finished Jan 22 04:40:17 PM PST 24
Peak memory 205132 kb
Host smart-37c5c776-bce0-49dd-b40f-6488b79285dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457234858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1457234858
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2785411850
Short name T132
Test name
Test status
Simulation time 14035763 ps
CPU time 0.72 seconds
Started Jan 22 04:40:17 PM PST 24
Finished Jan 22 04:40:19 PM PST 24
Peak memory 205064 kb
Host smart-9ea0f604-af96-4445-9652-7cf5b36ba70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785411850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2785411850
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3400687190
Short name T472
Test name
Test status
Simulation time 25663929 ps
CPU time 0.77 seconds
Started Jan 22 04:40:13 PM PST 24
Finished Jan 22 04:40:14 PM PST 24
Peak memory 205060 kb
Host smart-632488ea-65bf-415e-a1f5-35e5e9ef49fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400687190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3400687190
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.643287824
Short name T489
Test name
Test status
Simulation time 28060438 ps
CPU time 0.78 seconds
Started Jan 22 04:40:17 PM PST 24
Finished Jan 22 04:40:19 PM PST 24
Peak memory 204988 kb
Host smart-779bd786-c0f5-48d8-a21a-97f29581cd48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643287824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.643287824
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1081027951
Short name T418
Test name
Test status
Simulation time 10127514 ps
CPU time 0.73 seconds
Started Jan 22 04:40:16 PM PST 24
Finished Jan 22 04:40:17 PM PST 24
Peak memory 205056 kb
Host smart-a8816840-2177-4ff7-a592-0439359e9e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081027951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1081027951
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1400296817
Short name T441
Test name
Test status
Simulation time 13245674 ps
CPU time 0.76 seconds
Started Jan 22 04:40:20 PM PST 24
Finished Jan 22 04:40:25 PM PST 24
Peak memory 205084 kb
Host smart-92cb9636-ba65-4aed-8306-52362068a6b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400296817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1400296817
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.199063652
Short name T518
Test name
Test status
Simulation time 7405877 ps
CPU time 0.73 seconds
Started Jan 22 04:40:12 PM PST 24
Finished Jan 22 04:40:13 PM PST 24
Peak memory 205140 kb
Host smart-f2692dab-a3db-404b-bf4b-8102d283c802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199063652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.199063652
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1570317256
Short name T460
Test name
Test status
Simulation time 12194002 ps
CPU time 0.87 seconds
Started Jan 22 04:40:13 PM PST 24
Finished Jan 22 04:40:14 PM PST 24
Peak memory 205008 kb
Host smart-e9c516ff-c698-4c4a-ba43-c3bbd48f051e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570317256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1570317256
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.951340734
Short name T129
Test name
Test status
Simulation time 540353545 ps
CPU time 9.31 seconds
Started Jan 22 04:38:53 PM PST 24
Finished Jan 22 04:39:03 PM PST 24
Peak memory 205304 kb
Host smart-80b75dac-9851-4656-8ea8-c276977d108f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951340734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.951340734
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4192862760
Short name T173
Test name
Test status
Simulation time 20983231 ps
CPU time 0.93 seconds
Started Jan 22 04:38:50 PM PST 24
Finished Jan 22 04:38:51 PM PST 24
Peak memory 205052 kb
Host smart-b50d6b80-12e4-405d-923b-2e31228a7ebe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192862760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
192862760
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2575553624
Short name T165
Test name
Test status
Simulation time 27638593 ps
CPU time 0.96 seconds
Started Jan 22 04:38:57 PM PST 24
Finished Jan 22 04:38:58 PM PST 24
Peak memory 205304 kb
Host smart-dbb1e348-e8a2-4429-854d-de508c745b53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575553624 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2575553624
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1739784014
Short name T136
Test name
Test status
Simulation time 10126715 ps
CPU time 1.03 seconds
Started Jan 22 05:05:49 PM PST 24
Finished Jan 22 05:05:51 PM PST 24
Peak memory 205096 kb
Host smart-d0ea8db0-aadf-471f-995e-f45a31c1491e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739784014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1739784014
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4242743878
Short name T427
Test name
Test status
Simulation time 32453929 ps
CPU time 0.77 seconds
Started Jan 22 05:46:58 PM PST 24
Finished Jan 22 05:47:07 PM PST 24
Peak memory 205184 kb
Host smart-6be81593-c036-4516-8dd8-b286dd0c439e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242743878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.4242743878
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3730018780
Short name T519
Test name
Test status
Simulation time 73710931 ps
CPU time 1.75 seconds
Started Jan 22 04:38:50 PM PST 24
Finished Jan 22 04:38:52 PM PST 24
Peak memory 205144 kb
Host smart-e05ec4af-aa04-46f1-83dc-9c5d56d51508
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730018780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3730018780
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3896303634
Short name T177
Test name
Test status
Simulation time 167519877 ps
CPU time 2.42 seconds
Started Jan 22 04:38:48 PM PST 24
Finished Jan 22 04:38:51 PM PST 24
Peak memory 213700 kb
Host smart-d68184e8-894e-443a-ad7d-385a1e90bb93
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896303634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3896303634
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1447592208
Short name T515
Test name
Test status
Simulation time 1382328687 ps
CPU time 6.13 seconds
Started Jan 22 04:38:42 PM PST 24
Finished Jan 22 04:38:49 PM PST 24
Peak memory 213800 kb
Host smart-4f3ee7b3-2cff-453b-b852-bd8bb2282376
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447592208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1447592208
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2442221439
Short name T480
Test name
Test status
Simulation time 414379915 ps
CPU time 2.24 seconds
Started Jan 22 04:38:52 PM PST 24
Finished Jan 22 04:38:55 PM PST 24
Peak memory 213520 kb
Host smart-c720f3c4-3d76-4597-b426-5afc20886bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442221439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2442221439
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.83503104
Short name T498
Test name
Test status
Simulation time 12636304 ps
CPU time 0.89 seconds
Started Jan 22 04:40:14 PM PST 24
Finished Jan 22 04:40:16 PM PST 24
Peak memory 205116 kb
Host smart-64b76e8a-0eb3-4489-8faf-5d1f9491273b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83503104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.83503104
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2604344147
Short name T517
Test name
Test status
Simulation time 60186836 ps
CPU time 0.8 seconds
Started Jan 22 04:40:21 PM PST 24
Finished Jan 22 04:40:25 PM PST 24
Peak memory 204472 kb
Host smart-097ccf24-1058-4d9b-a1e1-1b237943f80b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604344147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2604344147
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.827971793
Short name T180
Test name
Test status
Simulation time 14675711 ps
CPU time 0.93 seconds
Started Jan 22 04:40:20 PM PST 24
Finished Jan 22 04:40:25 PM PST 24
Peak memory 205204 kb
Host smart-ab4a52f4-60cc-4d36-9e55-3a31fb2ba843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827971793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.827971793
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1532563740
Short name T451
Test name
Test status
Simulation time 35971862 ps
CPU time 0.81 seconds
Started Jan 22 04:40:14 PM PST 24
Finished Jan 22 04:40:15 PM PST 24
Peak memory 205064 kb
Host smart-80296869-0257-4486-92f8-783540757c03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532563740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1532563740
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1097906725
Short name T462
Test name
Test status
Simulation time 21426451 ps
CPU time 0.69 seconds
Started Jan 22 04:40:21 PM PST 24
Finished Jan 22 04:40:24 PM PST 24
Peak memory 205080 kb
Host smart-60b6a757-28f1-4242-9e0b-69a905108aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097906725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1097906725
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3972183346
Short name T409
Test name
Test status
Simulation time 11958008 ps
CPU time 0.72 seconds
Started Jan 22 04:40:22 PM PST 24
Finished Jan 22 04:40:24 PM PST 24
Peak memory 205020 kb
Host smart-614cccea-e863-437a-aa96-1f8194d69f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972183346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3972183346
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.395022876
Short name T453
Test name
Test status
Simulation time 13956350 ps
CPU time 0.74 seconds
Started Jan 22 04:40:22 PM PST 24
Finished Jan 22 04:40:25 PM PST 24
Peak memory 205100 kb
Host smart-bea6bfeb-8749-4c47-9aa5-f21ad7b501bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395022876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.395022876
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3498437215
Short name T407
Test name
Test status
Simulation time 27282788 ps
CPU time 0.82 seconds
Started Jan 22 04:40:22 PM PST 24
Finished Jan 22 04:40:25 PM PST 24
Peak memory 205176 kb
Host smart-1b1136de-df5e-4999-8941-26e801f287bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498437215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3498437215
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.751171540
Short name T455
Test name
Test status
Simulation time 36494113 ps
CPU time 0.96 seconds
Started Jan 22 04:40:22 PM PST 24
Finished Jan 22 04:40:25 PM PST 24
Peak memory 205128 kb
Host smart-b0da78f4-1fdf-4553-a158-634e142f7f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751171540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.751171540
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3065025649
Short name T413
Test name
Test status
Simulation time 27271744 ps
CPU time 0.91 seconds
Started Jan 22 04:40:18 PM PST 24
Finished Jan 22 04:40:20 PM PST 24
Peak memory 205268 kb
Host smart-cc4268eb-7d31-438d-bab3-c60c67e47cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065025649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3065025649
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.868418701
Short name T188
Test name
Test status
Simulation time 931972257 ps
CPU time 7.55 seconds
Started Jan 22 05:52:10 PM PST 24
Finished Jan 22 05:52:19 PM PST 24
Peak memory 205352 kb
Host smart-d9bbc0b4-b428-40ba-a88b-57ad2f6f0a72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868418701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.868418701
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3093493759
Short name T506
Test name
Test status
Simulation time 268488050 ps
CPU time 12.83 seconds
Started Jan 22 04:39:03 PM PST 24
Finished Jan 22 04:39:16 PM PST 24
Peak memory 205096 kb
Host smart-f783c27f-1b95-498b-89ee-29fbacf54414
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093493759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
093493759
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3589409537
Short name T167
Test name
Test status
Simulation time 42121495 ps
CPU time 0.97 seconds
Started Jan 22 04:39:09 PM PST 24
Finished Jan 22 04:39:11 PM PST 24
Peak memory 205140 kb
Host smart-63d398d5-3655-4808-8c6a-1244e78efd13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589409537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
589409537
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.25125959
Short name T130
Test name
Test status
Simulation time 29100850 ps
CPU time 1.66 seconds
Started Jan 22 04:39:01 PM PST 24
Finished Jan 22 04:39:03 PM PST 24
Peak memory 213564 kb
Host smart-db58d1e3-9a15-44f6-949b-a2dcf486f54c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25125959 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.25125959
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2064527583
Short name T454
Test name
Test status
Simulation time 16975979 ps
CPU time 1.25 seconds
Started Jan 22 04:39:03 PM PST 24
Finished Jan 22 04:39:04 PM PST 24
Peak memory 205268 kb
Host smart-754d2620-8045-4f4c-8208-99c889bdb2c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064527583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2064527583
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2889513882
Short name T417
Test name
Test status
Simulation time 43506504 ps
CPU time 0.73 seconds
Started Jan 22 04:39:01 PM PST 24
Finished Jan 22 04:39:02 PM PST 24
Peak memory 205056 kb
Host smart-3923dcf7-48a1-45f4-8543-e501982b4e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889513882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2889513882
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2607538315
Short name T426
Test name
Test status
Simulation time 154580113 ps
CPU time 4.58 seconds
Started Jan 22 04:39:02 PM PST 24
Finished Jan 22 04:39:08 PM PST 24
Peak memory 213708 kb
Host smart-7254699a-2dd4-46f7-9b5e-f534c6499fc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607538315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2607538315
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1592440818
Short name T513
Test name
Test status
Simulation time 258570227 ps
CPU time 7.01 seconds
Started Jan 22 04:38:55 PM PST 24
Finished Jan 22 04:39:03 PM PST 24
Peak memory 213756 kb
Host smart-577fcb66-e43e-4861-9964-74d94237aa17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592440818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1592440818
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.552259187
Short name T123
Test name
Test status
Simulation time 269052306 ps
CPU time 2.04 seconds
Started Jan 22 04:38:53 PM PST 24
Finished Jan 22 04:38:55 PM PST 24
Peak memory 221812 kb
Host smart-51466cd3-8b34-41ad-a82c-44e5d910394a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552259187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.552259187
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3800979565
Short name T474
Test name
Test status
Simulation time 21558208 ps
CPU time 0.83 seconds
Started Jan 22 04:40:18 PM PST 24
Finished Jan 22 04:40:20 PM PST 24
Peak memory 205184 kb
Host smart-b9682765-4b20-4883-9b17-eb4d324a556c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800979565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3800979565
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.98803577
Short name T473
Test name
Test status
Simulation time 21091753 ps
CPU time 0.71 seconds
Started Jan 22 04:40:22 PM PST 24
Finished Jan 22 04:40:24 PM PST 24
Peak memory 205244 kb
Host smart-8efc0927-989e-4d8b-9eb8-e78026622291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98803577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.98803577
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3225002413
Short name T443
Test name
Test status
Simulation time 52289775 ps
CPU time 0.74 seconds
Started Jan 22 04:40:18 PM PST 24
Finished Jan 22 04:40:23 PM PST 24
Peak memory 205104 kb
Host smart-6dfd87fe-ca0e-4b40-b58e-716f7688eceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225002413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3225002413
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.657449796
Short name T461
Test name
Test status
Simulation time 37720617 ps
CPU time 0.72 seconds
Started Jan 22 04:40:22 PM PST 24
Finished Jan 22 04:40:25 PM PST 24
Peak memory 205176 kb
Host smart-6abd923f-d14e-46d4-93fc-171deb641ef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657449796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.657449796
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1369380793
Short name T481
Test name
Test status
Simulation time 23160536 ps
CPU time 0.79 seconds
Started Jan 22 04:40:24 PM PST 24
Finished Jan 22 04:40:27 PM PST 24
Peak memory 205180 kb
Host smart-ad864ea0-0b88-4aa0-bc72-be92355c626a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369380793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1369380793
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.856924844
Short name T183
Test name
Test status
Simulation time 12189786 ps
CPU time 0.76 seconds
Started Jan 22 04:40:21 PM PST 24
Finished Jan 22 04:40:25 PM PST 24
Peak memory 204456 kb
Host smart-b8e02403-3e46-4273-85f8-13dbfda2f08e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856924844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.856924844
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.963595883
Short name T431
Test name
Test status
Simulation time 14386504 ps
CPU time 0.79 seconds
Started Jan 22 04:40:22 PM PST 24
Finished Jan 22 04:40:25 PM PST 24
Peak memory 205136 kb
Host smart-53cca5fd-af1f-4ad1-b9e3-ded22be02d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963595883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.963595883
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.649110527
Short name T416
Test name
Test status
Simulation time 30280177 ps
CPU time 1.16 seconds
Started Jan 22 04:40:20 PM PST 24
Finished Jan 22 04:40:25 PM PST 24
Peak memory 205308 kb
Host smart-ffd5ad3a-dd10-4849-ad11-652a4c86c0bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649110527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.649110527
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.537645321
Short name T401
Test name
Test status
Simulation time 15842270 ps
CPU time 0.78 seconds
Started Jan 22 04:40:19 PM PST 24
Finished Jan 22 04:40:25 PM PST 24
Peak memory 205108 kb
Host smart-1ee2c678-e7bd-4fe5-bb3e-804b870bc852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537645321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.537645321
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2992522300
Short name T133
Test name
Test status
Simulation time 13383243 ps
CPU time 0.91 seconds
Started Jan 22 04:40:30 PM PST 24
Finished Jan 22 04:40:32 PM PST 24
Peak memory 205192 kb
Host smart-de183277-c288-4c74-97ab-a947faf6c2d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992522300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2992522300
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2296316746
Short name T166
Test name
Test status
Simulation time 14063269 ps
CPU time 1.03 seconds
Started Jan 22 04:39:13 PM PST 24
Finished Jan 22 04:39:14 PM PST 24
Peak memory 205364 kb
Host smart-c0aa267b-68e4-4a5d-b215-95a66208a82e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296316746 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2296316746
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2464238158
Short name T484
Test name
Test status
Simulation time 13701738 ps
CPU time 0.88 seconds
Started Jan 22 04:39:10 PM PST 24
Finished Jan 22 04:39:12 PM PST 24
Peak memory 205092 kb
Host smart-8ad47062-3113-4e7a-801d-0bc9a81717f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464238158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2464238158
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3036634672
Short name T405
Test name
Test status
Simulation time 49790810 ps
CPU time 0.84 seconds
Started Jan 22 04:39:09 PM PST 24
Finished Jan 22 04:39:11 PM PST 24
Peak memory 205100 kb
Host smart-336d49b0-30f9-4082-9606-51d2dd0f247c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036634672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3036634672
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.50574283
Short name T503
Test name
Test status
Simulation time 818540632 ps
CPU time 4.55 seconds
Started Jan 22 04:39:10 PM PST 24
Finished Jan 22 04:39:15 PM PST 24
Peak memory 221936 kb
Host smart-5c40a0a0-f961-476f-b879-60f7212a036e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50574283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_
reg_errors.50574283
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2121586904
Short name T110
Test name
Test status
Simulation time 205701611 ps
CPU time 5.47 seconds
Started Jan 22 04:39:12 PM PST 24
Finished Jan 22 04:39:18 PM PST 24
Peak memory 213644 kb
Host smart-71bbf75f-f644-48f2-b4ec-17463d90fac8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121586904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2121586904
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2780898762
Short name T470
Test name
Test status
Simulation time 106729609 ps
CPU time 3.86 seconds
Started Jan 22 04:39:09 PM PST 24
Finished Jan 22 04:39:14 PM PST 24
Peak memory 213488 kb
Host smart-9581aee1-a816-4f18-8b61-0b7bc4e03b74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780898762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2780898762
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1444876032
Short name T151
Test name
Test status
Simulation time 216113267 ps
CPU time 3.72 seconds
Started Jan 22 04:39:10 PM PST 24
Finished Jan 22 04:39:14 PM PST 24
Peak memory 208704 kb
Host smart-b3ec86f4-f711-471d-a9cc-c3cc9841b41b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444876032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1444876032
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2026883435
Short name T171
Test name
Test status
Simulation time 27399638 ps
CPU time 1.1 seconds
Started Jan 22 06:05:15 PM PST 24
Finished Jan 22 06:05:17 PM PST 24
Peak memory 205328 kb
Host smart-be562538-1d26-43a3-b40d-bc252aeeafb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026883435 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2026883435
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1556640128
Short name T419
Test name
Test status
Simulation time 216701964 ps
CPU time 1.23 seconds
Started Jan 22 04:39:21 PM PST 24
Finished Jan 22 04:39:23 PM PST 24
Peak memory 205248 kb
Host smart-4d34152d-720d-46b8-90d6-d9c8f3796864
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556640128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1556640128
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1714249472
Short name T469
Test name
Test status
Simulation time 21348652 ps
CPU time 0.82 seconds
Started Jan 22 04:39:18 PM PST 24
Finished Jan 22 04:39:20 PM PST 24
Peak memory 205144 kb
Host smart-a6508e42-b2a7-43d4-aaa0-6b890515709e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714249472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1714249472
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3544788146
Short name T504
Test name
Test status
Simulation time 346191443 ps
CPU time 3.94 seconds
Started Jan 22 05:03:11 PM PST 24
Finished Jan 22 05:03:19 PM PST 24
Peak memory 221828 kb
Host smart-500c7474-7ba8-41cf-be86-7e9cc98b2caf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544788146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3544788146
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1901041508
Short name T488
Test name
Test status
Simulation time 161930515 ps
CPU time 4.63 seconds
Started Jan 22 04:39:22 PM PST 24
Finished Jan 22 04:39:27 PM PST 24
Peak memory 213668 kb
Host smart-c82e55fe-1d88-47fc-894b-8110892bd38d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901041508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1901041508
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1523800665
Short name T482
Test name
Test status
Simulation time 163553655 ps
CPU time 2.33 seconds
Started Jan 22 04:39:19 PM PST 24
Finished Jan 22 04:39:21 PM PST 24
Peak memory 213500 kb
Host smart-58e064a4-74f8-428c-9e6d-b396983660b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523800665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1523800665
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3100274682
Short name T172
Test name
Test status
Simulation time 125701296 ps
CPU time 1.46 seconds
Started Jan 22 04:39:23 PM PST 24
Finished Jan 22 04:39:25 PM PST 24
Peak memory 205192 kb
Host smart-ddc122a7-f761-4c3f-b744-775547dc6a67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100274682 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3100274682
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.586145019
Short name T445
Test name
Test status
Simulation time 21920433 ps
CPU time 1.4 seconds
Started Jan 22 04:39:22 PM PST 24
Finished Jan 22 04:39:24 PM PST 24
Peak memory 205296 kb
Host smart-dd8adad3-6e5c-40fc-81aa-d09cf43fdc74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586145019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.586145019
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4151660968
Short name T516
Test name
Test status
Simulation time 10814614 ps
CPU time 0.74 seconds
Started Jan 22 04:39:20 PM PST 24
Finished Jan 22 04:39:21 PM PST 24
Peak memory 205144 kb
Host smart-1db44cdc-4041-48eb-84fb-20d91a6a5755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151660968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.4151660968
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3580019386
Short name T514
Test name
Test status
Simulation time 112552551 ps
CPU time 2.68 seconds
Started Jan 22 04:39:22 PM PST 24
Finished Jan 22 04:39:25 PM PST 24
Peak memory 213500 kb
Host smart-96f63fa2-94d1-4e74-b7c2-1e90b3b51ab6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580019386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3580019386
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3387953640
Short name T402
Test name
Test status
Simulation time 89806635 ps
CPU time 2.2 seconds
Started Jan 22 05:33:52 PM PST 24
Finished Jan 22 05:33:56 PM PST 24
Peak memory 213684 kb
Host smart-b5243ca6-dd45-4304-bc0b-0e878f728cdf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387953640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3387953640
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.374282598
Short name T444
Test name
Test status
Simulation time 265641818 ps
CPU time 5.77 seconds
Started Jan 22 04:39:21 PM PST 24
Finished Jan 22 04:39:27 PM PST 24
Peak memory 219996 kb
Host smart-350d7d2e-a15a-4eb2-928c-32ecfabd4c58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374282598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.374282598
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2837967899
Short name T479
Test name
Test status
Simulation time 46578638 ps
CPU time 2.92 seconds
Started Jan 22 05:00:10 PM PST 24
Finished Jan 22 05:00:13 PM PST 24
Peak memory 221688 kb
Host smart-d839373c-a645-4fd8-8e57-98e9f9badfc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837967899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2837967899
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3502048241
Short name T449
Test name
Test status
Simulation time 27514278 ps
CPU time 1.12 seconds
Started Jan 22 04:39:35 PM PST 24
Finished Jan 22 04:39:37 PM PST 24
Peak memory 205328 kb
Host smart-439654bb-a9e0-40b2-96bd-f153c5262cea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502048241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3502048241
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1434530926
Short name T429
Test name
Test status
Simulation time 41301495 ps
CPU time 0.85 seconds
Started Jan 22 04:58:37 PM PST 24
Finished Jan 22 04:58:43 PM PST 24
Peak memory 205176 kb
Host smart-2079a39d-b54f-46e3-b55e-c344e290bef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434530926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1434530926
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.247643972
Short name T424
Test name
Test status
Simulation time 141535712 ps
CPU time 1.6 seconds
Started Jan 22 04:39:34 PM PST 24
Finished Jan 22 04:39:36 PM PST 24
Peak memory 205332 kb
Host smart-64fabed2-03f4-4515-9622-f47bdf393679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247643972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.247643972
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1793824225
Short name T520
Test name
Test status
Simulation time 1728907618 ps
CPU time 29.56 seconds
Started Jan 22 04:39:22 PM PST 24
Finished Jan 22 04:39:52 PM PST 24
Peak memory 217836 kb
Host smart-8269c16e-e141-41a7-bb2e-210facaf321c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793824225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1793824225
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1335479507
Short name T467
Test name
Test status
Simulation time 99528090 ps
CPU time 3.6 seconds
Started Jan 22 04:39:21 PM PST 24
Finished Jan 22 04:39:24 PM PST 24
Peak memory 213452 kb
Host smart-4f7367d9-c610-498c-bb72-11ebc4bf21e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335479507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1335479507
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2269545603
Short name T147
Test name
Test status
Simulation time 431271333 ps
CPU time 6.54 seconds
Started Jan 22 04:57:33 PM PST 24
Finished Jan 22 04:57:39 PM PST 24
Peak memory 213632 kb
Host smart-18b6d120-801d-4a94-b388-66b388a5e6af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269545603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2269545603
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.570399677
Short name T510
Test name
Test status
Simulation time 64277169 ps
CPU time 1.32 seconds
Started Jan 22 04:39:34 PM PST 24
Finished Jan 22 04:39:35 PM PST 24
Peak memory 213664 kb
Host smart-6b707609-628a-49d2-b264-09907ede2be6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570399677 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.570399677
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2446857938
Short name T509
Test name
Test status
Simulation time 15577735 ps
CPU time 1.14 seconds
Started Jan 22 04:39:36 PM PST 24
Finished Jan 22 04:39:37 PM PST 24
Peak memory 205172 kb
Host smart-c9be8d9c-80c1-4c35-8f70-8abe365bc448
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446857938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2446857938
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4150851018
Short name T440
Test name
Test status
Simulation time 12655219 ps
CPU time 0.74 seconds
Started Jan 22 04:39:29 PM PST 24
Finished Jan 22 04:39:30 PM PST 24
Peak memory 205012 kb
Host smart-a14ecc91-652a-4a1d-b897-377166162018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150851018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.4150851018
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2777949607
Short name T105
Test name
Test status
Simulation time 144179216 ps
CPU time 2.64 seconds
Started Jan 22 04:39:35 PM PST 24
Finished Jan 22 04:39:38 PM PST 24
Peak memory 213700 kb
Host smart-89d4b52d-c063-41d6-955a-88cdd8869aee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777949607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2777949607
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.593738616
Short name T175
Test name
Test status
Simulation time 130468772 ps
CPU time 2.06 seconds
Started Jan 22 04:39:31 PM PST 24
Finished Jan 22 04:39:34 PM PST 24
Peak memory 213604 kb
Host smart-3c485794-6cc7-4a4f-9338-52fd349c83b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593738616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.593738616
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.4193659745
Short name T571
Test name
Test status
Simulation time 21537235 ps
CPU time 0.85 seconds
Started Jan 22 04:58:32 PM PST 24
Finished Jan 22 04:58:33 PM PST 24
Peak memory 205772 kb
Host smart-ee1bcb85-4de8-4615-ac3a-2a9c2e9f7fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193659745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.4193659745
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1499941023
Short name T926
Test name
Test status
Simulation time 56004807 ps
CPU time 3.61 seconds
Started Jan 22 04:58:20 PM PST 24
Finished Jan 22 04:58:29 PM PST 24
Peak memory 214312 kb
Host smart-7ba9b454-93c0-4bed-bde6-6042361edc7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499941023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1499941023
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2696482718
Short name T713
Test name
Test status
Simulation time 80626716 ps
CPU time 1.44 seconds
Started Jan 22 04:58:19 PM PST 24
Finished Jan 22 04:58:25 PM PST 24
Peak memory 208128 kb
Host smart-4046873d-af1c-4905-bdb6-15213f89fbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696482718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2696482718
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3402274907
Short name T1040
Test name
Test status
Simulation time 171935094 ps
CPU time 6.68 seconds
Started Jan 22 04:58:19 PM PST 24
Finished Jan 22 04:58:29 PM PST 24
Peak memory 215124 kb
Host smart-85ce8186-70bc-4863-9b23-1a441ded782d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402274907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3402274907
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3921589000
Short name T310
Test name
Test status
Simulation time 3888063383 ps
CPU time 7.44 seconds
Started Jan 22 04:58:18 PM PST 24
Finished Jan 22 04:58:27 PM PST 24
Peak memory 207868 kb
Host smart-4c51ca26-9d7a-4946-a8d1-8f9a8f60d7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921589000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3921589000
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.520552828
Short name T939
Test name
Test status
Simulation time 266220589 ps
CPU time 3.51 seconds
Started Jan 22 04:58:15 PM PST 24
Finished Jan 22 04:58:20 PM PST 24
Peak memory 208716 kb
Host smart-72bf3384-62b8-4be1-b151-cdd0dc7f62df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520552828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.520552828
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1427786647
Short name T971
Test name
Test status
Simulation time 23564736 ps
CPU time 1.95 seconds
Started Jan 22 04:58:19 PM PST 24
Finished Jan 22 04:58:26 PM PST 24
Peak memory 206840 kb
Host smart-adedd7d4-6660-4ea9-828a-8aff725b4bb4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427786647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1427786647
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1607214491
Short name T610
Test name
Test status
Simulation time 264266590 ps
CPU time 7.49 seconds
Started Jan 22 04:58:19 PM PST 24
Finished Jan 22 04:58:32 PM PST 24
Peak memory 208160 kb
Host smart-dc5c4a05-f2ba-40cc-a2c2-cf056a7f3e6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607214491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1607214491
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3385940216
Short name T870
Test name
Test status
Simulation time 711470330 ps
CPU time 11.21 seconds
Started Jan 22 04:58:31 PM PST 24
Finished Jan 22 04:58:43 PM PST 24
Peak memory 208132 kb
Host smart-f47b549e-2d50-4e8b-855d-4bd12d9f1b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385940216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3385940216
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1868083295
Short name T722
Test name
Test status
Simulation time 52880338 ps
CPU time 2.87 seconds
Started Jan 22 04:58:23 PM PST 24
Finished Jan 22 04:58:28 PM PST 24
Peak memory 206812 kb
Host smart-f03fd1f4-66ca-4788-9735-e737c476108d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868083295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1868083295
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1604539942
Short name T347
Test name
Test status
Simulation time 114089202 ps
CPU time 5.08 seconds
Started Jan 22 04:58:23 PM PST 24
Finished Jan 22 04:58:30 PM PST 24
Peak memory 207684 kb
Host smart-baef9421-b666-415c-98e6-bac8bb62df41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604539942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1604539942
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3117201538
Short name T373
Test name
Test status
Simulation time 192120572 ps
CPU time 2.6 seconds
Started Jan 22 04:58:26 PM PST 24
Finished Jan 22 04:58:31 PM PST 24
Peak memory 210204 kb
Host smart-5e5c815d-10fb-401d-9674-847a5f8185a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117201538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3117201538
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.90650330
Short name T601
Test name
Test status
Simulation time 17598341 ps
CPU time 0.79 seconds
Started Jan 22 04:58:56 PM PST 24
Finished Jan 22 04:58:58 PM PST 24
Peak memory 205800 kb
Host smart-1bf954a8-7b14-41d6-9a73-4b8f1ca6840b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90650330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.90650330
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.285982408
Short name T877
Test name
Test status
Simulation time 477883035 ps
CPU time 8.16 seconds
Started Jan 22 05:22:09 PM PST 24
Finished Jan 22 05:22:18 PM PST 24
Peak memory 214940 kb
Host smart-f345ddd5-f9a7-4835-82b0-3cfeb3bef33e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285982408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.285982408
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1566724161
Short name T82
Test name
Test status
Simulation time 810527004 ps
CPU time 11.79 seconds
Started Jan 22 04:59:00 PM PST 24
Finished Jan 22 04:59:12 PM PST 24
Peak memory 208132 kb
Host smart-9d43ae97-4e84-441a-837f-9f886f221375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566724161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1566724161
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3690460622
Short name T258
Test name
Test status
Simulation time 291947501 ps
CPU time 4.16 seconds
Started Jan 22 04:58:56 PM PST 24
Finished Jan 22 04:59:01 PM PST 24
Peak memory 210484 kb
Host smart-1dde5406-8c9d-4455-b5e7-e2a03cf7f29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690460622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3690460622
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_random.3802204968
Short name T733
Test name
Test status
Simulation time 129536813 ps
CPU time 2.59 seconds
Started Jan 22 04:58:37 PM PST 24
Finished Jan 22 04:58:44 PM PST 24
Peak memory 207372 kb
Host smart-f233af06-e127-432b-aaf0-1feadf6949ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802204968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3802204968
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.4219167722
Short name T93
Test name
Test status
Simulation time 1062970384 ps
CPU time 19.99 seconds
Started Jan 22 04:58:57 PM PST 24
Finished Jan 22 04:59:17 PM PST 24
Peak memory 232436 kb
Host smart-3ca6276a-b14a-439c-af65-b8c08f87a043
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219167722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.4219167722
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1611016833
Short name T256
Test name
Test status
Simulation time 371010946 ps
CPU time 3.89 seconds
Started Jan 22 04:58:37 PM PST 24
Finished Jan 22 04:58:46 PM PST 24
Peak memory 206756 kb
Host smart-fc9b9faa-3795-448a-892a-228bc72e4bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611016833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1611016833
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2185765084
Short name T703
Test name
Test status
Simulation time 201187404 ps
CPU time 3.25 seconds
Started Jan 22 04:58:33 PM PST 24
Finished Jan 22 04:58:37 PM PST 24
Peak memory 206912 kb
Host smart-ae42e143-6858-4375-aded-64ecb87af615
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185765084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2185765084
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.4103629511
Short name T546
Test name
Test status
Simulation time 195152179 ps
CPU time 3.89 seconds
Started Jan 22 04:58:37 PM PST 24
Finished Jan 22 04:58:46 PM PST 24
Peak memory 206680 kb
Host smart-0028bf50-499c-4e73-8aca-e20418e1dcf1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103629511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.4103629511
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1624726873
Short name T950
Test name
Test status
Simulation time 345227737 ps
CPU time 4.35 seconds
Started Jan 22 05:04:55 PM PST 24
Finished Jan 22 05:05:04 PM PST 24
Peak memory 208140 kb
Host smart-a3af3933-67e0-4463-b126-476d2e1a9dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624726873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1624726873
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2202788270
Short name T566
Test name
Test status
Simulation time 41016825 ps
CPU time 2.65 seconds
Started Jan 22 04:58:34 PM PST 24
Finished Jan 22 04:58:37 PM PST 24
Peak memory 208232 kb
Host smart-7ef573a1-97fc-44c9-abc0-47dea1299925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202788270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2202788270
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.839149281
Short name T350
Test name
Test status
Simulation time 98998278 ps
CPU time 5.41 seconds
Started Jan 22 04:59:01 PM PST 24
Finished Jan 22 04:59:07 PM PST 24
Peak memory 207684 kb
Host smart-67bfe293-6868-4567-8480-b917cffd7bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839149281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.839149281
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2660076172
Short name T883
Test name
Test status
Simulation time 143545071 ps
CPU time 3.2 seconds
Started Jan 22 04:59:00 PM PST 24
Finished Jan 22 04:59:04 PM PST 24
Peak memory 210208 kb
Host smart-70281133-207a-4b35-add8-faf7f58297b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660076172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2660076172
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1774520727
Short name T816
Test name
Test status
Simulation time 148939580 ps
CPU time 0.91 seconds
Started Jan 22 05:00:26 PM PST 24
Finished Jan 22 05:00:32 PM PST 24
Peak memory 206008 kb
Host smart-77bfc239-bc14-45ac-b892-49bf8efdba79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774520727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1774520727
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.291263376
Short name T598
Test name
Test status
Simulation time 356919721 ps
CPU time 3.92 seconds
Started Jan 22 05:33:39 PM PST 24
Finished Jan 22 05:33:49 PM PST 24
Peak memory 214288 kb
Host smart-ad96358e-584d-4e9b-9131-4a4643c402c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291263376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.291263376
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.813680681
Short name T232
Test name
Test status
Simulation time 321708319 ps
CPU time 3 seconds
Started Jan 22 05:00:20 PM PST 24
Finished Jan 22 05:00:26 PM PST 24
Peak memory 209964 kb
Host smart-2bc7ae6a-5784-4627-a28e-569a32bf7e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813680681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.813680681
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1937310386
Short name T319
Test name
Test status
Simulation time 480308501 ps
CPU time 5.58 seconds
Started Jan 22 05:19:34 PM PST 24
Finished Jan 22 05:19:40 PM PST 24
Peak memory 219000 kb
Host smart-7a698e24-28b9-4d1e-9d4f-6501705a269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937310386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1937310386
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3701969450
Short name T549
Test name
Test status
Simulation time 62901970 ps
CPU time 3.11 seconds
Started Jan 22 05:38:57 PM PST 24
Finished Jan 22 05:39:09 PM PST 24
Peak memory 209688 kb
Host smart-60800cdf-0688-4263-8ca0-d275a910d8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701969450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3701969450
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload.785638355
Short name T817
Test name
Test status
Simulation time 234994606 ps
CPU time 2.93 seconds
Started Jan 22 05:44:52 PM PST 24
Finished Jan 22 05:44:56 PM PST 24
Peak memory 208868 kb
Host smart-b4e6c3d9-c9d5-42ae-9c91-6d1083acfc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785638355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.785638355
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.673204213
Short name T615
Test name
Test status
Simulation time 355363869 ps
CPU time 4.85 seconds
Started Jan 22 05:46:14 PM PST 24
Finished Jan 22 05:46:21 PM PST 24
Peak memory 208468 kb
Host smart-2295e486-f5ed-419a-8063-d514f400616b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673204213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.673204213
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.111802272
Short name T955
Test name
Test status
Simulation time 282601950 ps
CPU time 4.63 seconds
Started Jan 22 05:29:13 PM PST 24
Finished Jan 22 05:29:18 PM PST 24
Peak memory 206888 kb
Host smart-c712f7f7-4466-4dd0-89c3-91a0e41eff6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111802272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.111802272
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1258599660
Short name T637
Test name
Test status
Simulation time 505161066 ps
CPU time 7.51 seconds
Started Jan 22 05:00:19 PM PST 24
Finished Jan 22 05:00:29 PM PST 24
Peak memory 207876 kb
Host smart-3dca2f2a-1220-437f-8846-8cd85dcd5868
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258599660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1258599660
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.774787007
Short name T677
Test name
Test status
Simulation time 276476021 ps
CPU time 5.45 seconds
Started Jan 22 05:44:09 PM PST 24
Finished Jan 22 05:44:16 PM PST 24
Peak memory 209152 kb
Host smart-efeb64a4-83a9-4fd3-9e5f-74b2ef30a05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774787007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.774787007
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3124442742
Short name T674
Test name
Test status
Simulation time 296499384 ps
CPU time 7.14 seconds
Started Jan 22 05:00:11 PM PST 24
Finished Jan 22 05:00:19 PM PST 24
Peak memory 208304 kb
Host smart-edf36bf1-7d95-4c11-ae4d-2a11063188b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124442742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3124442742
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1794141826
Short name T721
Test name
Test status
Simulation time 155477531 ps
CPU time 4.75 seconds
Started Jan 22 05:00:20 PM PST 24
Finished Jan 22 05:00:27 PM PST 24
Peak memory 222580 kb
Host smart-04a15f42-c001-4596-b6e4-a5506cb072be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794141826 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1794141826
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3745814436
Short name T724
Test name
Test status
Simulation time 519753732 ps
CPU time 4.85 seconds
Started Jan 22 05:00:20 PM PST 24
Finished Jan 22 05:00:27 PM PST 24
Peak memory 206908 kb
Host smart-c58d03f6-254f-412e-87ae-0a55e664be95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745814436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3745814436
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1426198434
Short name T384
Test name
Test status
Simulation time 708610387 ps
CPU time 6.01 seconds
Started Jan 22 05:00:26 PM PST 24
Finished Jan 22 05:00:34 PM PST 24
Peak memory 222308 kb
Host smart-9141ac91-35ac-4877-ab5d-2ad85e6a4b84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426198434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1426198434
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3602338318
Short name T607
Test name
Test status
Simulation time 247913202 ps
CPU time 6.16 seconds
Started Jan 22 05:00:32 PM PST 24
Finished Jan 22 05:00:40 PM PST 24
Peak memory 209352 kb
Host smart-c7699a7c-45ff-4d9a-9c6a-816b84223410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602338318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3602338318
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3219186212
Short name T688
Test name
Test status
Simulation time 141525879 ps
CPU time 6.35 seconds
Started Jan 22 05:00:26 PM PST 24
Finished Jan 22 05:00:34 PM PST 24
Peak memory 214200 kb
Host smart-daa110cb-62c1-4381-8279-5ec4de9a628a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219186212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3219186212
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.288489099
Short name T952
Test name
Test status
Simulation time 388896153 ps
CPU time 3.15 seconds
Started Jan 22 05:00:27 PM PST 24
Finished Jan 22 05:00:35 PM PST 24
Peak memory 209264 kb
Host smart-252c712c-9ae8-4205-9b10-b252e1814559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288489099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.288489099
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3152630519
Short name T191
Test name
Test status
Simulation time 202036884 ps
CPU time 4.9 seconds
Started Jan 22 05:00:26 PM PST 24
Finished Jan 22 05:00:33 PM PST 24
Peak memory 209120 kb
Host smart-c9bc41d5-35f4-48b3-82d8-101141d2ba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152630519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3152630519
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1706516538
Short name T730
Test name
Test status
Simulation time 246711217 ps
CPU time 2.76 seconds
Started Jan 22 05:00:20 PM PST 24
Finished Jan 22 05:00:25 PM PST 24
Peak memory 208416 kb
Host smart-beda7d34-87e3-4d5a-b46f-93387c5fa4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706516538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1706516538
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1906644420
Short name T71
Test name
Test status
Simulation time 1244073007 ps
CPU time 9.07 seconds
Started Jan 22 05:00:26 PM PST 24
Finished Jan 22 05:00:37 PM PST 24
Peak memory 208720 kb
Host smart-d11e4e27-db6d-46ac-8f1e-36e90abb89b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906644420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1906644420
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2129335389
Short name T975
Test name
Test status
Simulation time 992655629 ps
CPU time 8.36 seconds
Started Jan 22 05:00:26 PM PST 24
Finished Jan 22 05:00:40 PM PST 24
Peak memory 207752 kb
Host smart-1d0c2e01-3c5d-4d7a-a9ed-ba0f7dbba1a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129335389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2129335389
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.391160947
Short name T119
Test name
Test status
Simulation time 1590787429 ps
CPU time 30.96 seconds
Started Jan 22 05:00:26 PM PST 24
Finished Jan 22 05:00:58 PM PST 24
Peak memory 217020 kb
Host smart-5d065369-c0d7-481a-81e4-1d9152b28926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391160947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.391160947
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2365161788
Short name T379
Test name
Test status
Simulation time 55595224 ps
CPU time 2.89 seconds
Started Jan 22 05:00:17 PM PST 24
Finished Jan 22 05:00:22 PM PST 24
Peak memory 206764 kb
Host smart-5bf40322-0b26-4e31-afe0-092f7ebcf8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365161788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2365161788
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1658868812
Short name T968
Test name
Test status
Simulation time 977324615 ps
CPU time 4.48 seconds
Started Jan 22 05:00:27 PM PST 24
Finished Jan 22 05:00:37 PM PST 24
Peak memory 222984 kb
Host smart-f99ce0a8-6fdb-495c-b714-f40b4d2a2b8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658868812 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1658868812
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3667335910
Short name T708
Test name
Test status
Simulation time 729649866 ps
CPU time 6.68 seconds
Started Jan 22 05:00:23 PM PST 24
Finished Jan 22 05:00:30 PM PST 24
Peak memory 207888 kb
Host smart-21c0b848-0028-4195-b7d3-4dac3d607e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667335910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3667335910
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.149441688
Short name T791
Test name
Test status
Simulation time 59048406 ps
CPU time 0.81 seconds
Started Jan 22 05:00:44 PM PST 24
Finished Jan 22 05:00:49 PM PST 24
Peak memory 205880 kb
Host smart-7b547f8b-1891-4632-8baa-ec7fb4c43c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149441688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.149441688
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2477297275
Short name T728
Test name
Test status
Simulation time 58622505 ps
CPU time 1.87 seconds
Started Jan 22 05:00:44 PM PST 24
Finished Jan 22 05:00:50 PM PST 24
Peak memory 207964 kb
Host smart-e962932b-6038-4876-8cc6-1ee6dbee5cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477297275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2477297275
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.902979335
Short name T61
Test name
Test status
Simulation time 60913681 ps
CPU time 3.56 seconds
Started Jan 22 05:00:40 PM PST 24
Finished Jan 22 05:00:45 PM PST 24
Peak memory 214232 kb
Host smart-f27b7b6f-a475-486c-9380-d01506683527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902979335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.902979335
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2650953676
Short name T375
Test name
Test status
Simulation time 4087190718 ps
CPU time 32.9 seconds
Started Jan 22 05:00:27 PM PST 24
Finished Jan 22 05:01:05 PM PST 24
Peak memory 222544 kb
Host smart-2032417e-b538-4fbf-80bb-09c4f6d433c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650953676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2650953676
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3865005600
Short name T658
Test name
Test status
Simulation time 826835199 ps
CPU time 19.15 seconds
Started Jan 22 05:00:23 PM PST 24
Finished Jan 22 05:00:43 PM PST 24
Peak memory 208820 kb
Host smart-233357d4-338e-4310-94bc-352febc73e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865005600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3865005600
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1482194244
Short name T597
Test name
Test status
Simulation time 408594496 ps
CPU time 3.93 seconds
Started Jan 22 05:00:25 PM PST 24
Finished Jan 22 05:00:31 PM PST 24
Peak memory 208720 kb
Host smart-6140a15f-a496-4e59-84bb-7da6d4fb547d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482194244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1482194244
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3984014204
Short name T782
Test name
Test status
Simulation time 814913278 ps
CPU time 3.78 seconds
Started Jan 22 05:00:22 PM PST 24
Finished Jan 22 05:00:27 PM PST 24
Peak memory 208464 kb
Host smart-52ea0153-1d47-4ee1-be52-fe34f9603d65
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984014204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3984014204
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.4009396893
Short name T875
Test name
Test status
Simulation time 188608235 ps
CPU time 6.81 seconds
Started Jan 22 05:00:26 PM PST 24
Finished Jan 22 05:00:35 PM PST 24
Peak memory 208520 kb
Host smart-1d233c3a-f260-4711-b7f4-c65f588d7efb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009396893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4009396893
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2635899912
Short name T568
Test name
Test status
Simulation time 81239749 ps
CPU time 1.92 seconds
Started Jan 22 05:00:44 PM PST 24
Finished Jan 22 05:00:50 PM PST 24
Peak memory 215572 kb
Host smart-d26ff063-2b56-4448-a2b8-dd2655a98fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635899912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2635899912
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1062958881
Short name T743
Test name
Test status
Simulation time 944371520 ps
CPU time 7.09 seconds
Started Jan 22 05:00:29 PM PST 24
Finished Jan 22 05:00:40 PM PST 24
Peak memory 206760 kb
Host smart-a9de7d83-38a5-4cc3-819e-bd4b19161684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062958881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1062958881
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.619125165
Short name T901
Test name
Test status
Simulation time 184833367 ps
CPU time 2.98 seconds
Started Jan 22 05:00:45 PM PST 24
Finished Jan 22 05:00:51 PM PST 24
Peak memory 222584 kb
Host smart-cb182496-c57d-4f44-9d2e-9cbcb88a98c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619125165 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.619125165
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1719032091
Short name T198
Test name
Test status
Simulation time 4203688866 ps
CPU time 7.44 seconds
Started Jan 22 05:13:50 PM PST 24
Finished Jan 22 05:14:00 PM PST 24
Peak memory 214396 kb
Host smart-f88e42df-b2e9-4325-84c9-f050f05d33b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719032091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1719032091
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3357969586
Short name T953
Test name
Test status
Simulation time 361835474 ps
CPU time 4.02 seconds
Started Jan 22 05:00:43 PM PST 24
Finished Jan 22 05:00:52 PM PST 24
Peak memory 210332 kb
Host smart-f1959a35-426a-4b7c-8dac-9d4205b37e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357969586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3357969586
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2953164111
Short name T524
Test name
Test status
Simulation time 48610039 ps
CPU time 0.88 seconds
Started Jan 22 05:00:39 PM PST 24
Finished Jan 22 05:00:41 PM PST 24
Peak memory 205864 kb
Host smart-1ddb8f4a-0b12-45e9-8d42-fef3a84cc180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953164111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2953164111
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.337227490
Short name T317
Test name
Test status
Simulation time 162918596 ps
CPU time 3.31 seconds
Started Jan 22 05:00:36 PM PST 24
Finished Jan 22 05:00:41 PM PST 24
Peak memory 215556 kb
Host smart-426227a2-219e-4afd-9da3-8f8914df5a41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337227490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.337227490
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3432026305
Short name T329
Test name
Test status
Simulation time 54343794 ps
CPU time 2.21 seconds
Started Jan 22 05:00:33 PM PST 24
Finished Jan 22 05:00:39 PM PST 24
Peak memory 209556 kb
Host smart-928921da-70a8-4a4e-bb9f-c8c77fc9d448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432026305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3432026305
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3580272872
Short name T189
Test name
Test status
Simulation time 168827411 ps
CPU time 6.78 seconds
Started Jan 22 05:00:35 PM PST 24
Finished Jan 22 05:00:44 PM PST 24
Peak memory 214188 kb
Host smart-bc5e4c5e-4d88-456a-8c8e-6ffb12ae9431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580272872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3580272872
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.914482411
Short name T774
Test name
Test status
Simulation time 161443087 ps
CPU time 3.59 seconds
Started Jan 22 05:00:32 PM PST 24
Finished Jan 22 05:00:37 PM PST 24
Peak memory 214816 kb
Host smart-9a870417-c0c6-4a8b-8b5a-e806115fdab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914482411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.914482411
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2476495692
Short name T594
Test name
Test status
Simulation time 536413582 ps
CPU time 7.85 seconds
Started Jan 22 05:00:37 PM PST 24
Finished Jan 22 05:00:46 PM PST 24
Peak memory 209568 kb
Host smart-e9a95cf4-4e88-4684-a0a1-a6463dd27b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476495692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2476495692
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.576082263
Short name T1046
Test name
Test status
Simulation time 137045989 ps
CPU time 3.35 seconds
Started Jan 22 05:00:41 PM PST 24
Finished Jan 22 05:00:45 PM PST 24
Peak memory 208520 kb
Host smart-bb4b0a29-a788-46eb-95f9-71aea2fa8593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576082263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.576082263
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1633079017
Short name T630
Test name
Test status
Simulation time 354242077 ps
CPU time 4.25 seconds
Started Jan 22 05:00:33 PM PST 24
Finished Jan 22 05:00:41 PM PST 24
Peak memory 207016 kb
Host smart-09011cd4-acde-42ca-846d-eb5a5c9219ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633079017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1633079017
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3147854308
Short name T125
Test name
Test status
Simulation time 328982030 ps
CPU time 2.54 seconds
Started Jan 22 05:00:36 PM PST 24
Finished Jan 22 05:00:40 PM PST 24
Peak memory 207152 kb
Host smart-f35496fd-5a8c-43be-af94-99a2cff7a963
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147854308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3147854308
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3618459764
Short name T378
Test name
Test status
Simulation time 166625914 ps
CPU time 2.53 seconds
Started Jan 22 05:00:42 PM PST 24
Finished Jan 22 05:00:50 PM PST 24
Peak memory 208848 kb
Host smart-5a2bc622-0a30-4e78-a015-df2997df15cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618459764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3618459764
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.562452752
Short name T810
Test name
Test status
Simulation time 74635322 ps
CPU time 3.39 seconds
Started Jan 22 05:00:41 PM PST 24
Finished Jan 22 05:00:45 PM PST 24
Peak memory 207988 kb
Host smart-891ad143-2b4d-4376-b773-a0aff9be6c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562452752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.562452752
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2218281793
Short name T541
Test name
Test status
Simulation time 91985354 ps
CPU time 1.95 seconds
Started Jan 22 05:00:38 PM PST 24
Finished Jan 22 05:00:40 PM PST 24
Peak memory 206752 kb
Host smart-1f08b325-c513-490a-82a7-fa32155cf855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218281793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2218281793
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2770687069
Short name T900
Test name
Test status
Simulation time 214487995 ps
CPU time 7.02 seconds
Started Jan 22 05:00:41 PM PST 24
Finished Jan 22 05:00:53 PM PST 24
Peak memory 222596 kb
Host smart-edad7d05-0208-4aeb-ba7f-6d7b9962d90b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770687069 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2770687069
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3339100268
Short name T1001
Test name
Test status
Simulation time 124337994 ps
CPU time 4.87 seconds
Started Jan 22 05:00:33 PM PST 24
Finished Jan 22 05:00:41 PM PST 24
Peak memory 207492 kb
Host smart-3d8ec68a-fe95-450e-9535-6a51dc68fde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339100268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3339100268
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.359206127
Short name T696
Test name
Test status
Simulation time 104289921 ps
CPU time 3.16 seconds
Started Jan 22 05:00:39 PM PST 24
Finished Jan 22 05:00:44 PM PST 24
Peak memory 210356 kb
Host smart-28db517c-ba81-43eb-a8e4-23b627554743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359206127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.359206127
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1656139585
Short name T1055
Test name
Test status
Simulation time 42708919 ps
CPU time 0.9 seconds
Started Jan 22 05:00:43 PM PST 24
Finished Jan 22 05:00:49 PM PST 24
Peak memory 205476 kb
Host smart-b3e9acdc-ec75-419e-9bb5-10db2046df22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656139585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1656139585
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2948764096
Short name T1017
Test name
Test status
Simulation time 694149125 ps
CPU time 18.04 seconds
Started Jan 22 05:00:42 PM PST 24
Finished Jan 22 05:01:06 PM PST 24
Peak memory 215464 kb
Host smart-16c17497-2973-49d6-9e9c-b6f3694a2bb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948764096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2948764096
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1274684485
Short name T829
Test name
Test status
Simulation time 163452248 ps
CPU time 7.01 seconds
Started Jan 22 05:00:41 PM PST 24
Finished Jan 22 05:00:53 PM PST 24
Peak memory 210516 kb
Host smart-3b9e0d39-cd37-4987-8e99-3db0c072c2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274684485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1274684485
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2447414346
Short name T618
Test name
Test status
Simulation time 971005949 ps
CPU time 6.3 seconds
Started Jan 22 05:00:39 PM PST 24
Finished Jan 22 05:00:47 PM PST 24
Peak memory 207960 kb
Host smart-30a6d17a-f232-4948-ab9d-c2aea8de505d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447414346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2447414346
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.79385851
Short name T958
Test name
Test status
Simulation time 276250018 ps
CPU time 5.06 seconds
Started Jan 22 05:00:42 PM PST 24
Finished Jan 22 05:00:52 PM PST 24
Peak memory 219800 kb
Host smart-07781645-9157-4874-b160-f4e44129cc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79385851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.79385851
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3225559962
Short name T991
Test name
Test status
Simulation time 96721536 ps
CPU time 4.99 seconds
Started Jan 22 05:00:44 PM PST 24
Finished Jan 22 05:00:53 PM PST 24
Peak memory 209776 kb
Host smart-94ef01b6-e173-4c2d-8dfd-9809850b4387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225559962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3225559962
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.152222694
Short name T275
Test name
Test status
Simulation time 52525626 ps
CPU time 3.1 seconds
Started Jan 22 05:00:42 PM PST 24
Finished Jan 22 05:00:49 PM PST 24
Peak memory 214268 kb
Host smart-382d648a-63df-41b3-bf2f-a443f5e50adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152222694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.152222694
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3434660659
Short name T1023
Test name
Test status
Simulation time 176579288 ps
CPU time 5.33 seconds
Started Jan 22 05:00:42 PM PST 24
Finished Jan 22 05:00:53 PM PST 24
Peak memory 218340 kb
Host smart-0b826f9a-cf27-431e-bb55-7cf12329d7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434660659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3434660659
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3376755292
Short name T606
Test name
Test status
Simulation time 412977783 ps
CPU time 4.29 seconds
Started Jan 22 05:00:38 PM PST 24
Finished Jan 22 05:00:43 PM PST 24
Peak memory 207744 kb
Host smart-f435f8f6-13f1-4645-bc06-7b26964c9eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376755292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3376755292
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.578331460
Short name T963
Test name
Test status
Simulation time 100893126 ps
CPU time 2.85 seconds
Started Jan 22 05:00:39 PM PST 24
Finished Jan 22 05:00:44 PM PST 24
Peak memory 206792 kb
Host smart-128c2c58-3196-43a4-b22c-e1c570a78699
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578331460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.578331460
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2314125156
Short name T717
Test name
Test status
Simulation time 221167387 ps
CPU time 3.09 seconds
Started Jan 22 05:00:37 PM PST 24
Finished Jan 22 05:00:41 PM PST 24
Peak memory 208756 kb
Host smart-410f9e62-4a3d-4d84-906b-e43d70c3a349
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314125156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2314125156
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2086889478
Short name T576
Test name
Test status
Simulation time 2652298171 ps
CPU time 6 seconds
Started Jan 22 05:00:38 PM PST 24
Finished Jan 22 05:00:45 PM PST 24
Peak memory 208056 kb
Host smart-7bafe2ee-18d5-441c-9e71-e4d00b52c891
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086889478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2086889478
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3352264104
Short name T990
Test name
Test status
Simulation time 134696723 ps
CPU time 3.01 seconds
Started Jan 22 05:00:42 PM PST 24
Finished Jan 22 05:00:51 PM PST 24
Peak memory 209596 kb
Host smart-67273790-4aeb-4b6e-9eca-46c626ea6d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352264104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3352264104
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.377239859
Short name T848
Test name
Test status
Simulation time 792580902 ps
CPU time 2.87 seconds
Started Jan 22 05:00:41 PM PST 24
Finished Jan 22 05:00:49 PM PST 24
Peak memory 208416 kb
Host smart-b42e5dc1-882e-498a-8886-1a565de0e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377239859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.377239859
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3541172779
Short name T672
Test name
Test status
Simulation time 98531872 ps
CPU time 3.37 seconds
Started Jan 22 05:00:45 PM PST 24
Finished Jan 22 05:00:51 PM PST 24
Peak memory 222508 kb
Host smart-ca12ecde-d258-46f9-8309-ee12f78e5264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541172779 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3541172779
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2653889588
Short name T656
Test name
Test status
Simulation time 223720530 ps
CPU time 6.48 seconds
Started Jan 22 05:00:43 PM PST 24
Finished Jan 22 05:00:54 PM PST 24
Peak memory 207964 kb
Host smart-efcdff3c-abd6-4f01-93ef-850b659303b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653889588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2653889588
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3460640092
Short name T822
Test name
Test status
Simulation time 103418257 ps
CPU time 2.52 seconds
Started Jan 22 05:00:42 PM PST 24
Finished Jan 22 05:00:50 PM PST 24
Peak memory 209564 kb
Host smart-a0773779-1f17-4cb0-a206-983b80512714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460640092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3460640092
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.279996381
Short name T99
Test name
Test status
Simulation time 42943793 ps
CPU time 0.85 seconds
Started Jan 22 05:00:54 PM PST 24
Finished Jan 22 05:00:55 PM PST 24
Peak memory 205816 kb
Host smart-f907a87a-d8b9-45bd-be8e-b62500592dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279996381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.279996381
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2754827584
Short name T922
Test name
Test status
Simulation time 462976765 ps
CPU time 10.06 seconds
Started Jan 22 05:00:52 PM PST 24
Finished Jan 22 05:01:03 PM PST 24
Peak memory 209632 kb
Host smart-d1e39402-674c-4acf-a71b-0472f4f6d497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754827584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2754827584
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3957384282
Short name T62
Test name
Test status
Simulation time 249057020 ps
CPU time 5.44 seconds
Started Jan 22 05:00:48 PM PST 24
Finished Jan 22 05:00:57 PM PST 24
Peak memory 207472 kb
Host smart-a03acf0a-db30-4d1e-81a6-b62d14c11d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957384282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3957384282
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.738434068
Short name T545
Test name
Test status
Simulation time 231163287 ps
CPU time 4.65 seconds
Started Jan 22 05:00:54 PM PST 24
Finished Jan 22 05:01:00 PM PST 24
Peak memory 208784 kb
Host smart-812b0c3a-fd7c-48bb-80d7-a524dccd5343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738434068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.738434068
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.736116714
Short name T47
Test name
Test status
Simulation time 299432036 ps
CPU time 7.35 seconds
Started Jan 22 05:00:57 PM PST 24
Finished Jan 22 05:01:05 PM PST 24
Peak memory 209756 kb
Host smart-390c3649-9546-4dfc-b0fe-5f334aaf0dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736116714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.736116714
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3475402885
Short name T718
Test name
Test status
Simulation time 120308996 ps
CPU time 3.5 seconds
Started Jan 22 05:21:55 PM PST 24
Finished Jan 22 05:22:04 PM PST 24
Peak memory 215204 kb
Host smart-aa9146ff-df84-46e9-8a9b-0e278c36fb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475402885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3475402885
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3054122146
Short name T828
Test name
Test status
Simulation time 2955684937 ps
CPU time 42.48 seconds
Started Jan 22 05:00:53 PM PST 24
Finished Jan 22 05:01:37 PM PST 24
Peak memory 209008 kb
Host smart-d4c752f5-57ba-4b6c-a1b2-607d4ab34503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054122146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3054122146
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3673480459
Short name T710
Test name
Test status
Simulation time 2294038875 ps
CPU time 46.3 seconds
Started Jan 22 05:00:53 PM PST 24
Finished Jan 22 05:01:40 PM PST 24
Peak memory 208936 kb
Host smart-0be3f450-5e65-4cca-b02c-408da1b7fe35
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673480459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3673480459
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1481624702
Short name T984
Test name
Test status
Simulation time 233534981 ps
CPU time 6.34 seconds
Started Jan 22 05:00:51 PM PST 24
Finished Jan 22 05:00:58 PM PST 24
Peak memory 208480 kb
Host smart-7fcf62f8-5f72-4c2a-bcb4-dc1e3d4574e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481624702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1481624702
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.951311039
Short name T288
Test name
Test status
Simulation time 62699973 ps
CPU time 2.97 seconds
Started Jan 22 05:00:58 PM PST 24
Finished Jan 22 05:01:01 PM PST 24
Peak memory 215632 kb
Host smart-c4758d53-e2f0-4329-9ed6-78332d510dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951311039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.951311039
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2188453173
Short name T1045
Test name
Test status
Simulation time 70676187 ps
CPU time 1.7 seconds
Started Jan 22 05:15:22 PM PST 24
Finished Jan 22 05:15:25 PM PST 24
Peak memory 206868 kb
Host smart-6600bc35-82a5-4540-99f8-f02d1ce744d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188453173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2188453173
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.906948341
Short name T820
Test name
Test status
Simulation time 163606741 ps
CPU time 8.73 seconds
Started Jan 22 05:00:55 PM PST 24
Finished Jan 22 05:01:04 PM PST 24
Peak memory 220968 kb
Host smart-9bd5dfd4-6146-4050-8654-20f3608fe186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906948341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.906948341
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.284575614
Short name T16
Test name
Test status
Simulation time 165065560 ps
CPU time 2.05 seconds
Started Jan 22 05:01:00 PM PST 24
Finished Jan 22 05:01:03 PM PST 24
Peak memory 222556 kb
Host smart-0e32fab6-d7b8-44e5-a7c7-0637f8213adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284575614 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.284575614
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1199648800
Short name T979
Test name
Test status
Simulation time 408251373 ps
CPU time 5.01 seconds
Started Jan 22 05:15:18 PM PST 24
Finished Jan 22 05:15:24 PM PST 24
Peak memory 208924 kb
Host smart-96ebd3f5-0a76-4b65-858a-93fa66eb5693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199648800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1199648800
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1668981597
Short name T916
Test name
Test status
Simulation time 247512222 ps
CPU time 2.18 seconds
Started Jan 22 05:00:53 PM PST 24
Finished Jan 22 05:00:56 PM PST 24
Peak memory 210180 kb
Host smart-7254dd39-324f-497b-8199-ae1a5ea15a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668981597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1668981597
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4008595105
Short name T884
Test name
Test status
Simulation time 11384981 ps
CPU time 0.89 seconds
Started Jan 22 05:22:42 PM PST 24
Finished Jan 22 05:22:44 PM PST 24
Peak memory 205808 kb
Host smart-27f3ef87-0f9b-4304-9c3f-f9735699aec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008595105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4008595105
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.4232874058
Short name T230
Test name
Test status
Simulation time 267920528 ps
CPU time 14.12 seconds
Started Jan 22 05:00:57 PM PST 24
Finished Jan 22 05:01:12 PM PST 24
Peak memory 214992 kb
Host smart-fb92df4c-728f-43f3-a7c5-ede78eff96d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232874058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.4232874058
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.739509172
Short name T919
Test name
Test status
Simulation time 59050275 ps
CPU time 2.27 seconds
Started Jan 22 05:00:55 PM PST 24
Finished Jan 22 05:00:57 PM PST 24
Peak memory 208080 kb
Host smart-0df299c7-385b-431b-952b-337677972a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739509172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.739509172
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.570766520
Short name T913
Test name
Test status
Simulation time 206834553 ps
CPU time 4.29 seconds
Started Jan 22 05:00:57 PM PST 24
Finished Jan 22 05:01:02 PM PST 24
Peak memory 219588 kb
Host smart-973f298f-47dc-4b6b-b094-be2c232c8f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570766520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.570766520
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1807887906
Short name T1053
Test name
Test status
Simulation time 331825201 ps
CPU time 4.63 seconds
Started Jan 22 05:11:23 PM PST 24
Finished Jan 22 05:11:30 PM PST 24
Peak memory 218536 kb
Host smart-41f8f8a7-e2a3-4893-af96-d48a43967631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807887906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1807887906
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.914296764
Short name T122
Test name
Test status
Simulation time 69653824 ps
CPU time 4.16 seconds
Started Jan 22 05:00:55 PM PST 24
Finished Jan 22 05:00:59 PM PST 24
Peak memory 218432 kb
Host smart-72280142-edd7-41fd-9857-f5b3611e9711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914296764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.914296764
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2758944030
Short name T843
Test name
Test status
Simulation time 133620880 ps
CPU time 4.35 seconds
Started Jan 22 05:47:37 PM PST 24
Finished Jan 22 05:47:44 PM PST 24
Peak memory 208504 kb
Host smart-ebc89be4-e474-4682-ba54-548c98590bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758944030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2758944030
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3337521342
Short name T667
Test name
Test status
Simulation time 920768431 ps
CPU time 10.39 seconds
Started Jan 22 05:05:37 PM PST 24
Finished Jan 22 05:05:48 PM PST 24
Peak memory 206840 kb
Host smart-0b7ff109-dac5-4ec2-aba5-643547c0921a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337521342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3337521342
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1003652187
Short name T772
Test name
Test status
Simulation time 202008808 ps
CPU time 2.91 seconds
Started Jan 22 05:53:45 PM PST 24
Finished Jan 22 05:53:50 PM PST 24
Peak memory 206948 kb
Host smart-fcafea1d-0e73-401c-8c10-f2f094e1a807
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003652187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1003652187
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2655857786
Short name T886
Test name
Test status
Simulation time 1299768600 ps
CPU time 34.3 seconds
Started Jan 22 05:00:57 PM PST 24
Finished Jan 22 05:01:32 PM PST 24
Peak memory 208004 kb
Host smart-254fbbaa-e9a6-47b6-add6-c5ac631f7454
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655857786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2655857786
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2090938384
Short name T894
Test name
Test status
Simulation time 1837112731 ps
CPU time 22.87 seconds
Started Jan 22 05:12:24 PM PST 24
Finished Jan 22 05:12:47 PM PST 24
Peak memory 208504 kb
Host smart-d0130586-0698-4029-a217-62ebc63f30ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090938384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2090938384
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1978503447
Short name T645
Test name
Test status
Simulation time 606150720 ps
CPU time 10.19 seconds
Started Jan 22 05:31:14 PM PST 24
Finished Jan 22 05:31:25 PM PST 24
Peak memory 207932 kb
Host smart-c96b298b-e968-481b-8c66-f722e47c6b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978503447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1978503447
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1943402446
Short name T821
Test name
Test status
Simulation time 741383639 ps
CPU time 9.51 seconds
Started Jan 22 05:01:04 PM PST 24
Finished Jan 22 05:01:15 PM PST 24
Peak memory 222660 kb
Host smart-6d0d8891-5858-4455-a08c-d67fa0cf5396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943402446 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1943402446
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.308428587
Short name T328
Test name
Test status
Simulation time 226784527 ps
CPU time 5.58 seconds
Started Jan 22 05:00:57 PM PST 24
Finished Jan 22 05:01:04 PM PST 24
Peak memory 218228 kb
Host smart-3e420e80-1fde-428e-b14c-e4c64ef54705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308428587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.308428587
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.568639577
Short name T669
Test name
Test status
Simulation time 117792194 ps
CPU time 2.85 seconds
Started Jan 22 05:01:08 PM PST 24
Finished Jan 22 05:01:12 PM PST 24
Peak memory 210148 kb
Host smart-b811915d-ddf8-405c-ae5c-c61dccc176aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568639577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.568639577
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1269345583
Short name T680
Test name
Test status
Simulation time 15011332 ps
CPU time 0.82 seconds
Started Jan 22 05:38:12 PM PST 24
Finished Jan 22 05:38:13 PM PST 24
Peak memory 205844 kb
Host smart-ef991ab2-c932-494b-853e-f98727980963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269345583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1269345583
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3997293848
Short name T879
Test name
Test status
Simulation time 882088580 ps
CPU time 22.85 seconds
Started Jan 22 05:01:19 PM PST 24
Finished Jan 22 05:01:43 PM PST 24
Peak memory 212536 kb
Host smart-79108504-1020-45a8-90de-b4fcaedfa557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997293848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3997293848
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1390306871
Short name T51
Test name
Test status
Simulation time 91614113 ps
CPU time 1.81 seconds
Started Jan 22 05:01:16 PM PST 24
Finished Jan 22 05:01:18 PM PST 24
Peak memory 207576 kb
Host smart-1194189b-3142-43a3-9e17-c878be00f076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390306871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1390306871
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2333715085
Short name T785
Test name
Test status
Simulation time 183028450 ps
CPU time 5.66 seconds
Started Jan 22 05:23:09 PM PST 24
Finished Jan 22 05:23:15 PM PST 24
Peak memory 208952 kb
Host smart-e15b0182-27ab-49d7-96bf-0066b8babcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333715085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2333715085
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2663992608
Short name T334
Test name
Test status
Simulation time 133334116 ps
CPU time 5.64 seconds
Started Jan 22 05:01:18 PM PST 24
Finished Jan 22 05:01:24 PM PST 24
Peak memory 222368 kb
Host smart-4ece7469-db3f-4608-bca9-c0069be38107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663992608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2663992608
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.559223353
Short name T871
Test name
Test status
Simulation time 117031540 ps
CPU time 3.64 seconds
Started Jan 22 05:01:13 PM PST 24
Finished Jan 22 05:01:18 PM PST 24
Peak memory 214184 kb
Host smart-2e447917-3afb-4a9a-ba37-564083037cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559223353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.559223353
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1696075290
Short name T346
Test name
Test status
Simulation time 114968055 ps
CPU time 4.04 seconds
Started Jan 22 05:01:16 PM PST 24
Finished Jan 22 05:01:21 PM PST 24
Peak memory 207992 kb
Host smart-a81f8d7f-c095-49c1-a7d7-a2ea9d6acb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696075290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1696075290
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2625015852
Short name T531
Test name
Test status
Simulation time 326621032 ps
CPU time 3.29 seconds
Started Jan 22 05:01:09 PM PST 24
Finished Jan 22 05:01:13 PM PST 24
Peak memory 206888 kb
Host smart-71c6adf6-f3ac-4395-bdeb-53501286e106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625015852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2625015852
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.4201107126
Short name T200
Test name
Test status
Simulation time 79889716 ps
CPU time 3.7 seconds
Started Jan 22 05:01:13 PM PST 24
Finished Jan 22 05:01:18 PM PST 24
Peak memory 208960 kb
Host smart-aca7c200-dafd-4388-852f-8df2b8d3c9ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201107126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.4201107126
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3678646776
Short name T823
Test name
Test status
Simulation time 40271285 ps
CPU time 2.62 seconds
Started Jan 22 05:01:07 PM PST 24
Finished Jan 22 05:01:10 PM PST 24
Peak memory 206896 kb
Host smart-37ae35d0-1134-4e3a-ad0a-3d890970bb21
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678646776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3678646776
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2448860787
Short name T654
Test name
Test status
Simulation time 24213170 ps
CPU time 1.82 seconds
Started Jan 22 05:30:57 PM PST 24
Finished Jan 22 05:31:00 PM PST 24
Peak memory 207100 kb
Host smart-0c08ebf5-411c-4dd6-9754-5639313a894e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448860787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2448860787
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2874157489
Short name T539
Test name
Test status
Simulation time 414824486 ps
CPU time 6.07 seconds
Started Jan 22 05:01:10 PM PST 24
Finished Jan 22 05:01:17 PM PST 24
Peak memory 209720 kb
Host smart-d9a5bc90-97e7-4df0-9087-3bbe04aba5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874157489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2874157489
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2494022109
Short name T36
Test name
Test status
Simulation time 1126989348 ps
CPU time 2.97 seconds
Started Jan 22 05:01:16 PM PST 24
Finished Jan 22 05:01:20 PM PST 24
Peak memory 210152 kb
Host smart-825f9fcd-c6e1-4073-8e4b-be98ebba8dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494022109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2494022109
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1961749231
Short name T535
Test name
Test status
Simulation time 44113763 ps
CPU time 0.77 seconds
Started Jan 22 05:01:30 PM PST 24
Finished Jan 22 05:01:31 PM PST 24
Peak memory 205872 kb
Host smart-71db27cd-8eed-4613-bfba-331eb9001792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961749231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1961749231
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.387505386
Short name T385
Test name
Test status
Simulation time 696721431 ps
CPU time 19.28 seconds
Started Jan 22 05:01:28 PM PST 24
Finished Jan 22 05:01:48 PM PST 24
Peak memory 214216 kb
Host smart-906e65cd-01db-43bc-912e-a3c2c8b7a937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387505386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.387505386
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1183012687
Short name T231
Test name
Test status
Simulation time 92766765 ps
CPU time 1.72 seconds
Started Jan 22 05:01:28 PM PST 24
Finished Jan 22 05:01:30 PM PST 24
Peak memory 207780 kb
Host smart-c8eaf824-a57a-4efa-a01c-3c06feb1e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183012687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1183012687
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.45731795
Short name T611
Test name
Test status
Simulation time 1208881347 ps
CPU time 28.38 seconds
Started Jan 22 05:01:24 PM PST 24
Finished Jan 22 05:01:53 PM PST 24
Peak memory 214316 kb
Host smart-986045e9-3f07-49eb-87d3-403291217f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45731795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.45731795
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1827946908
Short name T234
Test name
Test status
Simulation time 248760120 ps
CPU time 7.18 seconds
Started Jan 22 05:01:27 PM PST 24
Finished Jan 22 05:01:35 PM PST 24
Peak memory 214284 kb
Host smart-830cb0cc-c994-4175-bc8f-65bca3ddf448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827946908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1827946908
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4060577096
Short name T640
Test name
Test status
Simulation time 36047025 ps
CPU time 1.77 seconds
Started Jan 22 05:01:31 PM PST 24
Finished Jan 22 05:01:33 PM PST 24
Peak memory 214328 kb
Host smart-5f5c9910-34ed-4d08-a591-8b10b707ad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060577096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4060577096
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2952491980
Short name T794
Test name
Test status
Simulation time 116436236 ps
CPU time 5.02 seconds
Started Jan 22 06:04:14 PM PST 24
Finished Jan 22 06:04:23 PM PST 24
Peak memory 208056 kb
Host smart-4d933cda-57bb-4451-ba68-7cbf053e0658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952491980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2952491980
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.106456140
Short name T807
Test name
Test status
Simulation time 218012608 ps
CPU time 3.72 seconds
Started Jan 22 05:01:10 PM PST 24
Finished Jan 22 05:01:15 PM PST 24
Peak memory 208756 kb
Host smart-66c49522-c35d-4dd5-82cd-33a5bbf95d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106456140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.106456140
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.66848724
Short name T893
Test name
Test status
Simulation time 43955208 ps
CPU time 2.49 seconds
Started Jan 22 05:01:28 PM PST 24
Finished Jan 22 05:01:31 PM PST 24
Peak memory 208356 kb
Host smart-b3a3fc23-37b4-4189-9da4-26cbead6d52c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66848724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.66848724
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2278512399
Short name T604
Test name
Test status
Simulation time 118067549 ps
CPU time 2.64 seconds
Started Jan 22 05:01:13 PM PST 24
Finished Jan 22 05:01:16 PM PST 24
Peak memory 206864 kb
Host smart-2ac552ae-33c7-4a51-a7a8-8b5e0fa9627e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278512399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2278512399
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2290149274
Short name T995
Test name
Test status
Simulation time 90408176 ps
CPU time 2.17 seconds
Started Jan 22 05:01:31 PM PST 24
Finished Jan 22 05:01:33 PM PST 24
Peak memory 208504 kb
Host smart-43849c8d-0777-4065-89fd-676d8ca8c872
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290149274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2290149274
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2635467015
Short name T854
Test name
Test status
Simulation time 867009248 ps
CPU time 18.84 seconds
Started Jan 22 05:01:28 PM PST 24
Finished Jan 22 05:01:47 PM PST 24
Peak memory 209156 kb
Host smart-7e878858-3bc2-4692-9591-f6cf1db50cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635467015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2635467015
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1301118189
Short name T695
Test name
Test status
Simulation time 97024076 ps
CPU time 2.74 seconds
Started Jan 22 05:27:37 PM PST 24
Finished Jan 22 05:27:40 PM PST 24
Peak memory 206688 kb
Host smart-c01d85e3-db61-45be-b752-3eea25655b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301118189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1301118189
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3694394469
Short name T182
Test name
Test status
Simulation time 2230751083 ps
CPU time 49.88 seconds
Started Jan 22 05:01:29 PM PST 24
Finished Jan 22 05:02:19 PM PST 24
Peak memory 216212 kb
Host smart-ee0d6786-20de-4f79-bcae-5ba5b6811f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694394469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3694394469
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1341492983
Short name T210
Test name
Test status
Simulation time 161518130 ps
CPU time 7.26 seconds
Started Jan 22 05:01:27 PM PST 24
Finished Jan 22 05:01:35 PM PST 24
Peak memory 222508 kb
Host smart-427c5395-7a05-453b-9837-d9d1f2dc998a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341492983 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1341492983
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.523151427
Short name T904
Test name
Test status
Simulation time 4978756914 ps
CPU time 94.65 seconds
Started Jan 22 05:01:24 PM PST 24
Finished Jan 22 05:03:00 PM PST 24
Peak memory 209496 kb
Host smart-7faa772e-9514-4e34-aeb7-21c98e1834a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523151427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.523151427
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1026678655
Short name T55
Test name
Test status
Simulation time 11260435768 ps
CPU time 18.35 seconds
Started Jan 22 05:01:31 PM PST 24
Finished Jan 22 05:01:50 PM PST 24
Peak memory 211664 kb
Host smart-9dc155eb-f284-4bce-99b2-e9182c946505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026678655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1026678655
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3908893491
Short name T1024
Test name
Test status
Simulation time 13659985 ps
CPU time 0.98 seconds
Started Jan 22 05:01:40 PM PST 24
Finished Jan 22 05:01:41 PM PST 24
Peak memory 206036 kb
Host smart-cdfa90bd-cf47-4e91-b5fb-df539413179b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908893491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3908893491
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.919337333
Short name T1006
Test name
Test status
Simulation time 53338343 ps
CPU time 3.63 seconds
Started Jan 22 05:01:42 PM PST 24
Finished Jan 22 05:01:46 PM PST 24
Peak memory 209388 kb
Host smart-50eb7a7c-7ddf-460c-9423-8a2fb4bec290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919337333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.919337333
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1188491041
Short name T834
Test name
Test status
Simulation time 866238436 ps
CPU time 10.94 seconds
Started Jan 22 05:01:36 PM PST 24
Finished Jan 22 05:01:47 PM PST 24
Peak memory 208180 kb
Host smart-5e2009d2-be3d-4f5d-ba08-35d174d80c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188491041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1188491041
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.193872927
Short name T929
Test name
Test status
Simulation time 37542465 ps
CPU time 2.56 seconds
Started Jan 22 05:01:35 PM PST 24
Finished Jan 22 05:01:38 PM PST 24
Peak memory 208840 kb
Host smart-27d28749-783f-4792-bf55-fc572280b392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193872927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.193872927
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3268932350
Short name T779
Test name
Test status
Simulation time 71419093 ps
CPU time 4.4 seconds
Started Jan 22 05:01:36 PM PST 24
Finished Jan 22 05:01:41 PM PST 24
Peak memory 214248 kb
Host smart-52d50f50-5334-4f6c-9ff6-405fdb992b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268932350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3268932350
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1571222697
Short name T683
Test name
Test status
Simulation time 900855437 ps
CPU time 10.27 seconds
Started Jan 22 05:01:26 PM PST 24
Finished Jan 22 05:01:37 PM PST 24
Peak memory 208316 kb
Host smart-e8811241-6df1-4a9c-b889-f8c303f180a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571222697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1571222697
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2168075253
Short name T970
Test name
Test status
Simulation time 261561170 ps
CPU time 3.71 seconds
Started Jan 22 05:01:30 PM PST 24
Finished Jan 22 05:01:34 PM PST 24
Peak memory 208652 kb
Host smart-402d8e21-3eec-45c7-9ad5-c0571827fc79
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168075253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2168075253
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3715454491
Short name T555
Test name
Test status
Simulation time 156660052 ps
CPU time 2.89 seconds
Started Jan 22 05:01:29 PM PST 24
Finished Jan 22 05:01:32 PM PST 24
Peak memory 208416 kb
Host smart-732075ae-bf40-40a7-8d7f-3d612a29a972
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715454491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3715454491
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.939856048
Short name T935
Test name
Test status
Simulation time 353928127 ps
CPU time 7.25 seconds
Started Jan 22 05:01:44 PM PST 24
Finished Jan 22 05:01:52 PM PST 24
Peak memory 207932 kb
Host smart-229caaf7-f4ee-4d7f-bf6b-76944e7184f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939856048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.939856048
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2709113474
Short name T563
Test name
Test status
Simulation time 294441101 ps
CPU time 1.64 seconds
Started Jan 22 05:01:40 PM PST 24
Finished Jan 22 05:01:42 PM PST 24
Peak memory 209840 kb
Host smart-0889be87-8ff6-4f17-9843-e084d35a7f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709113474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2709113474
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1400469089
Short name T731
Test name
Test status
Simulation time 169213868 ps
CPU time 5.72 seconds
Started Jan 22 05:01:31 PM PST 24
Finished Jan 22 05:01:37 PM PST 24
Peak memory 208008 kb
Host smart-2dcdc1ff-7669-4fab-b74a-7f32f8ad3553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400469089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1400469089
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3764349438
Short name T293
Test name
Test status
Simulation time 2126470274 ps
CPU time 37.03 seconds
Started Jan 22 05:01:37 PM PST 24
Finished Jan 22 05:02:15 PM PST 24
Peak memory 215220 kb
Host smart-621d4c35-9968-40cd-9df0-619b4f24666f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764349438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3764349438
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3293229573
Short name T377
Test name
Test status
Simulation time 258245079 ps
CPU time 6.37 seconds
Started Jan 22 05:01:40 PM PST 24
Finished Jan 22 05:01:47 PM PST 24
Peak memory 223636 kb
Host smart-6af6568e-9d96-43bc-97b3-dbca82cdf825
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293229573 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3293229573
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2704764378
Short name T600
Test name
Test status
Simulation time 92962276 ps
CPU time 4.77 seconds
Started Jan 22 05:01:40 PM PST 24
Finished Jan 22 05:01:46 PM PST 24
Peak memory 206596 kb
Host smart-e5d2a14c-a443-4c8e-aa33-25b3d97506ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704764378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2704764378
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1284697079
Short name T956
Test name
Test status
Simulation time 58515338 ps
CPU time 2.76 seconds
Started Jan 22 05:01:40 PM PST 24
Finished Jan 22 05:01:44 PM PST 24
Peak memory 208892 kb
Host smart-c8d38ff8-a402-43d8-a377-37577f0e9bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284697079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1284697079
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3001922147
Short name T749
Test name
Test status
Simulation time 44226955 ps
CPU time 0.78 seconds
Started Jan 22 04:59:17 PM PST 24
Finished Jan 22 04:59:18 PM PST 24
Peak memory 205868 kb
Host smart-a4be220a-f319-4457-820a-8eb9afd1d530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001922147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3001922147
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1206974157
Short name T272
Test name
Test status
Simulation time 140359372 ps
CPU time 2.86 seconds
Started Jan 22 05:42:14 PM PST 24
Finished Jan 22 05:42:18 PM PST 24
Peak memory 214304 kb
Host smart-024222a6-eb24-449b-928d-a3ac7d7b7870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1206974157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1206974157
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3569879606
Short name T337
Test name
Test status
Simulation time 165425113 ps
CPU time 5.16 seconds
Started Jan 22 04:59:04 PM PST 24
Finished Jan 22 04:59:09 PM PST 24
Peak memory 209780 kb
Host smart-e7edbf84-e1ed-4e70-ad4a-6150d3f75ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569879606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3569879606
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3627152590
Short name T235
Test name
Test status
Simulation time 171366723 ps
CPU time 5.12 seconds
Started Jan 22 04:59:03 PM PST 24
Finished Jan 22 04:59:09 PM PST 24
Peak memory 214200 kb
Host smart-1417994c-1220-4413-9eb4-1d3dc293c6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627152590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3627152590
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1875658084
Short name T925
Test name
Test status
Simulation time 59968777 ps
CPU time 3.94 seconds
Started Jan 22 04:58:58 PM PST 24
Finished Jan 22 04:59:02 PM PST 24
Peak memory 220420 kb
Host smart-33589390-8719-420c-afb8-a8c8958b2408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875658084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1875658084
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3465748246
Short name T1031
Test name
Test status
Simulation time 438691130 ps
CPU time 4.61 seconds
Started Jan 22 04:59:05 PM PST 24
Finished Jan 22 04:59:10 PM PST 24
Peak memory 207316 kb
Host smart-6bffbbe5-cdd1-434b-b598-dc20321c6870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465748246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3465748246
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2709827680
Short name T12
Test name
Test status
Simulation time 1566524510 ps
CPU time 12.8 seconds
Started Jan 22 04:59:10 PM PST 24
Finished Jan 22 04:59:24 PM PST 24
Peak memory 238396 kb
Host smart-770ef614-3102-440b-bee3-3f26410d35f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709827680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2709827680
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.202405028
Short name T327
Test name
Test status
Simulation time 5925688573 ps
CPU time 38.36 seconds
Started Jan 22 05:08:18 PM PST 24
Finished Jan 22 05:08:57 PM PST 24
Peak memory 208868 kb
Host smart-4df3dd1d-6a04-455b-a503-f89fb0209589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202405028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.202405028
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2862707734
Short name T603
Test name
Test status
Simulation time 90544218 ps
CPU time 2.45 seconds
Started Jan 22 04:58:59 PM PST 24
Finished Jan 22 04:59:02 PM PST 24
Peak memory 207112 kb
Host smart-c0ad2ed0-3cd5-4b00-8a4c-5b0829539529
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862707734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2862707734
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.714935747
Short name T714
Test name
Test status
Simulation time 266985208 ps
CPU time 2.67 seconds
Started Jan 22 04:59:05 PM PST 24
Finished Jan 22 04:59:08 PM PST 24
Peak memory 208684 kb
Host smart-ba56688b-7d53-45b3-9d5a-450cccaaed0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714935747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.714935747
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3544698909
Short name T872
Test name
Test status
Simulation time 103291056 ps
CPU time 1.65 seconds
Started Jan 22 04:59:07 PM PST 24
Finished Jan 22 04:59:10 PM PST 24
Peak memory 207556 kb
Host smart-c4db076a-67a9-4a52-aea1-687a8786b715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544698909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3544698909
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2840069851
Short name T1000
Test name
Test status
Simulation time 297760942 ps
CPU time 2.61 seconds
Started Jan 22 04:59:01 PM PST 24
Finished Jan 22 04:59:04 PM PST 24
Peak memory 206808 kb
Host smart-879c05a9-5e00-4be3-bb51-9f70041651f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840069851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2840069851
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.781740782
Short name T111
Test name
Test status
Simulation time 191914545 ps
CPU time 6.08 seconds
Started Jan 22 04:59:07 PM PST 24
Finished Jan 22 04:59:13 PM PST 24
Peak memory 222512 kb
Host smart-1eed5bf0-5f63-415a-bd4e-99704e9f99a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781740782 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.781740782
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2211327144
Short name T869
Test name
Test status
Simulation time 334467193 ps
CPU time 4.33 seconds
Started Jan 22 05:13:44 PM PST 24
Finished Jan 22 05:13:49 PM PST 24
Peak memory 209576 kb
Host smart-172681dc-94d2-4e0b-af99-98aaf284c74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211327144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2211327144
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3697072379
Short name T657
Test name
Test status
Simulation time 119236074 ps
CPU time 2.14 seconds
Started Jan 22 04:59:11 PM PST 24
Finished Jan 22 04:59:13 PM PST 24
Peak memory 210080 kb
Host smart-245f6f73-1b0a-4047-9d3b-92e976270dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697072379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3697072379
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1391805407
Short name T856
Test name
Test status
Simulation time 38614055 ps
CPU time 0.72 seconds
Started Jan 22 05:01:44 PM PST 24
Finished Jan 22 05:01:45 PM PST 24
Peak memory 205900 kb
Host smart-3356ded2-f52e-47c4-96fd-46ecc4aab628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391805407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1391805407
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2187796208
Short name T325
Test name
Test status
Simulation time 989398817 ps
CPU time 34.48 seconds
Started Jan 22 05:01:40 PM PST 24
Finished Jan 22 05:02:15 PM PST 24
Peak memory 213780 kb
Host smart-1799d451-0836-4e17-bf49-2fc6b8bf9a6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187796208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2187796208
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3815340133
Short name T144
Test name
Test status
Simulation time 94603857 ps
CPU time 2.95 seconds
Started Jan 22 05:01:43 PM PST 24
Finished Jan 22 05:01:47 PM PST 24
Peak memory 222560 kb
Host smart-bfd66802-9adc-4f5c-9fe4-6eeb2b3bfde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815340133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3815340133
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3098326936
Short name T652
Test name
Test status
Simulation time 843359382 ps
CPU time 20.18 seconds
Started Jan 22 05:01:42 PM PST 24
Finished Jan 22 05:02:03 PM PST 24
Peak memory 209732 kb
Host smart-1cfa2046-16db-48f0-b866-b803393d19c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098326936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3098326936
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1090328072
Short name T227
Test name
Test status
Simulation time 1921683411 ps
CPU time 5.68 seconds
Started Jan 22 05:01:43 PM PST 24
Finished Jan 22 05:01:49 PM PST 24
Peak memory 219008 kb
Host smart-b60a64dd-6d20-4a94-94bc-f0911a7c0313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090328072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1090328072
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2215759609
Short name T259
Test name
Test status
Simulation time 137696233 ps
CPU time 4.88 seconds
Started Jan 22 05:01:40 PM PST 24
Finished Jan 22 05:01:46 PM PST 24
Peak memory 222356 kb
Host smart-3e56d9bb-cdd7-4f59-997d-1cae9e425a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215759609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2215759609
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2198217330
Short name T918
Test name
Test status
Simulation time 49835291 ps
CPU time 3.65 seconds
Started Jan 22 05:01:42 PM PST 24
Finished Jan 22 05:01:46 PM PST 24
Peak memory 218048 kb
Host smart-bd569d4d-49bf-4af5-b459-3cc617eb19b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198217330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2198217330
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2077351941
Short name T538
Test name
Test status
Simulation time 154703244 ps
CPU time 4.14 seconds
Started Jan 22 05:01:38 PM PST 24
Finished Jan 22 05:01:42 PM PST 24
Peak memory 209884 kb
Host smart-f5a7e33a-9c2d-4133-9d5d-fc729cefd64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077351941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2077351941
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1656708643
Short name T888
Test name
Test status
Simulation time 713658465 ps
CPU time 7.43 seconds
Started Jan 22 05:01:42 PM PST 24
Finished Jan 22 05:01:50 PM PST 24
Peak memory 208416 kb
Host smart-5840adac-11aa-4ceb-b55a-289aa7d67b53
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656708643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1656708643
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2077832518
Short name T274
Test name
Test status
Simulation time 215285766 ps
CPU time 2.82 seconds
Started Jan 22 05:01:42 PM PST 24
Finished Jan 22 05:01:46 PM PST 24
Peak memory 206700 kb
Host smart-cb3d0c53-8683-4f6a-917c-524f815119ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077832518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2077832518
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3281237351
Short name T778
Test name
Test status
Simulation time 299762259 ps
CPU time 1.69 seconds
Started Jan 22 05:01:44 PM PST 24
Finished Jan 22 05:01:46 PM PST 24
Peak memory 207676 kb
Host smart-6669297d-8690-4111-b660-c53f933658aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281237351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3281237351
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2221816175
Short name T959
Test name
Test status
Simulation time 240031757 ps
CPU time 5 seconds
Started Jan 22 05:01:38 PM PST 24
Finished Jan 22 05:01:44 PM PST 24
Peak memory 208824 kb
Host smart-6339c1ea-7775-44b6-a866-fb7e77a2afba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221816175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2221816175
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3370885153
Short name T352
Test name
Test status
Simulation time 1509954944 ps
CPU time 26.07 seconds
Started Jan 22 05:01:42 PM PST 24
Finished Jan 22 05:02:09 PM PST 24
Peak memory 215772 kb
Host smart-d35bad7d-35d3-4086-b116-178e3550c98f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370885153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3370885153
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.557370932
Short name T937
Test name
Test status
Simulation time 786893109 ps
CPU time 6.51 seconds
Started Jan 22 05:01:41 PM PST 24
Finished Jan 22 05:01:49 PM PST 24
Peak memory 219932 kb
Host smart-d4957081-4f13-4d85-8369-a14ae79ed511
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557370932 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.557370932
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2178557961
Short name T195
Test name
Test status
Simulation time 349744099 ps
CPU time 11.13 seconds
Started Jan 22 05:19:02 PM PST 24
Finished Jan 22 05:19:13 PM PST 24
Peak memory 214228 kb
Host smart-cc2a3f4d-5f51-4c8d-9890-6c1be9786a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178557961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2178557961
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.521648827
Short name T1003
Test name
Test status
Simulation time 48630298 ps
CPU time 2.72 seconds
Started Jan 22 05:01:43 PM PST 24
Finished Jan 22 05:01:46 PM PST 24
Peak memory 209988 kb
Host smart-eff3c8a0-5efb-4e06-b95d-abe204a9f88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521648827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.521648827
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.4049175907
Short name T909
Test name
Test status
Simulation time 15846486 ps
CPU time 0.78 seconds
Started Jan 22 05:01:46 PM PST 24
Finished Jan 22 05:01:48 PM PST 24
Peak memory 205904 kb
Host smart-730c0f2b-33d6-4bcd-828a-f86b07719267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049175907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.4049175907
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3238954906
Short name T633
Test name
Test status
Simulation time 97969094 ps
CPU time 1.8 seconds
Started Jan 22 05:01:46 PM PST 24
Finished Jan 22 05:01:49 PM PST 24
Peak memory 217588 kb
Host smart-bf85608e-322c-4299-b7b6-dce430e85fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238954906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3238954906
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3896773384
Short name T374
Test name
Test status
Simulation time 100792813 ps
CPU time 2.6 seconds
Started Jan 22 05:42:20 PM PST 24
Finished Jan 22 05:42:24 PM PST 24
Peak memory 208808 kb
Host smart-1dc40c54-2ee4-4877-950c-58a94d4f84c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896773384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3896773384
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2582883951
Short name T977
Test name
Test status
Simulation time 1041297204 ps
CPU time 5.66 seconds
Started Jan 22 05:25:28 PM PST 24
Finished Jan 22 05:25:34 PM PST 24
Peak memory 208224 kb
Host smart-61ae56db-83e5-48db-8724-2d0f6b571cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582883951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2582883951
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1577930961
Short name T261
Test name
Test status
Simulation time 987997666 ps
CPU time 12.21 seconds
Started Jan 22 05:01:48 PM PST 24
Finished Jan 22 05:02:01 PM PST 24
Peak memory 214172 kb
Host smart-e695c0dd-52c3-41fe-b383-9e85e058a728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577930961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1577930961
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3604579628
Short name T50
Test name
Test status
Simulation time 164554333 ps
CPU time 2.54 seconds
Started Jan 22 05:01:45 PM PST 24
Finished Jan 22 05:01:49 PM PST 24
Peak memory 215092 kb
Host smart-c640b258-2aac-4c57-8e1c-4779e2a5cac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604579628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3604579628
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3532169845
Short name T621
Test name
Test status
Simulation time 103745656 ps
CPU time 3.92 seconds
Started Jan 22 05:01:49 PM PST 24
Finished Jan 22 05:01:54 PM PST 24
Peak memory 206792 kb
Host smart-52dba170-9699-48bc-8150-97d1916c7efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532169845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3532169845
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3531452015
Short name T287
Test name
Test status
Simulation time 645523468 ps
CPU time 7.61 seconds
Started Jan 22 05:01:42 PM PST 24
Finished Jan 22 05:01:50 PM PST 24
Peak memory 208684 kb
Host smart-971cdc66-e9f0-48db-aeef-0fc4116c367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531452015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3531452015
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.969187559
Short name T920
Test name
Test status
Simulation time 187161116 ps
CPU time 5.83 seconds
Started Jan 22 05:01:46 PM PST 24
Finished Jan 22 05:01:53 PM PST 24
Peak memory 207920 kb
Host smart-5f049c9a-26e2-4022-87ba-8ee0a86a89e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969187559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.969187559
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2001854242
Short name T322
Test name
Test status
Simulation time 2140784339 ps
CPU time 30.28 seconds
Started Jan 22 05:01:43 PM PST 24
Finished Jan 22 05:02:14 PM PST 24
Peak memory 208420 kb
Host smart-25b921fa-254f-40cc-b682-7f373a8b20ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001854242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2001854242
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.917470984
Short name T693
Test name
Test status
Simulation time 72346934 ps
CPU time 2.82 seconds
Started Jan 22 05:01:45 PM PST 24
Finished Jan 22 05:01:48 PM PST 24
Peak memory 207532 kb
Host smart-d6fb37e5-df9e-4d54-a7fc-92c8ebc638d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917470984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.917470984
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1532912911
Short name T773
Test name
Test status
Simulation time 261920861 ps
CPU time 2.81 seconds
Started Jan 22 05:01:48 PM PST 24
Finished Jan 22 05:01:52 PM PST 24
Peak memory 214240 kb
Host smart-3be008a7-04ec-4f14-953b-83b9417e403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532912911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1532912911
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.728170019
Short name T625
Test name
Test status
Simulation time 259520314 ps
CPU time 3.62 seconds
Started Jan 22 05:01:42 PM PST 24
Finished Jan 22 05:01:46 PM PST 24
Peak memory 208116 kb
Host smart-c39cb0c7-c35b-4df3-bf7b-109794ce1039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728170019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.728170019
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1395130152
Short name T1027
Test name
Test status
Simulation time 14787640207 ps
CPU time 105.98 seconds
Started Jan 22 05:01:48 PM PST 24
Finished Jan 22 05:03:35 PM PST 24
Peak memory 215920 kb
Host smart-2a75b114-3c94-4f1d-9b70-b2d17e5f1cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395130152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1395130152
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.817803656
Short name T974
Test name
Test status
Simulation time 439066597 ps
CPU time 6.87 seconds
Started Jan 22 05:01:46 PM PST 24
Finished Jan 22 05:01:54 PM PST 24
Peak memory 222548 kb
Host smart-6dec277b-e66d-43e7-9435-46c57880ef2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817803656 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.817803656
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3763236088
Short name T362
Test name
Test status
Simulation time 1955873215 ps
CPU time 14.01 seconds
Started Jan 22 05:01:48 PM PST 24
Finished Jan 22 05:02:03 PM PST 24
Peak memory 218144 kb
Host smart-3ec0f2b5-a9aa-4270-b923-d88f48ac5bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763236088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3763236088
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3902297467
Short name T755
Test name
Test status
Simulation time 31628135 ps
CPU time 1.7 seconds
Started Jan 22 05:14:29 PM PST 24
Finished Jan 22 05:14:31 PM PST 24
Peak memory 209504 kb
Host smart-0327a75f-2896-4af6-a5d4-a0d944e78a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902297467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3902297467
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.931299811
Short name T720
Test name
Test status
Simulation time 13590381 ps
CPU time 0.76 seconds
Started Jan 22 05:02:06 PM PST 24
Finished Jan 22 05:02:07 PM PST 24
Peak memory 205872 kb
Host smart-67645716-9177-45b7-9a16-b342f91c9ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931299811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.931299811
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.259642740
Short name T254
Test name
Test status
Simulation time 122654200 ps
CPU time 2.66 seconds
Started Jan 22 05:01:41 PM PST 24
Finished Jan 22 05:01:44 PM PST 24
Peak memory 214380 kb
Host smart-0f02979e-4ec4-4b4c-abd1-5a71b1b5f62c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259642740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.259642740
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2139115132
Short name T889
Test name
Test status
Simulation time 214326324 ps
CPU time 3.05 seconds
Started Jan 22 05:02:02 PM PST 24
Finished Jan 22 05:02:06 PM PST 24
Peak memory 208856 kb
Host smart-3a8c484a-0389-49e1-9aab-24a5532b63df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139115132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2139115132
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.351776272
Short name T942
Test name
Test status
Simulation time 1325527519 ps
CPU time 5.75 seconds
Started Jan 22 05:01:45 PM PST 24
Finished Jan 22 05:01:51 PM PST 24
Peak memory 208028 kb
Host smart-10cc6029-5214-4f47-9b56-00cbeaf25535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351776272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.351776272
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2208042106
Short name T1054
Test name
Test status
Simulation time 5504561959 ps
CPU time 22.61 seconds
Started Jan 22 05:47:13 PM PST 24
Finished Jan 22 05:47:37 PM PST 24
Peak memory 220028 kb
Host smart-d8c3a571-dbc3-4d36-87d0-d4f46754beb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208042106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2208042106
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3960808572
Short name T858
Test name
Test status
Simulation time 148419046 ps
CPU time 3.13 seconds
Started Jan 22 05:01:44 PM PST 24
Finished Jan 22 05:01:47 PM PST 24
Peak memory 220220 kb
Host smart-0d5c5249-7ff6-4554-9843-e2029e594ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960808572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3960808572
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1051546412
Short name T819
Test name
Test status
Simulation time 222091623 ps
CPU time 7.76 seconds
Started Jan 22 05:01:49 PM PST 24
Finished Jan 22 05:01:58 PM PST 24
Peak memory 208160 kb
Host smart-c243fa5a-c5db-4f0d-ad87-f03fd1bdfb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051546412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1051546412
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1723586385
Short name T754
Test name
Test status
Simulation time 89245497 ps
CPU time 4.29 seconds
Started Jan 22 05:01:48 PM PST 24
Finished Jan 22 05:01:53 PM PST 24
Peak memory 208424 kb
Host smart-29e39c71-233d-4889-a3c1-753685c917c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723586385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1723586385
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.980221326
Short name T923
Test name
Test status
Simulation time 2985183940 ps
CPU time 18.93 seconds
Started Jan 22 05:01:46 PM PST 24
Finished Jan 22 05:02:06 PM PST 24
Peak memory 208028 kb
Host smart-7f82f098-8989-4191-801d-9c4f4bc07457
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980221326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.980221326
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1367598451
Short name T349
Test name
Test status
Simulation time 266234697 ps
CPU time 7.07 seconds
Started Jan 22 05:01:48 PM PST 24
Finished Jan 22 05:01:56 PM PST 24
Peak memory 208020 kb
Host smart-8a5293f2-5ce2-4959-87c4-a63537a46949
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367598451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1367598451
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.113975698
Short name T830
Test name
Test status
Simulation time 57245299 ps
CPU time 2.89 seconds
Started Jan 22 05:01:49 PM PST 24
Finished Jan 22 05:01:53 PM PST 24
Peak memory 207904 kb
Host smart-5117a546-4aaa-493d-b843-09551c838426
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113975698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.113975698
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1574412954
Short name T911
Test name
Test status
Simulation time 351090293 ps
CPU time 1.61 seconds
Started Jan 22 05:02:05 PM PST 24
Finished Jan 22 05:02:07 PM PST 24
Peak memory 207980 kb
Host smart-da97b768-024e-4d04-b63d-b04cb496afe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574412954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1574412954
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.142872961
Short name T529
Test name
Test status
Simulation time 263661471 ps
CPU time 5.63 seconds
Started Jan 22 05:01:46 PM PST 24
Finished Jan 22 05:01:53 PM PST 24
Peak memory 207692 kb
Host smart-c65de59f-6603-4161-a1cc-14b02b960f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142872961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.142872961
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3282181667
Short name T536
Test name
Test status
Simulation time 1172735852 ps
CPU time 5.55 seconds
Started Jan 22 05:01:57 PM PST 24
Finished Jan 22 05:02:03 PM PST 24
Peak memory 222556 kb
Host smart-c17cad78-ec95-43e9-8d23-30dbc9f134ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282181667 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3282181667
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.135326227
Short name T14
Test name
Test status
Simulation time 174741803 ps
CPU time 4.78 seconds
Started Jan 22 05:01:48 PM PST 24
Finished Jan 22 05:01:54 PM PST 24
Peak memory 207268 kb
Host smart-ccce9387-cf60-47da-a815-5c0c6e21ffd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135326227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.135326227
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4155612337
Short name T160
Test name
Test status
Simulation time 723237315 ps
CPU time 14.74 seconds
Started Jan 22 05:02:03 PM PST 24
Finished Jan 22 05:02:18 PM PST 24
Peak memory 211348 kb
Host smart-628f8969-8c03-44f0-a13c-e279d2ac0c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155612337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4155612337
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.956458518
Short name T699
Test name
Test status
Simulation time 103321832 ps
CPU time 0.81 seconds
Started Jan 22 05:02:06 PM PST 24
Finished Jan 22 05:02:07 PM PST 24
Peak memory 205872 kb
Host smart-784928af-cd94-471a-be14-3dbf5204ad66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956458518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.956458518
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2064984754
Short name T302
Test name
Test status
Simulation time 1606017769 ps
CPU time 58.5 seconds
Started Jan 22 05:02:01 PM PST 24
Finished Jan 22 05:03:00 PM PST 24
Peak memory 215628 kb
Host smart-f1502a8f-a2b6-4e4d-a6ce-8f5e10973707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064984754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2064984754
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3400887838
Short name T57
Test name
Test status
Simulation time 219983189 ps
CPU time 6.26 seconds
Started Jan 22 05:02:05 PM PST 24
Finished Jan 22 05:02:12 PM PST 24
Peak memory 210004 kb
Host smart-97d5d02b-839a-422b-8de8-175b71ed4085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400887838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3400887838
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4102499122
Short name T727
Test name
Test status
Simulation time 84726782 ps
CPU time 2.81 seconds
Started Jan 22 05:01:56 PM PST 24
Finished Jan 22 05:02:00 PM PST 24
Peak memory 208180 kb
Host smart-35d86ef9-7d7a-47ae-9851-0965e898b36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102499122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4102499122
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2883892189
Short name T332
Test name
Test status
Simulation time 303418558 ps
CPU time 4.67 seconds
Started Jan 22 05:02:03 PM PST 24
Finished Jan 22 05:02:08 PM PST 24
Peak memory 211584 kb
Host smart-61ec7c9e-b049-41bc-825e-838a5a85335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883892189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2883892189
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.861308300
Short name T686
Test name
Test status
Simulation time 1087109791 ps
CPU time 8.56 seconds
Started Jan 22 05:02:04 PM PST 24
Finished Jan 22 05:02:13 PM PST 24
Peak memory 222408 kb
Host smart-5292a5ce-8f87-48a3-93e7-336affacacac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861308300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.861308300
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2724609922
Short name T867
Test name
Test status
Simulation time 181738198 ps
CPU time 5.46 seconds
Started Jan 22 05:02:02 PM PST 24
Finished Jan 22 05:02:08 PM PST 24
Peak memory 209044 kb
Host smart-0a923322-c0e0-4302-aa57-16849ba181b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724609922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2724609922
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2654271937
Short name T684
Test name
Test status
Simulation time 70243677 ps
CPU time 1.99 seconds
Started Jan 22 05:02:07 PM PST 24
Finished Jan 22 05:02:09 PM PST 24
Peak memory 207304 kb
Host smart-95e5bd2a-2834-4512-9998-257c159ce3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654271937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2654271937
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1297476007
Short name T95
Test name
Test status
Simulation time 728604706 ps
CPU time 5.67 seconds
Started Jan 22 05:02:04 PM PST 24
Finished Jan 22 05:02:11 PM PST 24
Peak memory 207996 kb
Host smart-728b8b4a-469d-4c23-b9ac-aff581457650
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297476007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1297476007
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2881235275
Short name T612
Test name
Test status
Simulation time 69556209 ps
CPU time 2.6 seconds
Started Jan 22 05:02:02 PM PST 24
Finished Jan 22 05:02:05 PM PST 24
Peak memory 208680 kb
Host smart-046e64a3-b655-4b60-b8dc-89dfe70681cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881235275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2881235275
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1072333625
Short name T865
Test name
Test status
Simulation time 900063596 ps
CPU time 7.49 seconds
Started Jan 22 05:02:05 PM PST 24
Finished Jan 22 05:02:13 PM PST 24
Peak memory 208652 kb
Host smart-6e2c1187-e7c4-4f80-84ee-6b4859b5f9a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072333625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1072333625
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2423254486
Short name T744
Test name
Test status
Simulation time 311611243 ps
CPU time 4.7 seconds
Started Jan 22 05:02:05 PM PST 24
Finished Jan 22 05:02:10 PM PST 24
Peak memory 209540 kb
Host smart-6e5d9a43-176a-4b3d-b689-1e72840c4991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423254486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2423254486
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2103846905
Short name T525
Test name
Test status
Simulation time 773097744 ps
CPU time 25.96 seconds
Started Jan 22 05:02:04 PM PST 24
Finished Jan 22 05:02:30 PM PST 24
Peak memory 208132 kb
Host smart-f77b3ffd-d05a-410c-b281-36a51747e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103846905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2103846905
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2539820971
Short name T973
Test name
Test status
Simulation time 2141015157 ps
CPU time 6 seconds
Started Jan 22 05:01:58 PM PST 24
Finished Jan 22 05:02:04 PM PST 24
Peak memory 206880 kb
Host smart-a8d7db72-4973-4a98-a4f5-a0b9aa8f0e08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539820971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2539820971
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1365287396
Short name T887
Test name
Test status
Simulation time 1543066444 ps
CPU time 12.35 seconds
Started Jan 22 05:01:57 PM PST 24
Finished Jan 22 05:02:10 PM PST 24
Peak memory 222524 kb
Host smart-dd1c8388-b852-42a5-a029-28ccd3ea15d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365287396 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1365287396
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1724903755
Short name T691
Test name
Test status
Simulation time 238223873 ps
CPU time 3.89 seconds
Started Jan 22 05:02:05 PM PST 24
Finished Jan 22 05:02:09 PM PST 24
Peak memory 214272 kb
Host smart-8d43d8f3-455a-4902-967f-2bbec7998405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724903755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1724903755
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3182196967
Short name T1013
Test name
Test status
Simulation time 1524006537 ps
CPU time 12.92 seconds
Started Jan 22 05:02:02 PM PST 24
Finished Jan 22 05:02:16 PM PST 24
Peak memory 210348 kb
Host smart-72f326cc-cd95-4524-9e1a-25e54310dd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182196967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3182196967
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3911761220
Short name T557
Test name
Test status
Simulation time 118836098 ps
CPU time 0.99 seconds
Started Jan 22 05:02:12 PM PST 24
Finished Jan 22 05:02:15 PM PST 24
Peak memory 206004 kb
Host smart-1fc27195-cdc4-4a0e-abaf-d4f97a856167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911761220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3911761220
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1344555170
Short name T394
Test name
Test status
Simulation time 103128932 ps
CPU time 3.95 seconds
Started Jan 22 05:02:00 PM PST 24
Finished Jan 22 05:02:05 PM PST 24
Peak memory 215044 kb
Host smart-9b4b2465-d14e-418a-aba4-cbf73b27dcd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1344555170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1344555170
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.610763308
Short name T972
Test name
Test status
Simulation time 1131154421 ps
CPU time 9.17 seconds
Started Jan 22 05:02:08 PM PST 24
Finished Jan 22 05:02:18 PM PST 24
Peak memory 222728 kb
Host smart-8ac672de-02c1-40f8-bfe0-1a16033f6763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610763308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.610763308
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2569797518
Short name T63
Test name
Test status
Simulation time 64857301 ps
CPU time 2.99 seconds
Started Jan 22 05:02:07 PM PST 24
Finished Jan 22 05:02:10 PM PST 24
Peak memory 218172 kb
Host smart-0eb40b34-762a-440e-bc4b-3a1c71b50ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569797518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2569797518
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_random.840916026
Short name T266
Test name
Test status
Simulation time 456251014 ps
CPU time 5.71 seconds
Started Jan 22 05:02:02 PM PST 24
Finished Jan 22 05:02:08 PM PST 24
Peak memory 209768 kb
Host smart-66c6e2b1-97cb-4391-a44d-60a5ac70c531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840916026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.840916026
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3222838026
Short name T1047
Test name
Test status
Simulation time 4174997712 ps
CPU time 28.61 seconds
Started Jan 22 05:02:01 PM PST 24
Finished Jan 22 05:02:30 PM PST 24
Peak memory 208540 kb
Host smart-23697126-f34c-4d50-8518-3d65e4a5b418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222838026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3222838026
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1531376140
Short name T745
Test name
Test status
Simulation time 120536837 ps
CPU time 2.59 seconds
Started Jan 22 05:02:02 PM PST 24
Finished Jan 22 05:02:05 PM PST 24
Peak memory 206772 kb
Host smart-4afa8ec4-8c0b-45d6-9a1d-788d73723e26
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531376140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1531376140
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.414611472
Short name T863
Test name
Test status
Simulation time 1252204738 ps
CPU time 31.71 seconds
Started Jan 22 05:01:59 PM PST 24
Finished Jan 22 05:02:32 PM PST 24
Peak memory 208424 kb
Host smart-f506a613-9945-4b64-b774-bac228513fba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414611472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.414611472
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2621669406
Short name T572
Test name
Test status
Simulation time 20320598 ps
CPU time 1.77 seconds
Started Jan 22 05:01:59 PM PST 24
Finished Jan 22 05:02:02 PM PST 24
Peak memory 206816 kb
Host smart-ec0fffb4-6f85-4e4a-aa52-a69f28e3e2d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621669406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2621669406
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.963916832
Short name T567
Test name
Test status
Simulation time 80170823 ps
CPU time 1.92 seconds
Started Jan 22 05:02:12 PM PST 24
Finished Jan 22 05:02:16 PM PST 24
Peak memory 206884 kb
Host smart-3219c41c-fd80-4305-802e-0003b35f72e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963916832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.963916832
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2446078537
Short name T609
Test name
Test status
Simulation time 166701557 ps
CPU time 2.31 seconds
Started Jan 22 05:01:59 PM PST 24
Finished Jan 22 05:02:02 PM PST 24
Peak memory 206772 kb
Host smart-94ef35ff-0dea-4fb4-bf66-d3c64bfaf87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446078537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2446078537
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2511832022
Short name T216
Test name
Test status
Simulation time 5036481711 ps
CPU time 49.22 seconds
Started Jan 22 05:11:52 PM PST 24
Finished Jan 22 05:12:42 PM PST 24
Peak memory 215852 kb
Host smart-d7e1ba45-762e-478b-b5dd-5d1e81a4f577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511832022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2511832022
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.4101960346
Short name T113
Test name
Test status
Simulation time 605888544 ps
CPU time 12.53 seconds
Started Jan 22 05:42:14 PM PST 24
Finished Jan 22 05:42:28 PM PST 24
Peak memory 222476 kb
Host smart-fbfc9485-f983-4869-9016-9b329b533841
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101960346 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.4101960346
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3350301904
Short name T1056
Test name
Test status
Simulation time 155748655 ps
CPU time 2.81 seconds
Started Jan 22 05:02:01 PM PST 24
Finished Jan 22 05:02:04 PM PST 24
Peak memory 208204 kb
Host smart-a076ba4d-30ba-424b-9ddf-d2d852f2a851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350301904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3350301904
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2406977265
Short name T763
Test name
Test status
Simulation time 160357761 ps
CPU time 3.12 seconds
Started Jan 22 05:02:12 PM PST 24
Finished Jan 22 05:02:17 PM PST 24
Peak memory 210508 kb
Host smart-8399a97e-53a8-4a27-a863-75916f8130e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406977265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2406977265
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2323067050
Short name T651
Test name
Test status
Simulation time 28988649 ps
CPU time 0.98 seconds
Started Jan 22 05:02:29 PM PST 24
Finished Jan 22 05:02:46 PM PST 24
Peak memory 206168 kb
Host smart-a39a709e-f7d4-4e3f-b8e4-c05fe8205a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323067050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2323067050
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1305308372
Short name T949
Test name
Test status
Simulation time 1183770641 ps
CPU time 6.5 seconds
Started Jan 22 05:02:10 PM PST 24
Finished Jan 22 05:02:17 PM PST 24
Peak memory 214268 kb
Host smart-62203b84-4b05-4f92-ac1d-efe97fdf7d15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305308372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1305308372
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1169111968
Short name T890
Test name
Test status
Simulation time 5323734609 ps
CPU time 34.26 seconds
Started Jan 22 05:02:20 PM PST 24
Finished Jan 22 05:02:55 PM PST 24
Peak memory 222760 kb
Host smart-d53cc521-7276-4182-9dea-f6eb205cb085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169111968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1169111968
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.256233009
Short name T264
Test name
Test status
Simulation time 134713305 ps
CPU time 4.99 seconds
Started Jan 22 05:02:12 PM PST 24
Finished Jan 22 05:02:19 PM PST 24
Peak memory 218088 kb
Host smart-1653977d-5014-4e01-9998-58133a91ca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256233009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.256233009
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.657911024
Short name T806
Test name
Test status
Simulation time 1214653166 ps
CPU time 12.97 seconds
Started Jan 22 05:26:12 PM PST 24
Finished Jan 22 05:26:30 PM PST 24
Peak memory 214164 kb
Host smart-4e8b1355-984e-4314-adac-9ffec61e5f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657911024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.657911024
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_random.3119189999
Short name T780
Test name
Test status
Simulation time 1910831849 ps
CPU time 32.52 seconds
Started Jan 22 05:02:10 PM PST 24
Finished Jan 22 05:02:43 PM PST 24
Peak memory 207900 kb
Host smart-355f7aa7-f075-46b6-b320-71b1aa562c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119189999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3119189999
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3826190884
Short name T676
Test name
Test status
Simulation time 192754855 ps
CPU time 5.88 seconds
Started Jan 22 05:02:12 PM PST 24
Finished Jan 22 05:02:20 PM PST 24
Peak memory 208704 kb
Host smart-ef58794a-9bdc-42f6-89ba-e6bfaa3da6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826190884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3826190884
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3579174760
Short name T814
Test name
Test status
Simulation time 33533666 ps
CPU time 2.39 seconds
Started Jan 22 05:02:12 PM PST 24
Finished Jan 22 05:02:17 PM PST 24
Peak memory 206864 kb
Host smart-64e0fa9a-c78f-4217-8575-33bc82a415f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579174760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3579174760
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2378166193
Short name T623
Test name
Test status
Simulation time 5003842180 ps
CPU time 49.56 seconds
Started Jan 22 05:02:12 PM PST 24
Finished Jan 22 05:03:04 PM PST 24
Peak memory 206984 kb
Host smart-a10009b0-270f-4293-9e2f-4d24f245f190
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378166193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2378166193
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3186218346
Short name T653
Test name
Test status
Simulation time 966096337 ps
CPU time 7.95 seconds
Started Jan 22 05:02:12 PM PST 24
Finished Jan 22 05:02:22 PM PST 24
Peak memory 208040 kb
Host smart-4eb66e3e-b078-4cd0-be5f-8aeecdb97ae6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186218346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3186218346
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.966974206
Short name T776
Test name
Test status
Simulation time 611715583 ps
CPU time 4.05 seconds
Started Jan 22 05:02:16 PM PST 24
Finished Jan 22 05:02:21 PM PST 24
Peak memory 215368 kb
Host smart-7b58bf93-1973-4195-85d5-c2377b7ca9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966974206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.966974206
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3954055924
Short name T185
Test name
Test status
Simulation time 53795367 ps
CPU time 2.6 seconds
Started Jan 22 05:02:12 PM PST 24
Finished Jan 22 05:02:17 PM PST 24
Peak memory 206832 kb
Host smart-d1a3c6ec-f8ad-4691-b6f7-efc8301d65bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954055924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3954055924
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.766712971
Short name T8
Test name
Test status
Simulation time 2607897939 ps
CPU time 26.94 seconds
Started Jan 22 05:02:31 PM PST 24
Finished Jan 22 05:03:12 PM PST 24
Peak memory 215892 kb
Host smart-aff6d651-4e29-41f1-965f-859b0d393ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766712971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.766712971
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2625725019
Short name T396
Test name
Test status
Simulation time 1807316653 ps
CPU time 34.16 seconds
Started Jan 22 05:02:20 PM PST 24
Finished Jan 22 05:02:55 PM PST 24
Peak memory 218192 kb
Host smart-0c83c1f5-843c-4e3b-b991-fd166820b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625725019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2625725019
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2165562886
Short name T802
Test name
Test status
Simulation time 294078372 ps
CPU time 2.81 seconds
Started Jan 22 05:02:19 PM PST 24
Finished Jan 22 05:02:22 PM PST 24
Peak memory 209732 kb
Host smart-8b145239-97a9-4a33-9c80-6539a0b85440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165562886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2165562886
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.781860083
Short name T91
Test name
Test status
Simulation time 17524592 ps
CPU time 0.96 seconds
Started Jan 22 05:03:00 PM PST 24
Finished Jan 22 05:03:03 PM PST 24
Peak memory 206088 kb
Host smart-4fa9ff8f-9c2e-4911-adff-606aefd7e255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781860083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.781860083
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3212660783
Short name T367
Test name
Test status
Simulation time 50030997 ps
CPU time 3.25 seconds
Started Jan 22 05:02:34 PM PST 24
Finished Jan 22 05:02:48 PM PST 24
Peak memory 214436 kb
Host smart-3d8d64db-b8f8-471b-9437-d6d64ab847a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3212660783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3212660783
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3199464282
Short name T3
Test name
Test status
Simulation time 144545019 ps
CPU time 2.73 seconds
Started Jan 22 05:02:34 PM PST 24
Finished Jan 22 05:02:48 PM PST 24
Peak memory 209736 kb
Host smart-3b6b10b4-be96-4f03-b246-145288265065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199464282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3199464282
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3702931065
Short name T314
Test name
Test status
Simulation time 102755055 ps
CPU time 4.62 seconds
Started Jan 22 05:02:52 PM PST 24
Finished Jan 22 05:03:01 PM PST 24
Peak memory 209888 kb
Host smart-9cb033ab-c7e6-442b-a4b6-bcf2f73e5d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702931065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3702931065
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3514754945
Short name T214
Test name
Test status
Simulation time 122489187 ps
CPU time 2.63 seconds
Started Jan 22 05:02:30 PM PST 24
Finished Jan 22 05:02:48 PM PST 24
Peak memory 214344 kb
Host smart-3d7cc795-44bd-4e46-a647-012a4bd40797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514754945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3514754945
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.739790539
Short name T700
Test name
Test status
Simulation time 450009619 ps
CPU time 5.37 seconds
Started Jan 22 05:02:40 PM PST 24
Finished Jan 22 05:02:51 PM PST 24
Peak memory 208960 kb
Host smart-1e42109c-0ce3-449b-81c8-a84ff6adf35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739790539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.739790539
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3605200976
Short name T668
Test name
Test status
Simulation time 4057804051 ps
CPU time 56.64 seconds
Started Jan 22 06:03:41 PM PST 24
Finished Jan 22 06:04:39 PM PST 24
Peak memory 208200 kb
Host smart-1f1c911e-de3b-4686-8ac9-359b84491708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605200976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3605200976
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2141838793
Short name T796
Test name
Test status
Simulation time 562471728 ps
CPU time 4.62 seconds
Started Jan 22 05:02:30 PM PST 24
Finished Jan 22 05:02:50 PM PST 24
Peak memory 208472 kb
Host smart-ea96fc34-8386-465a-a27d-9cf4894b2f45
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141838793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2141838793
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3053833865
Short name T343
Test name
Test status
Simulation time 39002161 ps
CPU time 2.25 seconds
Started Jan 22 05:02:39 PM PST 24
Finished Jan 22 05:02:48 PM PST 24
Peak memory 207792 kb
Host smart-28382686-d06c-487b-a0e8-82388266eb7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053833865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3053833865
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1701461674
Short name T837
Test name
Test status
Simulation time 57883231 ps
CPU time 3.06 seconds
Started Jan 22 05:02:30 PM PST 24
Finished Jan 22 05:02:48 PM PST 24
Peak memory 208132 kb
Host smart-85e599ba-e774-4ec2-a228-83f13877d3c6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701461674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1701461674
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1257891583
Short name T678
Test name
Test status
Simulation time 568958878 ps
CPU time 9.67 seconds
Started Jan 22 05:42:21 PM PST 24
Finished Jan 22 05:42:32 PM PST 24
Peak memory 209300 kb
Host smart-77df2024-52e5-4991-badc-67991e2e56dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257891583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1257891583
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1071779587
Short name T522
Test name
Test status
Simulation time 45405089 ps
CPU time 2.47 seconds
Started Jan 22 05:02:31 PM PST 24
Finished Jan 22 05:02:48 PM PST 24
Peak memory 208260 kb
Host smart-734a362f-27a4-44d1-b21b-59344bb033be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071779587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1071779587
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4082341854
Short name T213
Test name
Test status
Simulation time 3490923369 ps
CPU time 36.56 seconds
Started Jan 22 05:02:59 PM PST 24
Finished Jan 22 05:03:38 PM PST 24
Peak memory 222424 kb
Host smart-4565a27b-c5c5-4c6f-b6b7-1e9ea4f85c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082341854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4082341854
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1923935003
Short name T648
Test name
Test status
Simulation time 573466435 ps
CPU time 5.43 seconds
Started Jan 22 05:02:53 PM PST 24
Finished Jan 22 05:03:01 PM PST 24
Peak memory 222484 kb
Host smart-79a4c5ff-7b4e-4d92-a363-5c227db15fd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923935003 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1923935003
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3038305648
Short name T976
Test name
Test status
Simulation time 2971598697 ps
CPU time 5.43 seconds
Started Jan 22 05:02:33 PM PST 24
Finished Jan 22 05:02:51 PM PST 24
Peak memory 207984 kb
Host smart-f3ed3c80-8147-4870-8ab4-94eef5912b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038305648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3038305648
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1980382501
Short name T635
Test name
Test status
Simulation time 128581881 ps
CPU time 1.63 seconds
Started Jan 22 05:03:00 PM PST 24
Finished Jan 22 05:03:03 PM PST 24
Peak memory 209824 kb
Host smart-aa5177a3-b184-4f32-8b0d-648aecf90ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980382501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1980382501
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3668238422
Short name T569
Test name
Test status
Simulation time 11737638 ps
CPU time 0.72 seconds
Started Jan 22 05:02:52 PM PST 24
Finished Jan 22 05:02:57 PM PST 24
Peak memory 205864 kb
Host smart-033f80ec-2998-4de8-a554-dc2830c43d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668238422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3668238422
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3610713803
Short name T1014
Test name
Test status
Simulation time 1421904985 ps
CPU time 8.6 seconds
Started Jan 22 05:02:42 PM PST 24
Finished Jan 22 05:02:54 PM PST 24
Peak memory 209344 kb
Host smart-fdeb34ed-c37a-498c-9916-b0895e6a3310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610713803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3610713803
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1557621232
Short name T342
Test name
Test status
Simulation time 143896329 ps
CPU time 4.45 seconds
Started Jan 22 05:02:59 PM PST 24
Finished Jan 22 05:03:06 PM PST 24
Peak memory 218144 kb
Host smart-d2e28807-704e-4a2e-9572-3d73e51d2442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557621232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1557621232
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1044893222
Short name T800
Test name
Test status
Simulation time 98939618 ps
CPU time 4.21 seconds
Started Jan 22 05:02:44 PM PST 24
Finished Jan 22 05:02:50 PM PST 24
Peak memory 209392 kb
Host smart-6b83832c-7bff-4dc4-8472-f196c50105db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044893222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1044893222
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3710359378
Short name T278
Test name
Test status
Simulation time 1486181286 ps
CPU time 5.43 seconds
Started Jan 22 05:03:00 PM PST 24
Finished Jan 22 05:03:07 PM PST 24
Peak memory 222372 kb
Host smart-c1114c68-3451-4a74-90d6-a4a96542428a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710359378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3710359378
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2991150241
Short name T60
Test name
Test status
Simulation time 336683880 ps
CPU time 4.37 seconds
Started Jan 22 05:03:03 PM PST 24
Finished Jan 22 05:03:08 PM PST 24
Peak memory 208524 kb
Host smart-f6e69574-910d-4d1a-84b0-ec2009f85eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991150241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2991150241
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2889626098
Short name T634
Test name
Test status
Simulation time 250751265 ps
CPU time 7.13 seconds
Started Jan 22 05:02:59 PM PST 24
Finished Jan 22 05:03:09 PM PST 24
Peak memory 208708 kb
Host smart-2a71c2ec-67f6-4388-89ad-10fb2750b8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889626098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2889626098
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1124665027
Short name T898
Test name
Test status
Simulation time 569934314 ps
CPU time 4.75 seconds
Started Jan 22 05:02:44 PM PST 24
Finished Jan 22 05:02:51 PM PST 24
Peak memory 208732 kb
Host smart-dbcc2836-f6b2-45fb-a278-ca1bc1ca4653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124665027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1124665027
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2273337921
Short name T965
Test name
Test status
Simulation time 110869686 ps
CPU time 2.86 seconds
Started Jan 22 05:02:44 PM PST 24
Finished Jan 22 05:02:49 PM PST 24
Peak memory 208636 kb
Host smart-0203e48b-3105-4607-8db5-3b641ef048db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273337921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2273337921
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.260800205
Short name T788
Test name
Test status
Simulation time 66884221 ps
CPU time 3.28 seconds
Started Jan 22 05:03:00 PM PST 24
Finished Jan 22 05:03:05 PM PST 24
Peak memory 208636 kb
Host smart-e1090f6a-36a9-4711-9bd8-37929200b6f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260800205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.260800205
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1994728417
Short name T783
Test name
Test status
Simulation time 2289167456 ps
CPU time 76.94 seconds
Started Jan 22 05:02:58 PM PST 24
Finished Jan 22 05:04:18 PM PST 24
Peak memory 208836 kb
Host smart-b0892cdf-1c0e-4d74-8a80-33cd3226dd30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994728417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1994728417
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3571680534
Short name T1038
Test name
Test status
Simulation time 83811322 ps
CPU time 2.33 seconds
Started Jan 22 05:02:59 PM PST 24
Finished Jan 22 05:03:04 PM PST 24
Peak memory 208988 kb
Host smart-122bf58c-5d28-41c4-b69f-f669528d251a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571680534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3571680534
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3662201770
Short name T1018
Test name
Test status
Simulation time 43047217 ps
CPU time 2.36 seconds
Started Jan 22 05:53:13 PM PST 24
Finished Jan 22 05:53:23 PM PST 24
Peak memory 206912 kb
Host smart-d61a45a0-b0c4-4d3a-b253-8ea2c154ee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662201770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3662201770
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3534365866
Short name T804
Test name
Test status
Simulation time 3123992544 ps
CPU time 20.63 seconds
Started Jan 22 05:02:59 PM PST 24
Finished Jan 22 05:03:22 PM PST 24
Peak memory 218976 kb
Host smart-3b89a026-563a-4cc4-9ec7-2abeeffc8564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534365866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3534365866
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3515783706
Short name T735
Test name
Test status
Simulation time 414111217 ps
CPU time 5.85 seconds
Started Jan 22 05:02:41 PM PST 24
Finished Jan 22 05:02:51 PM PST 24
Peak memory 207432 kb
Host smart-63586fe1-727c-4148-96b7-1781e7f173c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515783706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3515783706
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3572452931
Short name T861
Test name
Test status
Simulation time 343440906 ps
CPU time 2.5 seconds
Started Jan 22 05:02:59 PM PST 24
Finished Jan 22 05:03:04 PM PST 24
Peak memory 209728 kb
Host smart-2754eaeb-8a59-4e82-b400-3640f97899ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572452931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3572452931
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1363594023
Short name T978
Test name
Test status
Simulation time 66326297 ps
CPU time 0.76 seconds
Started Jan 22 05:02:53 PM PST 24
Finished Jan 22 05:02:57 PM PST 24
Peak memory 205904 kb
Host smart-5fa8fb27-a6bf-454c-b8bb-590f6407c822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363594023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1363594023
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2140601883
Short name T393
Test name
Test status
Simulation time 252060411 ps
CPU time 13.77 seconds
Started Jan 22 05:03:05 PM PST 24
Finished Jan 22 05:03:28 PM PST 24
Peak memory 215736 kb
Host smart-8f525c2a-a9c3-4439-ba64-5a7b273be227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2140601883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2140601883
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3759274256
Short name T853
Test name
Test status
Simulation time 100103236 ps
CPU time 2.5 seconds
Started Jan 22 05:02:53 PM PST 24
Finished Jan 22 05:02:58 PM PST 24
Peak memory 207656 kb
Host smart-dc702170-1652-44b2-9bea-b10ea64a80c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759274256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3759274256
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2780857808
Short name T300
Test name
Test status
Simulation time 178370325 ps
CPU time 5.71 seconds
Started Jan 22 05:02:54 PM PST 24
Finished Jan 22 05:03:02 PM PST 24
Peak memory 214276 kb
Host smart-178975e5-1e1b-4864-b09f-8b4398f0cf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780857808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2780857808
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2499951949
Short name T209
Test name
Test status
Simulation time 65913644 ps
CPU time 2.88 seconds
Started Jan 22 05:02:55 PM PST 24
Finished Jan 22 05:02:59 PM PST 24
Peak memory 209692 kb
Host smart-3efac9fe-7cc6-49f4-8550-5b6ed9ad4f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499951949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2499951949
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2422888762
Short name T859
Test name
Test status
Simulation time 90067297 ps
CPU time 3.86 seconds
Started Jan 22 05:02:59 PM PST 24
Finished Jan 22 05:03:05 PM PST 24
Peak memory 206924 kb
Host smart-005cf730-424a-4a72-ac03-c96bf825e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422888762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2422888762
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3977112438
Short name T961
Test name
Test status
Simulation time 201493113 ps
CPU time 2.62 seconds
Started Jan 22 05:02:54 PM PST 24
Finished Jan 22 05:02:59 PM PST 24
Peak memory 208340 kb
Host smart-86a2cb5f-52f3-4f2d-a9dc-ba149cf458bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977112438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3977112438
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.515004188
Short name T251
Test name
Test status
Simulation time 106602783 ps
CPU time 2.49 seconds
Started Jan 22 05:02:52 PM PST 24
Finished Jan 22 05:02:58 PM PST 24
Peak memory 207372 kb
Host smart-bb83b2e0-2a78-466d-b623-9b0705934994
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515004188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.515004188
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.757770262
Short name T620
Test name
Test status
Simulation time 7434924885 ps
CPU time 26.36 seconds
Started Jan 22 05:02:52 PM PST 24
Finished Jan 22 05:03:22 PM PST 24
Peak memory 208128 kb
Host smart-4c8bbdc6-de5e-40ca-93cc-361c985573ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757770262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.757770262
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1616533126
Short name T933
Test name
Test status
Simulation time 900648911 ps
CPU time 6.12 seconds
Started Jan 22 05:02:53 PM PST 24
Finished Jan 22 05:03:02 PM PST 24
Peak memory 208424 kb
Host smart-fee50558-2218-4845-a0dd-da1ba9de2ff4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616533126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1616533126
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1011768132
Short name T762
Test name
Test status
Simulation time 212318937 ps
CPU time 5.04 seconds
Started Jan 22 05:02:53 PM PST 24
Finished Jan 22 05:03:01 PM PST 24
Peak memory 210100 kb
Host smart-6f3a32ca-54d8-4085-b900-4a63cedb832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011768132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1011768132
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3813012849
Short name T880
Test name
Test status
Simulation time 1905060689 ps
CPU time 4.37 seconds
Started Jan 22 05:02:59 PM PST 24
Finished Jan 22 05:03:06 PM PST 24
Peak memory 208352 kb
Host smart-f60d418b-4139-474a-9ae1-1b9e2ca761c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813012849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3813012849
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1081693312
Short name T309
Test name
Test status
Simulation time 1608667066 ps
CPU time 14.98 seconds
Started Jan 22 05:02:53 PM PST 24
Finished Jan 22 05:03:11 PM PST 24
Peak memory 221120 kb
Host smart-6ce27aa7-8c12-466b-be08-3f7575d435e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081693312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1081693312
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2027097605
Short name T624
Test name
Test status
Simulation time 208639070 ps
CPU time 4.52 seconds
Started Jan 22 05:16:50 PM PST 24
Finished Jan 22 05:16:55 PM PST 24
Peak memory 219432 kb
Host smart-cdb55a91-9dce-4307-a403-0345c6f5c836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027097605 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2027097605
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3376674377
Short name T1051
Test name
Test status
Simulation time 58171244 ps
CPU time 2.86 seconds
Started Jan 22 05:02:54 PM PST 24
Finished Jan 22 05:03:00 PM PST 24
Peak memory 207456 kb
Host smart-48cec77d-b5d7-409b-8291-3202b0f5b6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376674377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3376674377
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1446078344
Short name T595
Test name
Test status
Simulation time 52364698 ps
CPU time 2.69 seconds
Started Jan 22 05:02:53 PM PST 24
Finished Jan 22 05:02:59 PM PST 24
Peak memory 209984 kb
Host smart-2cafb058-a052-4609-879f-df1b54908be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446078344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1446078344
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2042758668
Short name T881
Test name
Test status
Simulation time 19695726 ps
CPU time 0.83 seconds
Started Jan 22 05:02:57 PM PST 24
Finished Jan 22 05:03:02 PM PST 24
Peak memory 205852 kb
Host smart-78b46a99-008a-4bf4-97e9-7b5dc0b9c04f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042758668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2042758668
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.102528900
Short name T562
Test name
Test status
Simulation time 254308340 ps
CPU time 3.02 seconds
Started Jan 22 05:02:56 PM PST 24
Finished Jan 22 05:03:04 PM PST 24
Peak memory 210040 kb
Host smart-164aa9bb-7099-4cc2-a29e-13071b75a4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102528900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.102528900
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3678270530
Short name T263
Test name
Test status
Simulation time 253845974 ps
CPU time 6.47 seconds
Started Jan 22 05:02:54 PM PST 24
Finished Jan 22 05:03:03 PM PST 24
Peak memory 214268 kb
Host smart-e892fa93-42d3-4354-9bb7-111df214f7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678270530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3678270530
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2129595655
Short name T1050
Test name
Test status
Simulation time 515588820 ps
CPU time 4.27 seconds
Started Jan 22 05:02:53 PM PST 24
Finished Jan 22 05:03:00 PM PST 24
Peak memory 210864 kb
Host smart-3b601f05-4ae5-48b0-9947-3664b1e1c0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129595655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2129595655
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.673185301
Short name T967
Test name
Test status
Simulation time 115821196 ps
CPU time 3.44 seconds
Started Jan 22 05:02:53 PM PST 24
Finished Jan 22 05:02:59 PM PST 24
Peak memory 207692 kb
Host smart-64983ab7-5fc0-46b2-b22d-823678628e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673185301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.673185301
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3796561307
Short name T692
Test name
Test status
Simulation time 315794748 ps
CPU time 4.28 seconds
Started Jan 22 05:45:32 PM PST 24
Finished Jan 22 05:45:38 PM PST 24
Peak memory 208620 kb
Host smart-ccc25016-a99c-42e8-8ca8-fa1e49d29d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796561307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3796561307
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.700329810
Short name T673
Test name
Test status
Simulation time 1060562587 ps
CPU time 18.66 seconds
Started Jan 22 05:02:56 PM PST 24
Finished Jan 22 05:03:19 PM PST 24
Peak memory 208416 kb
Host smart-f4dd8193-b146-476f-88c8-d267437e2b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700329810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.700329810
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1858924547
Short name T675
Test name
Test status
Simulation time 344749361 ps
CPU time 3.71 seconds
Started Jan 22 05:02:54 PM PST 24
Finished Jan 22 05:03:00 PM PST 24
Peak memory 208832 kb
Host smart-863a993c-6db6-413d-9825-4297f400dbcc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858924547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1858924547
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1357834334
Short name T826
Test name
Test status
Simulation time 745372226 ps
CPU time 8.76 seconds
Started Jan 22 05:02:54 PM PST 24
Finished Jan 22 05:03:05 PM PST 24
Peak memory 208368 kb
Host smart-f28919a0-b77e-43ff-b98b-7b8f39c41c8f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357834334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1357834334
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1558967308
Short name T533
Test name
Test status
Simulation time 337455533 ps
CPU time 2.81 seconds
Started Jan 22 05:02:54 PM PST 24
Finished Jan 22 05:02:59 PM PST 24
Peak memory 207736 kb
Host smart-88514305-fe88-469f-bef4-bc55f8a443e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558967308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1558967308
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.718676552
Short name T371
Test name
Test status
Simulation time 71615505 ps
CPU time 3.18 seconds
Started Jan 22 05:02:56 PM PST 24
Finished Jan 22 05:03:04 PM PST 24
Peak memory 208280 kb
Host smart-b1049c7c-e3d3-4e0e-9e00-f3d7600b710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718676552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.718676552
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2103842224
Short name T681
Test name
Test status
Simulation time 113239231 ps
CPU time 7.49 seconds
Started Jan 22 05:02:58 PM PST 24
Finished Jan 22 05:03:09 PM PST 24
Peak memory 219980 kb
Host smart-b6c210bc-9009-433e-9d24-9fb3dcc85039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103842224 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2103842224
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1005241481
Short name T1029
Test name
Test status
Simulation time 106048312 ps
CPU time 5.63 seconds
Started Jan 22 05:02:53 PM PST 24
Finished Jan 22 05:03:02 PM PST 24
Peak memory 206380 kb
Host smart-5a01045c-be24-4f76-96cf-e4c0948d80d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005241481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1005241481
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2477203768
Short name T998
Test name
Test status
Simulation time 22562688 ps
CPU time 0.78 seconds
Started Jan 22 04:59:31 PM PST 24
Finished Jan 22 04:59:32 PM PST 24
Peak memory 205864 kb
Host smart-f9d8fa24-9ff5-4b02-af0f-86d8ec716af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477203768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2477203768
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3851128825
Short name T833
Test name
Test status
Simulation time 171113993 ps
CPU time 3.21 seconds
Started Jan 22 04:59:17 PM PST 24
Finished Jan 22 04:59:21 PM PST 24
Peak memory 214160 kb
Host smart-1b4d7efa-fc5d-42e1-b774-37398ef22bd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851128825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3851128825
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3284449574
Short name T905
Test name
Test status
Simulation time 297671609 ps
CPU time 3.29 seconds
Started Jan 22 04:59:30 PM PST 24
Finished Jan 22 04:59:33 PM PST 24
Peak memory 216124 kb
Host smart-9520719c-56f3-44c4-9a39-4669fddcca0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284449574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3284449574
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2953771926
Short name T632
Test name
Test status
Simulation time 95723223 ps
CPU time 2.83 seconds
Started Jan 22 04:59:15 PM PST 24
Finished Jan 22 04:59:18 PM PST 24
Peak memory 209336 kb
Host smart-6bfb9b7c-4314-44fb-b2dd-71f114fcb66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953771926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2953771926
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3932850598
Short name T87
Test name
Test status
Simulation time 160082647 ps
CPU time 4.09 seconds
Started Jan 22 04:59:18 PM PST 24
Finished Jan 22 04:59:22 PM PST 24
Peak memory 214264 kb
Host smart-abd05cb9-3c5d-4934-aa76-e9bc02486ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932850598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3932850598
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1718674690
Short name T192
Test name
Test status
Simulation time 186610654 ps
CPU time 7.12 seconds
Started Jan 22 04:59:15 PM PST 24
Finished Jan 22 04:59:22 PM PST 24
Peak memory 222392 kb
Host smart-9f5fc8cd-b7ca-424a-b262-1ce92c8c7fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718674690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1718674690
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.843807743
Short name T736
Test name
Test status
Simulation time 275142491 ps
CPU time 2.72 seconds
Started Jan 22 04:59:15 PM PST 24
Finished Jan 22 04:59:18 PM PST 24
Peak memory 214744 kb
Host smart-e61b79be-3400-4cda-90be-51e8de3a7228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843807743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.843807743
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.589594086
Short name T320
Test name
Test status
Simulation time 160826247 ps
CPU time 3.18 seconds
Started Jan 22 04:59:15 PM PST 24
Finished Jan 22 04:59:19 PM PST 24
Peak memory 209984 kb
Host smart-93395d12-a7a1-48d9-bcd8-d49ff8ec0631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589594086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.589594086
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.612546637
Short name T94
Test name
Test status
Simulation time 3445409738 ps
CPU time 27.75 seconds
Started Jan 22 04:59:36 PM PST 24
Finished Jan 22 05:00:04 PM PST 24
Peak memory 239108 kb
Host smart-dca12705-78f5-4151-a4fa-7b4db3f631cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612546637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.612546637
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2555020039
Short name T702
Test name
Test status
Simulation time 6151030804 ps
CPU time 31.7 seconds
Started Jan 22 04:59:19 PM PST 24
Finished Jan 22 04:59:51 PM PST 24
Peak memory 208524 kb
Host smart-41756804-6c40-4895-8e08-fbf75f20ea77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555020039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2555020039
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.796596107
Short name T781
Test name
Test status
Simulation time 2681636611 ps
CPU time 20.51 seconds
Started Jan 22 04:59:17 PM PST 24
Finished Jan 22 04:59:38 PM PST 24
Peak memory 208148 kb
Host smart-bd073ade-bda6-4d75-9191-8f69a27d4b9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796596107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.796596107
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1255766929
Short name T269
Test name
Test status
Simulation time 31557140 ps
CPU time 2.32 seconds
Started Jan 22 04:59:14 PM PST 24
Finished Jan 22 04:59:17 PM PST 24
Peak memory 206816 kb
Host smart-7961dbe7-e423-4ac8-9c47-8aa8659d6000
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255766929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1255766929
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4010447451
Short name T590
Test name
Test status
Simulation time 57867984 ps
CPU time 3.12 seconds
Started Jan 22 04:59:18 PM PST 24
Finished Jan 22 04:59:22 PM PST 24
Peak memory 207904 kb
Host smart-03af98fa-9142-434f-8279-2757da26c3ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010447451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4010447451
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4030644047
Short name T753
Test name
Test status
Simulation time 106379937 ps
CPU time 4.36 seconds
Started Jan 22 04:59:30 PM PST 24
Finished Jan 22 04:59:35 PM PST 24
Peak memory 217540 kb
Host smart-9947cbfe-5165-436d-88aa-1c0d40532c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030644047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4030644047
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1985332185
Short name T534
Test name
Test status
Simulation time 250710925 ps
CPU time 6.64 seconds
Started Jan 22 04:59:16 PM PST 24
Finished Jan 22 04:59:23 PM PST 24
Peak memory 207776 kb
Host smart-0d381e23-fae3-42d8-aaf4-c41554ce52f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985332185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1985332185
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2839166702
Short name T966
Test name
Test status
Simulation time 613164712 ps
CPU time 7.91 seconds
Started Jan 22 04:59:34 PM PST 24
Finished Jan 22 04:59:43 PM PST 24
Peak memory 222632 kb
Host smart-c007fde6-178e-4f03-a587-4338a666aad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839166702 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2839166702
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.4042200444
Short name T286
Test name
Test status
Simulation time 111131031 ps
CPU time 3.66 seconds
Started Jan 22 04:59:15 PM PST 24
Finished Jan 22 04:59:20 PM PST 24
Peak memory 218264 kb
Host smart-d601d887-0fa6-4706-b27b-6b29ab08b0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042200444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4042200444
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2390913368
Short name T769
Test name
Test status
Simulation time 1551992964 ps
CPU time 5.01 seconds
Started Jan 22 04:59:30 PM PST 24
Finished Jan 22 04:59:35 PM PST 24
Peak memory 209232 kb
Host smart-8f2e00db-8260-4123-b47c-66b627cb057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390913368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2390913368
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2295678551
Short name T752
Test name
Test status
Simulation time 9711238 ps
CPU time 0.87 seconds
Started Jan 22 05:03:03 PM PST 24
Finished Jan 22 05:03:05 PM PST 24
Peak memory 205916 kb
Host smart-498ab565-cdd6-40ec-a7df-0847f65bd4bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295678551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2295678551
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3518892698
Short name T120
Test name
Test status
Simulation time 40552479877 ps
CPU time 138.3 seconds
Started Jan 22 05:03:11 PM PST 24
Finished Jan 22 05:05:33 PM PST 24
Peak memory 214772 kb
Host smart-277df1e5-9106-4324-8f55-6184a635d1bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518892698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3518892698
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3701488485
Short name T1002
Test name
Test status
Simulation time 489646654 ps
CPU time 3.78 seconds
Started Jan 22 05:03:01 PM PST 24
Finished Jan 22 05:03:06 PM PST 24
Peak memory 207064 kb
Host smart-cd78b186-3bcd-4d04-abf5-80a050471a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701488485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3701488485
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1806050950
Short name T761
Test name
Test status
Simulation time 129930174 ps
CPU time 4.54 seconds
Started Jan 22 05:42:20 PM PST 24
Finished Jan 22 05:42:26 PM PST 24
Peak memory 220252 kb
Host smart-3d2d131b-e8e3-4f88-83ba-5b8c8dadd6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806050950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1806050950
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2790747375
Short name T812
Test name
Test status
Simulation time 84287999 ps
CPU time 4.21 seconds
Started Jan 22 05:02:58 PM PST 24
Finished Jan 22 05:03:05 PM PST 24
Peak memory 210040 kb
Host smart-cacb22e5-b7de-4200-8e13-d9c0c82bebc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790747375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2790747375
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2518395418
Short name T1043
Test name
Test status
Simulation time 1170292992 ps
CPU time 5.23 seconds
Started Jan 22 05:02:59 PM PST 24
Finished Jan 22 05:03:07 PM PST 24
Peak memory 208104 kb
Host smart-6b001e1a-9462-452c-b2a9-f1f11f4639eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518395418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2518395418
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2971461551
Short name T660
Test name
Test status
Simulation time 34245675 ps
CPU time 2.45 seconds
Started Jan 22 05:03:06 PM PST 24
Finished Jan 22 05:03:17 PM PST 24
Peak memory 206780 kb
Host smart-c2bb41a1-d424-4a28-89fe-82143ba2b78d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971461551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2971461551
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.647755306
Short name T936
Test name
Test status
Simulation time 280679578 ps
CPU time 10.44 seconds
Started Jan 22 05:02:58 PM PST 24
Finished Jan 22 05:03:11 PM PST 24
Peak memory 208692 kb
Host smart-088e5153-046f-42ef-a826-67aa0b6bd453
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647755306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.647755306
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2863800667
Short name T628
Test name
Test status
Simulation time 370472232 ps
CPU time 3.6 seconds
Started Jan 22 05:03:03 PM PST 24
Finished Jan 22 05:03:08 PM PST 24
Peak memory 206748 kb
Host smart-7b40d409-4fe7-440b-9e8e-b6403e1672f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863800667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2863800667
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2321422552
Short name T246
Test name
Test status
Simulation time 303196622 ps
CPU time 3.48 seconds
Started Jan 22 05:03:00 PM PST 24
Finished Jan 22 05:03:05 PM PST 24
Peak memory 218224 kb
Host smart-9940966e-9c42-4747-95d3-a8fd452a0f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321422552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2321422552
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2446204878
Short name T532
Test name
Test status
Simulation time 73166829 ps
CPU time 1.84 seconds
Started Jan 22 05:03:08 PM PST 24
Finished Jan 22 05:03:16 PM PST 24
Peak memory 206704 kb
Host smart-deea3ace-2e6d-4044-9c1e-c292a37d3519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446204878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2446204878
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.697882351
Short name T832
Test name
Test status
Simulation time 529241523 ps
CPU time 15.65 seconds
Started Jan 22 05:03:02 PM PST 24
Finished Jan 22 05:03:18 PM PST 24
Peak memory 222504 kb
Host smart-d2e096c5-d977-4fe5-a61a-21e54710164e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697882351 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.697882351
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.4140386527
Short name T827
Test name
Test status
Simulation time 95323863 ps
CPU time 3.74 seconds
Started Jan 22 05:03:01 PM PST 24
Finished Jan 22 05:03:06 PM PST 24
Peak memory 207628 kb
Host smart-b0695955-0b1b-455a-8f42-79e04f77c60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140386527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.4140386527
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1322336806
Short name T1033
Test name
Test status
Simulation time 357587112 ps
CPU time 2.34 seconds
Started Jan 22 05:02:59 PM PST 24
Finished Jan 22 05:03:04 PM PST 24
Peak memory 209820 kb
Host smart-af92bbb5-829a-4dde-9158-d4b61b047a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322336806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1322336806
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.4005728347
Short name T1020
Test name
Test status
Simulation time 33150017 ps
CPU time 0.71 seconds
Started Jan 22 05:36:07 PM PST 24
Finished Jan 22 05:36:19 PM PST 24
Peak memory 205916 kb
Host smart-eb547004-e299-4d1c-a5ab-8c6c66864e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005728347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.4005728347
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3981918141
Short name T268
Test name
Test status
Simulation time 249210470 ps
CPU time 4.85 seconds
Started Jan 22 05:03:12 PM PST 24
Finished Jan 22 05:03:20 PM PST 24
Peak memory 214484 kb
Host smart-7fa39e47-264d-4f65-9e24-2d7348f06277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981918141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3981918141
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.60550975
Short name T760
Test name
Test status
Simulation time 274290833 ps
CPU time 3.88 seconds
Started Jan 22 05:03:11 PM PST 24
Finished Jan 22 05:03:19 PM PST 24
Peak memory 207968 kb
Host smart-f67097c2-b949-4d9d-92f3-6084848e1fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60550975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.60550975
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1821176080
Short name T917
Test name
Test status
Simulation time 202952664 ps
CPU time 5.3 seconds
Started Jan 22 05:03:14 PM PST 24
Finished Jan 22 05:03:25 PM PST 24
Peak memory 210232 kb
Host smart-09065f7e-e02c-438b-960f-e1fd99bf093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821176080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1821176080
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.4266640728
Short name T706
Test name
Test status
Simulation time 3503596930 ps
CPU time 37.31 seconds
Started Jan 22 05:03:11 PM PST 24
Finished Jan 22 05:03:52 PM PST 24
Peak memory 214392 kb
Host smart-3a832b2e-1cfb-45eb-89de-b89a87998f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266640728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.4266640728
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3063433874
Short name T748
Test name
Test status
Simulation time 659765934 ps
CPU time 3.37 seconds
Started Jan 22 05:03:07 PM PST 24
Finished Jan 22 05:03:18 PM PST 24
Peak memory 209864 kb
Host smart-0b360ee4-5ebf-4adc-8b0a-456cfaa06129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063433874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3063433874
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.73305099
Short name T981
Test name
Test status
Simulation time 240106346 ps
CPU time 3.43 seconds
Started Jan 22 05:03:06 PM PST 24
Finished Jan 22 05:03:18 PM PST 24
Peak memory 207212 kb
Host smart-027486d4-38e9-4204-a665-53248b8586ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73305099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.73305099
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3400139818
Short name T5
Test name
Test status
Simulation time 182321164 ps
CPU time 4.72 seconds
Started Jan 22 05:03:06 PM PST 24
Finished Jan 22 05:03:19 PM PST 24
Peak memory 207960 kb
Host smart-5d59fb0e-633a-45b8-b998-0dae765070c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400139818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3400139818
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3347580740
Short name T1025
Test name
Test status
Simulation time 414362144 ps
CPU time 3.81 seconds
Started Jan 22 05:03:09 PM PST 24
Finished Jan 22 05:03:18 PM PST 24
Peak memory 208880 kb
Host smart-3c425262-9ee5-408d-904b-14dbdda4c90d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347580740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3347580740
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1459515264
Short name T938
Test name
Test status
Simulation time 102760976 ps
CPU time 3.18 seconds
Started Jan 22 05:03:04 PM PST 24
Finished Jan 22 05:03:16 PM PST 24
Peak memory 206836 kb
Host smart-fc2283e7-3551-4ed1-bcb1-be3b9a635304
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459515264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1459515264
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1151133154
Short name T742
Test name
Test status
Simulation time 91476592 ps
CPU time 4.36 seconds
Started Jan 22 05:03:09 PM PST 24
Finished Jan 22 05:03:19 PM PST 24
Peak memory 208580 kb
Host smart-83da8c50-2806-4288-b195-906126eaca6c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151133154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1151133154
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.4231391246
Short name T921
Test name
Test status
Simulation time 106233992 ps
CPU time 4.44 seconds
Started Jan 22 05:03:15 PM PST 24
Finished Jan 22 05:03:25 PM PST 24
Peak memory 210308 kb
Host smart-d059e837-b951-4206-a913-d0b3b0c3eeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231391246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4231391246
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.287614328
Short name T670
Test name
Test status
Simulation time 4457544560 ps
CPU time 43.62 seconds
Started Jan 22 05:03:06 PM PST 24
Finished Jan 22 05:03:58 PM PST 24
Peak memory 208312 kb
Host smart-b8707e43-adb6-4a7f-b2ab-a164076b0206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287614328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.287614328
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2693493706
Short name T273
Test name
Test status
Simulation time 861376027 ps
CPU time 31.07 seconds
Started Jan 22 05:03:07 PM PST 24
Finished Jan 22 05:03:46 PM PST 24
Peak memory 222404 kb
Host smart-b0e385b6-b140-48d5-968e-bd8a4f9b936b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693493706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2693493706
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.773989738
Short name T237
Test name
Test status
Simulation time 88374247 ps
CPU time 6.38 seconds
Started Jan 22 05:03:17 PM PST 24
Finished Jan 22 05:03:28 PM PST 24
Peak memory 219960 kb
Host smart-ec08e988-90be-491d-8b92-857e4e76900c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773989738 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.773989738
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.500780256
Short name T647
Test name
Test status
Simulation time 567859910 ps
CPU time 12.94 seconds
Started Jan 22 05:38:10 PM PST 24
Finished Jan 22 05:38:23 PM PST 24
Peak memory 210368 kb
Host smart-69693c6e-0b7a-4b80-84fc-948ad3d978dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500780256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.500780256
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.94513133
Short name T639
Test name
Test status
Simulation time 386564871 ps
CPU time 3.05 seconds
Started Jan 22 05:03:12 PM PST 24
Finished Jan 22 05:03:18 PM PST 24
Peak memory 209812 kb
Host smart-ea1c05c3-1216-493f-890a-5e4d72b904fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94513133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.94513133
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.118686156
Short name T855
Test name
Test status
Simulation time 11799986 ps
CPU time 0.74 seconds
Started Jan 22 05:03:44 PM PST 24
Finished Jan 22 05:03:46 PM PST 24
Peak memory 205872 kb
Host smart-46a0c9bf-0f43-4c72-bc17-c758ced66d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118686156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.118686156
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.202983512
Short name T248
Test name
Test status
Simulation time 65059241 ps
CPU time 3.98 seconds
Started Jan 22 05:03:17 PM PST 24
Finished Jan 22 05:03:26 PM PST 24
Peak memory 214336 kb
Host smart-b61bda66-d020-4f17-86dd-483bc2cd4da8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202983512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.202983512
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.348873900
Short name T928
Test name
Test status
Simulation time 127224067 ps
CPU time 2.75 seconds
Started Jan 22 05:34:06 PM PST 24
Finished Jan 22 05:34:22 PM PST 24
Peak memory 214596 kb
Host smart-e554ecd5-f71d-4de5-b68d-72a426ad7800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348873900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.348873900
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.94890333
Short name T873
Test name
Test status
Simulation time 219981763 ps
CPU time 5.92 seconds
Started Jan 22 05:32:23 PM PST 24
Finished Jan 22 05:32:37 PM PST 24
Peak memory 208012 kb
Host smart-d79cb3bc-7d4d-4ad4-b581-32ca7a514286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94890333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.94890333
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3460841423
Short name T241
Test name
Test status
Simulation time 6701358856 ps
CPU time 55.6 seconds
Started Jan 22 05:40:02 PM PST 24
Finished Jan 22 05:40:59 PM PST 24
Peak memory 212360 kb
Host smart-0468f33f-0db3-4466-9bab-462c5f515bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460841423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3460841423
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3324764675
Short name T292
Test name
Test status
Simulation time 282176047 ps
CPU time 4.18 seconds
Started Jan 22 05:28:03 PM PST 24
Finished Jan 22 05:28:16 PM PST 24
Peak memory 209808 kb
Host smart-6f2d1984-31fc-488e-b6d0-45f1fc77eebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324764675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3324764675
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2096739218
Short name T203
Test name
Test status
Simulation time 340056887 ps
CPU time 3.95 seconds
Started Jan 22 06:25:36 PM PST 24
Finished Jan 22 06:25:41 PM PST 24
Peak memory 209468 kb
Host smart-04f63f0b-d503-4b1a-bcb4-f26ed87e513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096739218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2096739218
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.68098801
Short name T335
Test name
Test status
Simulation time 174454876 ps
CPU time 4.57 seconds
Started Jan 22 05:14:49 PM PST 24
Finished Jan 22 05:14:55 PM PST 24
Peak memory 218232 kb
Host smart-e5ee36e4-f1e3-4e3a-b686-9ce680b0979e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68098801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.68098801
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2462914390
Short name T741
Test name
Test status
Simulation time 859683444 ps
CPU time 28.89 seconds
Started Jan 22 05:03:18 PM PST 24
Finished Jan 22 05:03:51 PM PST 24
Peak memory 207820 kb
Host smart-ca308e6f-3514-4447-84d2-a73b92a8cb39
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462914390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2462914390
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1498981035
Short name T1034
Test name
Test status
Simulation time 187020414 ps
CPU time 4.23 seconds
Started Jan 22 05:42:22 PM PST 24
Finished Jan 22 05:42:27 PM PST 24
Peak memory 208804 kb
Host smart-849c4bab-b1df-43ff-96d1-3bfba2bd9ff6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498981035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1498981035
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1949635960
Short name T544
Test name
Test status
Simulation time 240430417 ps
CPU time 1.97 seconds
Started Jan 22 05:03:16 PM PST 24
Finished Jan 22 05:03:24 PM PST 24
Peak memory 206832 kb
Host smart-a4f05873-e443-4b7a-9817-c505f27153c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949635960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1949635960
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.230365134
Short name T614
Test name
Test status
Simulation time 79336140 ps
CPU time 3.36 seconds
Started Jan 22 05:03:18 PM PST 24
Finished Jan 22 05:03:25 PM PST 24
Peak memory 208572 kb
Host smart-8a3e13c3-ec95-4bdb-a9ec-ab2dacb360c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230365134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.230365134
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2722118497
Short name T542
Test name
Test status
Simulation time 428395177 ps
CPU time 2.68 seconds
Started Jan 22 05:03:18 PM PST 24
Finished Jan 22 05:03:24 PM PST 24
Peak memory 206668 kb
Host smart-acbcb316-f8ad-4ec3-ad34-b2b604cef6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722118497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2722118497
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3832504923
Short name T960
Test name
Test status
Simulation time 1100835659 ps
CPU time 3.6 seconds
Started Jan 22 05:03:39 PM PST 24
Finished Jan 22 05:03:43 PM PST 24
Peak memory 222312 kb
Host smart-b5631ea2-61cd-4613-8673-5bec2d482f32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832504923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3832504923
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3613830192
Short name T1015
Test name
Test status
Simulation time 227506294 ps
CPU time 4.53 seconds
Started Jan 22 05:03:44 PM PST 24
Finished Jan 22 05:03:49 PM PST 24
Peak memory 222476 kb
Host smart-fd66b4a2-ad85-4d35-bd37-1d890b5ad825
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613830192 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3613830192
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.4231757173
Short name T326
Test name
Test status
Simulation time 56092214 ps
CPU time 3.59 seconds
Started Jan 22 05:03:21 PM PST 24
Finished Jan 22 05:03:28 PM PST 24
Peak memory 210064 kb
Host smart-9fd05228-9416-4ae0-aa5f-6af89468c9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231757173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.4231757173
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3972540850
Short name T746
Test name
Test status
Simulation time 376304968 ps
CPU time 2.89 seconds
Started Jan 22 05:03:18 PM PST 24
Finished Jan 22 05:03:25 PM PST 24
Peak memory 209984 kb
Host smart-8ffb4957-3f81-4d45-b407-e32f25f7d2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972540850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3972540850
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.697276789
Short name T578
Test name
Test status
Simulation time 66260976 ps
CPU time 0.89 seconds
Started Jan 22 05:03:55 PM PST 24
Finished Jan 22 05:03:58 PM PST 24
Peak memory 205544 kb
Host smart-ebf8f58d-36b5-4df0-a0d2-4ee8081ce916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697276789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.697276789
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1563988749
Short name T940
Test name
Test status
Simulation time 1544165659 ps
CPU time 38.68 seconds
Started Jan 22 05:03:43 PM PST 24
Finished Jan 22 05:04:22 PM PST 24
Peak memory 221896 kb
Host smart-2f2f85b3-47e5-458a-b2ad-fb913de973ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563988749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1563988749
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3103478928
Short name T616
Test name
Test status
Simulation time 487527049 ps
CPU time 3.79 seconds
Started Jan 22 05:03:47 PM PST 24
Finished Jan 22 05:03:52 PM PST 24
Peak memory 206760 kb
Host smart-f32d85fc-5e5d-4c0c-b09c-eb60dad057d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103478928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3103478928
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2396975885
Short name T795
Test name
Test status
Simulation time 340190591 ps
CPU time 8.14 seconds
Started Jan 22 05:03:44 PM PST 24
Finished Jan 22 05:03:53 PM PST 24
Peak memory 220364 kb
Host smart-53f0103d-d829-480f-9fe6-4ba79dc5a118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396975885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2396975885
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.397779042
Short name T283
Test name
Test status
Simulation time 154665267 ps
CPU time 5.36 seconds
Started Jan 22 05:03:41 PM PST 24
Finished Jan 22 05:03:47 PM PST 24
Peak memory 214168 kb
Host smart-5c216f81-2797-4345-ae54-6c1c1bfe9912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397779042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.397779042
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1372197911
Short name T570
Test name
Test status
Simulation time 253329686 ps
CPU time 2.91 seconds
Started Jan 22 05:03:44 PM PST 24
Finished Jan 22 05:03:47 PM PST 24
Peak memory 208288 kb
Host smart-0deadc42-0dec-4a09-8c5f-4a78ba982a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372197911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1372197911
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1085887133
Short name T729
Test name
Test status
Simulation time 151093612 ps
CPU time 3.67 seconds
Started Jan 22 05:03:41 PM PST 24
Finished Jan 22 05:03:46 PM PST 24
Peak memory 207492 kb
Host smart-f8ad7611-f785-4250-b5fe-ce7d3eb9328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085887133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1085887133
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.62552634
Short name T664
Test name
Test status
Simulation time 896496710 ps
CPU time 5.35 seconds
Started Jan 22 05:03:44 PM PST 24
Finished Jan 22 05:03:50 PM PST 24
Peak memory 208444 kb
Host smart-a7818841-17ce-48e2-80de-0b63f7b2353e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62552634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.62552634
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1790712770
Short name T661
Test name
Test status
Simulation time 1999938169 ps
CPU time 16.51 seconds
Started Jan 22 05:03:36 PM PST 24
Finished Jan 22 05:03:53 PM PST 24
Peak memory 208356 kb
Host smart-17c2f995-e228-4e13-bd47-fe80761aebce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790712770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1790712770
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4076332079
Short name T771
Test name
Test status
Simulation time 623559879 ps
CPU time 22.62 seconds
Started Jan 22 05:03:35 PM PST 24
Finished Jan 22 05:03:58 PM PST 24
Peak memory 208752 kb
Host smart-1061a134-a210-4dd3-ae37-cfd17864884c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076332079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4076332079
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3716556020
Short name T957
Test name
Test status
Simulation time 708342295 ps
CPU time 19.05 seconds
Started Jan 22 05:03:48 PM PST 24
Finished Jan 22 05:04:13 PM PST 24
Peak memory 208988 kb
Host smart-8c6247ef-227e-43eb-8b99-707d99e09468
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716556020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3716556020
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.379216515
Short name T944
Test name
Test status
Simulation time 4546831627 ps
CPU time 24.03 seconds
Started Jan 22 05:03:45 PM PST 24
Finished Jan 22 05:04:09 PM PST 24
Peak memory 219336 kb
Host smart-d67a0650-e39c-43dc-8b61-51c18502b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379216515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.379216515
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2508106783
Short name T759
Test name
Test status
Simulation time 1145615713 ps
CPU time 32.76 seconds
Started Jan 22 05:03:38 PM PST 24
Finished Jan 22 05:04:12 PM PST 24
Peak memory 208208 kb
Host smart-a7377124-46dc-4306-939a-80528e4dd75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508106783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2508106783
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1760001560
Short name T1048
Test name
Test status
Simulation time 153927610 ps
CPU time 3.94 seconds
Started Jan 22 05:03:44 PM PST 24
Finished Jan 22 05:03:48 PM PST 24
Peak memory 207740 kb
Host smart-921693e5-221c-4b29-a09d-050a06077552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760001560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1760001560
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2559486494
Short name T1022
Test name
Test status
Simulation time 516549582 ps
CPU time 4.76 seconds
Started Jan 22 05:03:46 PM PST 24
Finished Jan 22 05:03:52 PM PST 24
Peak memory 210332 kb
Host smart-551eae51-7a5e-4211-9785-d3445535dc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559486494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2559486494
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.839840264
Short name T596
Test name
Test status
Simulation time 51949303 ps
CPU time 0.76 seconds
Started Jan 22 05:04:00 PM PST 24
Finished Jan 22 05:04:02 PM PST 24
Peak memory 205908 kb
Host smart-2b53d066-8a9a-459a-b3ac-4d8bcc243f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839840264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.839840264
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3351574720
Short name T381
Test name
Test status
Simulation time 52050282 ps
CPU time 3.93 seconds
Started Jan 22 05:04:01 PM PST 24
Finished Jan 22 05:04:06 PM PST 24
Peak memory 214276 kb
Host smart-95c95160-46a0-4f1a-a900-d4b1d174ecbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3351574720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3351574720
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.152819852
Short name T553
Test name
Test status
Simulation time 1683814569 ps
CPU time 13.5 seconds
Started Jan 22 05:04:03 PM PST 24
Finished Jan 22 05:04:17 PM PST 24
Peak memory 222404 kb
Host smart-2bae713b-c153-4b34-bebb-828fafe31bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152819852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.152819852
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2595034198
Short name T395
Test name
Test status
Simulation time 84051812 ps
CPU time 2.91 seconds
Started Jan 22 05:03:56 PM PST 24
Finished Jan 22 05:04:01 PM PST 24
Peak memory 207848 kb
Host smart-4dafad33-b63e-4beb-836c-d24f0b6399b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595034198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2595034198
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1650517613
Short name T368
Test name
Test status
Simulation time 377122351 ps
CPU time 6.74 seconds
Started Jan 22 05:04:00 PM PST 24
Finished Jan 22 05:04:07 PM PST 24
Peak memory 208024 kb
Host smart-8ed071a6-3d61-470b-8253-44ddb41ee8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650517613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1650517613
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.4080928491
Short name T48
Test name
Test status
Simulation time 261464318 ps
CPU time 6.85 seconds
Started Jan 22 05:03:55 PM PST 24
Finished Jan 22 05:04:04 PM PST 24
Peak memory 222340 kb
Host smart-81f3002f-8e89-4ad9-ba7e-aa4782e47bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080928491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.4080928491
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1573714430
Short name T397
Test name
Test status
Simulation time 120673764 ps
CPU time 4.69 seconds
Started Jan 22 05:04:03 PM PST 24
Finished Jan 22 05:04:08 PM PST 24
Peak memory 214888 kb
Host smart-932bbf99-777a-41a5-b0c1-2f2b0e19d6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573714430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1573714430
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2949587455
Short name T899
Test name
Test status
Simulation time 976308804 ps
CPU time 5 seconds
Started Jan 22 05:04:01 PM PST 24
Finished Jan 22 05:04:07 PM PST 24
Peak memory 209768 kb
Host smart-abdb0168-9154-4a22-957f-bf3d01c52256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949587455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2949587455
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3689546693
Short name T982
Test name
Test status
Simulation time 153846049 ps
CPU time 2.5 seconds
Started Jan 22 05:03:55 PM PST 24
Finished Jan 22 05:04:00 PM PST 24
Peak memory 206500 kb
Host smart-a30a2f94-e564-4176-a083-9e55e0bc4576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689546693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3689546693
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2942718708
Short name T1019
Test name
Test status
Simulation time 337956576 ps
CPU time 3.97 seconds
Started Jan 22 05:03:57 PM PST 24
Finished Jan 22 05:04:02 PM PST 24
Peak memory 208748 kb
Host smart-99c81c34-33cf-4047-9209-277129dc952a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942718708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2942718708
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1637182449
Short name T348
Test name
Test status
Simulation time 157989823 ps
CPU time 2.52 seconds
Started Jan 22 05:04:01 PM PST 24
Finished Jan 22 05:04:05 PM PST 24
Peak memory 206860 kb
Host smart-17682a11-2d31-48f0-acff-4d25540007be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637182449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1637182449
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3242151938
Short name T96
Test name
Test status
Simulation time 84130084 ps
CPU time 2.45 seconds
Started Jan 22 05:04:01 PM PST 24
Finished Jan 22 05:04:04 PM PST 24
Peak memory 207560 kb
Host smart-a4aa438b-7c36-4076-8eb3-c1cbae1cda98
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242151938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3242151938
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1255706145
Short name T931
Test name
Test status
Simulation time 647454810 ps
CPU time 11.55 seconds
Started Jan 22 05:03:58 PM PST 24
Finished Jan 22 05:04:10 PM PST 24
Peak memory 209704 kb
Host smart-fccb727a-68a9-498b-a6d8-e6df416705d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255706145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1255706145
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.218460586
Short name T715
Test name
Test status
Simulation time 83820879 ps
CPU time 3.48 seconds
Started Jan 22 05:04:01 PM PST 24
Finished Jan 22 05:04:05 PM PST 24
Peak memory 208100 kb
Host smart-ee5cac9b-be91-4d34-828d-d20dde1480dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218460586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.218460586
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.162761255
Short name T257
Test name
Test status
Simulation time 835188605 ps
CPU time 10.45 seconds
Started Jan 22 05:04:00 PM PST 24
Finished Jan 22 05:04:11 PM PST 24
Peak memory 220548 kb
Host smart-b100232c-70f6-457f-84a9-e5f6eac78643
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162761255 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.162761255
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3837346243
Short name T646
Test name
Test status
Simulation time 2687969226 ps
CPU time 11.21 seconds
Started Jan 22 05:03:57 PM PST 24
Finished Jan 22 05:04:09 PM PST 24
Peak memory 214344 kb
Host smart-7223dd14-e210-4a11-adb9-c022e4a3b3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837346243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3837346243
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.452483808
Short name T370
Test name
Test status
Simulation time 129903535 ps
CPU time 3.05 seconds
Started Jan 22 05:04:00 PM PST 24
Finished Jan 22 05:04:03 PM PST 24
Peak memory 210264 kb
Host smart-cd837bae-4dcd-42d6-b133-94d96c27fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452483808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.452483808
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1735085446
Short name T737
Test name
Test status
Simulation time 12870043 ps
CPU time 0.87 seconds
Started Jan 22 05:04:03 PM PST 24
Finished Jan 22 05:04:05 PM PST 24
Peak memory 205856 kb
Host smart-17854d0e-a4d5-481e-bc32-0dc8bf4b9d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735085446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1735085446
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3592526012
Short name T304
Test name
Test status
Simulation time 1305782299 ps
CPU time 68.25 seconds
Started Jan 22 05:03:56 PM PST 24
Finished Jan 22 05:05:06 PM PST 24
Peak memory 214248 kb
Host smart-c319aed0-445a-4e9d-902e-780d83a47e54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3592526012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3592526012
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1779074395
Short name T27
Test name
Test status
Simulation time 352841313 ps
CPU time 5.18 seconds
Started Jan 22 05:04:07 PM PST 24
Finished Jan 22 05:04:13 PM PST 24
Peak memory 222776 kb
Host smart-2a37ac71-96b5-4460-9c36-81a940965c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779074395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1779074395
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3545191942
Short name T559
Test name
Test status
Simulation time 2214087446 ps
CPU time 12.56 seconds
Started Jan 22 05:04:08 PM PST 24
Finished Jan 22 05:04:21 PM PST 24
Peak memory 208560 kb
Host smart-795ef964-5935-4e66-b4ba-bea4b4ea62eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545191942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3545191942
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.131352319
Short name T77
Test name
Test status
Simulation time 181665899 ps
CPU time 3.32 seconds
Started Jan 22 05:04:01 PM PST 24
Finished Jan 22 05:04:05 PM PST 24
Peak memory 214300 kb
Host smart-8c48f8f8-180d-4206-b960-448aa208dbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131352319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.131352319
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.4215154142
Short name T197
Test name
Test status
Simulation time 1460458372 ps
CPU time 7.97 seconds
Started Jan 22 05:04:08 PM PST 24
Finished Jan 22 05:04:16 PM PST 24
Peak memory 210872 kb
Host smart-f878c105-31c7-43d4-82e7-b3f37f47f9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215154142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.4215154142
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3566623204
Short name T391
Test name
Test status
Simulation time 50794551 ps
CPU time 2.13 seconds
Started Jan 22 05:04:08 PM PST 24
Finished Jan 22 05:04:11 PM PST 24
Peak memory 215272 kb
Host smart-fc4535c9-e26b-45be-9c82-055dc0610b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566623204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3566623204
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.4102235105
Short name T980
Test name
Test status
Simulation time 133062595 ps
CPU time 2.8 seconds
Started Jan 22 05:03:56 PM PST 24
Finished Jan 22 05:04:01 PM PST 24
Peak memory 207740 kb
Host smart-83aad09c-0582-4de4-867d-89ca444b2623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102235105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.4102235105
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1858726667
Short name T638
Test name
Test status
Simulation time 118068687 ps
CPU time 2.41 seconds
Started Jan 22 05:03:55 PM PST 24
Finished Jan 22 05:04:00 PM PST 24
Peak memory 206700 kb
Host smart-29690a59-fe4a-4c93-8ec5-a1d01164d581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858726667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1858726667
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.111053012
Short name T201
Test name
Test status
Simulation time 99334707 ps
CPU time 4.48 seconds
Started Jan 22 05:04:00 PM PST 24
Finished Jan 22 05:04:05 PM PST 24
Peak memory 208860 kb
Host smart-c78e01a4-f98d-4155-9a28-6d96c9f000cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111053012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.111053012
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2032519558
Short name T361
Test name
Test status
Simulation time 199882041 ps
CPU time 2.66 seconds
Started Jan 22 05:04:03 PM PST 24
Finished Jan 22 05:04:06 PM PST 24
Peak memory 207000 kb
Host smart-d320e40c-b0ea-429e-8c6c-bc7e0bdb23fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032519558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2032519558
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.143510073
Short name T808
Test name
Test status
Simulation time 2743068374 ps
CPU time 49.88 seconds
Started Jan 22 05:03:55 PM PST 24
Finished Jan 22 05:04:47 PM PST 24
Peak memory 208416 kb
Host smart-81003190-5c1c-43a4-a896-cda6ddb300a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143510073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.143510073
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1312345923
Short name T1044
Test name
Test status
Simulation time 686995549 ps
CPU time 17.53 seconds
Started Jan 22 05:04:07 PM PST 24
Finished Jan 22 05:04:25 PM PST 24
Peak memory 218040 kb
Host smart-e401c6aa-d04e-4265-9d8f-19c518709370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312345923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1312345923
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.193819316
Short name T824
Test name
Test status
Simulation time 81553934 ps
CPU time 1.81 seconds
Started Jan 22 05:04:03 PM PST 24
Finished Jan 22 05:04:05 PM PST 24
Peak memory 206804 kb
Host smart-b2a06ab4-be94-42ce-a8d8-ff63f4291fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193819316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.193819316
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.256792218
Short name T126
Test name
Test status
Simulation time 118255796 ps
CPU time 5.16 seconds
Started Jan 22 05:04:08 PM PST 24
Finished Jan 22 05:04:14 PM PST 24
Peak memory 207936 kb
Host smart-0f989d2c-1537-4315-af6a-d34be8617f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256792218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.256792218
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3800087061
Short name T162
Test name
Test status
Simulation time 302645556 ps
CPU time 3.27 seconds
Started Jan 22 05:03:55 PM PST 24
Finished Jan 22 05:04:01 PM PST 24
Peak memory 209920 kb
Host smart-8d879b7d-4430-4d07-b3af-bf04cfe9a9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800087061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3800087061
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2774556520
Short name T98
Test name
Test status
Simulation time 29080203 ps
CPU time 0.83 seconds
Started Jan 22 05:04:10 PM PST 24
Finished Jan 22 05:04:11 PM PST 24
Peak memory 205860 kb
Host smart-990402b1-37c3-48de-bcaf-c6a471655684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774556520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2774556520
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.27988847
Short name T33
Test name
Test status
Simulation time 3914071149 ps
CPU time 29.3 seconds
Started Jan 22 05:04:03 PM PST 24
Finished Jan 22 05:04:33 PM PST 24
Peak memory 222808 kb
Host smart-1de00fea-3b5e-4639-b8a7-ca2ffed1f65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27988847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.27988847
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.26269073
Short name T277
Test name
Test status
Simulation time 94870159 ps
CPU time 2.61 seconds
Started Jan 22 05:04:03 PM PST 24
Finished Jan 22 05:04:06 PM PST 24
Peak memory 209532 kb
Host smart-7ae2f209-f256-465a-ab4d-170690300248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26269073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.26269073
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.139552230
Short name T83
Test name
Test status
Simulation time 597943646 ps
CPU time 3.41 seconds
Started Jan 22 05:03:59 PM PST 24
Finished Jan 22 05:04:03 PM PST 24
Peak memory 208884 kb
Host smart-d909a48c-3866-49a6-8056-d7c31ebd47ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139552230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.139552230
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4292347962
Short name T333
Test name
Test status
Simulation time 176536175 ps
CPU time 6.85 seconds
Started Jan 22 05:04:11 PM PST 24
Finished Jan 22 05:04:18 PM PST 24
Peak memory 222408 kb
Host smart-51a35b07-6f34-472e-8519-2fdf08bbe879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292347962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4292347962
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.436934411
Short name T305
Test name
Test status
Simulation time 89712807 ps
CPU time 3.76 seconds
Started Jan 22 05:04:03 PM PST 24
Finished Jan 22 05:04:07 PM PST 24
Peak memory 209404 kb
Host smart-04b73b97-49b2-484b-b433-2d0b5f6440f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436934411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.436934411
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.591078878
Short name T945
Test name
Test status
Simulation time 69634969 ps
CPU time 3.51 seconds
Started Jan 22 05:03:54 PM PST 24
Finished Jan 22 05:04:01 PM PST 24
Peak memory 208332 kb
Host smart-ff11f508-bf76-4ae9-8030-a3a09afb7d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591078878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.591078878
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3000603810
Short name T226
Test name
Test status
Simulation time 131650995 ps
CPU time 2.37 seconds
Started Jan 22 05:04:01 PM PST 24
Finished Jan 22 05:04:04 PM PST 24
Peak memory 206624 kb
Host smart-d68b4640-5b63-45e2-ac83-e105383eafd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000603810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3000603810
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.4262572178
Short name T1049
Test name
Test status
Simulation time 60447831 ps
CPU time 3.17 seconds
Started Jan 22 05:03:53 PM PST 24
Finished Jan 22 05:03:57 PM PST 24
Peak memory 208268 kb
Host smart-a2aca2d6-07ff-4b93-9cf2-90d43a9788b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262572178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.4262572178
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.4287821226
Short name T642
Test name
Test status
Simulation time 19329670420 ps
CPU time 37.03 seconds
Started Jan 22 05:04:02 PM PST 24
Finished Jan 22 05:04:40 PM PST 24
Peak memory 208740 kb
Host smart-8e11ccec-107a-40c7-923a-1f91d2723511
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287821226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.4287821226
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1022036773
Short name T15
Test name
Test status
Simulation time 1300617932 ps
CPU time 10.84 seconds
Started Jan 22 05:03:59 PM PST 24
Finished Jan 22 05:04:10 PM PST 24
Peak memory 207872 kb
Host smart-f8e9ae50-acda-466c-99f0-4d71667a391e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022036773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1022036773
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.305930251
Short name T537
Test name
Test status
Simulation time 362951042 ps
CPU time 2.46 seconds
Started Jan 22 05:04:11 PM PST 24
Finished Jan 22 05:04:14 PM PST 24
Peak memory 208108 kb
Host smart-a16ef7d5-030f-4ecb-8274-7dc7ac15d4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305930251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.305930251
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1468721476
Short name T540
Test name
Test status
Simulation time 765027041 ps
CPU time 3.94 seconds
Started Jan 22 05:04:01 PM PST 24
Finished Jan 22 05:04:06 PM PST 24
Peak memory 208580 kb
Host smart-02cf9742-46ea-4ad4-b045-defd893cee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468721476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1468721476
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3457991855
Short name T390
Test name
Test status
Simulation time 126011906 ps
CPU time 4.75 seconds
Started Jan 22 05:04:07 PM PST 24
Finished Jan 22 05:04:12 PM PST 24
Peak memory 218712 kb
Host smart-55001838-ad5f-42ed-8378-f67237c4bb90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457991855 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3457991855
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.29882654
Short name T339
Test name
Test status
Simulation time 131643900 ps
CPU time 3.71 seconds
Started Jan 22 05:04:09 PM PST 24
Finished Jan 22 05:04:13 PM PST 24
Peak memory 207424 kb
Host smart-712c2079-9023-497e-866b-714ddd03e3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29882654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.29882654
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3334278597
Short name T897
Test name
Test status
Simulation time 1047822491 ps
CPU time 16.06 seconds
Started Jan 22 05:04:11 PM PST 24
Finished Jan 22 05:04:28 PM PST 24
Peak memory 210512 kb
Host smart-e73c1427-6333-4def-94df-26ef739ad400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334278597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3334278597
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.114655672
Short name T775
Test name
Test status
Simulation time 39229467 ps
CPU time 0.71 seconds
Started Jan 22 05:04:11 PM PST 24
Finished Jan 22 05:04:13 PM PST 24
Peak memory 205928 kb
Host smart-354cad71-c905-4e85-b9d8-38bd10663e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114655672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.114655672
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.431567099
Short name T813
Test name
Test status
Simulation time 60012633 ps
CPU time 4.3 seconds
Started Jan 22 05:04:10 PM PST 24
Finished Jan 22 05:04:15 PM PST 24
Peak memory 214252 kb
Host smart-dace964e-d234-4cf1-b137-2ac4938ad58c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431567099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.431567099
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2721935251
Short name T39
Test name
Test status
Simulation time 577491222 ps
CPU time 2.62 seconds
Started Jan 22 05:04:12 PM PST 24
Finished Jan 22 05:04:15 PM PST 24
Peak memory 208416 kb
Host smart-f6d31334-25ad-4491-9875-9013bf61d2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721935251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2721935251
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1122955760
Short name T321
Test name
Test status
Simulation time 181184738 ps
CPU time 3.49 seconds
Started Jan 22 05:04:06 PM PST 24
Finished Jan 22 05:04:10 PM PST 24
Peak memory 209020 kb
Host smart-5bad2c9d-acad-4279-877a-a69963d1fd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122955760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1122955760
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.4208169142
Short name T279
Test name
Test status
Simulation time 63207750 ps
CPU time 4.16 seconds
Started Jan 22 05:04:11 PM PST 24
Finished Jan 22 05:04:16 PM PST 24
Peak memory 214184 kb
Host smart-7096d8b8-cc7d-4496-8713-bcc221cc7f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208169142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.4208169142
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1355364063
Short name T852
Test name
Test status
Simulation time 84986865 ps
CPU time 4.33 seconds
Started Jan 22 05:04:10 PM PST 24
Finished Jan 22 05:04:15 PM PST 24
Peak memory 209888 kb
Host smart-462f60cd-92d6-4f58-aae9-8d2398efd9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355364063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1355364063
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2941149679
Short name T340
Test name
Test status
Simulation time 401435657 ps
CPU time 7.67 seconds
Started Jan 22 05:04:12 PM PST 24
Finished Jan 22 05:04:20 PM PST 24
Peak memory 210288 kb
Host smart-415f7970-d1fa-4c86-9ec5-b32103d1e44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941149679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2941149679
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.668752934
Short name T809
Test name
Test status
Simulation time 155008545 ps
CPU time 2.3 seconds
Started Jan 22 05:04:08 PM PST 24
Finished Jan 22 05:04:11 PM PST 24
Peak memory 208680 kb
Host smart-bce36368-91c2-4ff6-81b0-028a29cbb204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668752934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.668752934
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1191936801
Short name T199
Test name
Test status
Simulation time 442849545 ps
CPU time 7.35 seconds
Started Jan 22 05:04:07 PM PST 24
Finished Jan 22 05:04:15 PM PST 24
Peak memory 208724 kb
Host smart-72bc93b4-2ac2-4245-9632-f9b89ea59908
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191936801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1191936801
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3840084337
Short name T711
Test name
Test status
Simulation time 871217505 ps
CPU time 22.1 seconds
Started Jan 22 05:04:10 PM PST 24
Finished Jan 22 05:04:33 PM PST 24
Peak memory 207984 kb
Host smart-aedf5698-2d28-486a-b056-33ac2b4df32e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840084337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3840084337
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.233391736
Short name T599
Test name
Test status
Simulation time 572091717 ps
CPU time 10.9 seconds
Started Jan 22 05:04:11 PM PST 24
Finished Jan 22 05:04:23 PM PST 24
Peak memory 208832 kb
Host smart-41be37dd-207e-4e1c-9ed7-9e784d76326d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233391736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.233391736
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1878989516
Short name T726
Test name
Test status
Simulation time 232730642 ps
CPU time 2.79 seconds
Started Jan 22 05:04:12 PM PST 24
Finished Jan 22 05:04:15 PM PST 24
Peak memory 218288 kb
Host smart-e60140bb-c256-4252-afb1-d9f975000e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878989516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1878989516
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3116045535
Short name T679
Test name
Test status
Simulation time 2958122872 ps
CPU time 19.61 seconds
Started Jan 22 05:04:03 PM PST 24
Finished Jan 22 05:04:23 PM PST 24
Peak memory 207672 kb
Host smart-b59f3065-18f2-4217-b97f-560a5ac50913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116045535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3116045535
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.878338992
Short name T301
Test name
Test status
Simulation time 826804913 ps
CPU time 25.52 seconds
Started Jan 22 05:04:07 PM PST 24
Finished Jan 22 05:04:33 PM PST 24
Peak memory 215628 kb
Host smart-c010a8e9-db84-4327-a08f-7e74666122d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878338992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.878338992
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.942109320
Short name T943
Test name
Test status
Simulation time 145005835 ps
CPU time 3.09 seconds
Started Jan 22 05:04:10 PM PST 24
Finished Jan 22 05:04:14 PM PST 24
Peak memory 217848 kb
Host smart-8e081a99-2d5d-4875-8e86-013aea388132
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942109320 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.942109320
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3953826803
Short name T765
Test name
Test status
Simulation time 259169669 ps
CPU time 4.53 seconds
Started Jan 22 05:04:08 PM PST 24
Finished Jan 22 05:04:13 PM PST 24
Peak memory 218244 kb
Host smart-53f961e1-2ec9-447f-aea2-c27c9523a788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953826803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3953826803
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2129067987
Short name T912
Test name
Test status
Simulation time 158549780 ps
CPU time 3.6 seconds
Started Jan 22 05:04:12 PM PST 24
Finished Jan 22 05:04:16 PM PST 24
Peak memory 209960 kb
Host smart-5b412e20-a0a6-4965-8bcc-b96155f36d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129067987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2129067987
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2627567758
Short name T701
Test name
Test status
Simulation time 18392403 ps
CPU time 0.82 seconds
Started Jan 22 05:04:30 PM PST 24
Finished Jan 22 05:04:32 PM PST 24
Peak memory 205876 kb
Host smart-64c393c7-85be-4918-863a-c817ba224085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627567758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2627567758
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2942990028
Short name T400
Test name
Test status
Simulation time 53985034 ps
CPU time 3.44 seconds
Started Jan 22 05:04:13 PM PST 24
Finished Jan 22 05:04:17 PM PST 24
Peak memory 215252 kb
Host smart-f22b154e-c26b-46e7-a53a-9467fd58f02a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942990028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2942990028
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3451311735
Short name T21
Test name
Test status
Simulation time 134934151 ps
CPU time 3.28 seconds
Started Jan 22 05:04:27 PM PST 24
Finished Jan 22 05:04:31 PM PST 24
Peak memory 217252 kb
Host smart-54bb5654-4959-40f5-9d9d-98de36adecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451311735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3451311735
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.274547515
Short name T997
Test name
Test status
Simulation time 11680319997 ps
CPU time 64.56 seconds
Started Jan 22 05:04:12 PM PST 24
Finished Jan 22 05:05:17 PM PST 24
Peak memory 220532 kb
Host smart-bb805be1-99f7-48ea-9315-527767e61d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274547515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.274547515
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1678491213
Short name T17
Test name
Test status
Simulation time 183016898 ps
CPU time 4.61 seconds
Started Jan 22 05:04:27 PM PST 24
Finished Jan 22 05:04:33 PM PST 24
Peak memory 220132 kb
Host smart-0137ca67-80a2-4e28-81a7-9c9948c3f2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678491213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1678491213
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3995295890
Short name T262
Test name
Test status
Simulation time 580322055 ps
CPU time 4.58 seconds
Started Jan 22 05:04:32 PM PST 24
Finished Jan 22 05:04:37 PM PST 24
Peak memory 214164 kb
Host smart-aa62b355-987d-4520-b1c8-7e2536a9040c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995295890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3995295890
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1859093213
Short name T850
Test name
Test status
Simulation time 64537054 ps
CPU time 3.23 seconds
Started Jan 22 05:04:22 PM PST 24
Finished Jan 22 05:04:26 PM PST 24
Peak memory 208236 kb
Host smart-5be75b1b-8507-4416-9b56-e142ec75798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859093213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1859093213
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3541526532
Short name T617
Test name
Test status
Simulation time 1235781279 ps
CPU time 8.32 seconds
Started Jan 22 05:04:09 PM PST 24
Finished Jan 22 05:04:18 PM PST 24
Peak memory 207276 kb
Host smart-cbafd5a4-b7f1-4a3e-9a67-8a1b7c90f946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541526532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3541526532
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.679352267
Short name T223
Test name
Test status
Simulation time 58222245 ps
CPU time 2.01 seconds
Started Jan 22 05:04:13 PM PST 24
Finished Jan 22 05:04:15 PM PST 24
Peak memory 206592 kb
Host smart-fd047963-d05a-430b-b0b5-53874baadf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679352267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.679352267
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1972904007
Short name T732
Test name
Test status
Simulation time 146657022 ps
CPU time 5.46 seconds
Started Jan 22 05:04:12 PM PST 24
Finished Jan 22 05:04:18 PM PST 24
Peak memory 208556 kb
Host smart-24176863-fa1a-48d4-886e-a7450e2cec42
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972904007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1972904007
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.4116476305
Short name T250
Test name
Test status
Simulation time 126994964 ps
CPU time 5.13 seconds
Started Jan 22 05:04:12 PM PST 24
Finished Jan 22 05:04:18 PM PST 24
Peak memory 206864 kb
Host smart-278c11bc-4a57-4365-a146-59c55fbeeffd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116476305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.4116476305
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.411548603
Short name T846
Test name
Test status
Simulation time 515528504 ps
CPU time 4.23 seconds
Started Jan 22 05:04:27 PM PST 24
Finished Jan 22 05:04:32 PM PST 24
Peak memory 214216 kb
Host smart-b473d05d-1924-4f8d-99e5-d704fbf7f704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411548603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.411548603
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3062233703
Short name T591
Test name
Test status
Simulation time 192115291 ps
CPU time 5.26 seconds
Started Jan 22 05:04:11 PM PST 24
Finished Jan 22 05:04:17 PM PST 24
Peak memory 206628 kb
Host smart-e090084d-0314-47c2-93c6-c125bcfb7f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062233703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3062233703
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1329886755
Short name T739
Test name
Test status
Simulation time 16640439288 ps
CPU time 43.43 seconds
Started Jan 22 05:04:28 PM PST 24
Finished Jan 22 05:05:12 PM PST 24
Peak memory 215416 kb
Host smart-e2604235-7cf5-4991-b0fe-ef0a6e892c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329886755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1329886755
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1269068917
Short name T839
Test name
Test status
Simulation time 105752801 ps
CPU time 5.9 seconds
Started Jan 22 05:04:28 PM PST 24
Finished Jan 22 05:04:34 PM PST 24
Peak memory 222932 kb
Host smart-e96c4316-bdda-431b-a62d-ebd2be69559d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269068917 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1269068917
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2508726603
Short name T627
Test name
Test status
Simulation time 121838773 ps
CPU time 4.9 seconds
Started Jan 22 05:04:27 PM PST 24
Finished Jan 22 05:04:32 PM PST 24
Peak memory 209184 kb
Host smart-b0ff6d0d-ba86-4dbe-b21b-64fe7dfeae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508726603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2508726603
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.4238486593
Short name T690
Test name
Test status
Simulation time 102031384 ps
CPU time 3.77 seconds
Started Jan 22 05:04:33 PM PST 24
Finished Jan 22 05:04:37 PM PST 24
Peak memory 209912 kb
Host smart-32efa9df-247b-4a75-a5d7-2f97761ae9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238486593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.4238486593
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.4133802614
Short name T605
Test name
Test status
Simulation time 18879802 ps
CPU time 0.94 seconds
Started Jan 22 05:04:36 PM PST 24
Finished Jan 22 05:04:38 PM PST 24
Peak memory 205976 kb
Host smart-f345fe77-9e49-478b-aeec-29ef0c02ccdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133802614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.4133802614
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3443708356
Short name T307
Test name
Test status
Simulation time 234056451 ps
CPU time 4.81 seconds
Started Jan 22 05:04:37 PM PST 24
Finished Jan 22 05:04:42 PM PST 24
Peak memory 214316 kb
Host smart-b6cc27cc-696e-46ad-a4c3-a9d067e44c3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443708356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3443708356
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.292087246
Short name T671
Test name
Test status
Simulation time 191618868 ps
CPU time 3.61 seconds
Started Jan 22 05:04:36 PM PST 24
Finished Jan 22 05:04:40 PM PST 24
Peak memory 208352 kb
Host smart-7d8cea99-f19e-4396-8baa-90edf978bf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292087246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.292087246
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3382062525
Short name T354
Test name
Test status
Simulation time 671444614 ps
CPU time 4.44 seconds
Started Jan 22 05:04:38 PM PST 24
Finished Jan 22 05:04:43 PM PST 24
Peak memory 214332 kb
Host smart-f4baec44-3e32-4322-8bc1-c5e976c8852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382062525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3382062525
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3885976681
Short name T389
Test name
Test status
Simulation time 81405199 ps
CPU time 1.79 seconds
Started Jan 22 05:04:30 PM PST 24
Finished Jan 22 05:04:32 PM PST 24
Peak memory 205880 kb
Host smart-65d905c0-9d03-422a-9c17-670bf41d9ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885976681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3885976681
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.603655773
Short name T276
Test name
Test status
Simulation time 906523355 ps
CPU time 5.96 seconds
Started Jan 22 05:04:36 PM PST 24
Finished Jan 22 05:04:42 PM PST 24
Peak memory 208164 kb
Host smart-2e3af53e-485f-478c-a8a3-da12234ecc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603655773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.603655773
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1631870503
Short name T75
Test name
Test status
Simulation time 713263520 ps
CPU time 5.12 seconds
Started Jan 22 05:04:31 PM PST 24
Finished Jan 22 05:04:37 PM PST 24
Peak memory 206708 kb
Host smart-41b3fa44-5b9b-40f5-ad8b-c1a5ecaafff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631870503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1631870503
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.847608248
Short name T756
Test name
Test status
Simulation time 4341456279 ps
CPU time 48.73 seconds
Started Jan 22 05:04:28 PM PST 24
Finished Jan 22 05:05:18 PM PST 24
Peak memory 208012 kb
Host smart-389b2a23-d869-4b43-8c1e-5dd6f426c4fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847608248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.847608248
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2888168855
Short name T908
Test name
Test status
Simulation time 321316511 ps
CPU time 3.11 seconds
Started Jan 22 05:04:28 PM PST 24
Finished Jan 22 05:04:32 PM PST 24
Peak memory 207096 kb
Host smart-4612decb-54a9-47a2-ae89-070e3cb1539d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888168855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2888168855
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.459126605
Short name T2
Test name
Test status
Simulation time 849653246 ps
CPU time 9.91 seconds
Started Jan 22 05:04:36 PM PST 24
Finished Jan 22 05:04:47 PM PST 24
Peak memory 208452 kb
Host smart-4671effc-2be1-47d6-bc3c-c696aad0bc15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459126605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.459126605
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1703763812
Short name T584
Test name
Test status
Simulation time 195568536 ps
CPU time 4.41 seconds
Started Jan 22 05:04:37 PM PST 24
Finished Jan 22 05:04:42 PM PST 24
Peak memory 209636 kb
Host smart-e6789524-550a-4b13-b5f3-4e44b5168c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703763812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1703763812
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2117028503
Short name T851
Test name
Test status
Simulation time 182249392 ps
CPU time 2.09 seconds
Started Jan 22 05:04:27 PM PST 24
Finished Jan 22 05:04:29 PM PST 24
Peak memory 208560 kb
Host smart-b3e4ed79-e6cb-4225-b10f-8f0f6ee20b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117028503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2117028503
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1157217061
Short name T225
Test name
Test status
Simulation time 1391736501 ps
CPU time 22.58 seconds
Started Jan 22 05:04:38 PM PST 24
Finished Jan 22 05:05:01 PM PST 24
Peak memory 222408 kb
Host smart-b573ff7f-824f-4097-aaa9-8a91c7c48348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157217061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1157217061
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.4159554941
Short name T208
Test name
Test status
Simulation time 83179174 ps
CPU time 4.4 seconds
Started Jan 22 05:04:48 PM PST 24
Finished Jan 22 05:04:53 PM PST 24
Peak memory 222512 kb
Host smart-9a72638b-c09c-4b72-a4d4-c5ce419241c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159554941 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.4159554941
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2807158459
Short name T862
Test name
Test status
Simulation time 666797644 ps
CPU time 7.97 seconds
Started Jan 22 05:04:35 PM PST 24
Finished Jan 22 05:04:44 PM PST 24
Peak memory 214320 kb
Host smart-2215d633-588b-4a8f-b20f-bc5aa052fe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807158459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2807158459
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.199876762
Short name T1009
Test name
Test status
Simulation time 86438024 ps
CPU time 3.18 seconds
Started Jan 22 05:04:43 PM PST 24
Finished Jan 22 05:04:47 PM PST 24
Peak memory 210432 kb
Host smart-9053d7da-7ec5-4b82-a631-e59550d604f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199876762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.199876762
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3445082
Short name T924
Test name
Test status
Simulation time 15384406 ps
CPU time 0.89 seconds
Started Jan 22 04:59:42 PM PST 24
Finished Jan 22 04:59:44 PM PST 24
Peak memory 205820 kb
Host smart-60edb8aa-4e0e-469a-b6a5-d5347843e03a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3445082
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2599242305
Short name T866
Test name
Test status
Simulation time 192467832 ps
CPU time 4.78 seconds
Started Jan 22 04:59:41 PM PST 24
Finished Jan 22 04:59:47 PM PST 24
Peak memory 214560 kb
Host smart-ad6de3f5-5f15-433d-abcc-65df17413803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599242305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2599242305
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4101758142
Short name T1007
Test name
Test status
Simulation time 437522803 ps
CPU time 6.52 seconds
Started Jan 22 04:59:30 PM PST 24
Finished Jan 22 04:59:37 PM PST 24
Peak memory 214232 kb
Host smart-d5743b2c-d513-4c30-9b11-28f0424943b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101758142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4101758142
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1418468758
Short name T80
Test name
Test status
Simulation time 204423621 ps
CPU time 3.47 seconds
Started Jan 22 04:59:36 PM PST 24
Finished Jan 22 04:59:40 PM PST 24
Peak memory 208232 kb
Host smart-751e0bed-ed76-4c55-b119-e51daf5890e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418468758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1418468758
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3249013466
Short name T365
Test name
Test status
Simulation time 65929023 ps
CPU time 3.43 seconds
Started Jan 22 04:59:30 PM PST 24
Finished Jan 22 04:59:34 PM PST 24
Peak memory 211056 kb
Host smart-6c654fb1-e508-4682-a36f-f02206a72744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249013466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3249013466
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3491694267
Short name T932
Test name
Test status
Simulation time 97581584 ps
CPU time 2.4 seconds
Started Jan 22 04:59:34 PM PST 24
Finished Jan 22 04:59:37 PM PST 24
Peak memory 214236 kb
Host smart-43451ce6-ed6c-43ac-87fc-9a1a8530c5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491694267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3491694267
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.4033379390
Short name T11
Test name
Test status
Simulation time 5576123927 ps
CPU time 120.84 seconds
Started Jan 22 04:59:41 PM PST 24
Finished Jan 22 05:01:43 PM PST 24
Peak memory 269492 kb
Host smart-c21f9f00-a101-4586-bb38-dc35ec6be0b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033379390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.4033379390
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1324421244
Short name T240
Test name
Test status
Simulation time 703797296 ps
CPU time 8.81 seconds
Started Jan 22 04:59:34 PM PST 24
Finished Jan 22 04:59:43 PM PST 24
Peak memory 208892 kb
Host smart-d4e3a5bc-d0c1-44fc-bf76-c416aee82fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324421244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1324421244
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3311115771
Short name T626
Test name
Test status
Simulation time 186079935 ps
CPU time 5.66 seconds
Started Jan 22 04:59:30 PM PST 24
Finished Jan 22 04:59:36 PM PST 24
Peak memory 207020 kb
Host smart-702d4d70-1691-4524-a76f-7f0c2c9114f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311115771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3311115771
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1988417156
Short name T554
Test name
Test status
Simulation time 178523686 ps
CPU time 2.74 seconds
Started Jan 22 04:59:36 PM PST 24
Finished Jan 22 04:59:39 PM PST 24
Peak memory 208588 kb
Host smart-2d4e8384-1e6d-4195-895f-3a6cdf283598
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988417156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1988417156
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3798182153
Short name T738
Test name
Test status
Simulation time 93759455 ps
CPU time 3.37 seconds
Started Jan 22 04:59:34 PM PST 24
Finished Jan 22 04:59:38 PM PST 24
Peak memory 206680 kb
Host smart-78f3cb0e-2b3b-48a3-ae7e-7fde5b7e0ea2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798182153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3798182153
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.695245822
Short name T860
Test name
Test status
Simulation time 92350697 ps
CPU time 2.92 seconds
Started Jan 22 04:59:30 PM PST 24
Finished Jan 22 04:59:34 PM PST 24
Peak memory 208008 kb
Host smart-5452688f-59db-45d5-adb2-2387652d3170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695245822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.695245822
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1065485357
Short name T1035
Test name
Test status
Simulation time 763692245 ps
CPU time 18.67 seconds
Started Jan 22 04:59:29 PM PST 24
Finished Jan 22 04:59:48 PM PST 24
Peak memory 207784 kb
Host smart-9b88834e-dd1b-48dc-81b3-72c81e6c475f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065485357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1065485357
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3657789696
Short name T1026
Test name
Test status
Simulation time 1725008106 ps
CPU time 17.74 seconds
Started Jan 22 04:59:29 PM PST 24
Finished Jan 22 04:59:47 PM PST 24
Peak memory 222532 kb
Host smart-93998126-6e2c-4172-809e-17828e0ecf52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657789696 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3657789696
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3924750594
Short name T324
Test name
Test status
Simulation time 234889463 ps
CPU time 7.16 seconds
Started Jan 22 04:59:26 PM PST 24
Finished Jan 22 04:59:33 PM PST 24
Peak memory 209984 kb
Host smart-6bedd729-1fa7-41a5-8106-6198462cca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924750594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3924750594
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3539236045
Short name T556
Test name
Test status
Simulation time 369252816 ps
CPU time 2.96 seconds
Started Jan 22 04:59:34 PM PST 24
Finished Jan 22 04:59:37 PM PST 24
Peak memory 210320 kb
Host smart-48efe616-9b7b-4deb-8433-5e13284b7188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539236045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3539236045
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.413805097
Short name T934
Test name
Test status
Simulation time 36933016 ps
CPU time 0.71 seconds
Started Jan 22 05:04:54 PM PST 24
Finished Jan 22 05:05:01 PM PST 24
Peak memory 205920 kb
Host smart-e5c38aeb-47eb-4076-b3ea-1c03114e715d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413805097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.413805097
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.115072783
Short name T392
Test name
Test status
Simulation time 37319360 ps
CPU time 2.77 seconds
Started Jan 22 05:04:48 PM PST 24
Finished Jan 22 05:04:51 PM PST 24
Peak memory 214276 kb
Host smart-a4fa1244-f2b1-4489-82ea-a78a94536bd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115072783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.115072783
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2416728198
Short name T548
Test name
Test status
Simulation time 482993122 ps
CPU time 7.31 seconds
Started Jan 22 05:04:48 PM PST 24
Finished Jan 22 05:04:56 PM PST 24
Peak memory 209416 kb
Host smart-380f6928-38a9-467b-a1c1-ddb01ca53844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416728198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2416728198
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1361832065
Short name T190
Test name
Test status
Simulation time 23704036 ps
CPU time 1.98 seconds
Started Jan 22 05:04:48 PM PST 24
Finished Jan 22 05:04:51 PM PST 24
Peak memory 209896 kb
Host smart-725743a3-11c1-45bb-852a-b241549e433b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361832065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1361832065
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1314438409
Short name T910
Test name
Test status
Simulation time 412276721 ps
CPU time 6.93 seconds
Started Jan 22 05:04:52 PM PST 24
Finished Jan 22 05:05:05 PM PST 24
Peak memory 214376 kb
Host smart-b0a32e58-22e0-430b-9b9a-4a63937dc0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314438409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1314438409
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.381179660
Short name T903
Test name
Test status
Simulation time 173742602 ps
CPU time 3.85 seconds
Started Jan 22 05:04:50 PM PST 24
Finished Jan 22 05:04:55 PM PST 24
Peak memory 214384 kb
Host smart-a6a992d4-7eb7-4f05-bd3f-788362bf84c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381179660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.381179660
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2758938551
Short name T218
Test name
Test status
Simulation time 39637028 ps
CPU time 2.71 seconds
Started Jan 22 05:04:49 PM PST 24
Finished Jan 22 05:04:52 PM PST 24
Peak memory 208576 kb
Host smart-48241f8f-ad1a-47c0-af26-f157970d6141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758938551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2758938551
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2559683775
Short name T602
Test name
Test status
Simulation time 140568522 ps
CPU time 5 seconds
Started Jan 22 05:04:42 PM PST 24
Finished Jan 22 05:04:48 PM PST 24
Peak memory 210072 kb
Host smart-86f5423b-8661-4c23-9ece-4d3347b6bb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559683775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2559683775
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1553223554
Short name T372
Test name
Test status
Simulation time 153938050 ps
CPU time 3.68 seconds
Started Jan 22 05:04:37 PM PST 24
Finished Jan 22 05:04:41 PM PST 24
Peak memory 208520 kb
Host smart-7709cdac-c2f5-4ea1-b851-a179a68e1a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553223554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1553223554
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2092323485
Short name T582
Test name
Test status
Simulation time 579469722 ps
CPU time 8.41 seconds
Started Jan 22 05:04:43 PM PST 24
Finished Jan 22 05:04:52 PM PST 24
Peak memory 207860 kb
Host smart-bb36560d-2dbd-4ad9-974f-5578283a9fba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092323485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2092323485
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3048041603
Short name T655
Test name
Test status
Simulation time 7814525273 ps
CPU time 80.38 seconds
Started Jan 22 05:04:38 PM PST 24
Finished Jan 22 05:05:59 PM PST 24
Peak memory 209092 kb
Host smart-92975b68-4050-4b92-a444-c82b6e4870d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048041603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3048041603
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3923466442
Short name T580
Test name
Test status
Simulation time 2833412722 ps
CPU time 48.84 seconds
Started Jan 22 05:04:43 PM PST 24
Finished Jan 22 05:05:33 PM PST 24
Peak memory 208944 kb
Host smart-9eb4ec02-9397-4582-98d9-4643e0b7b0ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923466442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3923466442
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.4069104343
Short name T986
Test name
Test status
Simulation time 617954211 ps
CPU time 4.61 seconds
Started Jan 22 05:04:50 PM PST 24
Finished Jan 22 05:04:56 PM PST 24
Peak memory 209188 kb
Host smart-48819ede-f9a0-4e35-b303-85c9e0635c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069104343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4069104343
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2926235959
Short name T857
Test name
Test status
Simulation time 163111650 ps
CPU time 5.51 seconds
Started Jan 22 05:04:37 PM PST 24
Finished Jan 22 05:04:43 PM PST 24
Peak memory 206788 kb
Host smart-b7e80deb-3af4-4b74-9c12-04a9bb290ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926235959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2926235959
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1622432843
Short name T962
Test name
Test status
Simulation time 250994160 ps
CPU time 6.77 seconds
Started Jan 22 05:04:47 PM PST 24
Finished Jan 22 05:04:55 PM PST 24
Peak memory 216108 kb
Host smart-cd199032-835e-4a23-8236-297bed4e5b5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622432843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1622432843
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1270752322
Short name T353
Test name
Test status
Simulation time 178739487 ps
CPU time 5.93 seconds
Started Jan 22 05:05:02 PM PST 24
Finished Jan 22 05:05:09 PM PST 24
Peak memory 219896 kb
Host smart-db7a625b-2646-4dda-826a-ddb18cbbe756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270752322 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1270752322
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2776281804
Short name T659
Test name
Test status
Simulation time 102500259 ps
CPU time 3.32 seconds
Started Jan 22 05:04:48 PM PST 24
Finished Jan 22 05:04:52 PM PST 24
Peak memory 207936 kb
Host smart-38c34715-7181-429b-b7bd-cefd3e5822aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776281804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2776281804
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3570812807
Short name T777
Test name
Test status
Simulation time 355448367 ps
CPU time 4.31 seconds
Started Jan 22 05:04:49 PM PST 24
Finished Jan 22 05:04:54 PM PST 24
Peak memory 210192 kb
Host smart-bad2ff7e-43cd-4c2c-b6f6-4a9c6a7139a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570812807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3570812807
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2603914590
Short name T1030
Test name
Test status
Simulation time 55042109 ps
CPU time 0.77 seconds
Started Jan 22 05:05:11 PM PST 24
Finished Jan 22 05:05:14 PM PST 24
Peak memory 205900 kb
Host smart-cb3b316f-e18e-4904-aef2-0be39c178f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603914590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2603914590
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.893120354
Short name T376
Test name
Test status
Simulation time 4809076573 ps
CPU time 131.27 seconds
Started Jan 22 05:04:54 PM PST 24
Finished Jan 22 05:07:11 PM PST 24
Peak memory 214400 kb
Host smart-27b42272-eb37-47f4-a7c5-7f2ecddb0631
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893120354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.893120354
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.12021704
Short name T205
Test name
Test status
Simulation time 1724955019 ps
CPU time 13.86 seconds
Started Jan 22 05:05:06 PM PST 24
Finished Jan 22 05:05:25 PM PST 24
Peak memory 222836 kb
Host smart-d4b24a30-9fb9-4958-be8b-97aa11f3d4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12021704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.12021704
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1692050726
Short name T751
Test name
Test status
Simulation time 67717905 ps
CPU time 2.44 seconds
Started Jan 22 05:05:04 PM PST 24
Finished Jan 22 05:05:08 PM PST 24
Peak memory 214316 kb
Host smart-be55ad65-abd6-4dc5-9b57-e2c792cf9411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692050726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1692050726
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3270645129
Short name T705
Test name
Test status
Simulation time 56401400 ps
CPU time 2.35 seconds
Started Jan 22 05:05:04 PM PST 24
Finished Jan 22 05:05:07 PM PST 24
Peak memory 209000 kb
Host smart-0c1906da-2283-429f-af60-54c3bab959d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270645129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3270645129
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1033849516
Short name T236
Test name
Test status
Simulation time 194232660 ps
CPU time 6.69 seconds
Started Jan 22 05:05:00 PM PST 24
Finished Jan 22 05:05:08 PM PST 24
Peak memory 211144 kb
Host smart-577dcddc-a988-4912-9826-6bea80819642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033849516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1033849516
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2216323672
Short name T1037
Test name
Test status
Simulation time 345416337 ps
CPU time 4.78 seconds
Started Jan 22 05:05:05 PM PST 24
Finished Jan 22 05:05:11 PM PST 24
Peak memory 209644 kb
Host smart-6aa588d3-a216-44ee-8f4e-0faca4abfc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216323672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2216323672
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2338186064
Short name T1032
Test name
Test status
Simulation time 294221931 ps
CPU time 2.76 seconds
Started Jan 22 05:04:54 PM PST 24
Finished Jan 22 05:05:02 PM PST 24
Peak memory 207604 kb
Host smart-2fed4448-11f4-4ca4-b86b-f9e76d48bf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338186064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2338186064
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.269273145
Short name T587
Test name
Test status
Simulation time 333117671 ps
CPU time 3.44 seconds
Started Jan 22 05:04:49 PM PST 24
Finished Jan 22 05:04:54 PM PST 24
Peak memory 208352 kb
Host smart-eeecc279-8d6d-47da-bc7f-440721d8b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269273145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.269273145
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1857560806
Short name T360
Test name
Test status
Simulation time 1330918981 ps
CPU time 3.72 seconds
Started Jan 22 05:04:48 PM PST 24
Finished Jan 22 05:04:52 PM PST 24
Peak memory 208812 kb
Host smart-d899a94c-fdfc-4ece-b8f8-34f3af15b70e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857560806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1857560806
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3642301198
Short name T896
Test name
Test status
Simulation time 413796641 ps
CPU time 13.18 seconds
Started Jan 22 05:04:50 PM PST 24
Finished Jan 22 05:05:05 PM PST 24
Peak memory 208348 kb
Host smart-8cb5d0a0-9858-4be0-8722-486750d91631
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642301198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3642301198
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3373039615
Short name T740
Test name
Test status
Simulation time 77980901 ps
CPU time 2.49 seconds
Started Jan 22 05:04:47 PM PST 24
Finished Jan 22 05:04:50 PM PST 24
Peak memory 206836 kb
Host smart-afc7fb0f-1530-4b84-b76b-85904862a769
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373039615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3373039615
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3899097035
Short name T593
Test name
Test status
Simulation time 147242613 ps
CPU time 5.11 seconds
Started Jan 22 05:05:11 PM PST 24
Finished Jan 22 05:05:19 PM PST 24
Peak memory 209180 kb
Host smart-0d47f92c-74be-4424-9695-112ef33ec3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899097035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3899097035
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1172118921
Short name T643
Test name
Test status
Simulation time 131785060 ps
CPU time 3.04 seconds
Started Jan 22 05:04:51 PM PST 24
Finished Jan 22 05:05:00 PM PST 24
Peak memory 208020 kb
Host smart-a95455b5-fd9d-4bce-bbb3-5d1043faffdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172118921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1172118921
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.4125902244
Short name T306
Test name
Test status
Simulation time 406705133 ps
CPU time 19.82 seconds
Started Jan 22 05:05:02 PM PST 24
Finished Jan 22 05:05:23 PM PST 24
Peak memory 222424 kb
Host smart-81f55ce6-ad10-4a8e-8282-751fa705295c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125902244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.4125902244
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1341564101
Short name T608
Test name
Test status
Simulation time 288552942 ps
CPU time 7.57 seconds
Started Jan 22 05:05:03 PM PST 24
Finished Jan 22 05:05:12 PM PST 24
Peak memory 209576 kb
Host smart-b3037cec-9c14-43ed-9f6d-6847430f0ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341564101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1341564101
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.402249301
Short name T1041
Test name
Test status
Simulation time 1395314953 ps
CPU time 6.18 seconds
Started Jan 22 05:05:01 PM PST 24
Finished Jan 22 05:05:09 PM PST 24
Peak memory 210888 kb
Host smart-a25482c5-2fdd-47d8-a791-71bee171e4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402249301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.402249301
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.188504923
Short name T523
Test name
Test status
Simulation time 70951656 ps
CPU time 0.97 seconds
Started Jan 22 05:05:24 PM PST 24
Finished Jan 22 05:05:27 PM PST 24
Peak memory 206040 kb
Host smart-eb0325d5-273d-473a-8e99-0b1492c9eb48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188504923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.188504923
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3030592428
Short name T366
Test name
Test status
Simulation time 68668732 ps
CPU time 4.83 seconds
Started Jan 22 05:05:06 PM PST 24
Finished Jan 22 05:05:16 PM PST 24
Peak memory 222364 kb
Host smart-96530f90-8e77-49e6-a364-b3146ef4d2c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030592428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3030592428
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1439901566
Short name T768
Test name
Test status
Simulation time 3218144079 ps
CPU time 10.56 seconds
Started Jan 22 05:05:07 PM PST 24
Finished Jan 22 05:05:23 PM PST 24
Peak memory 208380 kb
Host smart-57152301-4ff4-41bb-a7f4-1033bb889b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439901566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1439901566
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2015483603
Short name T92
Test name
Test status
Simulation time 261719620 ps
CPU time 9.43 seconds
Started Jan 22 05:05:15 PM PST 24
Finished Jan 22 05:05:26 PM PST 24
Peak memory 219804 kb
Host smart-a34894d6-0397-444b-8ccc-e650dac2777d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015483603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2015483603
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_random.1576973187
Short name T902
Test name
Test status
Simulation time 359097530 ps
CPU time 3.41 seconds
Started Jan 22 05:05:06 PM PST 24
Finished Jan 22 05:05:14 PM PST 24
Peak memory 218256 kb
Host smart-df3f7ea4-03df-466b-8a05-4c7bb31d2411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576973187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1576973187
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.272151113
Short name T323
Test name
Test status
Simulation time 61872980 ps
CPU time 2.31 seconds
Started Jan 22 05:05:09 PM PST 24
Finished Jan 22 05:05:15 PM PST 24
Peak memory 206700 kb
Host smart-dc0315d3-e78c-4e1a-8220-932eaaddda9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272151113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.272151113
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.607576255
Short name T547
Test name
Test status
Simulation time 153057586 ps
CPU time 3.37 seconds
Started Jan 22 05:05:11 PM PST 24
Finished Jan 22 05:05:17 PM PST 24
Peak memory 208744 kb
Host smart-d7b0cfcb-ebd2-4067-8eab-a575e7a4fe11
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607576255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.607576255
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1663388328
Short name T650
Test name
Test status
Simulation time 102113134 ps
CPU time 2.95 seconds
Started Jan 22 05:05:06 PM PST 24
Finished Jan 22 05:05:14 PM PST 24
Peak memory 207004 kb
Host smart-789e9ac1-c8cf-4b89-8016-c384d97928c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663388328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1663388328
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1641518354
Short name T294
Test name
Test status
Simulation time 138482531 ps
CPU time 2.62 seconds
Started Jan 22 05:05:11 PM PST 24
Finished Jan 22 05:05:16 PM PST 24
Peak memory 207512 kb
Host smart-bc77fd13-3a4f-4cae-8af0-0f7b29dd6449
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641518354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1641518354
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.843446776
Short name T844
Test name
Test status
Simulation time 892156179 ps
CPU time 21.82 seconds
Started Jan 22 05:05:08 PM PST 24
Finished Jan 22 05:05:35 PM PST 24
Peak memory 208960 kb
Host smart-809b601d-eedf-404d-b774-1db376be5c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843446776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.843446776
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.80183512
Short name T527
Test name
Test status
Simulation time 263170347 ps
CPU time 8.09 seconds
Started Jan 22 05:05:04 PM PST 24
Finished Jan 22 05:05:14 PM PST 24
Peak memory 208476 kb
Host smart-83242f8e-b872-47bf-8395-2766d23e55ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80183512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.80183512
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2660849577
Short name T369
Test name
Test status
Simulation time 35526281673 ps
CPU time 575.33 seconds
Started Jan 22 05:05:10 PM PST 24
Finished Jan 22 05:14:48 PM PST 24
Peak memory 220936 kb
Host smart-cb8976a7-fab4-48d2-8894-a01ba73843bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660849577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2660849577
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3565690687
Short name T750
Test name
Test status
Simulation time 84347818 ps
CPU time 4.9 seconds
Started Jan 22 05:05:15 PM PST 24
Finished Jan 22 05:05:22 PM PST 24
Peak memory 221924 kb
Host smart-8f8b15b9-90c2-45be-ad9a-35032f84fe44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565690687 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3565690687
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1574143632
Short name T228
Test name
Test status
Simulation time 211062172 ps
CPU time 3.66 seconds
Started Jan 22 05:05:09 PM PST 24
Finished Jan 22 05:05:17 PM PST 24
Peak memory 207464 kb
Host smart-2e6d63d6-5b65-4712-a9de-afa276b953dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574143632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1574143632
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.494380067
Short name T662
Test name
Test status
Simulation time 320804484 ps
CPU time 3.58 seconds
Started Jan 22 05:05:09 PM PST 24
Finished Jan 22 05:05:16 PM PST 24
Peak memory 210412 kb
Host smart-6c61a330-9f67-442d-b849-ed5c51ffa204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494380067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.494380067
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1144008289
Short name T564
Test name
Test status
Simulation time 13622006 ps
CPU time 0.95 seconds
Started Jan 22 05:05:24 PM PST 24
Finished Jan 22 05:05:27 PM PST 24
Peak memory 206060 kb
Host smart-ea0fe819-e741-4577-bdfd-0df5a2022ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144008289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1144008289
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1289259937
Short name T398
Test name
Test status
Simulation time 1302414846 ps
CPU time 18.23 seconds
Started Jan 22 05:05:15 PM PST 24
Finished Jan 22 05:05:35 PM PST 24
Peak memory 214396 kb
Host smart-6c637fd3-37fd-4904-aa67-c1bdcd26c48e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289259937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1289259937
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1903835574
Short name T40
Test name
Test status
Simulation time 173169275 ps
CPU time 3.09 seconds
Started Jan 22 05:05:23 PM PST 24
Finished Jan 22 05:05:28 PM PST 24
Peak memory 210436 kb
Host smart-cd785390-e397-44a1-9132-403d40b4ecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903835574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1903835574
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1884594698
Short name T588
Test name
Test status
Simulation time 3202953909 ps
CPU time 7.72 seconds
Started Jan 22 05:05:21 PM PST 24
Finished Jan 22 05:05:30 PM PST 24
Peak memory 214232 kb
Host smart-1ed31203-8139-4084-ba0d-20e82ebb5230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884594698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1884594698
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1668458265
Short name T25
Test name
Test status
Simulation time 170828297 ps
CPU time 2.82 seconds
Started Jan 22 05:05:23 PM PST 24
Finished Jan 22 05:05:28 PM PST 24
Peak memory 208656 kb
Host smart-78129368-d46b-43e6-acd6-cf2b349bfbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668458265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1668458265
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1417835915
Short name T351
Test name
Test status
Simulation time 69859784 ps
CPU time 4.02 seconds
Started Jan 22 05:05:26 PM PST 24
Finished Jan 22 05:05:31 PM PST 24
Peak memory 214248 kb
Host smart-c26a362e-c4c2-49fd-ac11-01260de6a4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417835915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1417835915
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3233927090
Short name T1042
Test name
Test status
Simulation time 145327457 ps
CPU time 6.36 seconds
Started Jan 22 05:05:23 PM PST 24
Finished Jan 22 05:05:32 PM PST 24
Peak memory 210068 kb
Host smart-8a96f80c-23a0-4bc0-a7ab-c97b3c78495c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233927090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3233927090
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1401870123
Short name T988
Test name
Test status
Simulation time 10410046186 ps
CPU time 73.62 seconds
Started Jan 22 05:05:15 PM PST 24
Finished Jan 22 05:06:31 PM PST 24
Peak memory 222600 kb
Host smart-42470fd4-f44d-4b6c-a8c3-beefea0ce6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401870123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1401870123
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1540404074
Short name T719
Test name
Test status
Simulation time 106197879 ps
CPU time 2.96 seconds
Started Jan 22 05:05:12 PM PST 24
Finished Jan 22 05:05:17 PM PST 24
Peak memory 208584 kb
Host smart-79fc8eb3-d818-454e-afa2-444008630564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540404074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1540404074
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3882581244
Short name T838
Test name
Test status
Simulation time 209589422 ps
CPU time 7.98 seconds
Started Jan 22 05:05:23 PM PST 24
Finished Jan 22 05:05:33 PM PST 24
Peak memory 208028 kb
Host smart-6bc030df-056a-49ce-91b7-68f459a94163
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882581244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3882581244
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1912818060
Short name T969
Test name
Test status
Simulation time 215519515 ps
CPU time 4.61 seconds
Started Jan 22 05:05:11 PM PST 24
Finished Jan 22 05:05:18 PM PST 24
Peak memory 208596 kb
Host smart-b6db88a5-fa04-4be3-a6aa-191cfec74d9d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912818060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1912818060
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3426368651
Short name T725
Test name
Test status
Simulation time 176549794 ps
CPU time 5.68 seconds
Started Jan 22 05:05:23 PM PST 24
Finished Jan 22 05:05:31 PM PST 24
Peak memory 208268 kb
Host smart-5b6100a7-939a-4634-8f1b-04f4c1fee1d1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426368651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3426368651
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2871822388
Short name T799
Test name
Test status
Simulation time 29533556 ps
CPU time 2.16 seconds
Started Jan 22 05:05:26 PM PST 24
Finished Jan 22 05:05:29 PM PST 24
Peak memory 209516 kb
Host smart-efa538eb-aafb-49e4-8790-877f16c8bc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871822388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2871822388
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3314111900
Short name T663
Test name
Test status
Simulation time 129846976 ps
CPU time 2.52 seconds
Started Jan 22 05:05:15 PM PST 24
Finished Jan 22 05:05:20 PM PST 24
Peak memory 205996 kb
Host smart-c876ae64-4322-40df-bd37-cafc1f47454c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314111900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3314111900
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2264837852
Short name T244
Test name
Test status
Simulation time 2269771122 ps
CPU time 37.08 seconds
Started Jan 22 05:05:26 PM PST 24
Finished Jan 22 05:06:04 PM PST 24
Peak memory 221780 kb
Host smart-29616919-d43c-4b36-ab1f-755add710fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264837852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2264837852
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1282851546
Short name T1028
Test name
Test status
Simulation time 124706135 ps
CPU time 2.81 seconds
Started Jan 22 05:05:26 PM PST 24
Finished Jan 22 05:05:30 PM PST 24
Peak memory 222600 kb
Host smart-88522d81-9fd2-47f0-831d-ca273464dcf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282851546 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1282851546
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3734648448
Short name T874
Test name
Test status
Simulation time 187572197 ps
CPU time 5 seconds
Started Jan 22 05:05:15 PM PST 24
Finished Jan 22 05:05:22 PM PST 24
Peak memory 207112 kb
Host smart-3834e3d2-256c-4737-bd51-650b248c2437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734648448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3734648448
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2441031094
Short name T907
Test name
Test status
Simulation time 132964938 ps
CPU time 3.85 seconds
Started Jan 22 05:05:24 PM PST 24
Finished Jan 22 05:05:30 PM PST 24
Peak memory 210072 kb
Host smart-48cd5324-45b7-4f12-b118-d27064fc546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441031094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2441031094
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2034968001
Short name T89
Test name
Test status
Simulation time 12007617 ps
CPU time 0.89 seconds
Started Jan 22 05:05:27 PM PST 24
Finished Jan 22 05:05:29 PM PST 24
Peak memory 205864 kb
Host smart-870df12a-f03c-4551-8679-fe6479ec616f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034968001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2034968001
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3556010760
Short name T840
Test name
Test status
Simulation time 145233809 ps
CPU time 3.13 seconds
Started Jan 22 05:05:29 PM PST 24
Finished Jan 22 05:05:34 PM PST 24
Peak memory 214608 kb
Host smart-6518bc55-0b0d-4f85-ae08-3e0a11f08f83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556010760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3556010760
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.911953365
Short name T363
Test name
Test status
Simulation time 65089431 ps
CPU time 2.98 seconds
Started Jan 22 05:05:20 PM PST 24
Finished Jan 22 05:05:23 PM PST 24
Peak memory 218448 kb
Host smart-7ae960c2-7fa2-4695-907b-cfdf96256c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911953365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.911953365
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.614268115
Short name T260
Test name
Test status
Simulation time 333905395 ps
CPU time 5.92 seconds
Started Jan 22 05:05:18 PM PST 24
Finished Jan 22 05:05:25 PM PST 24
Peak memory 222364 kb
Host smart-587530b6-aff6-458c-8a6c-4c772c8d9d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614268115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.614268115
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1763397848
Short name T798
Test name
Test status
Simulation time 1497965426 ps
CPU time 4.67 seconds
Started Jan 22 05:05:24 PM PST 24
Finished Jan 22 05:05:31 PM PST 24
Peak memory 209360 kb
Host smart-4df42146-4d83-4140-834b-3bd833c70e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763397848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1763397848
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1037406595
Short name T550
Test name
Test status
Simulation time 214491121 ps
CPU time 3.85 seconds
Started Jan 22 05:05:29 PM PST 24
Finished Jan 22 05:05:35 PM PST 24
Peak memory 218024 kb
Host smart-8477f25e-98de-4b56-b294-4649c6edbde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037406595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1037406595
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3649874607
Short name T581
Test name
Test status
Simulation time 1017880165 ps
CPU time 8.87 seconds
Started Jan 22 05:05:30 PM PST 24
Finished Jan 22 05:05:41 PM PST 24
Peak memory 206724 kb
Host smart-41ef2665-f007-428f-bd52-ddf1dcf59862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649874607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3649874607
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3598231018
Short name T709
Test name
Test status
Simulation time 25640691 ps
CPU time 2.03 seconds
Started Jan 22 05:05:24 PM PST 24
Finished Jan 22 05:05:28 PM PST 24
Peak memory 208552 kb
Host smart-b2187848-c02a-4001-9762-566c331660c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598231018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3598231018
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3117341044
Short name T296
Test name
Test status
Simulation time 1307160030 ps
CPU time 9.42 seconds
Started Jan 22 05:05:29 PM PST 24
Finished Jan 22 05:05:41 PM PST 24
Peak memory 208660 kb
Host smart-81ce1cd3-688a-43cd-b180-d22cc98b5b8d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117341044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3117341044
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1971520162
Short name T767
Test name
Test status
Simulation time 330581052 ps
CPU time 2.74 seconds
Started Jan 22 05:05:29 PM PST 24
Finished Jan 22 05:05:34 PM PST 24
Peak memory 206704 kb
Host smart-9f5369f6-f4a8-4fa9-a36e-ea992629336b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971520162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1971520162
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.4042201967
Short name T267
Test name
Test status
Simulation time 276716093 ps
CPU time 3.28 seconds
Started Jan 22 05:05:20 PM PST 24
Finished Jan 22 05:05:23 PM PST 24
Peak memory 209692 kb
Host smart-8885bd66-d4fd-4cd2-a90c-8fe8a18c4c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042201967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.4042201967
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3346145045
Short name T892
Test name
Test status
Simulation time 192659808 ps
CPU time 3.95 seconds
Started Jan 22 05:05:26 PM PST 24
Finished Jan 22 05:05:31 PM PST 24
Peak memory 208604 kb
Host smart-714bf9d1-155c-4e0d-a523-5e46c3f3cf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346145045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3346145045
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1928057258
Short name T308
Test name
Test status
Simulation time 39983799142 ps
CPU time 466.27 seconds
Started Jan 22 05:05:25 PM PST 24
Finished Jan 22 05:13:13 PM PST 24
Peak memory 216712 kb
Host smart-014e6501-f172-4d5d-bcdb-8f20d2c1d5ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928057258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1928057258
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.4209928610
Short name T835
Test name
Test status
Simulation time 385560722 ps
CPU time 7.31 seconds
Started Jan 22 05:05:34 PM PST 24
Finished Jan 22 05:05:43 PM PST 24
Peak memory 219836 kb
Host smart-c14d7cc0-a062-4cf5-a18f-cd4ff61fcdcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209928610 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.4209928610
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.81033204
Short name T948
Test name
Test status
Simulation time 198972600 ps
CPU time 3.57 seconds
Started Jan 22 05:05:30 PM PST 24
Finished Jan 22 05:05:35 PM PST 24
Peak memory 209908 kb
Host smart-0d5e688d-e5e6-40cc-a202-4421779961b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81033204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.81033204
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3975442317
Short name T1011
Test name
Test status
Simulation time 668814057 ps
CPU time 2.24 seconds
Started Jan 22 05:05:23 PM PST 24
Finished Jan 22 05:05:28 PM PST 24
Peak memory 210440 kb
Host smart-9daec9a9-b4d4-4672-834c-80eda4eb0cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975442317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3975442317
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.269510394
Short name T951
Test name
Test status
Simulation time 59048319 ps
CPU time 0.91 seconds
Started Jan 22 05:05:51 PM PST 24
Finished Jan 22 05:05:52 PM PST 24
Peak memory 206088 kb
Host smart-10645a5b-e925-4d25-a5e9-1e3a0420dec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269510394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.269510394
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1886430439
Short name T382
Test name
Test status
Simulation time 119060464 ps
CPU time 6.64 seconds
Started Jan 22 05:05:29 PM PST 24
Finished Jan 22 05:05:38 PM PST 24
Peak memory 214964 kb
Host smart-6373a07c-3904-40c7-b8e7-92fe9d6605d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886430439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1886430439
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.971701034
Short name T19
Test name
Test status
Simulation time 66872945 ps
CPU time 4.09 seconds
Started Jan 22 05:05:36 PM PST 24
Finished Jan 22 05:05:40 PM PST 24
Peak memory 221308 kb
Host smart-1e61a449-661f-4c25-93aa-17b23d5b5ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971701034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.971701034
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.115240605
Short name T636
Test name
Test status
Simulation time 390766117 ps
CPU time 3.35 seconds
Started Jan 22 05:05:29 PM PST 24
Finished Jan 22 05:05:33 PM PST 24
Peak memory 207248 kb
Host smart-a388fb3e-2a1a-458f-82a0-73d3eb1ab88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115240605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.115240605
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2587716668
Short name T585
Test name
Test status
Simulation time 495690100 ps
CPU time 4.75 seconds
Started Jan 22 05:05:29 PM PST 24
Finished Jan 22 05:05:36 PM PST 24
Peak memory 214256 kb
Host smart-336c9421-bb09-4418-af5f-1bc47bd15ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587716668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2587716668
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1245101711
Short name T194
Test name
Test status
Simulation time 106275666 ps
CPU time 4.43 seconds
Started Jan 22 05:05:36 PM PST 24
Finished Jan 22 05:05:41 PM PST 24
Peak memory 208240 kb
Host smart-7b52d838-d58a-47dc-94f5-c2e80dc7367d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245101711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1245101711
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2056486108
Short name T59
Test name
Test status
Simulation time 121694410 ps
CPU time 3.36 seconds
Started Jan 22 05:05:32 PM PST 24
Finished Jan 22 05:05:38 PM PST 24
Peak memory 209172 kb
Host smart-bf696d1a-e3f2-40d1-b6c9-9218d14fdbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056486108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2056486108
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.4055965683
Short name T316
Test name
Test status
Simulation time 294522658 ps
CPU time 8.44 seconds
Started Jan 22 05:05:30 PM PST 24
Finished Jan 22 05:05:40 PM PST 24
Peak memory 209756 kb
Host smart-2487a22b-d2be-4015-8e13-7d8b790a8297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055965683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.4055965683
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2172847717
Short name T560
Test name
Test status
Simulation time 35379858 ps
CPU time 2.57 seconds
Started Jan 22 05:05:29 PM PST 24
Finished Jan 22 05:05:34 PM PST 24
Peak memory 208520 kb
Host smart-92451bf8-ec59-4384-8fd2-31bf275bc294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172847717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2172847717
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3504514985
Short name T895
Test name
Test status
Simulation time 4509751489 ps
CPU time 69.03 seconds
Started Jan 22 05:05:26 PM PST 24
Finished Jan 22 05:06:36 PM PST 24
Peak memory 209152 kb
Host smart-284b0d07-65fa-476a-8311-40c30566c60c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504514985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3504514985
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.408740157
Short name T758
Test name
Test status
Simulation time 68310142 ps
CPU time 2.52 seconds
Started Jan 22 05:05:28 PM PST 24
Finished Jan 22 05:05:31 PM PST 24
Peak memory 206820 kb
Host smart-754ebc38-132a-41e8-84a5-6e9d9a86b9c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408740157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.408740157
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4237873792
Short name T734
Test name
Test status
Simulation time 25211393 ps
CPU time 2.05 seconds
Started Jan 22 05:05:27 PM PST 24
Finished Jan 22 05:05:30 PM PST 24
Peak memory 207536 kb
Host smart-393bb90b-c6a5-47c6-9da4-05614bd1e00b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237873792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4237873792
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3627791984
Short name T914
Test name
Test status
Simulation time 94630292 ps
CPU time 2.08 seconds
Started Jan 22 05:05:26 PM PST 24
Finished Jan 22 05:05:29 PM PST 24
Peak memory 207272 kb
Host smart-19572b39-e235-42a1-bffc-a04b3aea5933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627791984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3627791984
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.874569649
Short name T583
Test name
Test status
Simulation time 406913604 ps
CPU time 1.99 seconds
Started Jan 22 05:05:27 PM PST 24
Finished Jan 22 05:05:30 PM PST 24
Peak memory 208584 kb
Host smart-b6230893-75c1-422b-b70c-110b68bfd9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874569649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.874569649
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1153002910
Short name T265
Test name
Test status
Simulation time 139670169 ps
CPU time 5.58 seconds
Started Jan 22 05:36:41 PM PST 24
Finished Jan 22 05:36:51 PM PST 24
Peak memory 219808 kb
Host smart-54f8c502-cbf1-4773-90a9-8fcc7529a958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153002910 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1153002910
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3087630006
Short name T927
Test name
Test status
Simulation time 209234285 ps
CPU time 4.37 seconds
Started Jan 22 05:05:33 PM PST 24
Finished Jan 22 05:05:39 PM PST 24
Peak memory 207152 kb
Host smart-44787169-9d78-4418-9aaf-92efd306cc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087630006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3087630006
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.671845503
Short name T1004
Test name
Test status
Simulation time 127759497 ps
CPU time 2.08 seconds
Started Jan 22 06:21:59 PM PST 24
Finished Jan 22 06:22:04 PM PST 24
Peak memory 209752 kb
Host smart-60df1b6a-6a73-4639-a255-4045fa7a6f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671845503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.671845503
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.45472790
Short name T552
Test name
Test status
Simulation time 15886083 ps
CPU time 0.72 seconds
Started Jan 22 05:05:43 PM PST 24
Finished Jan 22 05:05:45 PM PST 24
Peak memory 205924 kb
Host smart-8910cd86-1932-4e54-9b75-0f51598ef22a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45472790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.45472790
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.51947299
Short name T18
Test name
Test status
Simulation time 140132089 ps
CPU time 3.9 seconds
Started Jan 22 05:05:49 PM PST 24
Finished Jan 22 05:05:54 PM PST 24
Peak memory 216880 kb
Host smart-c983542a-3da0-42e5-bcbb-0c4027fd2f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51947299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.51947299
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.58107170
Short name T641
Test name
Test status
Simulation time 91877341 ps
CPU time 1.93 seconds
Started Jan 22 05:05:41 PM PST 24
Finished Jan 22 05:05:43 PM PST 24
Peak memory 208116 kb
Host smart-fa37682c-9e24-4b8a-bd01-2e25967875aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58107170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.58107170
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1961568177
Short name T79
Test name
Test status
Simulation time 114300428 ps
CPU time 2.47 seconds
Started Jan 22 05:05:51 PM PST 24
Finished Jan 22 05:05:54 PM PST 24
Peak memory 214264 kb
Host smart-778bea7b-49ec-4595-b225-014474956593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961568177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1961568177
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3477173251
Short name T787
Test name
Test status
Simulation time 38324087 ps
CPU time 2.37 seconds
Started Jan 22 05:05:39 PM PST 24
Finished Jan 22 05:05:43 PM PST 24
Peak memory 206864 kb
Host smart-d67a0447-1de0-47c0-af99-7077ea2bf21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477173251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3477173251
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1445370885
Short name T983
Test name
Test status
Simulation time 265434882 ps
CPU time 3.62 seconds
Started Jan 22 05:05:39 PM PST 24
Finished Jan 22 05:05:43 PM PST 24
Peak memory 207592 kb
Host smart-4b38aa63-c88d-4d47-9dea-71f58c0151f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445370885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1445370885
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1183257564
Short name T882
Test name
Test status
Simulation time 95886976 ps
CPU time 3.56 seconds
Started Jan 22 05:05:49 PM PST 24
Finished Jan 22 05:05:53 PM PST 24
Peak memory 208652 kb
Host smart-cf27dbab-a644-4612-8c3e-365a57648f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183257564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1183257564
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.880617446
Short name T704
Test name
Test status
Simulation time 816116130 ps
CPU time 6.36 seconds
Started Jan 22 05:05:49 PM PST 24
Finished Jan 22 05:05:56 PM PST 24
Peak memory 207876 kb
Host smart-c0bad819-ad27-488f-aa00-051984365e32
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880617446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.880617446
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.61800462
Short name T242
Test name
Test status
Simulation time 266663428 ps
CPU time 3.56 seconds
Started Jan 22 05:05:45 PM PST 24
Finished Jan 22 05:05:49 PM PST 24
Peak memory 208664 kb
Host smart-f240c673-c9c4-4b09-a900-3bf0500e42cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61800462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.61800462
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3782314547
Short name T357
Test name
Test status
Simulation time 76105634 ps
CPU time 1.93 seconds
Started Jan 22 05:05:44 PM PST 24
Finished Jan 22 05:05:47 PM PST 24
Peak memory 206864 kb
Host smart-58de2a02-7c8f-4961-bdfd-55479946d85a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782314547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3782314547
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3481394456
Short name T289
Test name
Test status
Simulation time 86128221 ps
CPU time 4.05 seconds
Started Jan 22 05:05:49 PM PST 24
Finished Jan 22 05:05:54 PM PST 24
Peak memory 208524 kb
Host smart-ba637656-edf2-49d3-946a-c8652b22edd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481394456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3481394456
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3916131750
Short name T589
Test name
Test status
Simulation time 73925752 ps
CPU time 3.24 seconds
Started Jan 22 05:38:59 PM PST 24
Finished Jan 22 05:39:09 PM PST 24
Peak memory 208676 kb
Host smart-572177a6-20a0-465b-b187-174e8922f20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916131750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3916131750
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1294639771
Short name T689
Test name
Test status
Simulation time 478515179 ps
CPU time 17.03 seconds
Started Jan 22 05:05:44 PM PST 24
Finished Jan 22 05:06:02 PM PST 24
Peak memory 215976 kb
Host smart-6862f288-10ef-4bf8-9e8d-a002140c7fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294639771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1294639771
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2734459609
Short name T1005
Test name
Test status
Simulation time 113342587 ps
CPU time 3.33 seconds
Started Jan 22 05:29:22 PM PST 24
Finished Jan 22 05:29:26 PM PST 24
Peak memory 218936 kb
Host smart-01c65b41-0a24-46fc-803f-54d8878c9478
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734459609 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2734459609
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1711841391
Short name T906
Test name
Test status
Simulation time 420513155 ps
CPU time 4.73 seconds
Started Jan 22 05:05:40 PM PST 24
Finished Jan 22 05:05:46 PM PST 24
Peak memory 208676 kb
Host smart-b0297cec-534f-4235-836f-44dc2ae73fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711841391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1711841391
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1145766394
Short name T592
Test name
Test status
Simulation time 13460016 ps
CPU time 0.92 seconds
Started Jan 22 05:42:03 PM PST 24
Finished Jan 22 05:42:05 PM PST 24
Peak memory 205840 kb
Host smart-672c0dc8-b757-4a03-b9d7-593f4af88c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145766394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1145766394
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1458347985
Short name T387
Test name
Test status
Simulation time 743787179 ps
CPU time 4.67 seconds
Started Jan 22 05:05:44 PM PST 24
Finished Jan 22 05:05:49 PM PST 24
Peak memory 214236 kb
Host smart-5a5fd4a9-d19a-4be3-9e76-757a8b365673
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458347985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1458347985
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3845908777
Short name T30
Test name
Test status
Simulation time 195142287 ps
CPU time 4.39 seconds
Started Jan 22 05:10:21 PM PST 24
Finished Jan 22 05:10:26 PM PST 24
Peak memory 208756 kb
Host smart-685125d1-1a95-4f30-9bbb-c0af44ae0e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845908777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3845908777
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.820572152
Short name T330
Test name
Test status
Simulation time 151061965 ps
CPU time 4.29 seconds
Started Jan 22 05:05:49 PM PST 24
Finished Jan 22 05:05:54 PM PST 24
Peak memory 218360 kb
Host smart-50469501-1142-4fdc-9fbc-6039f4510e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820572152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.820572152
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.894267142
Short name T84
Test name
Test status
Simulation time 2464697481 ps
CPU time 30.75 seconds
Started Jan 22 05:17:30 PM PST 24
Finished Jan 22 05:18:02 PM PST 24
Peak memory 222468 kb
Host smart-8613fcf5-98c0-4b31-961c-c4ce3049ccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894267142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.894267142
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2749183281
Short name T999
Test name
Test status
Simulation time 703639818 ps
CPU time 10.82 seconds
Started Jan 22 05:05:46 PM PST 24
Finished Jan 22 05:05:58 PM PST 24
Peak memory 214184 kb
Host smart-3733abf3-f633-4bbc-8e6e-1c9992b85199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749183281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2749183281
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_random.3305847218
Short name T831
Test name
Test status
Simulation time 316468982 ps
CPU time 4.48 seconds
Started Jan 22 05:05:49 PM PST 24
Finished Jan 22 05:05:54 PM PST 24
Peak memory 207000 kb
Host smart-de49ede0-b54e-46a3-b57d-e4c0f4eda40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305847218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3305847218
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.415516050
Short name T954
Test name
Test status
Simulation time 66676612 ps
CPU time 2.45 seconds
Started Jan 22 05:05:47 PM PST 24
Finished Jan 22 05:05:50 PM PST 24
Peak memory 207420 kb
Host smart-af9f1354-754a-4a6a-9395-5135ad2b6a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415516050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.415516050
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3408285048
Short name T891
Test name
Test status
Simulation time 100102857 ps
CPU time 2.95 seconds
Started Jan 22 05:05:48 PM PST 24
Finished Jan 22 05:05:51 PM PST 24
Peak memory 208808 kb
Host smart-fb4596b7-b91f-432b-a3ff-9c82b9bc079d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408285048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3408285048
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.4108675268
Short name T586
Test name
Test status
Simulation time 287603277 ps
CPU time 7.69 seconds
Started Jan 22 05:38:53 PM PST 24
Finished Jan 22 05:39:04 PM PST 24
Peak memory 208608 kb
Host smart-89ea9877-98ec-41f9-8b5e-8e37019ca0c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108675268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.4108675268
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3043681514
Short name T687
Test name
Test status
Simulation time 382148128 ps
CPU time 3.23 seconds
Started Jan 22 05:05:45 PM PST 24
Finished Jan 22 05:05:49 PM PST 24
Peak memory 218352 kb
Host smart-b0b23b32-b543-4406-9032-5bfab526a3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043681514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3043681514
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.4204996793
Short name T985
Test name
Test status
Simulation time 168019596 ps
CPU time 4.55 seconds
Started Jan 22 05:05:46 PM PST 24
Finished Jan 22 05:05:51 PM PST 24
Peak memory 207772 kb
Host smart-67aa89b3-8545-4ca0-9680-c59414277f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204996793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.4204996793
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.95968500
Short name T629
Test name
Test status
Simulation time 13594973745 ps
CPU time 77.46 seconds
Started Jan 22 05:05:54 PM PST 24
Finished Jan 22 05:07:13 PM PST 24
Peak memory 217548 kb
Host smart-24630561-6d82-4d74-bddb-8eef75797390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95968500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.95968500
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3997056126
Short name T849
Test name
Test status
Simulation time 208708888 ps
CPU time 5.75 seconds
Started Jan 22 05:05:52 PM PST 24
Finished Jan 22 05:05:59 PM PST 24
Peak memory 220124 kb
Host smart-160fafd5-176c-48c2-8922-574bfeb8d4d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997056126 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3997056126
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1594083676
Short name T124
Test name
Test status
Simulation time 447068340 ps
CPU time 9.33 seconds
Started Jan 22 05:05:45 PM PST 24
Finished Jan 22 05:05:55 PM PST 24
Peak memory 218452 kb
Host smart-42d16fcb-6fd2-4b75-b786-dd19777ae0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594083676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1594083676
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3609272737
Short name T56
Test name
Test status
Simulation time 283959667 ps
CPU time 3.12 seconds
Started Jan 22 05:05:54 PM PST 24
Finished Jan 22 05:05:59 PM PST 24
Peak memory 210152 kb
Host smart-ff21f834-80ba-4294-a4ee-7ffb1ca66b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609272737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3609272737
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1833631373
Short name T864
Test name
Test status
Simulation time 45495147 ps
CPU time 0.75 seconds
Started Jan 22 05:06:07 PM PST 24
Finished Jan 22 05:06:15 PM PST 24
Peak memory 205952 kb
Host smart-362d3935-4466-4dac-ae12-74e897bd0a67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833631373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1833631373
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3511444559
Short name T789
Test name
Test status
Simulation time 560413007 ps
CPU time 4.71 seconds
Started Jan 22 05:05:57 PM PST 24
Finished Jan 22 05:06:03 PM PST 24
Peak memory 210680 kb
Host smart-75be7262-e307-4d4c-8ae3-b4070281bb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511444559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3511444559
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2670271237
Short name T764
Test name
Test status
Simulation time 3591993387 ps
CPU time 28.15 seconds
Started Jan 22 05:05:56 PM PST 24
Finished Jan 22 05:06:25 PM PST 24
Peak memory 221888 kb
Host smart-3fb22b4c-5086-4e99-833e-500824764807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670271237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2670271237
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.4270107289
Short name T238
Test name
Test status
Simulation time 295909796 ps
CPU time 7.95 seconds
Started Jan 22 05:06:08 PM PST 24
Finished Jan 22 05:06:23 PM PST 24
Peak memory 214316 kb
Host smart-40bcc822-9a16-4e70-adff-04a5ad861add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270107289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.4270107289
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1763526728
Short name T847
Test name
Test status
Simulation time 376325109 ps
CPU time 4.75 seconds
Started Jan 22 05:05:56 PM PST 24
Finished Jan 22 05:06:01 PM PST 24
Peak memory 216316 kb
Host smart-91cd36ba-3ef0-4e2f-8783-772618d5c2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763526728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1763526728
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.609483793
Short name T712
Test name
Test status
Simulation time 176090902 ps
CPU time 3.3 seconds
Started Jan 22 05:05:56 PM PST 24
Finished Jan 22 05:06:01 PM PST 24
Peak memory 207024 kb
Host smart-aa188ee2-bc74-4150-92a2-24575abe1541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609483793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.609483793
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2866053517
Short name T521
Test name
Test status
Simulation time 348403205 ps
CPU time 5.02 seconds
Started Jan 22 05:05:55 PM PST 24
Finished Jan 22 05:06:01 PM PST 24
Peak memory 206804 kb
Host smart-82104f76-63df-4e82-8707-512c215aca21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866053517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2866053517
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1700870508
Short name T558
Test name
Test status
Simulation time 387981591 ps
CPU time 3.43 seconds
Started Jan 22 05:05:56 PM PST 24
Finished Jan 22 05:06:00 PM PST 24
Peak memory 208388 kb
Host smart-874b75ad-a89f-4239-b9c8-7d7fa67710cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700870508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1700870508
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2279715021
Short name T574
Test name
Test status
Simulation time 197709087 ps
CPU time 2.89 seconds
Started Jan 22 05:05:52 PM PST 24
Finished Jan 22 05:05:56 PM PST 24
Peak memory 206652 kb
Host smart-ade20f1a-ec7a-4608-b6f5-258d519878bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279715021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2279715021
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.474105612
Short name T1008
Test name
Test status
Simulation time 5461043051 ps
CPU time 52.75 seconds
Started Jan 22 05:05:56 PM PST 24
Finished Jan 22 05:06:50 PM PST 24
Peak memory 208400 kb
Host smart-277bb75b-0476-44be-bcb8-0e377f87b78f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474105612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.474105612
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.50819376
Short name T1039
Test name
Test status
Simulation time 120906033 ps
CPU time 2.5 seconds
Started Jan 22 05:06:07 PM PST 24
Finished Jan 22 05:06:16 PM PST 24
Peak memory 210084 kb
Host smart-55eecb6e-6c03-43b6-8731-9feffe58a77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50819376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.50819376
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2129145654
Short name T526
Test name
Test status
Simulation time 22363543 ps
CPU time 1.84 seconds
Started Jan 22 05:05:56 PM PST 24
Finished Jan 22 05:05:58 PM PST 24
Peak memory 206560 kb
Host smart-979e5aea-1b98-4a43-abdc-e8f9bc1f2933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129145654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2129145654
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.119491458
Short name T757
Test name
Test status
Simulation time 4823161440 ps
CPU time 50.83 seconds
Started Jan 22 05:06:04 PM PST 24
Finished Jan 22 05:06:56 PM PST 24
Peak memory 214960 kb
Host smart-81be4a73-4c47-4df7-9a1d-c0d23c8d36a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119491458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.119491458
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3503061730
Short name T996
Test name
Test status
Simulation time 397096617 ps
CPU time 4.3 seconds
Started Jan 22 05:06:04 PM PST 24
Finished Jan 22 05:06:09 PM PST 24
Peak memory 219184 kb
Host smart-cc6eae84-ab6e-437a-96df-db4c4618246f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503061730 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3503061730
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1621772284
Short name T876
Test name
Test status
Simulation time 84939542 ps
CPU time 3.88 seconds
Started Jan 22 05:06:07 PM PST 24
Finished Jan 22 05:06:17 PM PST 24
Peak memory 209432 kb
Host smart-0d57ab5e-9bf8-456c-a004-dcd86b5d303c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621772284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1621772284
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.384523846
Short name T577
Test name
Test status
Simulation time 504849345 ps
CPU time 3.17 seconds
Started Jan 22 05:06:10 PM PST 24
Finished Jan 22 05:06:18 PM PST 24
Peak memory 210352 kb
Host smart-da39d255-fd4e-4980-967e-29f4d7417c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384523846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.384523846
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4276020859
Short name T993
Test name
Test status
Simulation time 308245737 ps
CPU time 1.13 seconds
Started Jan 22 05:06:10 PM PST 24
Finished Jan 22 05:06:16 PM PST 24
Peak memory 206048 kb
Host smart-37a2756d-9c40-4ef9-b658-4ae2266463b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276020859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4276020859
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2075681423
Short name T222
Test name
Test status
Simulation time 455371934 ps
CPU time 8.38 seconds
Started Jan 22 05:06:09 PM PST 24
Finished Jan 22 05:06:23 PM PST 24
Peak memory 214172 kb
Host smart-c41e1e04-f4db-49f8-8442-5105ac912772
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075681423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2075681423
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.9950888
Short name T32
Test name
Test status
Simulation time 268662035 ps
CPU time 8.79 seconds
Started Jan 22 05:06:12 PM PST 24
Finished Jan 22 05:06:24 PM PST 24
Peak memory 214328 kb
Host smart-b43de092-eed3-4526-b557-bbaa0b767c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9950888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.9950888
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3266507413
Short name T69
Test name
Test status
Simulation time 173241031 ps
CPU time 2.47 seconds
Started Jan 22 05:06:04 PM PST 24
Finished Jan 22 05:06:07 PM PST 24
Peak memory 208876 kb
Host smart-ed573bcb-4d92-4983-978f-cd8436545159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266507413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3266507413
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1106171218
Short name T86
Test name
Test status
Simulation time 480815516 ps
CPU time 6.71 seconds
Started Jan 22 05:06:10 PM PST 24
Finished Jan 22 05:06:22 PM PST 24
Peak memory 220180 kb
Host smart-e7b7abb6-08eb-4324-a155-b5e0b1bc5e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106171218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1106171218
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3274703545
Short name T284
Test name
Test status
Simulation time 1552664186 ps
CPU time 41.77 seconds
Started Jan 22 05:06:10 PM PST 24
Finished Jan 22 05:06:57 PM PST 24
Peak memory 215116 kb
Host smart-2d70324b-551f-4e86-8940-98cc5c8cac15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274703545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3274703545
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3194088467
Short name T52
Test name
Test status
Simulation time 66451309 ps
CPU time 3.33 seconds
Started Jan 22 05:06:04 PM PST 24
Finished Jan 22 05:06:09 PM PST 24
Peak memory 220644 kb
Host smart-51b9539c-0241-45e0-ac1a-78835e01a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194088467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3194088467
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.699347375
Short name T619
Test name
Test status
Simulation time 1119020143 ps
CPU time 23.04 seconds
Started Jan 22 05:06:01 PM PST 24
Finished Jan 22 05:06:25 PM PST 24
Peak memory 214180 kb
Host smart-94b880a4-ab3b-4054-a664-a14e60c81cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699347375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.699347375
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.86697994
Short name T698
Test name
Test status
Simulation time 4088274288 ps
CPU time 44.13 seconds
Started Jan 22 05:06:03 PM PST 24
Finished Jan 22 05:06:48 PM PST 24
Peak memory 208316 kb
Host smart-da365c1f-8c7b-4cdf-be22-6af9c39f0639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86697994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.86697994
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1024598084
Short name T992
Test name
Test status
Simulation time 229101616 ps
CPU time 3.19 seconds
Started Jan 22 05:06:05 PM PST 24
Finished Jan 22 05:06:10 PM PST 24
Peak memory 208604 kb
Host smart-1430746b-6f7e-4041-8e25-ca11f6f43ffa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024598084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1024598084
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.4261546530
Short name T797
Test name
Test status
Simulation time 482187861 ps
CPU time 4.18 seconds
Started Jan 22 05:06:02 PM PST 24
Finished Jan 22 05:06:07 PM PST 24
Peak memory 208652 kb
Host smart-2673ceee-3be4-4dcf-b3fc-c484a49804ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261546530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.4261546530
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1631893442
Short name T74
Test name
Test status
Simulation time 399481432 ps
CPU time 12.34 seconds
Started Jan 22 05:06:03 PM PST 24
Finished Jan 22 05:06:16 PM PST 24
Peak memory 208368 kb
Host smart-89c2c5a8-060b-4918-851f-c226cddba37a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631893442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1631893442
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2262379349
Short name T707
Test name
Test status
Simulation time 89687060 ps
CPU time 2.09 seconds
Started Jan 22 05:06:14 PM PST 24
Finished Jan 22 05:06:21 PM PST 24
Peak memory 209588 kb
Host smart-f25deb00-c41e-4163-bcae-cfdfd0bd53ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262379349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2262379349
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4093174723
Short name T565
Test name
Test status
Simulation time 144733333 ps
CPU time 2.35 seconds
Started Jan 22 05:06:04 PM PST 24
Finished Jan 22 05:06:07 PM PST 24
Peak memory 206512 kb
Host smart-c141dde9-c83e-467d-a661-bcfd63717601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093174723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4093174723
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1061638950
Short name T68
Test name
Test status
Simulation time 39702320938 ps
CPU time 437.37 seconds
Started Jan 22 05:06:14 PM PST 24
Finished Jan 22 05:13:36 PM PST 24
Peak memory 222672 kb
Host smart-f5bb0854-4ca5-40bc-8f27-5a303562bd95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061638950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1061638950
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1870734724
Short name T815
Test name
Test status
Simulation time 281454603 ps
CPU time 9.66 seconds
Started Jan 22 05:06:10 PM PST 24
Finished Jan 22 05:06:25 PM PST 24
Peak memory 219996 kb
Host smart-aa6df00f-ee07-4486-90c8-f00e5c261b81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870734724 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1870734724
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3233421459
Short name T239
Test name
Test status
Simulation time 499994908 ps
CPU time 4.4 seconds
Started Jan 22 05:06:05 PM PST 24
Finished Jan 22 05:06:11 PM PST 24
Peak memory 209868 kb
Host smart-8d63e7e8-e371-40c2-8d8c-4f1dc29b057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233421459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3233421459
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.547788080
Short name T723
Test name
Test status
Simulation time 149297181 ps
CPU time 4.54 seconds
Started Jan 22 05:06:12 PM PST 24
Finished Jan 22 05:06:20 PM PST 24
Peak memory 210648 kb
Host smart-44660ba6-db47-47e3-8734-04a18e0dd3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547788080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.547788080
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3663824642
Short name T964
Test name
Test status
Simulation time 25490246 ps
CPU time 0.86 seconds
Started Jan 22 04:59:32 PM PST 24
Finished Jan 22 04:59:33 PM PST 24
Peak memory 205892 kb
Host smart-e6b36d23-5763-4ebe-aeaf-818a1e2f87c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663824642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3663824642
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1845929539
Short name T336
Test name
Test status
Simulation time 128849359 ps
CPU time 2.59 seconds
Started Jan 22 04:59:41 PM PST 24
Finished Jan 22 04:59:44 PM PST 24
Peak memory 218380 kb
Host smart-c3774e86-86a9-417e-92bb-99c187aa94bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845929539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1845929539
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.4064464703
Short name T841
Test name
Test status
Simulation time 47183357 ps
CPU time 1.97 seconds
Started Jan 22 04:59:35 PM PST 24
Finished Jan 22 04:59:38 PM PST 24
Peak memory 207548 kb
Host smart-3942554d-0b46-4b76-b54a-e2d4c82f4e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064464703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.4064464703
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2296049819
Short name T78
Test name
Test status
Simulation time 327324923 ps
CPU time 9.13 seconds
Started Jan 22 04:59:33 PM PST 24
Finished Jan 22 04:59:43 PM PST 24
Peak memory 218528 kb
Host smart-4c643f1b-7b11-4fd6-a412-ff2b5c9a461d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296049819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2296049819
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4000547343
Short name T211
Test name
Test status
Simulation time 151153471 ps
CPU time 3.67 seconds
Started Jan 22 04:59:37 PM PST 24
Finished Jan 22 04:59:41 PM PST 24
Peak memory 215688 kb
Host smart-7d84d8d4-ee48-410e-a204-d6f993deede9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000547343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4000547343
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.462826667
Short name T579
Test name
Test status
Simulation time 449395276 ps
CPU time 4.35 seconds
Started Jan 22 04:59:33 PM PST 24
Finished Jan 22 04:59:38 PM PST 24
Peak memory 207664 kb
Host smart-c26c7d0a-39fe-4bd5-8dfa-d409244eea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462826667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.462826667
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3418726028
Short name T842
Test name
Test status
Simulation time 287671058 ps
CPU time 5.31 seconds
Started Jan 22 04:59:29 PM PST 24
Finished Jan 22 04:59:34 PM PST 24
Peak memory 206560 kb
Host smart-1305c373-e3f9-42a6-a7ff-a8cc766bd6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418726028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3418726028
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3107089157
Short name T72
Test name
Test status
Simulation time 48399775 ps
CPU time 2.87 seconds
Started Jan 22 04:59:32 PM PST 24
Finished Jan 22 04:59:36 PM PST 24
Peak memory 206856 kb
Host smart-12ac12a9-ef9f-419e-b266-9d546d2c5159
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107089157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3107089157
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3474899068
Short name T622
Test name
Test status
Simulation time 11226531936 ps
CPU time 22.55 seconds
Started Jan 22 04:59:42 PM PST 24
Finished Jan 22 05:00:05 PM PST 24
Peak memory 209020 kb
Host smart-9f4f8051-3740-47aa-8800-f0a2e14df17d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474899068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3474899068
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3710687549
Short name T697
Test name
Test status
Simulation time 266734147 ps
CPU time 3.51 seconds
Started Jan 22 04:59:35 PM PST 24
Finished Jan 22 04:59:39 PM PST 24
Peak memory 208516 kb
Host smart-0b6fc5c5-a024-484b-b5e9-f6272a872c61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710687549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3710687549
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2425994458
Short name T100
Test name
Test status
Simulation time 238748027 ps
CPU time 2.63 seconds
Started Jan 22 04:59:36 PM PST 24
Finished Jan 22 04:59:39 PM PST 24
Peak memory 208928 kb
Host smart-5be6ab6b-196d-4c47-b188-5a2e2f566281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425994458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2425994458
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.578594544
Short name T551
Test name
Test status
Simulation time 230739376 ps
CPU time 2.44 seconds
Started Jan 22 04:59:30 PM PST 24
Finished Jan 22 04:59:33 PM PST 24
Peak memory 206544 kb
Host smart-342cae54-accd-4efb-8500-8ec0d39693ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578594544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.578594544
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1243110543
Short name T45
Test name
Test status
Simulation time 209061480 ps
CPU time 6.96 seconds
Started Jan 22 04:59:34 PM PST 24
Finished Jan 22 04:59:41 PM PST 24
Peak memory 223432 kb
Host smart-2d860b81-8440-4f6d-9086-dc97c4af1146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243110543 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1243110543
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.14966827
Short name T747
Test name
Test status
Simulation time 988697971 ps
CPU time 13.5 seconds
Started Jan 22 04:59:32 PM PST 24
Finished Jan 22 04:59:46 PM PST 24
Peak memory 214252 kb
Host smart-f684c66a-322a-40d7-a118-8451d752abf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14966827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.14966827
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.647232118
Short name T770
Test name
Test status
Simulation time 213266261 ps
CPU time 1.93 seconds
Started Jan 22 04:59:32 PM PST 24
Finished Jan 22 04:59:34 PM PST 24
Peak memory 210800 kb
Host smart-0354ff18-d418-4160-a567-a2affe48f6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647232118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.647232118
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.225307977
Short name T694
Test name
Test status
Simulation time 28146139 ps
CPU time 0.75 seconds
Started Jan 22 04:59:40 PM PST 24
Finished Jan 22 04:59:41 PM PST 24
Peak memory 205856 kb
Host smart-5cc1f3ff-953e-4bff-9c7d-a18de60dd707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225307977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.225307977
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3490788993
Short name T399
Test name
Test status
Simulation time 120497250 ps
CPU time 2.72 seconds
Started Jan 22 04:59:33 PM PST 24
Finished Jan 22 04:59:36 PM PST 24
Peak memory 215032 kb
Host smart-e0a48b4f-7d1f-45b8-82c4-15ecebcc5a5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3490788993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3490788993
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1080358357
Short name T28
Test name
Test status
Simulation time 248688943 ps
CPU time 3.33 seconds
Started Jan 22 04:59:44 PM PST 24
Finished Jan 22 04:59:48 PM PST 24
Peak memory 209204 kb
Host smart-0bd49beb-3d79-409e-9775-ae004efad709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080358357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1080358357
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2633543573
Short name T1
Test name
Test status
Simulation time 174943759 ps
CPU time 4.97 seconds
Started Jan 22 04:59:33 PM PST 24
Finished Jan 22 04:59:39 PM PST 24
Peak memory 214280 kb
Host smart-7ccae109-7e06-4ee7-bc6d-41517aace1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633543573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2633543573
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3265414928
Short name T631
Test name
Test status
Simulation time 136319860 ps
CPU time 4.98 seconds
Started Jan 22 04:59:37 PM PST 24
Finished Jan 22 04:59:43 PM PST 24
Peak memory 214280 kb
Host smart-1e59e0b3-9f8c-44f5-a8be-db37dda2acb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265414928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3265414928
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3816314057
Short name T313
Test name
Test status
Simulation time 63178099 ps
CPU time 2.63 seconds
Started Jan 22 04:59:42 PM PST 24
Finished Jan 22 04:59:45 PM PST 24
Peak memory 210432 kb
Host smart-9afcd59e-f7d8-4e7e-8bbc-6325ca859346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816314057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3816314057
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.412824089
Short name T58
Test name
Test status
Simulation time 43518866 ps
CPU time 3.34 seconds
Started Jan 22 04:59:41 PM PST 24
Finished Jan 22 04:59:45 PM PST 24
Peak memory 208252 kb
Host smart-799bb232-38a4-4d22-af82-380e50445e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412824089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.412824089
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.4234032671
Short name T70
Test name
Test status
Simulation time 4122050218 ps
CPU time 35.77 seconds
Started Jan 22 04:59:35 PM PST 24
Finished Jan 22 05:00:11 PM PST 24
Peak memory 214340 kb
Host smart-3e0f4731-bd7c-4c50-a7c8-aad3e62be8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234032671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.4234032671
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1599357853
Short name T792
Test name
Test status
Simulation time 137875513 ps
CPU time 2.33 seconds
Started Jan 22 04:59:41 PM PST 24
Finished Jan 22 04:59:44 PM PST 24
Peak memory 206804 kb
Host smart-b00b1d9d-df17-4d99-ba43-e5842b5968e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599357853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1599357853
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1058914446
Short name T784
Test name
Test status
Simulation time 70673976 ps
CPU time 3.38 seconds
Started Jan 22 04:59:31 PM PST 24
Finished Jan 22 04:59:35 PM PST 24
Peak memory 208708 kb
Host smart-05fa4038-7a2d-4fd5-8f8e-64d298ad5b0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058914446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1058914446
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.887093973
Short name T666
Test name
Test status
Simulation time 118448329 ps
CPU time 3.29 seconds
Started Jan 22 04:59:32 PM PST 24
Finished Jan 22 04:59:36 PM PST 24
Peak memory 208308 kb
Host smart-94691437-5192-4c5e-9f1c-7699862b5169
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887093973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.887093973
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2058194038
Short name T252
Test name
Test status
Simulation time 371993625 ps
CPU time 5.61 seconds
Started Jan 22 04:59:41 PM PST 24
Finished Jan 22 04:59:47 PM PST 24
Peak memory 206868 kb
Host smart-9656210f-263d-451b-932d-83a9fb4d6a59
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058194038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2058194038
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2617952176
Short name T801
Test name
Test status
Simulation time 527574362 ps
CPU time 4.32 seconds
Started Jan 22 04:59:42 PM PST 24
Finished Jan 22 04:59:47 PM PST 24
Peak memory 209340 kb
Host smart-eb6b50e9-2303-44d7-8a87-639c9e28385e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617952176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2617952176
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2104214655
Short name T528
Test name
Test status
Simulation time 286478115 ps
CPU time 3.92 seconds
Started Jan 22 04:59:42 PM PST 24
Finished Jan 22 04:59:46 PM PST 24
Peak memory 208472 kb
Host smart-3016dfb3-a730-44af-9795-141f21992f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104214655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2104214655
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1210043658
Short name T665
Test name
Test status
Simulation time 265518571 ps
CPU time 8.32 seconds
Started Jan 22 04:59:41 PM PST 24
Finished Jan 22 04:59:50 PM PST 24
Peak memory 209084 kb
Host smart-7f324679-1c71-47fc-af29-01f0f8d6f417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210043658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1210043658
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2638190924
Short name T946
Test name
Test status
Simulation time 137575123 ps
CPU time 3.86 seconds
Started Jan 22 04:59:37 PM PST 24
Finished Jan 22 04:59:41 PM PST 24
Peak memory 218156 kb
Host smart-99dc4711-c222-44c8-bd98-53d900d3f00f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638190924 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2638190924
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2022662588
Short name T1010
Test name
Test status
Simulation time 386556779 ps
CPU time 4.39 seconds
Started Jan 22 04:59:35 PM PST 24
Finished Jan 22 04:59:40 PM PST 24
Peak memory 218228 kb
Host smart-c799dc8a-eae6-4eb7-a06d-b89223c248a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022662588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2022662588
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3113806975
Short name T561
Test name
Test status
Simulation time 320307004 ps
CPU time 4.66 seconds
Started Jan 22 04:59:36 PM PST 24
Finished Jan 22 04:59:41 PM PST 24
Peak memory 210912 kb
Host smart-2e975db2-6136-4a0f-b0fc-522793948c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113806975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3113806975
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2814843163
Short name T818
Test name
Test status
Simulation time 55666826 ps
CPU time 0.79 seconds
Started Jan 22 04:59:50 PM PST 24
Finished Jan 22 04:59:52 PM PST 24
Peak memory 205876 kb
Host smart-14b1981f-ebd6-48c7-8b16-fc0b5419fee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814843163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2814843163
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2670556083
Short name T20
Test name
Test status
Simulation time 309865910 ps
CPU time 3.54 seconds
Started Jan 22 04:59:46 PM PST 24
Finished Jan 22 04:59:50 PM PST 24
Peak memory 221468 kb
Host smart-e8124f6f-d416-4fc3-8c32-c368f100d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670556083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2670556083
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3815171752
Short name T312
Test name
Test status
Simulation time 55819270 ps
CPU time 1.81 seconds
Started Jan 22 04:59:50 PM PST 24
Finished Jan 22 04:59:52 PM PST 24
Peak memory 206756 kb
Host smart-a2a9b160-52c6-4bd7-b5c2-a422e9e82dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815171752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3815171752
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1436321997
Short name T1036
Test name
Test status
Simulation time 317167461 ps
CPU time 8.46 seconds
Started Jan 22 04:59:43 PM PST 24
Finished Jan 22 04:59:52 PM PST 24
Peak memory 209516 kb
Host smart-22dd18a1-1661-43fe-853c-29c374bf08ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436321997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1436321997
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3818988188
Short name T281
Test name
Test status
Simulation time 623547399 ps
CPU time 11.38 seconds
Started Jan 22 04:59:50 PM PST 24
Finished Jan 22 05:00:02 PM PST 24
Peak memory 214268 kb
Host smart-b5ea96a0-8cfa-4c65-b5aa-8a7b22c50bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818988188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3818988188
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3952665828
Short name T212
Test name
Test status
Simulation time 200567723 ps
CPU time 3.03 seconds
Started Jan 22 04:59:48 PM PST 24
Finished Jan 22 04:59:52 PM PST 24
Peak memory 218724 kb
Host smart-3eb90b35-6664-4fd7-8e28-5350bc5275c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952665828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3952665828
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1593277733
Short name T885
Test name
Test status
Simulation time 3153770735 ps
CPU time 73.47 seconds
Started Jan 22 04:59:34 PM PST 24
Finished Jan 22 05:00:48 PM PST 24
Peak memory 209520 kb
Host smart-d54a06ab-1962-45d3-b306-635df2d9c35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593277733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1593277733
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1282293003
Short name T878
Test name
Test status
Simulation time 97636157 ps
CPU time 2.78 seconds
Started Jan 22 04:59:40 PM PST 24
Finished Jan 22 04:59:44 PM PST 24
Peak memory 208508 kb
Host smart-43e37286-e701-4959-9ad4-2ba4648ae4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282293003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1282293003
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.522076588
Short name T811
Test name
Test status
Simulation time 432114134 ps
CPU time 3.13 seconds
Started Jan 22 04:59:42 PM PST 24
Finished Jan 22 04:59:46 PM PST 24
Peak memory 208572 kb
Host smart-6552bae2-973f-4575-9c76-3fc15a8399be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522076588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.522076588
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.66981040
Short name T530
Test name
Test status
Simulation time 149741999 ps
CPU time 6.05 seconds
Started Jan 22 04:59:42 PM PST 24
Finished Jan 22 04:59:48 PM PST 24
Peak memory 206928 kb
Host smart-9c98f79d-7d9f-4c6d-be2c-3b374e6cd770
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66981040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.66981040
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3287466177
Short name T803
Test name
Test status
Simulation time 283890749 ps
CPU time 3.41 seconds
Started Jan 22 04:59:36 PM PST 24
Finished Jan 22 04:59:41 PM PST 24
Peak memory 208884 kb
Host smart-f1f3c035-5d75-4246-8b88-3b6b17f7ad2b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287466177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3287466177
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1767671693
Short name T868
Test name
Test status
Simulation time 67878628 ps
CPU time 1.98 seconds
Started Jan 22 04:59:44 PM PST 24
Finished Jan 22 04:59:46 PM PST 24
Peak memory 215312 kb
Host smart-a9e26b96-cb7d-4449-ac66-8bf676bb61ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767671693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1767671693
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.283266262
Short name T716
Test name
Test status
Simulation time 913384647 ps
CPU time 6.98 seconds
Started Jan 22 04:59:37 PM PST 24
Finished Jan 22 04:59:44 PM PST 24
Peak memory 207812 kb
Host smart-572d0fd9-5644-4010-aca6-3c8376a005e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283266262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.283266262
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1337089234
Short name T290
Test name
Test status
Simulation time 4186811286 ps
CPU time 31.69 seconds
Started Jan 22 04:59:49 PM PST 24
Finished Jan 22 05:00:22 PM PST 24
Peak memory 216432 kb
Host smart-0b9cebbd-4358-4d7d-9f58-953c6da4a303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337089234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1337089234
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3271713153
Short name T786
Test name
Test status
Simulation time 331399023 ps
CPU time 3.09 seconds
Started Jan 22 04:59:48 PM PST 24
Finished Jan 22 04:59:51 PM PST 24
Peak memory 219452 kb
Host smart-9928920e-fe0c-4ff4-985c-dfc1335dfc70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271713153 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3271713153
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1287931597
Short name T682
Test name
Test status
Simulation time 587492621 ps
CPU time 18.87 seconds
Started Jan 22 04:59:43 PM PST 24
Finished Jan 22 05:00:02 PM PST 24
Peak memory 209344 kb
Host smart-ebc4862d-4ff4-4756-bf26-0e1e56360952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287931597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1287931597
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3873520522
Short name T825
Test name
Test status
Simulation time 118475357 ps
CPU time 1.52 seconds
Started Jan 22 04:59:47 PM PST 24
Finished Jan 22 04:59:49 PM PST 24
Peak memory 209596 kb
Host smart-6d13db81-a80f-42fa-bd65-a2d821ea7494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873520522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3873520522
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1339206121
Short name T941
Test name
Test status
Simulation time 43360879 ps
CPU time 0.86 seconds
Started Jan 22 04:59:51 PM PST 24
Finished Jan 22 04:59:53 PM PST 24
Peak memory 205868 kb
Host smart-2c03aea7-6fd2-4e15-b0db-5e42a94ddf30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339206121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1339206121
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1556251779
Short name T271
Test name
Test status
Simulation time 1876885729 ps
CPU time 17.7 seconds
Started Jan 22 04:59:56 PM PST 24
Finished Jan 22 05:00:14 PM PST 24
Peak memory 215140 kb
Host smart-c722fb60-355b-4bac-a066-80e67144fcbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1556251779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1556251779
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3084030065
Short name T9
Test name
Test status
Simulation time 169801196 ps
CPU time 2.37 seconds
Started Jan 22 04:59:55 PM PST 24
Finished Jan 22 04:59:58 PM PST 24
Peak memory 209376 kb
Host smart-52c483e1-6b6d-4b16-8a50-af836e639a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084030065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3084030065
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.457330294
Short name T845
Test name
Test status
Simulation time 81623611 ps
CPU time 2.5 seconds
Started Jan 22 04:59:59 PM PST 24
Finished Jan 22 05:00:02 PM PST 24
Peak memory 207428 kb
Host smart-145c140c-5aae-48fd-972b-8d2971442be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457330294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.457330294
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1201879821
Short name T1012
Test name
Test status
Simulation time 74453433 ps
CPU time 3.22 seconds
Started Jan 22 04:59:51 PM PST 24
Finished Jan 22 04:59:55 PM PST 24
Peak memory 208236 kb
Host smart-5e00e2ab-bcba-4da7-9b9f-64301c924903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201879821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1201879821
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3830450038
Short name T43
Test name
Test status
Simulation time 42309509 ps
CPU time 2.65 seconds
Started Jan 22 04:59:56 PM PST 24
Finished Jan 22 04:59:59 PM PST 24
Peak memory 209132 kb
Host smart-05d50782-0312-4fff-8815-e4aae8c328a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830450038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3830450038
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2309883584
Short name T97
Test name
Test status
Simulation time 67562070 ps
CPU time 3.98 seconds
Started Jan 22 04:59:56 PM PST 24
Finished Jan 22 05:00:00 PM PST 24
Peak memory 210204 kb
Host smart-8e5667e5-06d3-4b16-bf32-6aa62d24aa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309883584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2309883584
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.525018677
Short name T649
Test name
Test status
Simulation time 210992194 ps
CPU time 6.15 seconds
Started Jan 22 04:59:55 PM PST 24
Finished Jan 22 05:00:01 PM PST 24
Peak memory 208856 kb
Host smart-e4fb032f-c97e-49f4-a6d7-cd139730aca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525018677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.525018677
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1334704833
Short name T685
Test name
Test status
Simulation time 1220891523 ps
CPU time 9.65 seconds
Started Jan 22 04:59:52 PM PST 24
Finished Jan 22 05:00:02 PM PST 24
Peak memory 208056 kb
Host smart-fe6a550c-6112-4231-8c50-52244af1fb41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334704833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1334704833
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2865702336
Short name T836
Test name
Test status
Simulation time 114636775 ps
CPU time 3.85 seconds
Started Jan 22 04:59:51 PM PST 24
Finished Jan 22 04:59:55 PM PST 24
Peak memory 206636 kb
Host smart-2062813f-9bc3-4a11-ab63-de33c24245f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865702336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2865702336
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3335695748
Short name T947
Test name
Test status
Simulation time 319566494 ps
CPU time 4.36 seconds
Started Jan 22 04:59:56 PM PST 24
Finished Jan 22 05:00:01 PM PST 24
Peak memory 206848 kb
Host smart-a362164c-9faa-4d7d-a0e1-4bb9fccd2575
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335695748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3335695748
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1585719351
Short name T994
Test name
Test status
Simulation time 38417688 ps
CPU time 1.98 seconds
Started Jan 22 04:59:56 PM PST 24
Finished Jan 22 04:59:59 PM PST 24
Peak memory 208612 kb
Host smart-2c882422-a0d4-444e-94dc-aa9081669fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585719351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1585719351
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1597648790
Short name T930
Test name
Test status
Simulation time 931555903 ps
CPU time 12.33 seconds
Started Jan 22 04:59:54 PM PST 24
Finished Jan 22 05:00:07 PM PST 24
Peak memory 208736 kb
Host smart-7a52ef30-3329-436e-8a70-221b36914b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597648790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1597648790
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.978280071
Short name T358
Test name
Test status
Simulation time 4307353751 ps
CPU time 47 seconds
Started Jan 22 04:59:54 PM PST 24
Finished Jan 22 05:00:42 PM PST 24
Peak memory 222448 kb
Host smart-0462e20c-2254-461e-87c0-7ed9a268069d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978280071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.978280071
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3623810893
Short name T202
Test name
Test status
Simulation time 1866586008 ps
CPU time 9.45 seconds
Started Jan 22 04:59:56 PM PST 24
Finished Jan 22 05:00:05 PM PST 24
Peak memory 219724 kb
Host smart-9d08a038-01a6-4fe0-a2b3-8f9b0e9a0ead
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623810893 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3623810893
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.4202021122
Short name T790
Test name
Test status
Simulation time 210870473 ps
CPU time 4.56 seconds
Started Jan 22 04:59:59 PM PST 24
Finished Jan 22 05:00:03 PM PST 24
Peak memory 208132 kb
Host smart-585950f3-5619-4009-b9df-cf324f9813f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202021122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.4202021122
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1636268573
Short name T613
Test name
Test status
Simulation time 45828521 ps
CPU time 0.87 seconds
Started Jan 22 05:00:18 PM PST 24
Finished Jan 22 05:00:21 PM PST 24
Peak memory 205864 kb
Host smart-1a3891be-fe8c-4ab7-85e6-c7f2b091a072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636268573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1636268573
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2503530115
Short name T221
Test name
Test status
Simulation time 64195062 ps
CPU time 2.53 seconds
Started Jan 22 05:00:03 PM PST 24
Finished Jan 22 05:00:06 PM PST 24
Peak memory 214956 kb
Host smart-3331524f-462a-4044-9cf0-13d9b0a14053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2503530115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2503530115
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2672323381
Short name T766
Test name
Test status
Simulation time 548538392 ps
CPU time 3.14 seconds
Started Jan 22 05:00:09 PM PST 24
Finished Jan 22 05:00:13 PM PST 24
Peak memory 209172 kb
Host smart-8a787c6a-7b56-4848-bfa8-4858e174ac69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672323381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2672323381
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.221742880
Short name T66
Test name
Test status
Simulation time 24555538 ps
CPU time 1.99 seconds
Started Jan 22 05:00:07 PM PST 24
Finished Jan 22 05:00:09 PM PST 24
Peak memory 209460 kb
Host smart-71697b62-fb3c-4d6e-a5a5-17d938a90cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221742880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.221742880
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3682939943
Short name T1021
Test name
Test status
Simulation time 138098946 ps
CPU time 6.15 seconds
Started Jan 22 05:00:05 PM PST 24
Finished Jan 22 05:00:12 PM PST 24
Peak memory 209280 kb
Host smart-0015cd4c-6b27-4823-aba1-4aee04e71fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682939943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3682939943
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1350272682
Short name T915
Test name
Test status
Simulation time 689782497 ps
CPU time 20.78 seconds
Started Jan 22 05:00:18 PM PST 24
Finished Jan 22 05:00:41 PM PST 24
Peak memory 222404 kb
Host smart-1006710f-5afe-468b-a30c-f9f762811b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350272682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1350272682
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3945118554
Short name T1052
Test name
Test status
Simulation time 3988696807 ps
CPU time 69.5 seconds
Started Jan 22 05:00:05 PM PST 24
Finished Jan 22 05:01:15 PM PST 24
Peak memory 217868 kb
Host smart-7c2a4532-3dea-4145-b684-1dd3c027d1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945118554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3945118554
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1719607657
Short name T249
Test name
Test status
Simulation time 203803440 ps
CPU time 2.71 seconds
Started Jan 22 05:00:18 PM PST 24
Finished Jan 22 05:00:22 PM PST 24
Peak memory 206828 kb
Host smart-7b3c17be-de0e-4eb8-8daf-6823d611cdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719607657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1719607657
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1349069079
Short name T1016
Test name
Test status
Simulation time 166741288 ps
CPU time 5.95 seconds
Started Jan 22 05:00:04 PM PST 24
Finished Jan 22 05:00:11 PM PST 24
Peak memory 206940 kb
Host smart-56f53bb0-c8ef-45e4-9a8f-4d50edd36ae2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349069079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1349069079
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2298022885
Short name T355
Test name
Test status
Simulation time 469482071 ps
CPU time 10.4 seconds
Started Jan 22 05:00:06 PM PST 24
Finished Jan 22 05:00:17 PM PST 24
Peak memory 208456 kb
Host smart-4cf804ab-497a-4ee2-a7d5-8d16cef0e468
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298022885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2298022885
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.322627480
Short name T805
Test name
Test status
Simulation time 550044160 ps
CPU time 6.49 seconds
Started Jan 22 05:00:18 PM PST 24
Finished Jan 22 05:00:26 PM PST 24
Peak memory 207712 kb
Host smart-6aae8f53-2e82-4813-a2a3-c78b099b5785
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322627480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.322627480
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.418905410
Short name T543
Test name
Test status
Simulation time 2281194329 ps
CPU time 10.78 seconds
Started Jan 22 05:00:04 PM PST 24
Finished Jan 22 05:00:16 PM PST 24
Peak memory 208860 kb
Host smart-cea6b36f-1e22-485a-84c3-2b860626df8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418905410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.418905410
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.65878497
Short name T793
Test name
Test status
Simulation time 77327099 ps
CPU time 2.85 seconds
Started Jan 22 05:00:07 PM PST 24
Finished Jan 22 05:00:10 PM PST 24
Peak memory 206752 kb
Host smart-9ffb38bd-8bfc-43e9-8f89-d3aeb9b47bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65878497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.65878497
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2481817928
Short name T341
Test name
Test status
Simulation time 4729440918 ps
CPU time 62.52 seconds
Started Jan 22 05:00:09 PM PST 24
Finished Jan 22 05:01:12 PM PST 24
Peak memory 222616 kb
Host smart-aa638287-0f0c-415e-9d2c-f2b1526f7af3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481817928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2481817928
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2698751229
Short name T987
Test name
Test status
Simulation time 167944031 ps
CPU time 5.22 seconds
Started Jan 22 05:00:12 PM PST 24
Finished Jan 22 05:00:18 PM PST 24
Peak memory 222508 kb
Host smart-50a5b96e-cda3-417f-9ad9-83d5ea41202a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698751229 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2698751229
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2271382644
Short name T575
Test name
Test status
Simulation time 2724090583 ps
CPU time 67.17 seconds
Started Jan 22 05:00:05 PM PST 24
Finished Jan 22 05:01:13 PM PST 24
Peak memory 209448 kb
Host smart-47c4e71a-341f-4774-8535-1b5b0c314e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271382644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2271382644
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4269319407
Short name T989
Test name
Test status
Simulation time 462058992 ps
CPU time 11.7 seconds
Started Jan 22 05:00:13 PM PST 24
Finished Jan 22 05:00:25 PM PST 24
Peak memory 210960 kb
Host smart-35480cdd-4be9-42d3-9734-87bb263a593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269319407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4269319407
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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