Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11282

1

T1

6

T2

8

T3

10

auto[Attestation]

7906

1

T1

3

T2

12

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2831	1			T1	1		T2	3		T3	4
auto[Aes]	3504	1			T1	1		T2	3		T3	1
auto[Kmac]	3488	1			T1	2		T2	4		T3	2
auto[Otbn]	3344	1			T1	2		T2	1		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7611	1			T1	8		T2	2		T3	8
auto[OpGenId]	6021	1			T1	3		T2	9		T3	5
auto[OpGenSwOut]	5954	1			T1	6		T2	7		T3	3
auto[OpGenHwOut]	7213	1			T2	4		T3	5		T4	8
auto[OpDisable]	132	1			T48	1		T49	1		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10037

1

T1

8

T2

2

T3

8

auto[OpDoneFail]

16894

1

T1

9

T2

20

T3

13

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6260	1			T1	2		T2	20		T3	6
auto[StInit]	4344	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3029	1			T1	2		T3	2		T4	2
auto[StOwnerIntKey]	2625	1			T1	2		T3	2		T4	1
auto[StOwnerKey]	2257	1			T1	2		T3	2		T4	4
auto[StDisabled]	7367	1			T1	7		T3	7		T4	13
auto[StInvalid]	1049	1			T34	25		T40	33		T170	25

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	316	1			T2	2		T3	2		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	113	1			T48	1		T50	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	68	1			T26	1		T32	1		T48	5
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T19	1		T171	1		T48	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	63	1			T35	1		T48	1		T77	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	210	1			T1	1		T15	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	28	1			T170	2		T82	1		T172	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	329	1			T1	1		T2	1		T110	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	121	1			T5	1		T96	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	89	1			T119	1		T48	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	72	1			T19	1		T35	1		T48	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	57	1			T48	1		T46	1		T173	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	201	1			T4	1		T5	2		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	31	1			T34	1		T40	2		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	296	1			T15	1		T110	1		T96	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	120	1			T120	1		T174	1		T96	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T120	1		T95	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	71	1			T95	1		T48	4		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	53	1			T4	1		T5	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	193	1			T1	1		T5	1		T120	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	44	1			T34	1		T40	1		T170	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	304	1			T139	1		T96	1		T32	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	101	1			T1	1		T44	1		T171	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	80	1			T15	1		T79	1		T120	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	56	1			T15	1		T5	1		T48	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	69	1			T171	1		T121	1		T8	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	190	1			T4	1		T5	3		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	34	1			T66	1		T82	1		T172	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	68	1			T48	1		T113	2		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	133	1			T17	1		T119	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	81	1			T48	1		T46	1		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T35	1		T174	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	47	1			T5	1		T110	1		T48	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	199	1			T4	1		T79	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	30	1			T34	1		T170	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	80	1			T48	1		T46	2		T8	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	98	1			T5	1		T6	1		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	73	1			T26	1		T110	1		T174	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	82	1			T48	2		T140	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	51	1			T5	1		T48	2		T175	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	195	1			T15	1		T5	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	24	1			T40	1		T66	1		T176	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	78	1			T2	3		T114	1		T8	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	119	1			T26	1		T35	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	88	1			T110	1		T120	1		T171	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T1	1		T48	4		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	52	1			T174	1		T48	2		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	201	1			T3	1		T79	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	34	1			T40	1		T170	1		T66	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	70	1			T2	1		T113	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	125	1			T174	1		T32	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	72	1			T1	1		T32	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T19	1		T110	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	56	1			T15	1		T5	1		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	203	1			T5	1		T79	2		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	32	1			T40	1		T66	1		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	289	1			T2	1		T3	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	121	1			T6	1		T32	1		T48	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	64	1			T17	1		T96	1		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	44	1			T110	1		T171	1		T95	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	61	1			T35	1		T171	1		T75	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	166	1			T4	1		T120	1		T174	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	36	1			T170	1		T66	1		T82	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	464	1			T2	2		T19	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	149	1			T80	1		T95	1		T177	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	123	1			T80	1		T110	1		T177	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	114	1			T177	1		T48	2		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T4	1		T80	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	277	1			T3	1		T80	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	24	1			T34	1		T40	3		T170	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	462	1			T16	7		T110	1		T139	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	143	1			T5	1		T18	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	108	1			T174	1		T48	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	98	1			T16	1		T19	1		T119	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	87	1			T16	1		T171	1		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	274	1			T3	1		T4	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T82	1		T83	2		T89	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	419	1			T110	2		T44	1		T178	17
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	124	1			T6	1		T48	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	115	1			T48	3		T49	2		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T3	1		T17	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	84	1			T35	1		T178	1		T171	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	262	1			T4	1		T120	1		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	38	1			T170	2		T82	2		T172	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	55	1			T113	1		T46	1		T114	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	116	1			T35	1		T6	1		T48	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	75	1			T4	1		T48	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	49	1			T5	1		T50	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	46	1			T171	1		T48	2		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	180	1			T4	1		T120	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	31	1			T34	1		T40	1		T172	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	56	1			T48	2		T113	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	150	1			T35	1		T6	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	102	1			T110	1		T48	2		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	93	1			T19	2		T80	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	80	1			T110	1		T171	1		T95	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	254	1			T5	4		T80	3		T120	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	32	1			T34	3		T40	1		T170	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	55	1			T2	1		T48	1		T113	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	134	1			T5	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	112	1			T16	1		T18	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T17	2		T18	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	81	1			T18	1		T48	1		T122	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	285	1			T5	1		T16	4		T18	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	34	1			T40	2		T170	2		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	60	1			T54	1		T46	1		T114	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	123	1			T26	1		T94	1		T178	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T19	1		T178	1		T174	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	92	1			T5	1		T17	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	73	1			T4	1		T48	1		T179	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	277	1			T4	1		T110	1		T120	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	34	1			T34	1		T40	1		T66	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	181	1			T19	1		T26	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	685	1			T1	1		T2	2		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	200	1			T19	1		T119	1		T48	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	700	1			T1	1		T2	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	189	1			T5	1		T120	1		T95	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	668	1			T1	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	187	1			T15	2		T5	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	647	1			T1	1		T4	1		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	183	1			T5	1		T110	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	449	1			T4	1		T17	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	193	1			T26	1		T110	1		T174	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	410	1			T15	1		T5	3		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	200	1			T1	1		T110	1		T120	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	439	1			T2	3		T3	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	175	1			T1	1		T15	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	448	1			T2	1		T5	2		T79	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	153	1			T17	1		T110	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	628	1			T2	1		T3	2		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	306	1			T4	1		T80	2		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	928	1			T2	2		T3	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	280	1			T16	2		T19	1		T119	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	920	1			T3	1		T4	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T3	1		T17	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	858	1			T4	1		T110	2		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	157	1			T4	1		T171	1		T48	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	395	1			T4	1		T5	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	258	1			T19	2		T80	1		T110	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	509	1			T5	4		T80	3		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	267	1			T16	1		T17	2		T18	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	525	1			T2	1		T5	2		T16	5
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	251	1			T4	1		T5	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	505	1			T4	1		T26	1		T94	1