Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30907

1

T1

18

T2

23

T3

26

auto[1]

292

1

T110

2

T140

8

T121

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30917	1			T1	18		T2	23		T3	26
auto[134217728:268435455]	8	1			T208	1		T358	1		T240	1
auto[268435456:402653183]	7	1			T358	1		T289	1		T379	1
auto[402653184:536870911]	7	1			T140	1		T284	1		T380	1
auto[536870912:671088639]	8	1			T226	1		T240	1		T379	1
auto[671088640:805306367]	15	1			T124	1		T264	1		T208	1
auto[805306368:939524095]	9	1			T110	1		T264	1		T208	2
auto[939524096:1073741823]	7	1			T124	1		T264	1		T221	1
auto[1073741824:1207959551]	12	1			T121	1		T221	1		T226	1
auto[1207959552:1342177279]	7	1			T226	1		T240	1		T265	1
auto[1342177280:1476395007]	9	1			T140	1		T121	1		T316	1
auto[1476395008:1610612735]	6	1			T202	1		T221	1		T240	1
auto[1610612736:1744830463]	9	1			T140	1		T121	1		T381	2
auto[1744830464:1879048191]	10	1			T140	1		T264	1		T202	1
auto[1879048192:2013265919]	12	1			T121	1		T208	1		T381	1
auto[2013265920:2147483647]	12	1			T140	3		T240	2		T284	1
auto[2147483648:2281701375]	7	1			T221	1		T382	1		T316	1
auto[2281701376:2415919103]	9	1			T124	1		T273	1		T358	1
auto[2415919104:2550136831]	9	1			T264	1		T201	1		T240	1
auto[2550136832:2684354559]	9	1			T208	1		T293	1		T240	1
auto[2684354560:2818572287]	5	1			T264	1		T380	2		T341	1
auto[2818572288:2952790015]	12	1			T201	1		T226	1		T208	1
auto[2952790016:3087007743]	8	1			T226	1		T316	1		T383	1
auto[3087007744:3221225471]	13	1			T140	1		T124	2		T201	1
auto[3221225472:3355443199]	12	1			T201	1		T358	1		T384	1
auto[3355443200:3489660927]	15	1			T110	1		T264	1		T201	1
auto[3489660928:3623878655]	11	1			T121	1		T201	1		T226	1
auto[3623878656:3758096383]	9	1			T122	1		T226	1		T380	2
auto[3758096384:3892314111]	4	1			T202	1		T208	1		T385	1
auto[3892314112:4026531839]	8	1			T358	1		T383	1		T284	1
auto[4026531840:4160749567]	6	1			T264	1		T386	1		T380	1
auto[4160749568:4294967295]	7	1			T122	1		T358	1		T381	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30907	1			T1	18		T2	23		T3	26
auto[0:134217727]	auto[1]	10	1			T264	1		T293	2		T240	1
auto[134217728:268435455]	auto[1]	8	1			T208	1		T358	1		T240	1
auto[268435456:402653183]	auto[1]	7	1			T358	1		T289	1		T379	1
auto[402653184:536870911]	auto[1]	7	1			T140	1		T284	1		T380	1
auto[536870912:671088639]	auto[1]	8	1			T226	1		T240	1		T379	1
auto[671088640:805306367]	auto[1]	15	1			T124	1		T264	1		T208	1
auto[805306368:939524095]	auto[1]	9	1			T110	1		T264	1		T208	2
auto[939524096:1073741823]	auto[1]	7	1			T124	1		T264	1		T221	1
auto[1073741824:1207959551]	auto[1]	12	1			T121	1		T221	1		T226	1
auto[1207959552:1342177279]	auto[1]	7	1			T226	1		T240	1		T265	1
auto[1342177280:1476395007]	auto[1]	9	1			T140	1		T121	1		T316	1
auto[1476395008:1610612735]	auto[1]	6	1			T202	1		T221	1		T240	1
auto[1610612736:1744830463]	auto[1]	9	1			T140	1		T121	1		T381	2
auto[1744830464:1879048191]	auto[1]	10	1			T140	1		T264	1		T202	1
auto[1879048192:2013265919]	auto[1]	12	1			T121	1		T208	1		T381	1
auto[2013265920:2147483647]	auto[1]	12	1			T140	3		T240	2		T284	1
auto[2147483648:2281701375]	auto[1]	7	1			T221	1		T382	1		T316	1
auto[2281701376:2415919103]	auto[1]	9	1			T124	1		T273	1		T358	1
auto[2415919104:2550136831]	auto[1]	9	1			T264	1		T201	1		T240	1
auto[2550136832:2684354559]	auto[1]	9	1			T208	1		T293	1		T240	1
auto[2684354560:2818572287]	auto[1]	5	1			T264	1		T380	2		T341	1
auto[2818572288:2952790015]	auto[1]	12	1			T201	1		T226	1		T208	1
auto[2952790016:3087007743]	auto[1]	8	1			T226	1		T316	1		T383	1
auto[3087007744:3221225471]	auto[1]	13	1			T140	1		T124	2		T201	1
auto[3221225472:3355443199]	auto[1]	12	1			T201	1		T358	1		T384	1
auto[3355443200:3489660927]	auto[1]	15	1			T110	1		T264	1		T201	1
auto[3489660928:3623878655]	auto[1]	11	1			T121	1		T201	1		T226	1
auto[3623878656:3758096383]	auto[1]	9	1			T122	1		T226	1		T380	2
auto[3758096384:3892314111]	auto[1]	4	1			T202	1		T208	1		T385	1
auto[3892314112:4026531839]	auto[1]	8	1			T358	1		T383	1		T284	1
auto[4026531840:4160749567]	auto[1]	6	1			T264	1		T386	1		T380	1
auto[4160749568:4294967295]	auto[1]	7	1			T122	1		T358	1		T381	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1568

1

T2

2

T110

7

T35

2

auto[1]

1707

1

T2

2

T4

4

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T96	1		T48	2		T49	1
auto[134217728:268435455]	103	1			T110	1		T120	1		T95	1
auto[268435456:402653183]	113	1			T110	1		T48	1		T58	1
auto[402653184:536870911]	95	1			T120	1		T48	1		T180	1
auto[536870912:671088639]	100	1			T26	1		T28	1		T174	1
auto[671088640:805306367]	95	1			T48	4		T121	1		T113	1
auto[805306368:939524095]	105	1			T26	1		T6	1		T174	1
auto[939524096:1073741823]	95	1			T48	4		T53	1		T50	1
auto[1073741824:1207959551]	100	1			T4	1		T110	1		T48	1
auto[1207959552:1342177279]	103	1			T2	1		T48	1		T45	2
auto[1342177280:1476395007]	114	1			T35	1		T6	1		T48	2
auto[1476395008:1610612735]	106	1			T110	1		T120	1		T206	1
auto[1610612736:1744830463]	97	1			T4	1		T110	1		T35	1
auto[1744830464:1879048191]	92	1			T44	1		T35	1		T171	1
auto[1879048192:2013265919]	110	1			T27	1		T48	1		T23	1
auto[2013265920:2147483647]	105	1			T5	1		T48	3		T53	1
auto[2147483648:2281701375]	94	1			T2	1		T4	1		T139	1
auto[2281701376:2415919103]	103	1			T120	1		T171	1		T48	2
auto[2415919104:2550136831]	81	1			T44	1		T27	1		T48	1
auto[2550136832:2684354559]	97	1			T174	1		T96	1		T48	2
auto[2684354560:2818572287]	102	1			T2	1		T94	1		T48	2
auto[2818572288:2952790015]	89	1			T19	1		T110	1		T35	1
auto[2952790016:3087007743]	98	1			T48	2		T59	1		T45	2
auto[3087007744:3221225471]	96	1			T120	1		T48	2		T49	1
auto[3221225472:3355443199]	99	1			T5	1		T48	4		T7	1
auto[3355443200:3489660927]	115	1			T48	3		T53	1		T40	1
auto[3489660928:3623878655]	100	1			T48	6		T180	1		T23	1
auto[3623878656:3758096383]	124	1			T19	1		T94	1		T48	3
auto[3758096384:3892314111]	119	1			T2	1		T4	1		T17	1
auto[3892314112:4026531839]	102	1			T110	1		T6	1		T48	5
auto[4026531840:4160749567]	119	1			T27	1		T48	1		T50	2
auto[4160749568:4294967295]	104	1			T48	3		T53	1		T144	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T96	1		T48	1		T53	1
auto[0:134217727]	auto[1]	47	1			T48	1		T49	1		T206	1
auto[134217728:268435455]	auto[0]	45	1			T110	1		T46	1		T211	1
auto[134217728:268435455]	auto[1]	58	1			T120	1		T95	1		T96	1
auto[268435456:402653183]	auto[0]	48	1			T110	1		T23	1		T113	1
auto[268435456:402653183]	auto[1]	65	1			T48	1		T58	1		T144	1
auto[402653184:536870911]	auto[0]	40	1			T120	1		T40	1		T214	1
auto[402653184:536870911]	auto[1]	55	1			T48	1		T180	1		T45	1
auto[536870912:671088639]	auto[0]	55	1			T48	3		T46	1		T170	1
auto[536870912:671088639]	auto[1]	45	1			T26	1		T28	1		T174	1
auto[671088640:805306367]	auto[0]	44	1			T48	3		T271	1		T47	1
auto[671088640:805306367]	auto[1]	51	1			T48	1		T121	1		T113	1
auto[805306368:939524095]	auto[0]	58	1			T6	1		T174	1		T144	1
auto[805306368:939524095]	auto[1]	47	1			T26	1		T48	1		T144	1
auto[939524096:1073741823]	auto[0]	48	1			T48	2		T50	1		T45	1
auto[939524096:1073741823]	auto[1]	47	1			T48	2		T53	1		T7	1
auto[1073741824:1207959551]	auto[0]	48	1			T110	1		T205	1		T8	2
auto[1073741824:1207959551]	auto[1]	52	1			T4	1		T48	1		T58	1
auto[1207959552:1342177279]	auto[0]	42	1			T2	1		T48	1		T54	1
auto[1207959552:1342177279]	auto[1]	61	1			T45	2		T122	1		T78	2
auto[1342177280:1476395007]	auto[0]	57	1			T48	1		T78	1		T46	1
auto[1342177280:1476395007]	auto[1]	57	1			T35	1		T6	1		T48	1
auto[1476395008:1610612735]	auto[0]	57	1			T110	1		T24	2		T46	1
auto[1476395008:1610612735]	auto[1]	49	1			T120	1		T206	1		T54	2
auto[1610612736:1744830463]	auto[0]	48	1			T110	1		T35	1		T78	1
auto[1610612736:1744830463]	auto[1]	49	1			T4	1		T48	1		T58	1
auto[1744830464:1879048191]	auto[0]	48	1			T35	1		T171	1		T48	1
auto[1744830464:1879048191]	auto[1]	44	1			T44	1		T54	1		T46	1
auto[1879048192:2013265919]	auto[0]	50	1			T27	1		T48	1		T23	1
auto[1879048192:2013265919]	auto[1]	60	1			T54	1		T46	2		T173	1
auto[2013265920:2147483647]	auto[0]	50	1			T48	2		T53	1		T181	1
auto[2013265920:2147483647]	auto[1]	55	1			T5	1		T48	1		T315	1
auto[2147483648:2281701375]	auto[0]	36	1			T140	1		T24	1		T8	1
auto[2147483648:2281701375]	auto[1]	58	1			T2	1		T4	1		T139	1
auto[2281701376:2415919103]	auto[0]	54	1			T214	1		T46	1		T8	2
auto[2281701376:2415919103]	auto[1]	49	1			T120	1		T171	1		T48	2
auto[2415919104:2550136831]	auto[0]	36	1			T27	1		T53	1		T46	1
auto[2415919104:2550136831]	auto[1]	45	1			T44	1		T48	1		T46	1
auto[2550136832:2684354559]	auto[0]	51	1			T48	1		T50	1		T8	1
auto[2550136832:2684354559]	auto[1]	46	1			T174	1		T96	1		T48	1
auto[2684354560:2818572287]	auto[0]	40	1			T53	1		T23	1		T83	1
auto[2684354560:2818572287]	auto[1]	62	1			T2	1		T94	1		T48	2
auto[2818572288:2952790015]	auto[0]	40	1			T110	1		T96	1		T140	1
auto[2818572288:2952790015]	auto[1]	49	1			T19	1		T35	1		T48	1
auto[2952790016:3087007743]	auto[0]	49	1			T48	2		T8	1		T82	1
auto[2952790016:3087007743]	auto[1]	49	1			T59	1		T45	2		T46	1
auto[3087007744:3221225471]	auto[0]	41	1			T48	2		T49	1		T214	1
auto[3087007744:3221225471]	auto[1]	55	1			T120	1		T206	1		T121	1
auto[3221225472:3355443199]	auto[0]	43	1			T48	2		T7	1		T54	1
auto[3221225472:3355443199]	auto[1]	56	1			T5	1		T48	2		T46	2
auto[3355443200:3489660927]	auto[0]	63	1			T48	1		T53	1		T40	1
auto[3355443200:3489660927]	auto[1]	52	1			T48	2		T173	1		T82	1
auto[3489660928:3623878655]	auto[0]	50	1			T48	2		T114	2		T8	3
auto[3489660928:3623878655]	auto[1]	50	1			T48	4		T180	1		T23	1
auto[3623878656:3758096383]	auto[0]	53	1			T48	1		T7	1		T122	1
auto[3623878656:3758096383]	auto[1]	71	1			T19	1		T94	1		T48	2
auto[3758096384:3892314111]	auto[0]	50	1			T2	1		T48	1		T45	1
auto[3758096384:3892314111]	auto[1]	69	1			T4	1		T17	1		T110	1
auto[3892314112:4026531839]	auto[0]	56	1			T110	1		T48	2		T23	1
auto[3892314112:4026531839]	auto[1]	46	1			T6	1		T48	3		T123	2
auto[4026531840:4160749567]	auto[0]	56	1			T27	1		T48	1		T50	2
auto[4026531840:4160749567]	auto[1]	63	1			T45	1		T123	1		T46	1
auto[4160749568:4294967295]	auto[0]	59	1			T48	2		T53	1		T144	1
auto[4160749568:4294967295]	auto[1]	45	1			T48	1		T34	1		T46	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1580

1

T2

1

T110

5

T44

1

auto[1]

1691

1

T2

3

T4

4

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T180	1		T24	1		T46	1
auto[134217728:268435455]	106	1			T48	3		T49	1		T53	1
auto[268435456:402653183]	134	1			T94	1		T110	2		T96	1
auto[402653184:536870911]	124	1			T35	1		T48	3		T58	1
auto[536870912:671088639]	96	1			T96	1		T48	2		T140	1
auto[671088640:805306367]	106	1			T5	1		T120	1		T48	1
auto[805306368:939524095]	109	1			T48	4		T7	1		T222	1
auto[939524096:1073741823]	90	1			T5	1		T27	2		T48	2
auto[1073741824:1207959551]	109	1			T94	1		T110	1		T28	1
auto[1207959552:1342177279]	92	1			T4	1		T53	2		T23	1
auto[1342177280:1476395007]	95	1			T48	1		T53	1		T45	1
auto[1476395008:1610612735]	93	1			T48	5		T34	1		T46	2
auto[1610612736:1744830463]	102	1			T26	1		T171	1		T48	2
auto[1744830464:1879048191]	124	1			T4	1		T48	1		T49	1
auto[1879048192:2013265919]	108	1			T35	1		T174	3		T48	1
auto[2013265920:2147483647]	111	1			T19	1		T110	1		T120	1
auto[2147483648:2281701375]	88	1			T48	1		T25	1		T366	2
auto[2281701376:2415919103]	88	1			T4	1		T6	1		T27	1
auto[2415919104:2550136831]	90	1			T48	3		T53	1		T121	1
auto[2550136832:2684354559]	110	1			T44	1		T35	1		T48	2
auto[2684354560:2818572287]	93	1			T110	1		T45	1		T123	1
auto[2818572288:2952790015]	94	1			T17	1		T48	2		T46	1
auto[2952790016:3087007743]	110	1			T4	1		T110	2		T96	1
auto[3087007744:3221225471]	100	1			T26	1		T6	1		T171	1
auto[3221225472:3355443199]	109	1			T2	2		T110	1		T48	1
auto[3355443200:3489660927]	97	1			T48	1		T50	1		T121	1
auto[3489660928:3623878655]	120	1			T2	1		T35	1		T120	1
auto[3623878656:3758096383]	102	1			T120	1		T6	1		T48	3
auto[3758096384:3892314111]	79	1			T95	1		T180	1		T40	1
auto[3892314112:4026531839]	89	1			T19	1		T96	1		T48	4
auto[4026531840:4160749567]	115	1			T2	1		T120	1		T48	6
auto[4160749568:4294967295]	96	1			T48	2		T50	1		T34	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T24	1		T46	1		T374	1
auto[0:134217727]	auto[1]	41	1			T180	1		T67	1		T221	1
auto[134217728:268435455]	auto[0]	44	1			T48	1		T53	1		T7	1
auto[134217728:268435455]	auto[1]	62	1			T48	2		T49	1		T50	1
auto[268435456:402653183]	auto[0]	71	1			T110	2		T96	1		T48	2
auto[268435456:402653183]	auto[1]	63	1			T94	1		T206	1		T45	1
auto[402653184:536870911]	auto[0]	67	1			T35	1		T48	1		T50	1
auto[402653184:536870911]	auto[1]	57	1			T48	2		T58	1		T78	1
auto[536870912:671088639]	auto[0]	50	1			T48	1		T140	1		T78	1
auto[536870912:671088639]	auto[1]	46	1			T96	1		T48	1		T46	2
auto[671088640:805306367]	auto[0]	52	1			T48	1		T54	1		T46	2
auto[671088640:805306367]	auto[1]	54	1			T5	1		T120	1		T173	1
auto[805306368:939524095]	auto[0]	52	1			T48	1		T7	1		T222	1
auto[805306368:939524095]	auto[1]	57	1			T48	3		T214	1		T46	1
auto[939524096:1073741823]	auto[0]	45	1			T27	2		T24	1		T8	1
auto[939524096:1073741823]	auto[1]	45	1			T5	1		T48	2		T54	1
auto[1073741824:1207959551]	auto[0]	45	1			T110	1		T48	2		T8	2
auto[1073741824:1207959551]	auto[1]	64	1			T94	1		T28	1		T48	1
auto[1207959552:1342177279]	auto[0]	44	1			T53	1		T23	1		T122	1
auto[1207959552:1342177279]	auto[1]	48	1			T4	1		T53	1		T123	1
auto[1342177280:1476395007]	auto[0]	49	1			T48	1		T53	1		T8	2
auto[1342177280:1476395007]	auto[1]	46	1			T45	1		T121	1		T46	1
auto[1476395008:1610612735]	auto[0]	34	1			T48	3		T8	2		T66	1
auto[1476395008:1610612735]	auto[1]	59	1			T48	2		T34	1		T46	2
auto[1610612736:1744830463]	auto[0]	47	1			T48	1		T54	1		T387	1
auto[1610612736:1744830463]	auto[1]	55	1			T26	1		T171	1		T48	1
auto[1744830464:1879048191]	auto[0]	61	1			T50	2		T54	1		T24	1
auto[1744830464:1879048191]	auto[1]	63	1			T4	1		T48	1		T49	1
auto[1879048192:2013265919]	auto[0]	49	1			T140	1		T24	1		T170	1
auto[1879048192:2013265919]	auto[1]	59	1			T35	1		T174	3		T48	1
auto[2013265920:2147483647]	auto[0]	47	1			T120	1		T48	3		T144	1
auto[2013265920:2147483647]	auto[1]	64	1			T19	1		T110	1		T48	2
auto[2147483648:2281701375]	auto[0]	42	1			T48	1		T366	2		T185	1
auto[2147483648:2281701375]	auto[1]	46	1			T25	1		T21	1		T88	1
auto[2281701376:2415919103]	auto[0]	54	1			T6	1		T27	1		T48	1
auto[2281701376:2415919103]	auto[1]	34	1			T4	1		T48	1		T206	1
auto[2415919104:2550136831]	auto[0]	37	1			T48	2		T53	1		T388	1
auto[2415919104:2550136831]	auto[1]	53	1			T48	1		T121	1		T124	1
auto[2550136832:2684354559]	auto[0]	50	1			T44	1		T45	1		T46	1
auto[2550136832:2684354559]	auto[1]	60	1			T35	1		T48	2		T58	1
auto[2684354560:2818572287]	auto[0]	51	1			T110	1		T45	1		T123	1
auto[2684354560:2818572287]	auto[1]	42	1			T46	1		T114	1		T8	2
auto[2818572288:2952790015]	auto[0]	45	1			T46	1		T8	1		T66	1
auto[2818572288:2952790015]	auto[1]	49	1			T17	1		T48	2		T8	2
auto[2952790016:3087007743]	auto[0]	52	1			T110	1		T48	1		T45	1
auto[2952790016:3087007743]	auto[1]	58	1			T4	1		T110	1		T96	1
auto[3087007744:3221225471]	auto[0]	44	1			T50	1		T144	2		T23	2
auto[3087007744:3221225471]	auto[1]	56	1			T26	1		T6	1		T171	1
auto[3221225472:3355443199]	auto[0]	58	1			T2	1		T48	1		T53	2
auto[3221225472:3355443199]	auto[1]	51	1			T2	1		T110	1		T46	1
auto[3355443200:3489660927]	auto[0]	45	1			T48	1		T8	1		T66	1
auto[3355443200:3489660927]	auto[1]	52	1			T50	1		T121	1		T222	1
auto[3489660928:3623878655]	auto[0]	61	1			T120	1		T48	1		T40	1
auto[3489660928:3623878655]	auto[1]	59	1			T2	1		T35	1		T34	1
auto[3623878656:3758096383]	auto[0]	50	1			T48	3		T123	1		T46	1
auto[3623878656:3758096383]	auto[1]	52	1			T120	1		T6	1		T50	1
auto[3758096384:3892314111]	auto[0]	43	1			T180	1		T40	1		T8	1
auto[3758096384:3892314111]	auto[1]	36	1			T95	1		T206	1		T123	1
auto[3892314112:4026531839]	auto[0]	44	1			T96	1		T48	1		T113	1
auto[3892314112:4026531839]	auto[1]	45	1			T19	1		T48	3		T40	1
auto[4026531840:4160749567]	auto[0]	51	1			T48	3		T45	1		T46	2
auto[4026531840:4160749567]	auto[1]	64	1			T2	1		T120	1		T48	3
auto[4160749568:4294967295]	auto[0]	45	1			T48	1		T50	1		T211	1
auto[4160749568:4294967295]	auto[1]	51	1			T48	1		T34	1		T59	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1559

1

T2

1

T26

1

T110

6

auto[1]

1710

1

T2

1

T4

4

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	119	1			T19	1		T44	1		T120	1
auto[134217728:268435455]	101	1			T4	1		T26	1		T110	1
auto[268435456:402653183]	99	1			T35	1		T96	1		T48	4
auto[402653184:536870911]	106	1			T26	1		T120	1		T27	1
auto[536870912:671088639]	103	1			T48	2		T7	1		T23	1
auto[671088640:805306367]	104	1			T171	1		T48	2		T49	1
auto[805306368:939524095]	92	1			T28	1		T95	1		T48	2
auto[939524096:1073741823]	101	1			T110	1		T96	1		T48	4
auto[1073741824:1207959551]	91	1			T96	1		T54	2		T46	2
auto[1207959552:1342177279]	103	1			T19	1		T174	1		T48	4
auto[1342177280:1476395007]	90	1			T48	5		T144	1		T78	1
auto[1476395008:1610612735]	89	1			T35	2		T174	1		T96	1
auto[1610612736:1744830463]	113	1			T35	1		T139	1		T171	1
auto[1744830464:1879048191]	109	1			T48	5		T34	1		T45	2
auto[1879048192:2013265919]	94	1			T94	1		T48	3		T49	1
auto[2013265920:2147483647]	86	1			T48	4		T121	2		T54	1
auto[2147483648:2281701375]	109	1			T110	1		T34	1		T206	1
auto[2281701376:2415919103]	94	1			T5	2		T110	1		T48	1
auto[2415919104:2550136831]	109	1			T2	1		T113	1		T54	1
auto[2550136832:2684354559]	110	1			T17	1		T94	1		T48	3
auto[2684354560:2818572287]	116	1			T110	1		T48	2		T54	2
auto[2818572288:2952790015]	104	1			T44	1		T48	1		T50	1
auto[2952790016:3087007743]	90	1			T50	2		T45	1		T23	1
auto[3087007744:3221225471]	97	1			T4	1		T48	1		T53	1
auto[3221225472:3355443199]	88	1			T48	1		T206	1		T23	1
auto[3355443200:3489660927]	101	1			T4	1		T6	1		T48	3
auto[3489660928:3623878655]	88	1			T6	1		T53	1		T58	2
auto[3623878656:3758096383]	113	1			T120	1		T27	1		T48	2
auto[3758096384:3892314111]	102	1			T2	1		T110	1		T120	1
auto[3892314112:4026531839]	121	1			T144	2		T206	1		T45	1
auto[4026531840:4160749567]	110	1			T110	1		T120	1		T48	3
auto[4160749568:4294967295]	117	1			T4	1		T110	1		T174	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T44	1		T6	1		T48	1
auto[0:134217727]	auto[1]	65	1			T19	1		T120	1		T54	1
auto[134217728:268435455]	auto[0]	53	1			T110	1		T48	1		T40	1
auto[134217728:268435455]	auto[1]	48	1			T4	1		T26	1		T34	1
auto[268435456:402653183]	auto[0]	38	1			T96	1		T48	1		T50	1
auto[268435456:402653183]	auto[1]	61	1			T35	1		T48	3		T58	1
auto[402653184:536870911]	auto[0]	50	1			T26	1		T27	1		T48	1
auto[402653184:536870911]	auto[1]	56	1			T120	1		T206	1		T114	1
auto[536870912:671088639]	auto[0]	54	1			T48	1		T23	1		T123	1
auto[536870912:671088639]	auto[1]	49	1			T48	1		T7	1		T8	1
auto[671088640:805306367]	auto[0]	45	1			T48	1		T144	1		T66	1
auto[671088640:805306367]	auto[1]	59	1			T171	1		T48	1		T49	1
auto[805306368:939524095]	auto[0]	41	1			T24	1		T46	1		T170	1
auto[805306368:939524095]	auto[1]	51	1			T28	1		T95	1		T48	2
auto[939524096:1073741823]	auto[0]	49	1			T110	1		T96	1		T48	2
auto[939524096:1073741823]	auto[1]	52	1			T48	2		T24	1		T114	1
auto[1073741824:1207959551]	auto[0]	47	1			T96	1		T54	1		T46	2
auto[1073741824:1207959551]	auto[1]	44	1			T54	1		T8	1		T203	1
auto[1207959552:1342177279]	auto[0]	46	1			T48	3		T53	2		T122	1
auto[1207959552:1342177279]	auto[1]	57	1			T19	1		T174	1		T48	1
auto[1342177280:1476395007]	auto[0]	40	1			T48	2		T144	1		T8	1
auto[1342177280:1476395007]	auto[1]	50	1			T48	3		T78	1		T46	3
auto[1476395008:1610612735]	auto[0]	49	1			T35	2		T48	1		T8	2
auto[1476395008:1610612735]	auto[1]	40	1			T174	1		T96	1		T48	2
auto[1610612736:1744830463]	auto[0]	60	1			T171	1		T48	2		T45	1
auto[1610612736:1744830463]	auto[1]	53	1			T35	1		T139	1		T48	2
auto[1744830464:1879048191]	auto[0]	50	1			T45	1		T46	1		T211	1
auto[1744830464:1879048191]	auto[1]	59	1			T48	5		T34	1		T45	1
auto[1879048192:2013265919]	auto[0]	46	1			T46	1		T8	1		T124	1
auto[1879048192:2013265919]	auto[1]	48	1			T94	1		T48	3		T49	1
auto[2013265920:2147483647]	auto[0]	41	1			T48	2		T214	1		T66	1
auto[2013265920:2147483647]	auto[1]	45	1			T48	2		T121	2		T54	1
auto[2147483648:2281701375]	auto[0]	46	1			T110	1		T46	1		T8	2
auto[2147483648:2281701375]	auto[1]	63	1			T34	1		T206	1		T114	1
auto[2281701376:2415919103]	auto[0]	39	1			T23	1		T176	1		T22	1
auto[2281701376:2415919103]	auto[1]	55	1			T5	2		T110	1		T48	1
auto[2415919104:2550136831]	auto[0]	62	1			T222	1		T46	1		T8	2
auto[2415919104:2550136831]	auto[1]	47	1			T2	1		T113	1		T54	1
auto[2550136832:2684354559]	auto[0]	44	1			T48	3		T53	1		T23	1
auto[2550136832:2684354559]	auto[1]	66	1			T17	1		T94	1		T45	1
auto[2684354560:2818572287]	auto[0]	62	1			T110	1		T48	2		T54	1
auto[2684354560:2818572287]	auto[1]	54	1			T54	1		T78	1		T46	1
auto[2818572288:2952790015]	auto[0]	49	1			T48	1		T40	1		T113	1
auto[2818572288:2952790015]	auto[1]	55	1			T44	1		T50	1		T46	2
auto[2952790016:3087007743]	auto[0]	47	1			T50	1		T45	1		T23	1
auto[2952790016:3087007743]	auto[1]	43	1			T50	1		T267	1		T253	1
auto[3087007744:3221225471]	auto[0]	47	1			T48	1		T53	1		T40	1
auto[3087007744:3221225471]	auto[1]	50	1			T4	1		T123	1		T46	2
auto[3221225472:3355443199]	auto[0]	42	1			T48	1		T23	1		T46	1
auto[3221225472:3355443199]	auto[1]	46	1			T206	1		T46	1		T274	1
auto[3355443200:3489660927]	auto[0]	47	1			T48	2		T78	1		T46	1
auto[3355443200:3489660927]	auto[1]	54	1			T4	1		T6	1		T48	1
auto[3489660928:3623878655]	auto[0]	42	1			T53	1		T24	1		T65	1
auto[3489660928:3623878655]	auto[1]	46	1			T6	1		T58	2		T180	1
auto[3623878656:3758096383]	auto[0]	52	1			T120	1		T27	1		T48	2
auto[3623878656:3758096383]	auto[1]	61	1			T24	1		T46	1		T8	2
auto[3758096384:3892314111]	auto[0]	55	1			T2	1		T110	1		T180	1
auto[3758096384:3892314111]	auto[1]	47	1			T120	1		T48	2		T46	1
auto[3892314112:4026531839]	auto[0]	49	1			T144	1		T45	1		T54	1
auto[3892314112:4026531839]	auto[1]	72	1			T144	1		T206	1		T54	1
auto[4026531840:4160749567]	auto[0]	50	1			T110	1		T120	1		T48	2
auto[4026531840:4160749567]	auto[1]	60	1			T48	1		T50	1		T170	1
auto[4160749568:4294967295]	auto[0]	63	1			T27	1		T48	1		T53	1
auto[4160749568:4294967295]	auto[1]	54	1			T4	1		T110	1		T174	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1548

1

T26

1

T94

1

T110

6

auto[1]

1722

1

T2

3

T4

4

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T110	2		T174	1		T48	1
auto[134217728:268435455]	101	1			T4	1		T35	1		T48	1
auto[268435456:402653183]	112	1			T2	1		T5	1		T48	4
auto[402653184:536870911]	105	1			T35	1		T48	1		T50	1
auto[536870912:671088639]	104	1			T4	1		T120	1		T48	2
auto[671088640:805306367]	96	1			T53	1		T58	2		T144	1
auto[805306368:939524095]	82	1			T139	1		T48	2		T23	1
auto[939524096:1073741823]	115	1			T44	1		T48	1		T23	1
auto[1073741824:1207959551]	110	1			T110	1		T96	1		T48	2
auto[1207959552:1342177279]	99	1			T19	1		T35	1		T96	1
auto[1342177280:1476395007]	111	1			T17	1		T6	1		T48	2
auto[1476395008:1610612735]	100	1			T110	2		T120	1		T174	1
auto[1610612736:1744830463]	118	1			T171	1		T48	7		T34	1
auto[1744830464:1879048191]	94	1			T48	3		T144	1		T121	1
auto[1879048192:2013265919]	97	1			T96	1		T48	1		T113	2
auto[2013265920:2147483647]	105	1			T5	1		T110	1		T48	1
auto[2147483648:2281701375]	109	1			T26	1		T110	1		T7	1
auto[2281701376:2415919103]	104	1			T2	1		T94	1		T174	1
auto[2415919104:2550136831]	113	1			T120	1		T48	3		T50	1
auto[2550136832:2684354559]	93	1			T110	1		T35	1		T27	1
auto[2684354560:2818572287]	92	1			T48	3		T214	1		T46	1
auto[2818572288:2952790015]	97	1			T19	1		T48	3		T50	1
auto[2952790016:3087007743]	107	1			T6	1		T48	2		T53	1
auto[3087007744:3221225471]	107	1			T120	2		T48	2		T49	1
auto[3221225472:3355443199]	97	1			T4	1		T44	1		T48	3
auto[3355443200:3489660927]	114	1			T28	1		T48	3		T121	1
auto[3489660928:3623878655]	99	1			T2	1		T96	1		T48	3
auto[3623878656:3758096383]	110	1			T94	1		T171	1		T95	1
auto[3758096384:3892314111]	103	1			T26	1		T6	1		T27	2
auto[3892314112:4026531839]	91	1			T48	1		T53	1		T23	1
auto[4026531840:4160749567]	85	1			T53	1		T180	1		T40	1
auto[4160749568:4294967295]	91	1			T4	1		T48	1		T34	1