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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2876 1 T2 4 T4 4 T5 2
auto[1] 293 1 T110 1 T140 8 T122 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 82 1 T4 1 T35 1 T96 1
auto[134217728:268435455] 89 1 T48 3 T53 1 T45 1
auto[268435456:402653183] 94 1 T48 3 T53 1 T206 1
auto[402653184:536870911] 96 1 T5 1 T94 1 T6 1
auto[536870912:671088639] 111 1 T5 1 T48 4 T58 1
auto[671088640:805306367] 101 1 T2 1 T110 1 T48 1
auto[805306368:939524095] 115 1 T140 1 T122 1 T54 1
auto[939524096:1073741823] 96 1 T4 1 T53 1 T50 1
auto[1073741824:1207959551] 108 1 T4 2 T17 1 T174 1
auto[1207959552:1342177279] 102 1 T174 1 T48 1 T50 1
auto[1342177280:1476395007] 102 1 T110 2 T59 1 T140 2
auto[1476395008:1610612735] 89 1 T58 1 T144 1 T140 1
auto[1610612736:1744830463] 85 1 T2 1 T48 1 T173 1
auto[1744830464:1879048191] 105 1 T120 1 T171 1 T48 1
auto[1879048192:2013265919] 91 1 T171 1 T48 1 T50 1
auto[2013265920:2147483647] 108 1 T139 1 T48 3 T50 1
auto[2147483648:2281701375] 91 1 T35 1 T27 1 T48 3
auto[2281701376:2415919103] 88 1 T26 1 T110 1 T44 1
auto[2415919104:2550136831] 120 1 T94 1 T110 1 T48 2
auto[2550136832:2684354559] 88 1 T19 1 T96 1 T48 2
auto[2684354560:2818572287] 109 1 T48 3 T49 2 T144 1
auto[2818572288:2952790015] 97 1 T2 2 T48 2 T206 2
auto[2952790016:3087007743] 95 1 T35 1 T120 1 T48 1
auto[3087007744:3221225471] 109 1 T110 2 T35 1 T120 1
auto[3221225472:3355443199] 108 1 T110 1 T6 1 T27 1
auto[3355443200:3489660927] 85 1 T48 3 T23 1 T54 1
auto[3489660928:3623878655] 101 1 T48 2 T53 1 T24 1
auto[3623878656:3758096383] 89 1 T110 1 T48 2 T180 1
auto[3758096384:3892314111] 100 1 T95 1 T48 3 T34 1
auto[3892314112:4026531839] 94 1 T120 1 T48 1 T46 1
auto[4026531840:4160749567] 103 1 T19 1 T120 1 T27 1
auto[4160749568:4294967295] 118 1 T6 1 T174 1 T96 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 76 1 T4 1 T35 1 T96 1
auto[0:134217727] auto[1] 6 1 T201 1 T240 1 T241 1
auto[134217728:268435455] auto[0] 83 1 T48 3 T53 1 T45 1
auto[134217728:268435455] auto[1] 6 1 T201 1 T341 1 T396 3
auto[268435456:402653183] auto[0] 81 1 T48 3 T53 1 T206 1
auto[268435456:402653183] auto[1] 13 1 T124 2 T202 1 T221 1
auto[402653184:536870911] auto[0] 89 1 T5 1 T94 1 T6 1
auto[402653184:536870911] auto[1] 7 1 T392 1 T382 1 T265 1
auto[536870912:671088639] auto[0] 94 1 T5 1 T48 4 T58 1
auto[536870912:671088639] auto[1] 17 1 T140 1 T208 1 T358 1
auto[671088640:805306367] auto[0] 94 1 T2 1 T110 1 T48 1
auto[671088640:805306367] auto[1] 7 1 T358 2 T293 1 T265 1
auto[805306368:939524095] auto[0] 105 1 T54 1 T24 1 T46 1
auto[805306368:939524095] auto[1] 10 1 T140 1 T122 1 T124 1
auto[939524096:1073741823] auto[0] 86 1 T4 1 T53 1 T50 1
auto[939524096:1073741823] auto[1] 10 1 T208 2 T284 1 T380 1
auto[1073741824:1207959551] auto[0] 96 1 T4 2 T17 1 T174 1
auto[1073741824:1207959551] auto[1] 12 1 T140 1 T358 1 T240 2
auto[1207959552:1342177279] auto[0] 95 1 T174 1 T48 1 T50 1
auto[1207959552:1342177279] auto[1] 7 1 T124 1 T201 2 T240 1
auto[1342177280:1476395007] auto[0] 88 1 T110 2 T59 1 T140 1
auto[1342177280:1476395007] auto[1] 14 1 T140 1 T221 1 T273 1
auto[1476395008:1610612735] auto[0] 79 1 T58 1 T144 1 T54 1
auto[1476395008:1610612735] auto[1] 10 1 T140 1 T202 1 T201 1
auto[1610612736:1744830463] auto[0] 80 1 T2 1 T48 1 T173 1
auto[1610612736:1744830463] auto[1] 5 1 T124 1 T202 1 T383 1
auto[1744830464:1879048191] auto[0] 97 1 T120 1 T171 1 T48 1
auto[1744830464:1879048191] auto[1] 8 1 T124 1 T226 1 T208 1
auto[1879048192:2013265919] auto[0] 84 1 T171 1 T48 1 T50 1
auto[1879048192:2013265919] auto[1] 7 1 T358 1 T383 1 T284 1
auto[2013265920:2147483647] auto[0] 96 1 T139 1 T48 3 T50 1
auto[2013265920:2147483647] auto[1] 12 1 T123 1 T265 2 T289 1
auto[2147483648:2281701375] auto[0] 83 1 T35 1 T27 1 T48 3
auto[2147483648:2281701375] auto[1] 8 1 T140 1 T124 1 T358 1
auto[2281701376:2415919103] auto[0] 79 1 T26 1 T110 1 T44 1
auto[2281701376:2415919103] auto[1] 9 1 T124 1 T208 2 T382 1
auto[2415919104:2550136831] auto[0] 100 1 T94 1 T110 1 T48 2
auto[2415919104:2550136831] auto[1] 20 1 T123 1 T124 2 T201 1
auto[2550136832:2684354559] auto[0] 80 1 T19 1 T96 1 T48 2
auto[2550136832:2684354559] auto[1] 8 1 T202 2 T201 1 T208 1
auto[2684354560:2818572287] auto[0] 105 1 T48 3 T49 2 T144 1
auto[2684354560:2818572287] auto[1] 4 1 T382 1 T240 1 T265 1
auto[2818572288:2952790015] auto[0] 90 1 T2 2 T48 2 T206 2
auto[2818572288:2952790015] auto[1] 7 1 T226 1 T293 1 T383 1
auto[2952790016:3087007743] auto[0] 87 1 T35 1 T120 1 T48 1
auto[2952790016:3087007743] auto[1] 8 1 T140 1 T202 1 T201 1
auto[3087007744:3221225471] auto[0] 102 1 T110 1 T35 1 T120 1
auto[3087007744:3221225471] auto[1] 7 1 T110 1 T358 1 T382 2
auto[3221225472:3355443199] auto[0] 96 1 T110 1 T6 1 T27 1
auto[3221225472:3355443199] auto[1] 12 1 T140 1 T264 1 T358 1
auto[3355443200:3489660927] auto[0] 78 1 T48 3 T23 1 T54 1
auto[3355443200:3489660927] auto[1] 7 1 T264 1 T221 1 T358 1
auto[3489660928:3623878655] auto[0] 92 1 T48 2 T53 1 T24 1
auto[3489660928:3623878655] auto[1] 9 1 T124 1 T381 1 T240 1
auto[3623878656:3758096383] auto[0] 80 1 T110 1 T48 2 T180 1
auto[3623878656:3758096383] auto[1] 9 1 T122 1 T124 1 T226 1
auto[3758096384:3892314111] auto[0] 91 1 T95 1 T48 3 T34 1
auto[3758096384:3892314111] auto[1] 9 1 T264 1 T381 1 T382 1
auto[3892314112:4026531839] auto[0] 86 1 T120 1 T48 1 T46 1
auto[3892314112:4026531839] auto[1] 8 1 T124 2 T264 1 T358 1
auto[4026531840:4160749567] auto[0] 95 1 T19 1 T120 1 T27 1
auto[4026531840:4160749567] auto[1] 8 1 T265 2 T379 1 T395 1
auto[4160749568:4294967295] auto[0] 109 1 T6 1 T174 1 T96 1
auto[4160749568:4294967295] auto[1] 9 1 T202 1 T381 1 T392 1

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