Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6679

1

T2

7

T4

7

T5

20

auto[1]

282

1

T110

4

T140

6

T121

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2809	1			T2	3		T4	2		T5	9
auto[134217728:268435455]	175	1			T6	1		T174	2		T48	1
auto[268435456:402653183]	141	1			T5	1		T110	1		T96	1
auto[402653184:536870911]	148	1			T5	3		T26	1		T110	1
auto[536870912:671088639]	130	1			T120	1		T48	4		T140	2
auto[671088640:805306367]	152	1			T4	1		T48	1		T50	1
auto[805306368:939524095]	134	1			T5	1		T110	1		T139	1
auto[939524096:1073741823]	137	1			T5	1		T50	1		T45	1
auto[1073741824:1207959551]	131	1			T110	1		T120	1		T171	1
auto[1207959552:1342177279]	138	1			T4	1		T48	1		T144	1
auto[1342177280:1476395007]	133	1			T110	1		T120	1		T95	1
auto[1476395008:1610612735]	119	1			T2	1		T19	1		T110	1
auto[1610612736:1744830463]	138	1			T96	1		T48	4		T49	1
auto[1744830464:1879048191]	131	1			T4	1		T120	1		T27	1
auto[1879048192:2013265919]	131	1			T110	1		T6	1		T48	1
auto[2013265920:2147483647]	119	1			T5	1		T110	1		T35	1
auto[2147483648:2281701375]	120	1			T5	1		T110	1		T35	1
auto[2281701376:2415919103]	133	1			T35	1		T48	1		T140	1
auto[2415919104:2550136831]	129	1			T94	1		T48	2		T45	1
auto[2550136832:2684354559]	133	1			T2	1		T35	2		T120	1
auto[2684354560:2818572287]	133	1			T110	2		T48	5		T50	1
auto[2818572288:2952790015]	116	1			T17	1		T19	1		T48	2
auto[2952790016:3087007743]	116	1			T4	1		T35	1		T48	2
auto[3087007744:3221225471]	124	1			T171	1		T48	5		T53	1
auto[3221225472:3355443199]	139	1			T120	2		T48	4		T53	1
auto[3355443200:3489660927]	139	1			T2	1		T48	4		T58	1
auto[3489660928:3623878655]	133	1			T94	1		T44	1		T35	1
auto[3623878656:3758096383]	120	1			T48	3		T121	1		T122	1
auto[3758096384:3892314111]	143	1			T2	1		T5	1		T35	1
auto[3892314112:4026531839]	132	1			T4	1		T5	1		T110	1
auto[4026531840:4160749567]	142	1			T5	1		T27	1		T48	2
auto[4160749568:4294967295]	143	1			T96	1		T48	3		T53	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2799	1			T2	3		T4	2		T5	9
auto[0:134217727]	auto[1]	10	1			T264	1		T381	1		T240	1
auto[134217728:268435455]	auto[0]	166	1			T6	1		T174	2		T48	1
auto[134217728:268435455]	auto[1]	9	1			T221	1		T226	1		T381	1
auto[268435456:402653183]	auto[0]	126	1			T5	1		T96	1		T48	2
auto[268435456:402653183]	auto[1]	15	1			T110	1		T122	1		T201	1
auto[402653184:536870911]	auto[0]	137	1			T5	3		T26	1		T110	1
auto[402653184:536870911]	auto[1]	11	1			T201	1		T381	1		T316	2
auto[536870912:671088639]	auto[0]	122	1			T120	1		T48	4		T140	1
auto[536870912:671088639]	auto[1]	8	1			T140	1		T201	1		T358	1
auto[671088640:805306367]	auto[0]	142	1			T4	1		T48	1		T50	1
auto[671088640:805306367]	auto[1]	10	1			T121	1		T122	1		T208	1
auto[805306368:939524095]	auto[0]	129	1			T5	1		T139	1		T48	4
auto[805306368:939524095]	auto[1]	5	1			T110	1		T124	1		T201	1
auto[939524096:1073741823]	auto[0]	126	1			T5	1		T50	1		T45	1
auto[939524096:1073741823]	auto[1]	11	1			T122	1		T358	1		T265	3
auto[1073741824:1207959551]	auto[0]	120	1			T120	1		T171	1		T95	1
auto[1073741824:1207959551]	auto[1]	11	1			T110	1		T202	1		T208	1
auto[1207959552:1342177279]	auto[0]	128	1			T4	1		T48	1		T144	1
auto[1207959552:1342177279]	auto[1]	10	1			T124	1		T264	1		T226	1
auto[1342177280:1476395007]	auto[0]	125	1			T110	1		T120	1		T95	1
auto[1342177280:1476395007]	auto[1]	8	1			T123	1		T202	1		T293	1
auto[1476395008:1610612735]	auto[0]	112	1			T2	1		T19	1		T35	1
auto[1476395008:1610612735]	auto[1]	7	1			T110	1		T140	1		T122	1
auto[1610612736:1744830463]	auto[0]	132	1			T96	1		T48	4		T49	1
auto[1610612736:1744830463]	auto[1]	6	1			T121	1		T383	1		T284	1
auto[1744830464:1879048191]	auto[0]	120	1			T4	1		T120	1		T27	1
auto[1744830464:1879048191]	auto[1]	11	1			T121	1		T264	1		T202	1
auto[1879048192:2013265919]	auto[0]	123	1			T110	1		T6	1		T48	1
auto[1879048192:2013265919]	auto[1]	8	1			T201	1		T382	1		T284	1
auto[2013265920:2147483647]	auto[0]	113	1			T5	1		T110	1		T35	1
auto[2013265920:2147483647]	auto[1]	6	1			T383	1		T284	1		T390	1
auto[2147483648:2281701375]	auto[0]	114	1			T5	1		T110	1		T35	1
auto[2147483648:2281701375]	auto[1]	6	1			T124	1		T221	1		T358	1
auto[2281701376:2415919103]	auto[0]	129	1			T35	1		T48	1		T24	1
auto[2281701376:2415919103]	auto[1]	4	1			T140	1		T358	2		T391	1
auto[2415919104:2550136831]	auto[0]	120	1			T94	1		T48	2		T45	1
auto[2415919104:2550136831]	auto[1]	9	1			T122	1		T264	1		T380	1
auto[2550136832:2684354559]	auto[0]	127	1			T2	1		T35	2		T120	1
auto[2550136832:2684354559]	auto[1]	6	1			T122	1		T201	1		T381	1
auto[2684354560:2818572287]	auto[0]	126	1			T110	2		T48	5		T50	1
auto[2684354560:2818572287]	auto[1]	7	1			T124	1		T202	1		T201	1
auto[2818572288:2952790015]	auto[0]	106	1			T17	1		T19	1		T48	2
auto[2818572288:2952790015]	auto[1]	10	1			T140	1		T121	1		T208	2
auto[2952790016:3087007743]	auto[0]	110	1			T4	1		T35	1		T48	2
auto[2952790016:3087007743]	auto[1]	6	1			T201	1		T358	2		T351	1
auto[3087007744:3221225471]	auto[0]	116	1			T171	1		T48	5		T53	1
auto[3087007744:3221225471]	auto[1]	8	1			T121	1		T201	1		T208	1
auto[3221225472:3355443199]	auto[0]	126	1			T120	2		T48	4		T53	1
auto[3221225472:3355443199]	auto[1]	13	1			T140	1		T201	2		T226	2
auto[3355443200:3489660927]	auto[0]	130	1			T2	1		T48	4		T58	1
auto[3355443200:3489660927]	auto[1]	9	1			T122	1		T202	2		T201	1
auto[3489660928:3623878655]	auto[0]	118	1			T94	1		T44	1		T35	1
auto[3489660928:3623878655]	auto[1]	15	1			T140	1		T121	1		T240	2
auto[3623878656:3758096383]	auto[0]	112	1			T48	3		T121	1		T122	1
auto[3623878656:3758096383]	auto[1]	8	1			T240	1		T316	2		T383	2
auto[3758096384:3892314111]	auto[0]	130	1			T2	1		T5	1		T35	1
auto[3758096384:3892314111]	auto[1]	13	1			T121	1		T264	2		T208	1
auto[3892314112:4026531839]	auto[0]	123	1			T4	1		T5	1		T110	1
auto[3892314112:4026531839]	auto[1]	9	1			T122	1		T392	1		T382	1
auto[4026531840:4160749567]	auto[0]	134	1			T5	1		T27	1		T48	2
auto[4026531840:4160749567]	auto[1]	8	1			T293	1		T382	1		T265	2
auto[4160749568:4294967295]	auto[0]	138	1			T96	1		T48	3		T53	1
auto[4160749568:4294967295]	auto[1]	5	1			T264	1		T358	1		T390	1