Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.83 99.10 98.03 98.50 100.00 99.11 98.41 91.66


Total test records in report: 1077
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T364 /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3106054104 Jan 25 02:51:32 PM PST 24 Jan 25 02:51:53 PM PST 24 251148783 ps
T1012 /workspace/coverage/default/3.keymgr_direct_to_disabled.3490379245 Jan 25 02:45:41 PM PST 24 Jan 25 02:46:08 PM PST 24 24365356 ps
T327 /workspace/coverage/default/46.keymgr_hwsw_invalid_input.600494458 Jan 25 02:52:53 PM PST 24 Jan 25 02:53:15 PM PST 24 709439482 ps
T1013 /workspace/coverage/default/14.keymgr_sideload_otbn.2469409156 Jan 25 02:47:21 PM PST 24 Jan 25 02:48:10 PM PST 24 222099822 ps
T1014 /workspace/coverage/default/7.keymgr_kmac_rsp_err.506691626 Jan 25 02:46:18 PM PST 24 Jan 25 02:46:39 PM PST 24 164758029 ps
T1015 /workspace/coverage/default/4.keymgr_random.415202498 Jan 25 02:45:41 PM PST 24 Jan 25 02:46:14 PM PST 24 280779908 ps
T1016 /workspace/coverage/default/12.keymgr_stress_all.1301241741 Jan 25 02:46:59 PM PST 24 Jan 25 02:47:57 PM PST 24 321784084 ps
T1017 /workspace/coverage/default/3.keymgr_sideload_protect.2236757213 Jan 25 02:45:34 PM PST 24 Jan 25 02:46:04 PM PST 24 148501620 ps
T1018 /workspace/coverage/default/30.keymgr_custom_cm.3781674818 Jan 25 02:49:54 PM PST 24 Jan 25 02:50:21 PM PST 24 321196802 ps
T227 /workspace/coverage/default/12.keymgr_custom_cm.1393648714 Jan 25 02:47:04 PM PST 24 Jan 25 02:47:58 PM PST 24 1622522257 ps
T1019 /workspace/coverage/default/38.keymgr_sideload_protect.1645355177 Jan 25 02:51:32 PM PST 24 Jan 25 02:51:48 PM PST 24 196047529 ps
T1020 /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1959966946 Jan 25 02:49:50 PM PST 24 Jan 25 02:50:16 PM PST 24 47345093 ps
T1021 /workspace/coverage/default/12.keymgr_sideload_aes.1372559197 Jan 25 02:47:10 PM PST 24 Jan 25 02:48:01 PM PST 24 23869828 ps
T292 /workspace/coverage/default/16.keymgr_hwsw_invalid_input.138050461 Jan 25 02:47:25 PM PST 24 Jan 25 02:48:21 PM PST 24 507328838 ps
T1022 /workspace/coverage/default/7.keymgr_sideload.2144022859 Jan 25 02:46:19 PM PST 24 Jan 25 02:46:36 PM PST 24 149103614 ps
T1023 /workspace/coverage/default/38.keymgr_stress_all.3231180541 Jan 25 02:51:32 PM PST 24 Jan 25 02:52:09 PM PST 24 1966230724 ps
T1024 /workspace/coverage/default/33.keymgr_random.3129729434 Jan 25 02:50:34 PM PST 24 Jan 25 02:50:50 PM PST 24 160346136 ps
T1025 /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3911878481 Jan 25 02:47:22 PM PST 24 Jan 25 02:48:13 PM PST 24 262458093 ps
T1026 /workspace/coverage/default/7.keymgr_direct_to_disabled.2273645587 Jan 25 02:46:17 PM PST 24 Jan 25 02:46:34 PM PST 24 59123694 ps
T1027 /workspace/coverage/default/23.keymgr_sideload_otbn.3739838755 Jan 25 02:49:07 PM PST 24 Jan 25 02:49:23 PM PST 24 25191677 ps
T1028 /workspace/coverage/default/40.keymgr_alert_test.1990123555 Jan 25 02:51:49 PM PST 24 Jan 25 02:52:09 PM PST 24 31591887 ps
T198 /workspace/coverage/default/13.keymgr_custom_cm.2748090537 Jan 25 02:47:10 PM PST 24 Jan 25 02:48:05 PM PST 24 213757385 ps
T1029 /workspace/coverage/default/39.keymgr_sideload_otbn.624827984 Jan 25 02:51:28 PM PST 24 Jan 25 02:52:03 PM PST 24 5787483320 ps
T1030 /workspace/coverage/default/24.keymgr_lc_disable.4285045671 Jan 25 02:49:29 PM PST 24 Jan 25 02:49:53 PM PST 24 85884649 ps
T1031 /workspace/coverage/default/4.keymgr_cfg_regwen.1498799941 Jan 25 02:45:49 PM PST 24 Jan 25 02:46:17 PM PST 24 520221965 ps
T1032 /workspace/coverage/default/41.keymgr_custom_cm.2672823588 Jan 25 02:52:10 PM PST 24 Jan 25 02:52:29 PM PST 24 400918615 ps
T1033 /workspace/coverage/default/37.keymgr_cfg_regwen.4239957904 Jan 25 02:51:40 PM PST 24 Jan 25 02:52:26 PM PST 24 635204841 ps
T1034 /workspace/coverage/default/17.keymgr_smoke.176858128 Jan 25 02:48:06 PM PST 24 Jan 25 02:48:41 PM PST 24 59515758 ps
T1035 /workspace/coverage/default/11.keymgr_random.3240639740 Jan 25 02:46:56 PM PST 24 Jan 25 02:47:48 PM PST 24 82362970 ps
T1036 /workspace/coverage/default/7.keymgr_sideload_kmac.2614678552 Jan 25 02:46:13 PM PST 24 Jan 25 02:46:34 PM PST 24 487543203 ps
T1037 /workspace/coverage/default/27.keymgr_kmac_rsp_err.3543321099 Jan 25 02:49:24 PM PST 24 Jan 25 02:50:11 PM PST 24 776215766 ps
T1038 /workspace/coverage/default/11.keymgr_sw_invalid_input.2536148220 Jan 25 02:47:00 PM PST 24 Jan 25 02:48:23 PM PST 24 3682200713 ps
T1039 /workspace/coverage/default/31.keymgr_sideload_kmac.3224868748 Jan 25 02:50:28 PM PST 24 Jan 25 02:50:42 PM PST 24 36469185 ps
T1040 /workspace/coverage/default/18.keymgr_sw_invalid_input.2840946195 Jan 25 03:33:48 PM PST 24 Jan 25 03:35:33 PM PST 24 110153465 ps
T1041 /workspace/coverage/default/6.keymgr_sideload_kmac.4136518982 Jan 25 02:46:15 PM PST 24 Jan 25 02:46:36 PM PST 24 530111067 ps
T1042 /workspace/coverage/default/26.keymgr_sideload_aes.92759469 Jan 25 02:49:29 PM PST 24 Jan 25 02:49:53 PM PST 24 632303017 ps
T1043 /workspace/coverage/default/41.keymgr_sideload_otbn.202094951 Jan 25 02:51:30 PM PST 24 Jan 25 02:51:48 PM PST 24 50815168 ps
T1044 /workspace/coverage/default/32.keymgr_cfg_regwen.1632433064 Jan 25 02:50:28 PM PST 24 Jan 25 02:50:42 PM PST 24 280851769 ps
T1045 /workspace/coverage/default/10.keymgr_custom_cm.1375023068 Jan 25 02:46:38 PM PST 24 Jan 25 02:47:24 PM PST 24 59333370 ps
T1046 /workspace/coverage/default/9.keymgr_sw_invalid_input.3161277458 Jan 25 02:46:43 PM PST 24 Jan 25 02:47:31 PM PST 24 213442771 ps
T160 /workspace/coverage/default/36.keymgr_sync_async_fault_cross.612940499 Jan 25 02:51:48 PM PST 24 Jan 25 02:52:09 PM PST 24 66125627 ps
T1047 /workspace/coverage/default/39.keymgr_custom_cm.668829703 Jan 25 02:51:50 PM PST 24 Jan 25 02:52:14 PM PST 24 521189930 ps
T1048 /workspace/coverage/default/28.keymgr_sideload_kmac.1952467770 Jan 25 02:49:52 PM PST 24 Jan 25 02:50:26 PM PST 24 513183404 ps
T385 /workspace/coverage/default/14.keymgr_cfg_regwen.2046111200 Jan 25 02:47:27 PM PST 24 Jan 25 02:49:52 PM PST 24 9804921529 ps
T1049 /workspace/coverage/default/44.keymgr_sw_invalid_input.4239729096 Jan 25 02:52:01 PM PST 24 Jan 25 02:52:22 PM PST 24 1276443834 ps
T1050 /workspace/coverage/default/8.keymgr_direct_to_disabled.3260539656 Jan 25 02:46:36 PM PST 24 Jan 25 02:47:18 PM PST 24 80526527 ps
T1051 /workspace/coverage/default/47.keymgr_stress_all.1336350725 Jan 25 02:52:53 PM PST 24 Jan 25 02:53:31 PM PST 24 2643234403 ps
T1052 /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3832160720 Jan 25 02:49:33 PM PST 24 Jan 25 02:49:59 PM PST 24 301489088 ps
T1053 /workspace/coverage/default/27.keymgr_smoke.3088215821 Jan 25 02:49:39 PM PST 24 Jan 25 02:50:08 PM PST 24 220528203 ps
T1054 /workspace/coverage/default/45.keymgr_random.18438572 Jan 25 02:52:11 PM PST 24 Jan 25 02:52:43 PM PST 24 2309154871 ps
T1055 /workspace/coverage/default/26.keymgr_sideload_otbn.2442977523 Jan 25 02:49:30 PM PST 24 Jan 25 02:49:58 PM PST 24 231119524 ps
T1056 /workspace/coverage/default/21.keymgr_sideload_protect.3596308488 Jan 25 02:49:07 PM PST 24 Jan 25 02:49:32 PM PST 24 1700433929 ps
T397 /workspace/coverage/default/7.keymgr_cfg_regwen.1954364079 Jan 25 02:46:13 PM PST 24 Jan 25 02:46:44 PM PST 24 578361975 ps
T1057 /workspace/coverage/default/46.keymgr_random.983884704 Jan 25 02:52:57 PM PST 24 Jan 25 02:53:21 PM PST 24 1110001638 ps
T1058 /workspace/coverage/default/13.keymgr_random.3531572293 Jan 25 02:47:09 PM PST 24 Jan 25 02:48:01 PM PST 24 336394733 ps
T1059 /workspace/coverage/default/27.keymgr_sideload_protect.435338713 Jan 25 02:49:28 PM PST 24 Jan 25 02:49:50 PM PST 24 207039253 ps
T1060 /workspace/coverage/default/18.keymgr_smoke.2435561519 Jan 25 03:27:05 PM PST 24 Jan 25 03:28:03 PM PST 24 424498859 ps
T1061 /workspace/coverage/default/17.keymgr_stress_all.1634083720 Jan 25 03:23:03 PM PST 24 Jan 25 03:24:29 PM PST 24 7523970780 ps
T1062 /workspace/coverage/default/36.keymgr_random.4186166112 Jan 25 02:50:57 PM PST 24 Jan 25 02:51:09 PM PST 24 403301844 ps
T1063 /workspace/coverage/default/40.keymgr_smoke.2640007151 Jan 25 02:51:45 PM PST 24 Jan 25 02:52:07 PM PST 24 529390783 ps
T362 /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1930811551 Jan 25 02:47:00 PM PST 24 Jan 25 02:49:51 PM PST 24 11878514042 ps
T1064 /workspace/coverage/default/24.keymgr_cfg_regwen.358677394 Jan 25 02:49:30 PM PST 24 Jan 25 02:49:56 PM PST 24 71882561 ps
T1065 /workspace/coverage/default/12.keymgr_smoke.2782317701 Jan 25 02:47:07 PM PST 24 Jan 25 02:48:51 PM PST 24 11917490739 ps
T1066 /workspace/coverage/default/40.keymgr_direct_to_disabled.920468342 Jan 25 02:51:26 PM PST 24 Jan 25 02:51:40 PM PST 24 2374726003 ps
T1067 /workspace/coverage/default/48.keymgr_custom_cm.2964760381 Jan 25 02:52:54 PM PST 24 Jan 25 02:53:20 PM PST 24 426658734 ps
T1068 /workspace/coverage/default/10.keymgr_sideload_kmac.3091472172 Jan 25 02:46:42 PM PST 24 Jan 25 02:47:29 PM PST 24 99292604 ps
T143 /workspace/coverage/default/34.keymgr_custom_cm.468132033 Jan 25 02:50:58 PM PST 24 Jan 25 02:51:13 PM PST 24 385226610 ps
T1069 /workspace/coverage/default/0.keymgr_lc_disable.2837144917 Jan 25 02:44:57 PM PST 24 Jan 25 02:45:37 PM PST 24 101562858 ps
T196 /workspace/coverage/default/44.keymgr_lc_disable.1418217766 Jan 25 02:52:10 PM PST 24 Jan 25 02:52:28 PM PST 24 68990249 ps
T1070 /workspace/coverage/default/31.keymgr_sideload_protect.822701983 Jan 25 02:50:34 PM PST 24 Jan 25 02:50:52 PM PST 24 177561442 ps
T1071 /workspace/coverage/default/13.keymgr_direct_to_disabled.3774697264 Jan 25 02:47:09 PM PST 24 Jan 25 02:48:07 PM PST 24 961358758 ps
T1072 /workspace/coverage/default/43.keymgr_smoke.2931239288 Jan 25 02:52:08 PM PST 24 Jan 25 02:53:06 PM PST 24 8134131220 ps
T1073 /workspace/coverage/default/9.keymgr_random.1590102541 Jan 25 02:46:39 PM PST 24 Jan 25 02:47:33 PM PST 24 456949991 ps
T1074 /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3304619781 Jan 25 03:04:42 PM PST 24 Jan 25 03:05:00 PM PST 24 191994032 ps
T1075 /workspace/coverage/default/3.keymgr_sideload_otbn.2044877266 Jan 25 02:45:40 PM PST 24 Jan 25 02:46:08 PM PST 24 21744531 ps
T1076 /workspace/coverage/default/28.keymgr_sideload_protect.1427689449 Jan 25 02:49:49 PM PST 24 Jan 25 02:50:14 PM PST 24 153590524 ps
T1077 /workspace/coverage/default/49.keymgr_random.2944953128 Jan 25 02:52:54 PM PST 24 Jan 25 02:53:21 PM PST 24 839579182 ps

Test location /workspace/coverage/default/14.keymgr_stress_all.2264376792
Short name T5
Test name
Test status
Simulation time 1012150794 ps
CPU time 23.82 seconds
Started Jan 25 02:47:20 PM PST 24
Finished Jan 25 02:48:31 PM PST 24
Peak memory 214128 kb
Host smart-6df456a1-4508-4b76-91ef-685904b80eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264376792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2264376792
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2585353521
Short name T48
Test name
Test status
Simulation time 1389987401 ps
CPU time 54.13 seconds
Started Jan 25 02:49:34 PM PST 24
Finished Jan 25 02:50:52 PM PST 24
Peak memory 222408 kb
Host smart-0cc45cf8-830b-4589-b502-11d8d72e6b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585353521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2585353521
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3885478812
Short name T8
Test name
Test status
Simulation time 2878327072 ps
CPU time 67.25 seconds
Started Jan 25 02:49:31 PM PST 24
Finished Jan 25 02:50:59 PM PST 24
Peak memory 222336 kb
Host smart-c66b136e-26bf-4d6f-833d-7c2745e8856d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885478812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3885478812
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.929393884
Short name T44
Test name
Test status
Simulation time 715619781 ps
CPU time 3.16 seconds
Started Jan 25 02:51:32 PM PST 24
Finished Jan 25 02:51:49 PM PST 24
Peak memory 222640 kb
Host smart-0f08ea01-9c6d-4755-ae87-f2df5ee8eb0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929393884 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.929393884
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.489007693
Short name T42
Test name
Test status
Simulation time 633684772 ps
CPU time 10.23 seconds
Started Jan 25 02:44:59 PM PST 24
Finished Jan 25 02:45:47 PM PST 24
Peak memory 230428 kb
Host smart-62ea6e6f-8cf7-4614-9f1d-c644f970fe89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489007693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.489007693
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1701188268
Short name T46
Test name
Test status
Simulation time 8473156181 ps
CPU time 40.67 seconds
Started Jan 25 02:51:40 PM PST 24
Finished Jan 25 02:52:35 PM PST 24
Peak memory 222456 kb
Host smart-da7f4759-bc37-4692-9d74-160d1973ca97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701188268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1701188268
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1652147664
Short name T11
Test name
Test status
Simulation time 192371709 ps
CPU time 2.32 seconds
Started Jan 25 02:47:24 PM PST 24
Finished Jan 25 02:48:12 PM PST 24
Peak memory 209880 kb
Host smart-8fa5d4d4-4f82-4ccb-8828-bc1eb5122e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652147664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1652147664
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.421200875
Short name T106
Test name
Test status
Simulation time 180596445 ps
CPU time 4.86 seconds
Started Jan 25 12:49:36 PM PST 24
Finished Jan 25 12:49:42 PM PST 24
Peak memory 213704 kb
Host smart-39cc15a9-6357-4f66-93c8-9586a65630c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421200875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.421200875
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.225820224
Short name T124
Test name
Test status
Simulation time 315860880 ps
CPU time 16.91 seconds
Started Jan 25 02:47:04 PM PST 24
Finished Jan 25 02:48:11 PM PST 24
Peak memory 215420 kb
Host smart-9f7f55ce-7725-4897-a6f0-82fe5713b5eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225820224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.225820224
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.352911826
Short name T341
Test name
Test status
Simulation time 2506321974 ps
CPU time 130.17 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:54:17 PM PST 24
Peak memory 219388 kb
Host smart-0837b873-a7ea-4797-993b-a2ccf8a3578e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352911826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.352911826
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3746343498
Short name T113
Test name
Test status
Simulation time 166431364 ps
CPU time 10.71 seconds
Started Jan 25 02:49:49 PM PST 24
Finished Jan 25 02:50:23 PM PST 24
Peak memory 222504 kb
Host smart-bae613f5-0787-48e4-91b8-9e972931f3a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746343498 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3746343498
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2128422355
Short name T83
Test name
Test status
Simulation time 99032375 ps
CPU time 5.71 seconds
Started Jan 25 02:49:55 PM PST 24
Finished Jan 25 02:50:26 PM PST 24
Peak memory 222344 kb
Host smart-f2fe5c8b-d255-49f4-8c11-4614f9375fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128422355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2128422355
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.4080673687
Short name T240
Test name
Test status
Simulation time 10763699257 ps
CPU time 74.61 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:54:23 PM PST 24
Peak memory 215124 kb
Host smart-d7726827-b030-403b-a25a-c1dd17aed26a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080673687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.4080673687
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1177289966
Short name T32
Test name
Test status
Simulation time 141186443 ps
CPU time 3.03 seconds
Started Jan 25 02:49:44 PM PST 24
Finished Jan 25 02:50:11 PM PST 24
Peak memory 210080 kb
Host smart-5a26f5e5-9d67-4472-a34d-290ef6e4114d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177289966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1177289966
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.4136064691
Short name T191
Test name
Test status
Simulation time 4550754906 ps
CPU time 99.94 seconds
Started Jan 25 02:46:13 PM PST 24
Finished Jan 25 02:48:08 PM PST 24
Peak memory 222512 kb
Host smart-ca5d49ef-af12-4790-b596-022f95648da5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136064691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.4136064691
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2818323344
Short name T358
Test name
Test status
Simulation time 278110772 ps
CPU time 14.53 seconds
Started Jan 25 02:50:29 PM PST 24
Finished Jan 25 02:50:55 PM PST 24
Peak memory 214316 kb
Host smart-96ea7360-52fb-455a-9ad4-297bb7dff378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818323344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2818323344
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1522572017
Short name T21
Test name
Test status
Simulation time 165529812 ps
CPU time 5.46 seconds
Started Jan 25 02:50:53 PM PST 24
Finished Jan 25 02:51:03 PM PST 24
Peak memory 214200 kb
Host smart-c1c6b76e-5d57-4822-8147-43c8224b1a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522572017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1522572017
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3490947448
Short name T6
Test name
Test status
Simulation time 412088915 ps
CPU time 9.62 seconds
Started Jan 25 02:49:27 PM PST 24
Finished Jan 25 02:49:55 PM PST 24
Peak memory 222540 kb
Host smart-e5a9fda6-8bb5-4212-9921-f00fe46ebf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490947448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3490947448
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2024305615
Short name T135
Test name
Test status
Simulation time 352899673 ps
CPU time 11.81 seconds
Started Jan 25 12:49:14 PM PST 24
Finished Jan 25 12:49:28 PM PST 24
Peak memory 213776 kb
Host smart-0b94bc57-eccc-4ed2-b0be-22e7e2475eb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024305615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2024305615
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2100937833
Short name T241
Test name
Test status
Simulation time 385621480 ps
CPU time 20.56 seconds
Started Jan 25 02:47:01 PM PST 24
Finished Jan 25 02:48:12 PM PST 24
Peak memory 214928 kb
Host smart-cf445f94-1a88-4213-ad2a-41b66bc5a526
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100937833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2100937833
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2758096142
Short name T68
Test name
Test status
Simulation time 784750643 ps
CPU time 30.15 seconds
Started Jan 25 02:47:03 PM PST 24
Finished Jan 25 02:48:24 PM PST 24
Peak memory 216208 kb
Host smart-32844076-5c03-4015-8c03-558a3c5cbfac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758096142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2758096142
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2060738301
Short name T380
Test name
Test status
Simulation time 1189660831 ps
CPU time 16.2 seconds
Started Jan 25 02:45:41 PM PST 24
Finished Jan 25 02:46:23 PM PST 24
Peak memory 215272 kb
Host smart-74f2b06c-0739-4e31-8cbe-7017a06a6c17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2060738301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2060738301
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.871670586
Short name T37
Test name
Test status
Simulation time 291400968 ps
CPU time 3.53 seconds
Started Jan 25 02:49:04 PM PST 24
Finished Jan 25 02:49:22 PM PST 24
Peak memory 208372 kb
Host smart-d5e6d987-7d8c-4f12-97e6-7f8716ed8af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871670586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.871670586
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3869477099
Short name T24
Test name
Test status
Simulation time 2507775842 ps
CPU time 6.38 seconds
Started Jan 25 02:48:33 PM PST 24
Finished Jan 25 02:49:01 PM PST 24
Peak memory 219356 kb
Host smart-b4a4254c-6e44-4b27-8dbe-413e0bfbcb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869477099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3869477099
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2916108869
Short name T69
Test name
Test status
Simulation time 2854626558 ps
CPU time 67.5 seconds
Started Jan 25 02:45:49 PM PST 24
Finished Jan 25 02:47:20 PM PST 24
Peak memory 222568 kb
Host smart-f343a70d-9eb1-460b-9ab6-fe44a198818e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916108869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2916108869
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2076919515
Short name T16
Test name
Test status
Simulation time 60287109 ps
CPU time 3.11 seconds
Started Jan 25 02:47:58 PM PST 24
Finished Jan 25 02:48:37 PM PST 24
Peak memory 208504 kb
Host smart-0ed5d5b6-7ef1-4f22-823d-f666dfdacf39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076919515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2076919515
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2445310228
Short name T249
Test name
Test status
Simulation time 2886366122 ps
CPU time 88.67 seconds
Started Jan 25 02:47:17 PM PST 24
Finished Jan 25 02:49:34 PM PST 24
Peak memory 222544 kb
Host smart-447caabb-55f7-4faa-96cd-da5ce0c34618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445310228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2445310228
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3485683115
Short name T28
Test name
Test status
Simulation time 164291150 ps
CPU time 2.28 seconds
Started Jan 25 02:49:28 PM PST 24
Finished Jan 25 02:49:50 PM PST 24
Peak memory 214188 kb
Host smart-c2f7b43c-aac1-47b9-bafe-bdae2348984f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485683115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3485683115
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.578955845
Short name T149
Test name
Test status
Simulation time 1408442441 ps
CPU time 9.69 seconds
Started Jan 25 12:49:45 PM PST 24
Finished Jan 25 12:49:57 PM PST 24
Peak memory 213548 kb
Host smart-13a792ed-98ad-4f22-a5b5-2006105789f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578955845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.578955845
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.699547992
Short name T141
Test name
Test status
Simulation time 66052689 ps
CPU time 2.7 seconds
Started Jan 25 02:49:00 PM PST 24
Finished Jan 25 02:49:15 PM PST 24
Peak memory 222752 kb
Host smart-4492a70b-dba6-413d-bcc0-704cfe4e90cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699547992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.699547992
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1867316706
Short name T170
Test name
Test status
Simulation time 347591062 ps
CPU time 10.52 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:52:18 PM PST 24
Peak memory 210200 kb
Host smart-6c1bd191-1045-4d37-8b9f-7ea4c8ebab5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867316706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1867316706
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.879287769
Short name T202
Test name
Test status
Simulation time 4193991340 ps
CPU time 38.7 seconds
Started Jan 25 02:51:38 PM PST 24
Finished Jan 25 02:52:30 PM PST 24
Peak memory 214652 kb
Host smart-3b6c29c3-3304-4929-b082-47503134c665
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879287769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.879287769
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2425212195
Short name T284
Test name
Test status
Simulation time 6543667166 ps
CPU time 90.77 seconds
Started Jan 25 02:45:00 PM PST 24
Finished Jan 25 02:47:08 PM PST 24
Peak memory 215056 kb
Host smart-b63b0626-5296-46b3-ab5b-644b4a2ac161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425212195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2425212195
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.177303773
Short name T216
Test name
Test status
Simulation time 4041464838 ps
CPU time 93.44 seconds
Started Jan 25 02:45:49 PM PST 24
Finished Jan 25 02:47:46 PM PST 24
Peak memory 222524 kb
Host smart-aa55dd8a-858a-49ba-bbe6-ddea129aa982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177303773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.177303773
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1487855657
Short name T400
Test name
Test status
Simulation time 26248146 ps
CPU time 0.9 seconds
Started Jan 25 02:47:09 PM PST 24
Finished Jan 25 02:47:59 PM PST 24
Peak memory 205988 kb
Host smart-fd552719-67aa-403f-a01d-27202bc77180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487855657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1487855657
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3324051833
Short name T54
Test name
Test status
Simulation time 2113882680 ps
CPU time 19.85 seconds
Started Jan 25 02:50:07 PM PST 24
Finished Jan 25 02:50:50 PM PST 24
Peak memory 215004 kb
Host smart-5af51e89-a923-4eeb-b2ee-68debef550d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324051833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3324051833
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.395946631
Short name T73
Test name
Test status
Simulation time 4004260227 ps
CPU time 77.44 seconds
Started Jan 25 02:50:34 PM PST 24
Finished Jan 25 02:52:04 PM PST 24
Peak memory 222484 kb
Host smart-c0b9927e-5270-4ab7-bfba-71b7a700b2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395946631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.395946631
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3975111015
Short name T84
Test name
Test status
Simulation time 292452111 ps
CPU time 4.26 seconds
Started Jan 25 02:47:10 PM PST 24
Finished Jan 25 02:48:03 PM PST 24
Peak memory 210396 kb
Host smart-eded3cd8-9861-43eb-8209-03e3a54c5bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975111015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3975111015
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3792211843
Short name T151
Test name
Test status
Simulation time 193578062 ps
CPU time 5.42 seconds
Started Jan 25 12:50:08 PM PST 24
Finished Jan 25 12:50:17 PM PST 24
Peak memory 208792 kb
Host smart-b37fea38-b9fd-4367-ab1e-758ad0eed69c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792211843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3792211843
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3632150912
Short name T264
Test name
Test status
Simulation time 3045729790 ps
CPU time 129.27 seconds
Started Jan 25 02:45:43 PM PST 24
Finished Jan 25 02:48:18 PM PST 24
Peak memory 222592 kb
Host smart-3db35ee1-ffff-4504-bc26-6a0563e49ee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3632150912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3632150912
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.1594890919
Short name T114
Test name
Test status
Simulation time 504682429 ps
CPU time 7.88 seconds
Started Jan 25 02:49:04 PM PST 24
Finished Jan 25 02:49:26 PM PST 24
Peak memory 222488 kb
Host smart-6847b520-cb0d-403e-b99a-64124cf64bc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594890919 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.1594890919
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.948405901
Short name T146
Test name
Test status
Simulation time 592742253 ps
CPU time 4.65 seconds
Started Jan 25 02:49:48 PM PST 24
Finished Jan 25 02:50:15 PM PST 24
Peak memory 222924 kb
Host smart-f8b90666-d89c-4d31-96b8-f42c48fe0390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948405901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.948405901
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.194905389
Short name T254
Test name
Test status
Simulation time 4325943056 ps
CPU time 28.62 seconds
Started Jan 25 02:45:00 PM PST 24
Finished Jan 25 02:46:06 PM PST 24
Peak memory 214208 kb
Host smart-2d9c77d2-fd1f-4e54-85ce-26e1de3f529c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194905389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.194905389
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1942243711
Short name T221
Test name
Test status
Simulation time 400957124 ps
CPU time 3.71 seconds
Started Jan 25 02:47:10 PM PST 24
Finished Jan 25 02:48:03 PM PST 24
Peak memory 214168 kb
Host smart-37604560-9e39-416d-8b8b-94e998c21386
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1942243711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1942243711
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1181680893
Short name T61
Test name
Test status
Simulation time 117046390 ps
CPU time 2.19 seconds
Started Jan 25 02:46:16 PM PST 24
Finished Jan 25 02:46:32 PM PST 24
Peak memory 209592 kb
Host smart-ec4df20d-15a6-43cf-9415-cd819f80140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181680893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1181680893
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.330355343
Short name T145
Test name
Test status
Simulation time 60931018 ps
CPU time 3.78 seconds
Started Jan 25 02:49:54 PM PST 24
Finished Jan 25 02:50:21 PM PST 24
Peak memory 217600 kb
Host smart-ce7bc16d-89fc-4014-bde0-c998a1ef9c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330355343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.330355343
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3316486350
Short name T140
Test name
Test status
Simulation time 115917084 ps
CPU time 6.2 seconds
Started Jan 25 02:47:19 PM PST 24
Finished Jan 25 02:48:13 PM PST 24
Peak memory 214268 kb
Host smart-80912463-c281-4893-b1be-6b8af0a501fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316486350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3316486350
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.138050461
Short name T292
Test name
Test status
Simulation time 507328838 ps
CPU time 10.33 seconds
Started Jan 25 02:47:25 PM PST 24
Finished Jan 25 02:48:21 PM PST 24
Peak memory 220432 kb
Host smart-55720910-0ced-4642-961d-da04cc374525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138050461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.138050461
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3731208645
Short name T293
Test name
Test status
Simulation time 238464658 ps
CPU time 4.74 seconds
Started Jan 25 02:47:57 PM PST 24
Finished Jan 25 02:48:39 PM PST 24
Peak memory 222444 kb
Host smart-d47db888-f58a-45dd-9a18-aacdcfb7d72a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731208645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3731208645
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1335903820
Short name T277
Test name
Test status
Simulation time 1295293461 ps
CPU time 11.73 seconds
Started Jan 25 02:52:07 PM PST 24
Finished Jan 25 02:52:35 PM PST 24
Peak memory 222600 kb
Host smart-1aad5cf2-2f67-4814-917b-d017f5644708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335903820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1335903820
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.468132033
Short name T143
Test name
Test status
Simulation time 385226610 ps
CPU time 6.39 seconds
Started Jan 25 02:50:58 PM PST 24
Finished Jan 25 02:51:13 PM PST 24
Peak memory 222708 kb
Host smart-76d864a9-91ae-435b-a9ab-4f4e6affb83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468132033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.468132033
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2426170681
Short name T154
Test name
Test status
Simulation time 508273521 ps
CPU time 12.52 seconds
Started Jan 25 12:49:33 PM PST 24
Finished Jan 25 12:49:47 PM PST 24
Peak memory 213472 kb
Host smart-0eaabd21-b2c4-480c-bde3-fd6ebf9c677d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426170681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2426170681
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3279244092
Short name T155
Test name
Test status
Simulation time 7754133111 ps
CPU time 69.09 seconds
Started Jan 25 12:50:07 PM PST 24
Finished Jan 25 12:51:20 PM PST 24
Peak memory 213644 kb
Host smart-df710c51-6a83-48b7-b234-fce22b6fc42d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279244092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3279244092
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4016573780
Short name T150
Test name
Test status
Simulation time 864008779 ps
CPU time 8.32 seconds
Started Jan 25 12:48:36 PM PST 24
Finished Jan 25 12:48:49 PM PST 24
Peak memory 208996 kb
Host smart-f82341a4-a673-4e23-bcba-6840f14e86bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016573780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.4016573780
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1904894709
Short name T184
Test name
Test status
Simulation time 748321858 ps
CPU time 21.26 seconds
Started Jan 25 02:45:01 PM PST 24
Finished Jan 25 02:45:59 PM PST 24
Peak memory 222412 kb
Host smart-3bca18d9-0e9b-466d-a6ea-0cee1510a2af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904894709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1904894709
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3870521224
Short name T236
Test name
Test status
Simulation time 501586819 ps
CPU time 8.13 seconds
Started Jan 25 02:47:09 PM PST 24
Finished Jan 25 02:48:07 PM PST 24
Peak memory 211312 kb
Host smart-03b1492e-16e6-47e9-8e08-2e1a80dc6ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870521224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3870521224
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_random.1019422652
Short name T120
Test name
Test status
Simulation time 264830723 ps
CPU time 4.87 seconds
Started Jan 25 02:48:54 PM PST 24
Finished Jan 25 02:49:12 PM PST 24
Peak memory 207968 kb
Host smart-d218d30b-b223-4b66-a6b2-6098f298d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019422652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1019422652
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1233095779
Short name T47
Test name
Test status
Simulation time 152750633 ps
CPU time 3.75 seconds
Started Jan 25 02:50:56 PM PST 24
Finished Jan 25 02:51:05 PM PST 24
Peak memory 210436 kb
Host smart-07ed7dfd-f4db-4715-9808-8a9def07ca0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233095779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1233095779
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2056870929
Short name T144
Test name
Test status
Simulation time 250188916 ps
CPU time 4.25 seconds
Started Jan 25 02:49:02 PM PST 24
Finished Jan 25 02:49:19 PM PST 24
Peak memory 222684 kb
Host smart-c390298d-c68b-4b76-aa77-d695dec2f50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056870929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2056870929
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.207045824
Short name T142
Test name
Test status
Simulation time 536625414 ps
CPU time 4.14 seconds
Started Jan 25 02:52:06 PM PST 24
Finished Jan 25 02:52:27 PM PST 24
Peak memory 218456 kb
Host smart-e6c5ff9e-9b2f-4249-8418-6e5adf7b292a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207045824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.207045824
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1930811551
Short name T362
Test name
Test status
Simulation time 11878514042 ps
CPU time 121.54 seconds
Started Jan 25 02:47:00 PM PST 24
Finished Jan 25 02:49:51 PM PST 24
Peak memory 222504 kb
Host smart-84f52539-f12e-49a1-b3d0-650ec9644cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930811551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1930811551
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.4094576564
Short name T246
Test name
Test status
Simulation time 156579343 ps
CPU time 2.63 seconds
Started Jan 25 02:47:52 PM PST 24
Finished Jan 25 02:48:34 PM PST 24
Peak memory 207324 kb
Host smart-1777f474-beae-4661-9c03-6bedcf9c28a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094576564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.4094576564
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2692570727
Short name T243
Test name
Test status
Simulation time 775889502 ps
CPU time 25.38 seconds
Started Jan 25 02:49:35 PM PST 24
Finished Jan 25 02:50:26 PM PST 24
Peak memory 215308 kb
Host smart-70b1ca8f-dbed-4336-a9bd-2bdc29c2ed10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692570727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2692570727
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1354794532
Short name T121
Test name
Test status
Simulation time 228745658 ps
CPU time 4.31 seconds
Started Jan 25 02:50:01 PM PST 24
Finished Jan 25 02:50:29 PM PST 24
Peak memory 214224 kb
Host smart-aecc04a8-226b-4b7e-ae54-e70226c19f17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354794532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1354794532
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3840852882
Short name T181
Test name
Test status
Simulation time 632306200 ps
CPU time 5.88 seconds
Started Jan 25 02:51:02 PM PST 24
Finished Jan 25 02:51:16 PM PST 24
Peak memory 220364 kb
Host smart-44566e73-1f59-4b14-9184-554e427dee05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840852882 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3840852882
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3140154676
Short name T212
Test name
Test status
Simulation time 149223602 ps
CPU time 3.5 seconds
Started Jan 25 02:51:46 PM PST 24
Finished Jan 25 02:52:07 PM PST 24
Peak memory 210940 kb
Host smart-89d59d44-543f-4ab4-b7c1-1c84aec67b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140154676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3140154676
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1596435088
Short name T85
Test name
Test status
Simulation time 11890864613 ps
CPU time 59.51 seconds
Started Jan 25 02:45:31 PM PST 24
Finished Jan 25 02:46:59 PM PST 24
Peak memory 214592 kb
Host smart-e054cb59-8430-490f-a120-eb249870563b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596435088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1596435088
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1194272038
Short name T302
Test name
Test status
Simulation time 1861815811 ps
CPU time 11.98 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:20 PM PST 24
Peak memory 222300 kb
Host smart-17a2ba85-2210-4303-aec1-6a7922be0752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194272038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1194272038
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.100243945
Short name T238
Test name
Test status
Simulation time 137702268 ps
CPU time 4.75 seconds
Started Jan 25 02:46:35 PM PST 24
Finished Jan 25 02:47:17 PM PST 24
Peak memory 214216 kb
Host smart-eb2c8740-b27c-4ad0-bb9a-d0289e7e30b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100243945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.100243945
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.454440834
Short name T353
Test name
Test status
Simulation time 398744889 ps
CPU time 17.19 seconds
Started Jan 25 02:46:40 PM PST 24
Finished Jan 25 02:47:41 PM PST 24
Peak memory 222660 kb
Host smart-58b861ec-96c3-4dce-9d05-ebc48aeaada0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454440834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.454440834
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3274181667
Short name T162
Test name
Test status
Simulation time 141571001 ps
CPU time 5.48 seconds
Started Jan 25 12:48:39 PM PST 24
Finished Jan 25 12:48:50 PM PST 24
Peak memory 213540 kb
Host smart-b967ad04-ccba-452b-b048-1e8c4e123fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274181667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3274181667
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.362704698
Short name T159
Test name
Test status
Simulation time 1653131009 ps
CPU time 8.45 seconds
Started Jan 25 12:54:08 PM PST 24
Finished Jan 25 12:54:22 PM PST 24
Peak memory 208720 kb
Host smart-2ea98b72-0745-4342-9df2-edd58196df54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362704698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
362704698
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3465660702
Short name T31
Test name
Test status
Simulation time 195485237 ps
CPU time 3.25 seconds
Started Jan 25 02:49:26 PM PST 24
Finished Jan 25 02:49:49 PM PST 24
Peak memory 208464 kb
Host smart-26fdb405-6318-4e92-99b8-ab03575cf149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465660702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3465660702
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.563330537
Short name T163
Test name
Test status
Simulation time 38906257 ps
CPU time 2.17 seconds
Started Jan 25 02:49:53 PM PST 24
Finished Jan 25 02:50:19 PM PST 24
Peak memory 209988 kb
Host smart-f4d1acf5-292c-42bf-92ee-70c6d02f26d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563330537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.563330537
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1243829220
Short name T112
Test name
Test status
Simulation time 58043680 ps
CPU time 2.51 seconds
Started Jan 25 12:48:21 PM PST 24
Finished Jan 25 12:48:27 PM PST 24
Peak memory 221760 kb
Host smart-6f025d8c-5928-494e-98ae-caa0542d8545
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243829220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1243829220
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.885877063
Short name T226
Test name
Test status
Simulation time 63360957 ps
CPU time 3.94 seconds
Started Jan 25 02:46:41 PM PST 24
Finished Jan 25 02:47:30 PM PST 24
Peak memory 214172 kb
Host smart-5ef7836a-4990-4c9a-ba45-8615ac0c9405
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885877063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.885877063
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.944593570
Short name T26
Test name
Test status
Simulation time 174043361 ps
CPU time 8.5 seconds
Started Jan 25 02:47:00 PM PST 24
Finished Jan 25 02:47:59 PM PST 24
Peak memory 214584 kb
Host smart-a4a2b6f7-9284-49ab-8fe5-262b74609007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944593570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.944593570
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3363441351
Short name T349
Test name
Test status
Simulation time 52057568 ps
CPU time 3.08 seconds
Started Jan 25 02:47:03 PM PST 24
Finished Jan 25 02:47:57 PM PST 24
Peak memory 218712 kb
Host smart-deab303b-2950-47c3-b779-ae152a005f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363441351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3363441351
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.551860446
Short name T89
Test name
Test status
Simulation time 270357895 ps
CPU time 5.63 seconds
Started Jan 25 02:47:04 PM PST 24
Finished Jan 25 02:47:59 PM PST 24
Peak memory 213956 kb
Host smart-8a5bc78c-8733-4b80-91ea-30e10758162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551860446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.551860446
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3320269948
Short name T926
Test name
Test status
Simulation time 360222458 ps
CPU time 9.46 seconds
Started Jan 25 02:47:04 PM PST 24
Finished Jan 25 02:48:03 PM PST 24
Peak memory 222460 kb
Host smart-5b415847-d037-4218-879f-6b66e2e01cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320269948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3320269948
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.265747030
Short name T601
Test name
Test status
Simulation time 690030966 ps
CPU time 6.43 seconds
Started Jan 25 02:47:00 PM PST 24
Finished Jan 25 02:47:56 PM PST 24
Peak memory 220600 kb
Host smart-f980706c-d3c8-4895-a26e-e1794bd121e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265747030 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.265747030
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1481670060
Short name T310
Test name
Test status
Simulation time 4092184521 ps
CPU time 21.27 seconds
Started Jan 25 02:47:30 PM PST 24
Finished Jan 25 02:48:35 PM PST 24
Peak memory 221008 kb
Host smart-a28d3489-a68f-45d3-b744-a585d2072164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481670060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1481670060
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1566297191
Short name T123
Test name
Test status
Simulation time 69548278 ps
CPU time 2.9 seconds
Started Jan 25 05:32:36 PM PST 24
Finished Jan 25 05:32:44 PM PST 24
Peak memory 214236 kb
Host smart-2e9b28c1-e390-4b5a-914b-0920bbeacc2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1566297191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1566297191
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.104062128
Short name T781
Test name
Test status
Simulation time 196425077 ps
CPU time 13.09 seconds
Started Jan 25 03:48:36 PM PST 24
Finished Jan 25 03:49:41 PM PST 24
Peak memory 222516 kb
Host smart-26c218d0-4404-477c-aaba-36fa93974278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104062128 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.104062128
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.731848
Short name T390
Test name
Test status
Simulation time 702552479 ps
CPU time 3.84 seconds
Started Jan 25 02:48:31 PM PST 24
Finished Jan 25 02:48:58 PM PST 24
Peak memory 214304 kb
Host smart-4cd1004e-cca0-46cd-905c-a3b93982f286
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.731848
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.368086436
Short name T313
Test name
Test status
Simulation time 70225083 ps
CPU time 1.57 seconds
Started Jan 25 02:49:26 PM PST 24
Finished Jan 25 02:49:47 PM PST 24
Peak memory 207848 kb
Host smart-240929e3-c3e8-42d5-a269-79bfefd18ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368086436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.368086436
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.896894226
Short name T307
Test name
Test status
Simulation time 242151082 ps
CPU time 2.89 seconds
Started Jan 25 02:49:27 PM PST 24
Finished Jan 25 02:49:50 PM PST 24
Peak memory 209256 kb
Host smart-6fd87f76-4035-4ee6-aaf1-c4100eac8c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896894226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.896894226
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.287713157
Short name T316
Test name
Test status
Simulation time 304481598 ps
CPU time 3.97 seconds
Started Jan 25 02:49:24 PM PST 24
Finished Jan 25 02:49:46 PM PST 24
Peak memory 222368 kb
Host smart-3bb478f4-e630-4e0c-a151-ca5a98d83bf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287713157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.287713157
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1149762522
Short name T176
Test name
Test status
Simulation time 90478447 ps
CPU time 3.5 seconds
Started Jan 25 02:49:35 PM PST 24
Finished Jan 25 02:50:03 PM PST 24
Peak memory 222372 kb
Host smart-8ffdf1f8-f2ca-4005-b0bc-9613e33e0af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149762522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1149762522
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.101984044
Short name T200
Test name
Test status
Simulation time 62213846 ps
CPU time 3.16 seconds
Started Jan 25 02:49:31 PM PST 24
Finished Jan 25 02:49:55 PM PST 24
Peak memory 214344 kb
Host smart-248775c8-11d4-4c26-bb7f-78743f23d16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101984044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.101984044
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2853781859
Short name T217
Test name
Test status
Simulation time 11130916657 ps
CPU time 56.99 seconds
Started Jan 25 02:50:53 PM PST 24
Finished Jan 25 02:51:55 PM PST 24
Peak memory 222640 kb
Host smart-51158c94-f260-4a51-a312-ac1b26379750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853781859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2853781859
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3106054104
Short name T364
Test name
Test status
Simulation time 251148783 ps
CPU time 7.23 seconds
Started Jan 25 02:51:32 PM PST 24
Finished Jan 25 02:51:53 PM PST 24
Peak memory 210012 kb
Host smart-c12c9a9f-5bb7-4942-b401-4a203a61078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106054104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3106054104
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3470974176
Short name T197
Test name
Test status
Simulation time 192750527 ps
CPU time 4.33 seconds
Started Jan 25 02:52:51 PM PST 24
Finished Jan 25 02:53:11 PM PST 24
Peak memory 209680 kb
Host smart-9e4f584b-903f-45af-b175-d2a80feb7128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470974176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3470974176
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2500271646
Short name T363
Test name
Test status
Simulation time 4091723074 ps
CPU time 17.58 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:28 PM PST 24
Peak memory 214288 kb
Host smart-fbec4ded-fdb5-4a37-a45c-bacac70c79fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500271646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2500271646
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2389853570
Short name T60
Test name
Test status
Simulation time 151890212 ps
CPU time 4.1 seconds
Started Jan 25 02:46:41 PM PST 24
Finished Jan 25 02:47:30 PM PST 24
Peak memory 209976 kb
Host smart-e6fa2e03-9866-4d4a-a366-1e77f07b6732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389853570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2389853570
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3528059829
Short name T462
Test name
Test status
Simulation time 142166527 ps
CPU time 4.09 seconds
Started Jan 25 12:48:34 PM PST 24
Finished Jan 25 12:48:41 PM PST 24
Peak memory 205232 kb
Host smart-0d056812-ac87-45f1-90d1-e1f0cc3a2e80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528059829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
528059829
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4049727433
Short name T497
Test name
Test status
Simulation time 999180008 ps
CPU time 14.35 seconds
Started Jan 25 12:48:31 PM PST 24
Finished Jan 25 12:48:48 PM PST 24
Peak memory 205236 kb
Host smart-4f4dc201-e623-4ce6-b03d-bb7d23ca163d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049727433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.4
049727433
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.67900236
Short name T524
Test name
Test status
Simulation time 43678731 ps
CPU time 1.18 seconds
Started Jan 25 12:48:31 PM PST 24
Finished Jan 25 12:48:35 PM PST 24
Peak memory 205164 kb
Host smart-558a6711-d076-4132-a6e7-43b6066d0c52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67900236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.67900236
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1990841419
Short name T459
Test name
Test status
Simulation time 25232224 ps
CPU time 1.06 seconds
Started Jan 25 12:48:34 PM PST 24
Finished Jan 25 12:48:38 PM PST 24
Peak memory 205352 kb
Host smart-ab2fe441-194d-4ff3-a1f5-f65c8ead60b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990841419 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1990841419
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3552096292
Short name T474
Test name
Test status
Simulation time 43700145 ps
CPU time 0.86 seconds
Started Jan 25 12:48:26 PM PST 24
Finished Jan 25 12:48:29 PM PST 24
Peak memory 205104 kb
Host smart-0bb258d6-e678-42c9-98f9-17db2a159894
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552096292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3552096292
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3618195155
Short name T500
Test name
Test status
Simulation time 52880027 ps
CPU time 0.79 seconds
Started Jan 25 12:48:30 PM PST 24
Finished Jan 25 12:48:33 PM PST 24
Peak memory 205088 kb
Host smart-5d0e1892-00af-4e38-88bf-7fcdbdfd7bfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618195155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3618195155
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.113988033
Short name T132
Test name
Test status
Simulation time 639333858 ps
CPU time 5.01 seconds
Started Jan 25 12:48:31 PM PST 24
Finished Jan 25 12:48:38 PM PST 24
Peak memory 213564 kb
Host smart-2e596352-77d8-4c25-af66-4a36cf9b0bcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113988033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.113988033
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.465892687
Short name T514
Test name
Test status
Simulation time 284218257 ps
CPU time 3.72 seconds
Started Jan 25 12:48:33 PM PST 24
Finished Jan 25 12:48:40 PM PST 24
Peak memory 213372 kb
Host smart-0eba7ff0-3471-4f65-805a-4ddceb572249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465892687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.465892687
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1300757644
Short name T164
Test name
Test status
Simulation time 1138068770 ps
CPU time 15.08 seconds
Started Jan 25 12:48:31 PM PST 24
Finished Jan 25 12:48:49 PM PST 24
Peak memory 213600 kb
Host smart-f4c040b3-8dc1-43d5-ba34-8c2df08da197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300757644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1300757644
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.731513622
Short name T516
Test name
Test status
Simulation time 250462785 ps
CPU time 4.88 seconds
Started Jan 25 12:48:35 PM PST 24
Finished Jan 25 12:48:43 PM PST 24
Peak memory 205148 kb
Host smart-e2a47762-881b-46ea-acfb-4f24ccfd6f52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731513622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.731513622
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4092090423
Short name T131
Test name
Test status
Simulation time 3427876929 ps
CPU time 18.2 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:49:02 PM PST 24
Peak memory 205388 kb
Host smart-3f1b2b58-10ff-411f-9490-603b3b5ea795
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092090423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.4
092090423
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2745957952
Short name T410
Test name
Test status
Simulation time 77665765 ps
CPU time 1.1 seconds
Started Jan 25 12:48:34 PM PST 24
Finished Jan 25 12:48:38 PM PST 24
Peak memory 205036 kb
Host smart-feba6139-ab40-496a-aefc-05ad8d7daf8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745957952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
745957952
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.874506214
Short name T535
Test name
Test status
Simulation time 36013979 ps
CPU time 0.97 seconds
Started Jan 25 12:48:34 PM PST 24
Finished Jan 25 12:48:39 PM PST 24
Peak memory 205192 kb
Host smart-87acdb9d-632b-4f5f-84ac-24913cf636dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874506214 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.874506214
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2439485269
Short name T486
Test name
Test status
Simulation time 27915103 ps
CPU time 0.87 seconds
Started Jan 25 12:48:35 PM PST 24
Finished Jan 25 12:48:40 PM PST 24
Peak memory 204976 kb
Host smart-7cd5d341-82e3-431f-bab5-7bbda64cf3b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439485269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2439485269
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1126300616
Short name T477
Test name
Test status
Simulation time 40300536 ps
CPU time 0.7 seconds
Started Jan 25 12:48:37 PM PST 24
Finished Jan 25 12:48:42 PM PST 24
Peak memory 205096 kb
Host smart-09846968-be19-4a3d-90aa-1c21ee7878f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126300616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1126300616
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2524731384
Short name T137
Test name
Test status
Simulation time 37560231 ps
CPU time 2.47 seconds
Started Jan 25 12:48:35 PM PST 24
Finished Jan 25 12:48:40 PM PST 24
Peak memory 205184 kb
Host smart-3159414d-5ca1-431c-87ab-d9e7dfd324a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524731384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2524731384
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3108066051
Short name T534
Test name
Test status
Simulation time 118398217 ps
CPU time 4.28 seconds
Started Jan 25 12:48:30 PM PST 24
Finished Jan 25 12:48:37 PM PST 24
Peak memory 221916 kb
Host smart-c9e8541a-9bf5-40d6-873d-561b008d25b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108066051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3108066051
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.346684240
Short name T491
Test name
Test status
Simulation time 239831128 ps
CPU time 5.74 seconds
Started Jan 25 12:48:31 PM PST 24
Finished Jan 25 12:48:40 PM PST 24
Peak memory 213624 kb
Host smart-54741da5-9b0c-4ded-a68d-1ec04ce2fef1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346684240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.346684240
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3237314444
Short name T452
Test name
Test status
Simulation time 420457616 ps
CPU time 4.2 seconds
Started Jan 25 12:48:31 PM PST 24
Finished Jan 25 12:48:37 PM PST 24
Peak memory 213476 kb
Host smart-cb9e76bd-8237-4f98-90c0-b8ca0591ce6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237314444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3237314444
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.4257129943
Short name T161
Test name
Test status
Simulation time 884269245 ps
CPU time 9.78 seconds
Started Jan 25 12:48:35 PM PST 24
Finished Jan 25 12:48:48 PM PST 24
Peak memory 208624 kb
Host smart-7dac02fd-4e7e-403f-b714-f7cfded2ee26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257129943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.4257129943
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3069132703
Short name T423
Test name
Test status
Simulation time 47535029 ps
CPU time 1.21 seconds
Started Jan 25 12:49:16 PM PST 24
Finished Jan 25 12:49:19 PM PST 24
Peak memory 213584 kb
Host smart-6192d841-ffd6-4baf-94fd-1393b5cb0bbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069132703 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3069132703
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1951315591
Short name T148
Test name
Test status
Simulation time 413135142 ps
CPU time 1.4 seconds
Started Jan 25 12:49:17 PM PST 24
Finished Jan 25 12:49:22 PM PST 24
Peak memory 205052 kb
Host smart-44ccd4e6-994a-4a00-97b7-ee841a419bef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951315591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1951315591
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1067770852
Short name T520
Test name
Test status
Simulation time 10127285 ps
CPU time 0.77 seconds
Started Jan 25 12:49:25 PM PST 24
Finished Jan 25 12:49:27 PM PST 24
Peak memory 205148 kb
Host smart-eeea5c7b-bf46-4dfc-b90e-657ab4695827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067770852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1067770852
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4050719037
Short name T449
Test name
Test status
Simulation time 98016899 ps
CPU time 2.49 seconds
Started Jan 25 12:49:15 PM PST 24
Finished Jan 25 12:49:20 PM PST 24
Peak memory 205428 kb
Host smart-c4ff0ac3-aea2-4474-9dc9-71169cc4839a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050719037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.4050719037
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4019467695
Short name T108
Test name
Test status
Simulation time 727217608 ps
CPU time 5.27 seconds
Started Jan 25 12:49:17 PM PST 24
Finished Jan 25 12:49:24 PM PST 24
Peak memory 213704 kb
Host smart-0ecb06b6-4872-4417-b906-a64dad258a4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019467695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4019467695
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2714732631
Short name T541
Test name
Test status
Simulation time 345858334 ps
CPU time 3.37 seconds
Started Jan 25 12:49:15 PM PST 24
Finished Jan 25 12:49:20 PM PST 24
Peak memory 213780 kb
Host smart-2bdda83a-240c-4501-b61a-ec349fbda1ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714732631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2714732631
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1907254965
Short name T117
Test name
Test status
Simulation time 117417596 ps
CPU time 4.79 seconds
Started Jan 25 12:49:15 PM PST 24
Finished Jan 25 12:49:21 PM PST 24
Peak memory 209004 kb
Host smart-43436079-d0cf-4e43-8cd8-bd17d1e6181e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907254965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1907254965
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.804800839
Short name T458
Test name
Test status
Simulation time 35228317 ps
CPU time 1.37 seconds
Started Jan 25 12:49:14 PM PST 24
Finished Jan 25 12:49:18 PM PST 24
Peak memory 213456 kb
Host smart-baafd5ec-246b-4570-8c73-19feaca85b7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804800839 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.804800839
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2072182285
Short name T465
Test name
Test status
Simulation time 61889145 ps
CPU time 1.07 seconds
Started Jan 25 12:49:14 PM PST 24
Finished Jan 25 12:49:16 PM PST 24
Peak memory 205168 kb
Host smart-9fcf76d3-e064-494f-8740-559107b6744f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072182285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2072182285
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1668939607
Short name T450
Test name
Test status
Simulation time 10535389 ps
CPU time 0.77 seconds
Started Jan 25 12:49:12 PM PST 24
Finished Jan 25 12:49:14 PM PST 24
Peak memory 204948 kb
Host smart-3642fa67-4f2a-4b2f-8afe-47787f95a5f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668939607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1668939607
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1303820666
Short name T533
Test name
Test status
Simulation time 48671162 ps
CPU time 1.53 seconds
Started Jan 25 12:49:15 PM PST 24
Finished Jan 25 12:49:18 PM PST 24
Peak memory 213552 kb
Host smart-487c7347-f274-4316-ab5f-5a4d39974d37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303820666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1303820666
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2016281619
Short name T166
Test name
Test status
Simulation time 481265702 ps
CPU time 4.41 seconds
Started Jan 25 12:49:18 PM PST 24
Finished Jan 25 12:49:25 PM PST 24
Peak memory 213712 kb
Host smart-8d4d9467-267f-4b32-850b-a6dd20869c1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016281619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2016281619
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2928537141
Short name T472
Test name
Test status
Simulation time 249881165 ps
CPU time 1.88 seconds
Started Jan 25 12:49:15 PM PST 24
Finished Jan 25 12:49:19 PM PST 24
Peak memory 216176 kb
Host smart-bec5fe1e-b8b5-4fbf-8c1f-f188b7d071f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928537141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2928537141
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3519197159
Short name T432
Test name
Test status
Simulation time 19730472 ps
CPU time 1.57 seconds
Started Jan 25 12:49:38 PM PST 24
Finished Jan 25 12:49:41 PM PST 24
Peak memory 213560 kb
Host smart-d6cde330-1a47-4c0e-8241-a66369a6fb51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519197159 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3519197159
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.724196368
Short name T530
Test name
Test status
Simulation time 87653359 ps
CPU time 1.11 seconds
Started Jan 25 12:49:45 PM PST 24
Finished Jan 25 12:49:47 PM PST 24
Peak memory 205144 kb
Host smart-3fdafc6d-36c0-4a54-995d-2f636e119299
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724196368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.724196368
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2902648236
Short name T490
Test name
Test status
Simulation time 42626680 ps
CPU time 0.69 seconds
Started Jan 25 12:49:30 PM PST 24
Finished Jan 25 12:49:32 PM PST 24
Peak memory 205132 kb
Host smart-27745fbb-731d-4759-a282-1ff8998ff4d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902648236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2902648236
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2173198723
Short name T435
Test name
Test status
Simulation time 105179874 ps
CPU time 1.45 seconds
Started Jan 25 12:49:38 PM PST 24
Finished Jan 25 12:49:41 PM PST 24
Peak memory 205192 kb
Host smart-7e305535-3cdf-4ddd-b1ac-7aff068ee852
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173198723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2173198723
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2774993915
Short name T519
Test name
Test status
Simulation time 199594227 ps
CPU time 6.47 seconds
Started Jan 25 12:49:14 PM PST 24
Finished Jan 25 12:49:22 PM PST 24
Peak memory 222156 kb
Host smart-199d3ab8-c22e-4948-9460-828cc70afe7e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774993915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2774993915
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1373827550
Short name T115
Test name
Test status
Simulation time 161856869 ps
CPU time 1.93 seconds
Started Jan 25 12:49:38 PM PST 24
Finished Jan 25 12:49:42 PM PST 24
Peak memory 213480 kb
Host smart-d41123d0-622e-4d5a-bd92-f2339d37c0fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373827550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1373827550
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.741294488
Short name T471
Test name
Test status
Simulation time 109036166 ps
CPU time 2.05 seconds
Started Jan 25 12:49:41 PM PST 24
Finished Jan 25 12:49:45 PM PST 24
Peak memory 213508 kb
Host smart-604d7609-bde6-4f30-bd35-a2f54987e293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741294488 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.741294488
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3608747073
Short name T138
Test name
Test status
Simulation time 47121006 ps
CPU time 1.13 seconds
Started Jan 25 12:49:37 PM PST 24
Finished Jan 25 12:49:40 PM PST 24
Peak memory 205116 kb
Host smart-0e2b5bec-5c21-48a7-860c-652a1b512158
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608747073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3608747073
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3479724280
Short name T444
Test name
Test status
Simulation time 10057211 ps
CPU time 0.7 seconds
Started Jan 25 12:49:37 PM PST 24
Finished Jan 25 12:49:39 PM PST 24
Peak memory 205108 kb
Host smart-6496ed41-6ae7-44c7-8e1c-93d72145b1b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479724280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3479724280
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.154399789
Short name T136
Test name
Test status
Simulation time 153270615 ps
CPU time 2.32 seconds
Started Jan 25 12:49:36 PM PST 24
Finished Jan 25 12:49:40 PM PST 24
Peak memory 205488 kb
Host smart-85150a68-47a9-4af0-84a1-eabaf82072c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154399789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.154399789
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2252016298
Short name T468
Test name
Test status
Simulation time 356999809 ps
CPU time 4.44 seconds
Started Jan 25 12:49:41 PM PST 24
Finished Jan 25 12:49:47 PM PST 24
Peak memory 213768 kb
Host smart-e3d91c38-1f8f-4d5c-bca0-dced5a646989
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252016298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2252016298
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2699545513
Short name T493
Test name
Test status
Simulation time 92943991 ps
CPU time 4.25 seconds
Started Jan 25 12:49:39 PM PST 24
Finished Jan 25 12:49:45 PM PST 24
Peak memory 213688 kb
Host smart-16888ac2-ce19-4777-ab63-1bf6b0ea8e3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699545513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2699545513
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.987056596
Short name T118
Test name
Test status
Simulation time 58219813 ps
CPU time 2.18 seconds
Started Jan 25 12:49:36 PM PST 24
Finished Jan 25 12:49:40 PM PST 24
Peak memory 213544 kb
Host smart-53beb335-165a-4ff4-8b4d-d8dd5b67bc8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987056596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.987056596
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3399444019
Short name T408
Test name
Test status
Simulation time 119054908 ps
CPU time 1.31 seconds
Started Jan 25 12:49:39 PM PST 24
Finished Jan 25 12:49:42 PM PST 24
Peak memory 213560 kb
Host smart-15e0ad19-e541-4c0d-8689-a53388ffd883
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399444019 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3399444019
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2970930792
Short name T485
Test name
Test status
Simulation time 45741742 ps
CPU time 1.46 seconds
Started Jan 25 12:49:36 PM PST 24
Finished Jan 25 12:49:39 PM PST 24
Peak memory 205256 kb
Host smart-3330e396-c226-40bf-8f54-997c8d3f2412
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970930792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2970930792
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3814649546
Short name T518
Test name
Test status
Simulation time 42238151 ps
CPU time 0.75 seconds
Started Jan 25 12:49:36 PM PST 24
Finished Jan 25 12:49:38 PM PST 24
Peak memory 205128 kb
Host smart-567a9c21-bef8-4646-9ac8-badc90a3168f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814649546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3814649546
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3249247032
Short name T109
Test name
Test status
Simulation time 237317422 ps
CPU time 4.36 seconds
Started Jan 25 12:49:37 PM PST 24
Finished Jan 25 12:49:43 PM PST 24
Peak memory 221864 kb
Host smart-9b5c5589-76aa-49cf-af5e-77672f3f5e34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249247032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3249247032
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.983449729
Short name T133
Test name
Test status
Simulation time 282393124 ps
CPU time 9.13 seconds
Started Jan 25 12:49:39 PM PST 24
Finished Jan 25 12:49:50 PM PST 24
Peak memory 219700 kb
Host smart-60564430-cd54-469c-b056-4536588261c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983449729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.983449729
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3408290771
Short name T169
Test name
Test status
Simulation time 79369422 ps
CPU time 2.13 seconds
Started Jan 25 12:49:35 PM PST 24
Finished Jan 25 12:49:39 PM PST 24
Peak memory 213728 kb
Host smart-d966ffb1-c4df-4d7f-94da-f9af3c56e28b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408290771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3408290771
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3232836275
Short name T434
Test name
Test status
Simulation time 14859450 ps
CPU time 0.95 seconds
Started Jan 25 12:49:41 PM PST 24
Finished Jan 25 12:49:43 PM PST 24
Peak memory 205288 kb
Host smart-fe0d31b5-5976-42ef-9280-5825a8724d32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232836275 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3232836275
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.4281754875
Short name T419
Test name
Test status
Simulation time 29801489 ps
CPU time 1.1 seconds
Started Jan 25 12:49:41 PM PST 24
Finished Jan 25 12:49:43 PM PST 24
Peak memory 205104 kb
Host smart-bfecfd99-c81c-4a6f-8909-be2ba567ebd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281754875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.4281754875
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3670817595
Short name T494
Test name
Test status
Simulation time 10364342 ps
CPU time 0.7 seconds
Started Jan 25 12:49:33 PM PST 24
Finished Jan 25 12:49:35 PM PST 24
Peak memory 205048 kb
Host smart-db2ee36c-4d03-46de-8b9c-2f99d984775a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670817595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3670817595
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3161086367
Short name T425
Test name
Test status
Simulation time 179587526 ps
CPU time 2.91 seconds
Started Jan 25 12:49:32 PM PST 24
Finished Jan 25 12:49:37 PM PST 24
Peak memory 205232 kb
Host smart-8cd77f65-080e-434b-9d5f-345e952a7283
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161086367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3161086367
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1566864496
Short name T167
Test name
Test status
Simulation time 686927152 ps
CPU time 5.13 seconds
Started Jan 25 12:49:34 PM PST 24
Finished Jan 25 12:49:41 PM PST 24
Peak memory 213748 kb
Host smart-76fa26cf-b8c9-4fda-8419-cc415ed2d88f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566864496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1566864496
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2773108208
Short name T527
Test name
Test status
Simulation time 23648448 ps
CPU time 1.63 seconds
Started Jan 25 12:49:40 PM PST 24
Finished Jan 25 12:49:44 PM PST 24
Peak memory 213440 kb
Host smart-428a685a-8fdc-4742-8e04-3a3736b1c01f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773108208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2773108208
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1965157310
Short name T153
Test name
Test status
Simulation time 793703901 ps
CPU time 12.64 seconds
Started Jan 25 01:15:57 PM PST 24
Finished Jan 25 01:16:13 PM PST 24
Peak memory 213652 kb
Host smart-9e43249a-1ef5-400c-9228-520be8cf4e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965157310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1965157310
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1727186023
Short name T420
Test name
Test status
Simulation time 313749810 ps
CPU time 1.81 seconds
Started Jan 25 12:49:45 PM PST 24
Finished Jan 25 12:49:49 PM PST 24
Peak memory 213560 kb
Host smart-74f40dac-4263-4cde-b56b-2823b38bf806
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727186023 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1727186023
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2174152984
Short name T438
Test name
Test status
Simulation time 49798891 ps
CPU time 1.43 seconds
Started Jan 25 12:49:43 PM PST 24
Finished Jan 25 12:49:46 PM PST 24
Peak memory 205308 kb
Host smart-789ecf9e-53cf-46af-9e59-6ca47df34b20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174152984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2174152984
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3566094295
Short name T506
Test name
Test status
Simulation time 16744228 ps
CPU time 0.72 seconds
Started Jan 25 12:49:37 PM PST 24
Finished Jan 25 12:49:40 PM PST 24
Peak memory 205112 kb
Host smart-6a85d366-fb38-4317-8aee-9560bfc34911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566094295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3566094295
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2168233106
Short name T437
Test name
Test status
Simulation time 126235752 ps
CPU time 1.5 seconds
Started Jan 25 12:49:36 PM PST 24
Finished Jan 25 12:49:39 PM PST 24
Peak memory 205296 kb
Host smart-2eb4d87e-4ecf-4587-84da-7291ad0d6993
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168233106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2168233106
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3648869303
Short name T440
Test name
Test status
Simulation time 579078524 ps
CPU time 2.53 seconds
Started Jan 25 12:49:42 PM PST 24
Finished Jan 25 12:49:46 PM PST 24
Peak memory 213744 kb
Host smart-bbd5a6cc-a2f2-4cb2-a1b8-7b63fd5c7c0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648869303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3648869303
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3451685651
Short name T445
Test name
Test status
Simulation time 973233389 ps
CPU time 7.5 seconds
Started Jan 25 12:49:45 PM PST 24
Finished Jan 25 12:49:54 PM PST 24
Peak memory 213716 kb
Host smart-3b0ff3e8-4795-4e03-b8cb-91ba8667386e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451685651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3451685651
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3579993581
Short name T464
Test name
Test status
Simulation time 352638529 ps
CPU time 3.27 seconds
Started Jan 25 12:49:40 PM PST 24
Finished Jan 25 12:49:45 PM PST 24
Peak memory 213556 kb
Host smart-e899a5f3-b719-409e-b91c-9349eb75b628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579993581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3579993581
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4256605092
Short name T469
Test name
Test status
Simulation time 250124726 ps
CPU time 1.12 seconds
Started Jan 25 12:50:02 PM PST 24
Finished Jan 25 12:50:06 PM PST 24
Peak memory 213528 kb
Host smart-cde22a6c-3c4b-4847-9d05-09b0dfb192e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256605092 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.4256605092
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1408505490
Short name T495
Test name
Test status
Simulation time 16669721 ps
CPU time 0.99 seconds
Started Jan 25 12:50:00 PM PST 24
Finished Jan 25 12:50:04 PM PST 24
Peak memory 205100 kb
Host smart-a1332573-be46-4d40-b372-5876a7e859cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408505490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1408505490
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1483177393
Short name T488
Test name
Test status
Simulation time 42977868 ps
CPU time 0.85 seconds
Started Jan 25 12:50:06 PM PST 24
Finished Jan 25 12:50:09 PM PST 24
Peak memory 205340 kb
Host smart-9cde194a-30c2-4505-a504-65833cae73c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483177393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1483177393
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.255040119
Short name T517
Test name
Test status
Simulation time 66993728 ps
CPU time 2.39 seconds
Started Jan 25 12:50:03 PM PST 24
Finished Jan 25 12:50:08 PM PST 24
Peak memory 205280 kb
Host smart-030c82fd-31ae-4639-9c99-8d89708aacd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255040119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.255040119
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2972662034
Short name T484
Test name
Test status
Simulation time 387255526 ps
CPU time 3.86 seconds
Started Jan 25 12:49:41 PM PST 24
Finished Jan 25 12:49:47 PM PST 24
Peak memory 213764 kb
Host smart-5fbe478c-c285-45ab-b1e3-fdd0caaf5031
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972662034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2972662034
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1870888493
Short name T116
Test name
Test status
Simulation time 135475874 ps
CPU time 2.62 seconds
Started Jan 25 12:50:03 PM PST 24
Finished Jan 25 12:50:08 PM PST 24
Peak memory 213524 kb
Host smart-caaa1b2a-81cd-44bc-9113-c23a7afa198e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870888493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1870888493
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.300647893
Short name T406
Test name
Test status
Simulation time 33009597 ps
CPU time 2.38 seconds
Started Jan 25 12:50:07 PM PST 24
Finished Jan 25 12:50:12 PM PST 24
Peak memory 213756 kb
Host smart-28bf28de-f2e5-4b66-9e20-d137d4ebf6f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300647893 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.300647893
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2838353120
Short name T125
Test name
Test status
Simulation time 34979916 ps
CPU time 1.15 seconds
Started Jan 25 12:50:04 PM PST 24
Finished Jan 25 12:50:08 PM PST 24
Peak memory 205036 kb
Host smart-2bb9aa91-42f0-498d-9caa-31e11a750f44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838353120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2838353120
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3833359521
Short name T489
Test name
Test status
Simulation time 8089754 ps
CPU time 0.67 seconds
Started Jan 25 12:50:09 PM PST 24
Finished Jan 25 12:50:14 PM PST 24
Peak memory 205104 kb
Host smart-3d2338f3-d026-4d44-868b-3148d8c72774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833359521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3833359521
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.744715309
Short name T496
Test name
Test status
Simulation time 435080445 ps
CPU time 2.12 seconds
Started Jan 25 12:50:08 PM PST 24
Finished Jan 25 12:50:14 PM PST 24
Peak memory 205240 kb
Host smart-2aee1d34-ca35-46c3-b11a-fa5a5b4a0b4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744715309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.744715309
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2518580143
Short name T448
Test name
Test status
Simulation time 297861096 ps
CPU time 4.4 seconds
Started Jan 25 12:50:13 PM PST 24
Finished Jan 25 12:50:21 PM PST 24
Peak memory 213744 kb
Host smart-698d8d33-5f0b-4abf-b418-730ecd5ee8f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518580143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2518580143
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1168097991
Short name T498
Test name
Test status
Simulation time 1185360541 ps
CPU time 8.17 seconds
Started Jan 25 12:50:13 PM PST 24
Finished Jan 25 12:50:25 PM PST 24
Peak memory 213808 kb
Host smart-a22a2709-642e-40da-8d73-0c4bc5f651c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168097991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1168097991
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1406139755
Short name T443
Test name
Test status
Simulation time 124541619 ps
CPU time 3.98 seconds
Started Jan 25 12:50:05 PM PST 24
Finished Jan 25 12:50:11 PM PST 24
Peak memory 216956 kb
Host smart-2b07c0f6-4f74-4488-b075-59334d00d55d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406139755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1406139755
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3852384504
Short name T418
Test name
Test status
Simulation time 60778009 ps
CPU time 1.68 seconds
Started Jan 25 12:50:04 PM PST 24
Finished Jan 25 12:50:08 PM PST 24
Peak memory 213548 kb
Host smart-310b321c-3143-4d5e-a5c4-b2cc10ca03e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852384504 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3852384504
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.914838226
Short name T130
Test name
Test status
Simulation time 14308553 ps
CPU time 0.75 seconds
Started Jan 25 12:50:15 PM PST 24
Finished Jan 25 12:50:21 PM PST 24
Peak memory 205152 kb
Host smart-8b190774-46ae-4913-a303-15e015caa07f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914838226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.914838226
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.4021867141
Short name T107
Test name
Test status
Simulation time 465694820 ps
CPU time 4.69 seconds
Started Jan 25 12:50:07 PM PST 24
Finished Jan 25 12:50:14 PM PST 24
Peak memory 213652 kb
Host smart-2fc43795-8021-4599-afa8-d8239dc0a748
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021867141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.4021867141
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.127741231
Short name T129
Test name
Test status
Simulation time 142140326 ps
CPU time 3.34 seconds
Started Jan 25 12:50:04 PM PST 24
Finished Jan 25 12:50:10 PM PST 24
Peak memory 213452 kb
Host smart-5bac97e5-5a21-4b66-9938-a4fc8458ff83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127741231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.127741231
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3538456665
Short name T442
Test name
Test status
Simulation time 133352109 ps
CPU time 7.78 seconds
Started Jan 25 12:48:28 PM PST 24
Finished Jan 25 12:48:37 PM PST 24
Peak memory 205132 kb
Host smart-05b34732-7cf3-439d-9fad-a2b3de28664d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538456665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
538456665
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3479704166
Short name T429
Test name
Test status
Simulation time 38916935 ps
CPU time 1.45 seconds
Started Jan 25 12:48:36 PM PST 24
Finished Jan 25 12:48:40 PM PST 24
Peak memory 205220 kb
Host smart-13392b23-93b6-4d72-a203-8c39d3f00307
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479704166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
479704166
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.896720589
Short name T436
Test name
Test status
Simulation time 54587952 ps
CPU time 0.98 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:48:45 PM PST 24
Peak memory 205224 kb
Host smart-efe4bb95-b424-4fd8-9732-0a92a402be7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896720589 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.896720589
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.336851546
Short name T407
Test name
Test status
Simulation time 27323961 ps
CPU time 1.08 seconds
Started Jan 25 12:48:35 PM PST 24
Finished Jan 25 12:48:39 PM PST 24
Peak memory 205216 kb
Host smart-6ddfba26-da8d-4357-81a5-cb22a15f8a25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336851546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.336851546
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2696120532
Short name T539
Test name
Test status
Simulation time 1670576892 ps
CPU time 6.22 seconds
Started Jan 25 12:48:34 PM PST 24
Finished Jan 25 12:48:44 PM PST 24
Peak memory 213656 kb
Host smart-b23b75f0-414a-47a0-a169-2192e83ae941
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696120532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2696120532
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.881423399
Short name T542
Test name
Test status
Simulation time 197631284 ps
CPU time 5.47 seconds
Started Jan 25 12:48:35 PM PST 24
Finished Jan 25 12:48:44 PM PST 24
Peak memory 213720 kb
Host smart-39e405d1-94ec-40e0-a0c5-55c00d7848d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881423399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.881423399
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3515557388
Short name T439
Test name
Test status
Simulation time 203046568 ps
CPU time 1.48 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:48:45 PM PST 24
Peak memory 213520 kb
Host smart-d9a5a3ef-c28a-4fe3-ae29-45949c82546b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515557388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3515557388
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1240846328
Short name T509
Test name
Test status
Simulation time 35072759 ps
CPU time 0.7 seconds
Started Jan 25 12:50:08 PM PST 24
Finished Jan 25 12:50:13 PM PST 24
Peak memory 205040 kb
Host smart-d63326e6-ca37-46a5-9ef9-a16fc60481c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240846328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1240846328
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2229870468
Short name T411
Test name
Test status
Simulation time 25878163 ps
CPU time 0.77 seconds
Started Jan 25 12:50:07 PM PST 24
Finished Jan 25 12:50:11 PM PST 24
Peak memory 205064 kb
Host smart-69fe14c9-e413-474d-80f5-15aae7636eac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229870468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2229870468
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2272003844
Short name T460
Test name
Test status
Simulation time 12732403 ps
CPU time 0.83 seconds
Started Jan 25 12:50:09 PM PST 24
Finished Jan 25 12:50:14 PM PST 24
Peak memory 205032 kb
Host smart-7ef6ad7c-9189-4c66-b107-6a460ff1b39d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272003844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2272003844
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2416483668
Short name T502
Test name
Test status
Simulation time 70990402 ps
CPU time 0.74 seconds
Started Jan 25 12:50:05 PM PST 24
Finished Jan 25 12:50:08 PM PST 24
Peak memory 205252 kb
Host smart-a69cd652-12d9-4b8a-9035-b0bc24a42618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416483668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2416483668
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3368904870
Short name T528
Test name
Test status
Simulation time 11149650 ps
CPU time 0.89 seconds
Started Jan 25 12:50:10 PM PST 24
Finished Jan 25 12:50:16 PM PST 24
Peak memory 205036 kb
Host smart-ea2b9294-cbff-4924-a94e-bf1793a14124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368904870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3368904870
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2275174584
Short name T403
Test name
Test status
Simulation time 12479307 ps
CPU time 0.85 seconds
Started Jan 25 12:50:13 PM PST 24
Finished Jan 25 12:50:18 PM PST 24
Peak memory 205016 kb
Host smart-ae4d2217-5aa1-4f20-8f62-69f15d87405c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275174584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2275174584
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3168336715
Short name T405
Test name
Test status
Simulation time 32251634 ps
CPU time 0.75 seconds
Started Jan 25 12:50:09 PM PST 24
Finished Jan 25 12:50:15 PM PST 24
Peak memory 205004 kb
Host smart-61f25fb2-503d-4461-b30d-7cd3b82016d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168336715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3168336715
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.56908313
Short name T446
Test name
Test status
Simulation time 22621112 ps
CPU time 0.84 seconds
Started Jan 25 12:50:09 PM PST 24
Finished Jan 25 12:50:14 PM PST 24
Peak memory 204948 kb
Host smart-df01cda7-c9f2-483e-a23f-a269277defa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56908313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.56908313
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3250021873
Short name T513
Test name
Test status
Simulation time 7796111 ps
CPU time 0.69 seconds
Started Jan 25 12:50:09 PM PST 24
Finished Jan 25 12:50:14 PM PST 24
Peak memory 205080 kb
Host smart-d8fd1a44-b426-4a38-9ec0-7567bae10448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250021873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3250021873
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.59460706
Short name T126
Test name
Test status
Simulation time 57100095 ps
CPU time 0.88 seconds
Started Jan 25 12:50:14 PM PST 24
Finished Jan 25 12:50:19 PM PST 24
Peak memory 205184 kb
Host smart-07cd6e6e-31a5-4f70-9093-3adcaee4f24f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59460706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.59460706
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2229138634
Short name T467
Test name
Test status
Simulation time 368943967 ps
CPU time 8.89 seconds
Started Jan 25 12:48:39 PM PST 24
Finished Jan 25 12:48:53 PM PST 24
Peak memory 205144 kb
Host smart-fd6bdc0c-a9d7-49dc-840e-94d98ef72b14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229138634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
229138634
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2930351865
Short name T526
Test name
Test status
Simulation time 28797422 ps
CPU time 0.91 seconds
Started Jan 25 12:48:28 PM PST 24
Finished Jan 25 12:48:31 PM PST 24
Peak memory 205112 kb
Host smart-661b15e0-7fc0-44b8-9c22-5c2fffb57689
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930351865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
930351865
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4207088485
Short name T451
Test name
Test status
Simulation time 114552796 ps
CPU time 2.59 seconds
Started Jan 25 12:48:33 PM PST 24
Finished Jan 25 12:48:39 PM PST 24
Peak memory 213604 kb
Host smart-a0daf9c4-cb91-45b2-8e89-2d57cf869278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207088485 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.4207088485
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3552101371
Short name T128
Test name
Test status
Simulation time 10860150 ps
CPU time 0.94 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:48:44 PM PST 24
Peak memory 205104 kb
Host smart-a8ac753d-4bbb-42f8-b0c4-2e8266e477d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552101371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3552101371
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.305944442
Short name T505
Test name
Test status
Simulation time 55277769 ps
CPU time 0.78 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:48:43 PM PST 24
Peak memory 205056 kb
Host smart-21eba904-3209-4236-b3f6-7a64ea25a769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305944442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.305944442
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3389127187
Short name T466
Test name
Test status
Simulation time 72925859 ps
CPU time 1.4 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:48:45 PM PST 24
Peak memory 205212 kb
Host smart-84182d5a-8054-40ec-b256-c497f7b14a39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389127187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3389127187
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3921407313
Short name T111
Test name
Test status
Simulation time 301027886 ps
CPU time 2.6 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:48:46 PM PST 24
Peak memory 213752 kb
Host smart-3d361467-d4c7-45be-a4c8-6b2517996d44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921407313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3921407313
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2320700367
Short name T427
Test name
Test status
Simulation time 192722113 ps
CPU time 4.35 seconds
Started Jan 25 12:48:36 PM PST 24
Finished Jan 25 12:48:45 PM PST 24
Peak memory 213676 kb
Host smart-29b9e605-5845-46d5-9234-26c1b8ba9d87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320700367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2320700367
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3204858962
Short name T404
Test name
Test status
Simulation time 83789007 ps
CPU time 1.31 seconds
Started Jan 25 12:48:36 PM PST 24
Finished Jan 25 12:48:41 PM PST 24
Peak memory 205376 kb
Host smart-0a105ed9-8f13-47f0-845b-cdd4e3b3dcc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204858962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3204858962
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1310885504
Short name T529
Test name
Test status
Simulation time 15631102244 ps
CPU time 35.57 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:49:19 PM PST 24
Peak memory 213624 kb
Host smart-4f735d67-0e42-4771-904a-4fea6a956ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310885504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1310885504
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1130149537
Short name T511
Test name
Test status
Simulation time 12116006 ps
CPU time 0.74 seconds
Started Jan 25 12:50:12 PM PST 24
Finished Jan 25 12:50:18 PM PST 24
Peak memory 205000 kb
Host smart-8c60361b-f97d-4925-9860-a49ec74e43e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130149537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1130149537
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3900703125
Short name T512
Test name
Test status
Simulation time 9755352 ps
CPU time 0.73 seconds
Started Jan 25 12:50:06 PM PST 24
Finished Jan 25 12:50:09 PM PST 24
Peak memory 205332 kb
Host smart-d3b6d648-96a2-4bb6-be61-acfda5109ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900703125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3900703125
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1346476972
Short name T482
Test name
Test status
Simulation time 28228824 ps
CPU time 0.71 seconds
Started Jan 25 12:50:14 PM PST 24
Finished Jan 25 12:50:19 PM PST 24
Peak memory 205016 kb
Host smart-fce9374d-58f9-4233-8505-a7faaa098ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346476972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1346476972
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.364375533
Short name T475
Test name
Test status
Simulation time 41903650 ps
CPU time 0.82 seconds
Started Jan 25 12:50:08 PM PST 24
Finished Jan 25 12:50:13 PM PST 24
Peak memory 205048 kb
Host smart-f5a002a4-63e0-4c26-989b-795174c67cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364375533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.364375533
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2406551425
Short name T515
Test name
Test status
Simulation time 31459769 ps
CPU time 0.81 seconds
Started Jan 25 12:50:12 PM PST 24
Finished Jan 25 12:50:18 PM PST 24
Peak memory 205000 kb
Host smart-a5354f96-c8d0-4918-9eda-65a861fa173c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406551425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2406551425
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2643428052
Short name T431
Test name
Test status
Simulation time 39792700 ps
CPU time 0.83 seconds
Started Jan 25 12:50:13 PM PST 24
Finished Jan 25 12:50:18 PM PST 24
Peak memory 205080 kb
Host smart-2ecd395c-fa0a-4731-bbe4-b18e19d808e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643428052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2643428052
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1524389764
Short name T457
Test name
Test status
Simulation time 34002530 ps
CPU time 0.83 seconds
Started Jan 25 12:50:10 PM PST 24
Finished Jan 25 12:50:16 PM PST 24
Peak memory 205076 kb
Host smart-db6bce3d-ebfc-4851-b701-f68d65088490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524389764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1524389764
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3250379804
Short name T492
Test name
Test status
Simulation time 8052729 ps
CPU time 0.85 seconds
Started Jan 25 12:50:15 PM PST 24
Finished Jan 25 12:50:22 PM PST 24
Peak memory 205076 kb
Host smart-4e5f47fe-6c18-4470-a6c2-c28a2edbe1cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250379804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3250379804
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.516369669
Short name T501
Test name
Test status
Simulation time 59677665 ps
CPU time 0.82 seconds
Started Jan 25 12:50:14 PM PST 24
Finished Jan 25 12:50:19 PM PST 24
Peak memory 205096 kb
Host smart-92f45596-754d-4ddf-a5eb-845f159db53a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516369669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.516369669
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.615321003
Short name T538
Test name
Test status
Simulation time 73733190 ps
CPU time 0.76 seconds
Started Jan 25 12:50:13 PM PST 24
Finished Jan 25 12:50:18 PM PST 24
Peak memory 205092 kb
Host smart-1790bbd3-f3bf-4582-99eb-1ba012a5c74e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615321003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.615321003
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3892741858
Short name T522
Test name
Test status
Simulation time 798593261 ps
CPU time 4.4 seconds
Started Jan 25 12:48:31 PM PST 24
Finished Jan 25 12:48:38 PM PST 24
Peak memory 205192 kb
Host smart-b8f3fb93-0699-4f28-900b-b486f7a3576e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892741858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
892741858
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2870351299
Short name T414
Test name
Test status
Simulation time 260658393 ps
CPU time 7.29 seconds
Started Jan 25 12:48:31 PM PST 24
Finished Jan 25 12:48:41 PM PST 24
Peak memory 205192 kb
Host smart-6664e7e3-b4d1-466b-b5e8-75863e993c19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870351299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
870351299
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2401780563
Short name T454
Test name
Test status
Simulation time 28433635 ps
CPU time 1.16 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:48:44 PM PST 24
Peak memory 205144 kb
Host smart-2d1a8434-a738-47e3-b718-1e7b276146c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401780563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
401780563
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3417527468
Short name T447
Test name
Test status
Simulation time 52004416 ps
CPU time 1.28 seconds
Started Jan 25 12:49:01 PM PST 24
Finished Jan 25 12:49:05 PM PST 24
Peak memory 205412 kb
Host smart-3223edc0-63da-462c-bf2f-a9056b10349a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417527468 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3417527468
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1466632639
Short name T540
Test name
Test status
Simulation time 30613006 ps
CPU time 1.02 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:48:44 PM PST 24
Peak memory 205140 kb
Host smart-a959e5b6-21bf-4f17-9270-da09750957b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466632639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1466632639
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1600484404
Short name T521
Test name
Test status
Simulation time 28448268 ps
CPU time 0.7 seconds
Started Jan 25 12:48:37 PM PST 24
Finished Jan 25 12:48:43 PM PST 24
Peak memory 205064 kb
Host smart-470143f4-e30b-418a-95d5-2ed53ead69e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600484404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1600484404
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3183321802
Short name T416
Test name
Test status
Simulation time 335659733 ps
CPU time 5.92 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:48:50 PM PST 24
Peak memory 213804 kb
Host smart-8e4b7a62-cf78-4da6-a504-d11b8e798c1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183321802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3183321802
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.933597464
Short name T479
Test name
Test status
Simulation time 803755826 ps
CPU time 13.82 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:48:56 PM PST 24
Peak memory 221768 kb
Host smart-a48469db-4336-48a2-88e2-f86b134e84df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933597464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.933597464
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1846655766
Short name T487
Test name
Test status
Simulation time 888574730 ps
CPU time 2.97 seconds
Started Jan 25 12:48:38 PM PST 24
Finished Jan 25 12:48:46 PM PST 24
Peak memory 213552 kb
Host smart-7a9bab2c-1d73-4398-bee2-ce64f1439184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846655766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1846655766
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1261106592
Short name T417
Test name
Test status
Simulation time 13857398 ps
CPU time 0.9 seconds
Started Jan 25 12:50:10 PM PST 24
Finished Jan 25 12:50:16 PM PST 24
Peak memory 205140 kb
Host smart-264eab5e-c5d4-47a6-8214-077780c5bee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261106592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1261106592
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3207983265
Short name T409
Test name
Test status
Simulation time 28895985 ps
CPU time 1.16 seconds
Started Jan 25 12:50:14 PM PST 24
Finished Jan 25 12:50:20 PM PST 24
Peak memory 205120 kb
Host smart-e7781bce-93a2-4855-be07-af68b2720577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207983265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3207983265
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.133451387
Short name T503
Test name
Test status
Simulation time 24920188 ps
CPU time 0.71 seconds
Started Jan 25 12:50:10 PM PST 24
Finished Jan 25 12:50:16 PM PST 24
Peak memory 205076 kb
Host smart-543bdb7d-2553-4257-827a-d59d2d07e928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133451387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.133451387
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2397244514
Short name T536
Test name
Test status
Simulation time 36447627 ps
CPU time 0.8 seconds
Started Jan 25 12:50:16 PM PST 24
Finished Jan 25 12:50:22 PM PST 24
Peak memory 205152 kb
Host smart-0610a73c-1f7c-4b78-9413-66f9df224970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397244514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2397244514
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.305889692
Short name T430
Test name
Test status
Simulation time 12515859 ps
CPU time 0.71 seconds
Started Jan 25 12:50:14 PM PST 24
Finished Jan 25 12:50:20 PM PST 24
Peak memory 205072 kb
Host smart-b2797b18-0f20-4608-a211-f39274f6542f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305889692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.305889692
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3338709708
Short name T402
Test name
Test status
Simulation time 10270853 ps
CPU time 0.71 seconds
Started Jan 25 12:50:13 PM PST 24
Finished Jan 25 12:50:18 PM PST 24
Peak memory 205124 kb
Host smart-ddb493ac-808a-413f-b301-8ad808678c08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338709708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3338709708
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2596061503
Short name T168
Test name
Test status
Simulation time 225762143 ps
CPU time 0.82 seconds
Started Jan 25 12:50:08 PM PST 24
Finished Jan 25 12:50:13 PM PST 24
Peak memory 205260 kb
Host smart-90dd4b77-ce44-4162-a7d3-997ceae8063d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596061503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2596061503
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1090717278
Short name T476
Test name
Test status
Simulation time 12192976 ps
CPU time 0.68 seconds
Started Jan 25 12:50:14 PM PST 24
Finished Jan 25 12:50:19 PM PST 24
Peak memory 205052 kb
Host smart-e81834f9-0982-46b9-88a0-4058c948b7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090717278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1090717278
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3831729421
Short name T525
Test name
Test status
Simulation time 17053913 ps
CPU time 0.68 seconds
Started Jan 25 12:50:13 PM PST 24
Finished Jan 25 12:50:18 PM PST 24
Peak memory 205128 kb
Host smart-4c616617-85bf-4363-8ff7-a53a3b76ba56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831729421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3831729421
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2407800954
Short name T433
Test name
Test status
Simulation time 12753707 ps
CPU time 0.87 seconds
Started Jan 25 12:50:24 PM PST 24
Finished Jan 25 12:50:27 PM PST 24
Peak memory 205136 kb
Host smart-5a2bd55b-5869-43ba-841f-1c5162dde8f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407800954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2407800954
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2477455621
Short name T463
Test name
Test status
Simulation time 115661107 ps
CPU time 1.37 seconds
Started Jan 25 12:49:00 PM PST 24
Finished Jan 25 12:49:04 PM PST 24
Peak memory 213528 kb
Host smart-759f7796-61ac-46b9-935f-76985b5559ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477455621 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2477455621
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3471785406
Short name T470
Test name
Test status
Simulation time 247451926 ps
CPU time 1.27 seconds
Started Jan 25 12:49:01 PM PST 24
Finished Jan 25 12:49:06 PM PST 24
Peak memory 205292 kb
Host smart-ae9e59f8-51a2-4ade-8e93-d23b7ef442e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471785406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3471785406
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1619910216
Short name T412
Test name
Test status
Simulation time 17477701 ps
CPU time 0.76 seconds
Started Jan 25 12:49:01 PM PST 24
Finished Jan 25 12:49:04 PM PST 24
Peak memory 205136 kb
Host smart-a88425d7-48d5-466b-aff9-16d12b0df57c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619910216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1619910216
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4201483334
Short name T424
Test name
Test status
Simulation time 191373743 ps
CPU time 2.12 seconds
Started Jan 25 12:48:49 PM PST 24
Finished Jan 25 12:48:53 PM PST 24
Peak memory 205164 kb
Host smart-58cc0245-8dca-4e15-8bf5-f3e778d5ac84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201483334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4201483334
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1364613047
Short name T422
Test name
Test status
Simulation time 720341058 ps
CPU time 17.32 seconds
Started Jan 25 12:48:50 PM PST 24
Finished Jan 25 12:49:09 PM PST 24
Peak memory 215744 kb
Host smart-4363b9a5-ebf2-4a0a-b983-7b8e12ab8074
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364613047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1364613047
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.876730879
Short name T455
Test name
Test status
Simulation time 215402197 ps
CPU time 8.23 seconds
Started Jan 25 12:48:51 PM PST 24
Finished Jan 25 12:49:01 PM PST 24
Peak memory 219812 kb
Host smart-09ad9f4b-9464-4006-bbe3-25650719cd9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876730879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.876730879
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3301780299
Short name T537
Test name
Test status
Simulation time 152251503 ps
CPU time 2.33 seconds
Started Jan 25 12:49:01 PM PST 24
Finished Jan 25 12:49:07 PM PST 24
Peak memory 213632 kb
Host smart-401e97de-2829-4b56-96c6-c7f05bf0dbff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301780299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3301780299
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2944869153
Short name T481
Test name
Test status
Simulation time 15763497 ps
CPU time 1.27 seconds
Started Jan 25 12:49:00 PM PST 24
Finished Jan 25 12:49:04 PM PST 24
Peak memory 213556 kb
Host smart-eb1f8c64-59f7-4be1-829d-37a9fd4f9668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944869153 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2944869153
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1654867920
Short name T147
Test name
Test status
Simulation time 115411611 ps
CPU time 1.13 seconds
Started Jan 25 12:48:51 PM PST 24
Finished Jan 25 12:48:54 PM PST 24
Peak memory 205200 kb
Host smart-a85bdd6b-328b-4153-8a6f-3b90081186e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654867920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1654867920
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1052677084
Short name T504
Test name
Test status
Simulation time 13690536 ps
CPU time 0.89 seconds
Started Jan 25 12:49:00 PM PST 24
Finished Jan 25 12:49:04 PM PST 24
Peak memory 205228 kb
Host smart-c217a68c-5d57-4508-858b-48f651b691b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052677084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1052677084
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2890414527
Short name T508
Test name
Test status
Simulation time 119630885 ps
CPU time 1.83 seconds
Started Jan 25 12:49:01 PM PST 24
Finished Jan 25 12:49:05 PM PST 24
Peak memory 205304 kb
Host smart-7574e912-9810-4459-af39-5623de35aff8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890414527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2890414527
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1227025549
Short name T531
Test name
Test status
Simulation time 188504670 ps
CPU time 5.23 seconds
Started Jan 25 12:48:54 PM PST 24
Finished Jan 25 12:49:00 PM PST 24
Peak memory 218612 kb
Host smart-424fc4f2-d9de-4c22-bec6-72da9a7cf47c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227025549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1227025549
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2831112969
Short name T441
Test name
Test status
Simulation time 1360940374 ps
CPU time 8.35 seconds
Started Jan 25 12:48:57 PM PST 24
Finished Jan 25 12:49:07 PM PST 24
Peak memory 219876 kb
Host smart-c585bfd6-797a-4082-b9f1-36a9e20fe870
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831112969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2831112969
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1798491021
Short name T523
Test name
Test status
Simulation time 228420378 ps
CPU time 2.98 seconds
Started Jan 25 12:48:54 PM PST 24
Finished Jan 25 12:48:58 PM PST 24
Peak memory 213500 kb
Host smart-48e453b0-b4c4-40ac-8610-4c3df778b825
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798491021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1798491021
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.182284620
Short name T361
Test name
Test status
Simulation time 388329249 ps
CPU time 4.03 seconds
Started Jan 25 12:48:54 PM PST 24
Finished Jan 25 12:48:59 PM PST 24
Peak memory 213544 kb
Host smart-3635562c-3abd-44cb-a664-a20f6b458652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182284620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
182284620
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4280150431
Short name T510
Test name
Test status
Simulation time 18760535 ps
CPU time 1.36 seconds
Started Jan 25 12:48:55 PM PST 24
Finished Jan 25 12:48:58 PM PST 24
Peak memory 213548 kb
Host smart-69244158-5a6a-412a-bf3c-034fcca132e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280150431 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.4280150431
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.4084288601
Short name T473
Test name
Test status
Simulation time 14742780 ps
CPU time 1.13 seconds
Started Jan 25 12:48:56 PM PST 24
Finished Jan 25 12:48:58 PM PST 24
Peak memory 205116 kb
Host smart-76fcae68-0b2d-4502-b8d1-a4c978377e80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084288601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.4084288601
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.23653712
Short name T426
Test name
Test status
Simulation time 11419179 ps
CPU time 0.77 seconds
Started Jan 25 03:24:17 PM PST 24
Finished Jan 25 03:24:47 PM PST 24
Peak memory 205216 kb
Host smart-632feb4b-0f5c-4824-918a-1c4ff79d0ed4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23653712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.23653712
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3821071120
Short name T413
Test name
Test status
Simulation time 1179988884 ps
CPU time 6.33 seconds
Started Jan 25 12:48:59 PM PST 24
Finished Jan 25 12:49:06 PM PST 24
Peak memory 213644 kb
Host smart-d96bd6de-1a43-4390-adf1-9a075db36e59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821071120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3821071120
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2710904368
Short name T478
Test name
Test status
Simulation time 1746138085 ps
CPU time 11.35 seconds
Started Jan 25 12:57:22 PM PST 24
Finished Jan 25 12:57:41 PM PST 24
Peak memory 213988 kb
Host smart-a971a62e-9795-4559-bc46-32ac2004c9af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710904368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2710904368
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2889245764
Short name T415
Test name
Test status
Simulation time 126976366 ps
CPU time 4.41 seconds
Started Jan 25 01:29:32 PM PST 24
Finished Jan 25 01:29:37 PM PST 24
Peak memory 213452 kb
Host smart-194e8387-152c-4c0c-b461-7a23a11ed670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889245764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2889245764
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1276212614
Short name T157
Test name
Test status
Simulation time 702285663 ps
CPU time 7.65 seconds
Started Jan 25 12:48:59 PM PST 24
Finished Jan 25 12:49:09 PM PST 24
Peak memory 213396 kb
Host smart-0844171d-240d-4e63-86cc-a1793a82fd7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276212614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1276212614
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2386651461
Short name T499
Test name
Test status
Simulation time 23232591 ps
CPU time 1.79 seconds
Started Jan 25 12:49:06 PM PST 24
Finished Jan 25 12:49:09 PM PST 24
Peak memory 213560 kb
Host smart-8a5408bc-1c42-4153-928d-cdb174a2b679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386651461 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2386651461
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2065289284
Short name T483
Test name
Test status
Simulation time 51740143 ps
CPU time 1.32 seconds
Started Jan 25 12:49:06 PM PST 24
Finished Jan 25 12:49:09 PM PST 24
Peak memory 204952 kb
Host smart-47af40fb-adbc-47af-81b1-c2bbdb50ba19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065289284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2065289284
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.590014265
Short name T461
Test name
Test status
Simulation time 36409494 ps
CPU time 0.83 seconds
Started Jan 25 01:27:43 PM PST 24
Finished Jan 25 01:27:52 PM PST 24
Peak memory 205084 kb
Host smart-d79f2fb0-85f7-408d-9a2d-4ef14313fc43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590014265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.590014265
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2146972427
Short name T428
Test name
Test status
Simulation time 47389827 ps
CPU time 1.47 seconds
Started Jan 25 12:49:06 PM PST 24
Finished Jan 25 12:49:09 PM PST 24
Peak memory 205304 kb
Host smart-4540e638-aa64-4f97-b462-f06aea4bea1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146972427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2146972427
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2782198554
Short name T165
Test name
Test status
Simulation time 167970155 ps
CPU time 2.95 seconds
Started Jan 25 12:49:06 PM PST 24
Finished Jan 25 12:49:11 PM PST 24
Peak memory 213580 kb
Host smart-375df9e6-1fd1-4a26-9445-139a897044b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782198554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2782198554
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4053467122
Short name T456
Test name
Test status
Simulation time 1536947015 ps
CPU time 10.17 seconds
Started Jan 25 01:32:47 PM PST 24
Finished Jan 25 01:32:59 PM PST 24
Peak memory 219876 kb
Host smart-2d6a7f6b-65a6-43f2-9602-de7db4a5d6c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053467122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4053467122
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3318614992
Short name T421
Test name
Test status
Simulation time 36902223 ps
CPU time 2.4 seconds
Started Jan 25 12:48:56 PM PST 24
Finished Jan 25 12:49:00 PM PST 24
Peak memory 213576 kb
Host smart-257c77b8-da9b-4531-be22-dddd6464e761
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318614992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3318614992
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3796751354
Short name T453
Test name
Test status
Simulation time 68097958 ps
CPU time 1.47 seconds
Started Jan 25 12:49:11 PM PST 24
Finished Jan 25 12:49:14 PM PST 24
Peak memory 205228 kb
Host smart-2bdbcdac-26ff-4d41-b5e6-bc542ea68c6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796751354 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3796751354
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2867838146
Short name T134
Test name
Test status
Simulation time 19515434 ps
CPU time 1.11 seconds
Started Jan 25 12:49:06 PM PST 24
Finished Jan 25 12:49:09 PM PST 24
Peak memory 205236 kb
Host smart-84f3c23e-f321-44eb-b77c-0f6061dc303c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867838146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2867838146
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1052091835
Short name T480
Test name
Test status
Simulation time 8920339 ps
CPU time 0.8 seconds
Started Jan 25 02:31:35 PM PST 24
Finished Jan 25 02:31:57 PM PST 24
Peak memory 205020 kb
Host smart-892c2404-97e3-4343-b7cf-575acedd0e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052091835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1052091835
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.339211689
Short name T507
Test name
Test status
Simulation time 48412857 ps
CPU time 1.73 seconds
Started Jan 25 12:49:15 PM PST 24
Finished Jan 25 12:49:19 PM PST 24
Peak memory 205240 kb
Host smart-acf45be8-3742-4ab2-9f37-2eeabdfccf8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339211689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.339211689
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.753817209
Short name T532
Test name
Test status
Simulation time 349511721 ps
CPU time 3.02 seconds
Started Jan 25 12:49:06 PM PST 24
Finished Jan 25 12:49:11 PM PST 24
Peak memory 213768 kb
Host smart-5bd758ae-6ac4-4595-862e-88136fe220cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753817209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.753817209
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3807363987
Short name T127
Test name
Test status
Simulation time 581056465 ps
CPU time 3.81 seconds
Started Jan 25 12:49:06 PM PST 24
Finished Jan 25 12:49:12 PM PST 24
Peak memory 213532 kb
Host smart-16a1c1b9-5324-4bc3-a032-12ce70cf568d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807363987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3807363987
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3416233401
Short name T949
Test name
Test status
Simulation time 20470793 ps
CPU time 0.7 seconds
Started Jan 25 02:44:57 PM PST 24
Finished Jan 25 02:45:35 PM PST 24
Peak memory 205880 kb
Host smart-6f4e38a0-16f8-4fa2-91b1-6e624273ae67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416233401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3416233401
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.440694549
Short name T331
Test name
Test status
Simulation time 70693282 ps
CPU time 3.08 seconds
Started Jan 25 02:44:57 PM PST 24
Finished Jan 25 02:45:38 PM PST 24
Peak memory 213892 kb
Host smart-0a1b2e3e-949e-4a50-ac14-1fcae93f62bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440694549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.440694549
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1554379059
Short name T686
Test name
Test status
Simulation time 130822377 ps
CPU time 5.43 seconds
Started Jan 25 02:44:58 PM PST 24
Finished Jan 25 02:45:41 PM PST 24
Peak memory 218232 kb
Host smart-501e05f1-0cc1-41f4-af62-7bfead36b816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554379059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1554379059
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.983684437
Short name T930
Test name
Test status
Simulation time 3243726390 ps
CPU time 31.89 seconds
Started Jan 25 02:44:57 PM PST 24
Finished Jan 25 02:46:07 PM PST 24
Peak memory 208992 kb
Host smart-27009c42-62a1-46b5-9972-35f9c8da3bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983684437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.983684437
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2800948096
Short name T343
Test name
Test status
Simulation time 10153302087 ps
CPU time 68.33 seconds
Started Jan 25 02:44:57 PM PST 24
Finished Jan 25 02:46:43 PM PST 24
Peak memory 222232 kb
Host smart-a3e9c55f-1344-419b-95f2-2b9df5e72c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800948096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2800948096
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1526576418
Short name T359
Test name
Test status
Simulation time 210121768 ps
CPU time 6.16 seconds
Started Jan 25 02:45:00 PM PST 24
Finished Jan 25 02:45:44 PM PST 24
Peak memory 214188 kb
Host smart-3aefcf86-669a-4952-ab93-928273bcfcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526576418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1526576418
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2837144917
Short name T1069
Test name
Test status
Simulation time 101562858 ps
CPU time 2.71 seconds
Started Jan 25 02:44:57 PM PST 24
Finished Jan 25 02:45:37 PM PST 24
Peak memory 214620 kb
Host smart-9ebca73b-e691-4d55-84b3-0e054a91154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837144917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2837144917
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.897414236
Short name T205
Test name
Test status
Simulation time 410320454 ps
CPU time 3.75 seconds
Started Jan 25 02:44:54 PM PST 24
Finished Jan 25 02:45:34 PM PST 24
Peak memory 222412 kb
Host smart-98c295db-eb1c-4067-9c2c-50e5312e5000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897414236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.897414236
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2797447055
Short name T43
Test name
Test status
Simulation time 5190334446 ps
CPU time 62.95 seconds
Started Jan 25 02:44:57 PM PST 24
Finished Jan 25 02:46:37 PM PST 24
Peak memory 248620 kb
Host smart-74acc1c1-51c4-40af-a1c5-d08f76300dc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797447055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2797447055
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3473868856
Short name T3
Test name
Test status
Simulation time 76664685 ps
CPU time 3.04 seconds
Started Jan 25 02:44:52 PM PST 24
Finished Jan 25 02:45:31 PM PST 24
Peak memory 208436 kb
Host smart-2cfbd9a4-ecb8-45ce-b01f-bf58a83d47c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473868856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3473868856
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2681049731
Short name T736
Test name
Test status
Simulation time 221538686 ps
CPU time 2.87 seconds
Started Jan 25 02:44:56 PM PST 24
Finished Jan 25 02:45:36 PM PST 24
Peak memory 208212 kb
Host smart-18054ba5-da83-4571-83a8-6acbceb77607
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681049731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2681049731
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.923217179
Short name T707
Test name
Test status
Simulation time 82132463 ps
CPU time 3.75 seconds
Started Jan 25 02:44:56 PM PST 24
Finished Jan 25 02:45:37 PM PST 24
Peak memory 208428 kb
Host smart-f7aac83b-2387-4004-9b2d-47b3cc6ba9e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923217179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.923217179
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2973240775
Short name T792
Test name
Test status
Simulation time 92632600 ps
CPU time 2.57 seconds
Started Jan 25 02:45:00 PM PST 24
Finished Jan 25 02:45:40 PM PST 24
Peak memory 206828 kb
Host smart-b9241e87-0869-4779-ba6b-43235baba0f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973240775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2973240775
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3320985862
Short name T754
Test name
Test status
Simulation time 79763632 ps
CPU time 2.77 seconds
Started Jan 25 02:44:56 PM PST 24
Finished Jan 25 02:45:36 PM PST 24
Peak memory 209696 kb
Host smart-7760bb1d-502a-4385-9fef-26428e9e7bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320985862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3320985862
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2880040746
Short name T376
Test name
Test status
Simulation time 348150478 ps
CPU time 4.74 seconds
Started Jan 25 02:44:50 PM PST 24
Finished Jan 25 02:45:30 PM PST 24
Peak memory 208540 kb
Host smart-7cd0628e-3c73-436c-b2c9-83c5ac0efa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880040746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2880040746
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.668831822
Short name T189
Test name
Test status
Simulation time 6385047976 ps
CPU time 66.58 seconds
Started Jan 25 02:44:56 PM PST 24
Finished Jan 25 02:46:40 PM PST 24
Peak memory 222532 kb
Host smart-7536237e-5836-4680-980e-480babf30e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668831822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.668831822
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.4208684644
Short name T272
Test name
Test status
Simulation time 300705194 ps
CPU time 8.49 seconds
Started Jan 25 02:44:57 PM PST 24
Finished Jan 25 02:45:42 PM PST 24
Peak memory 222664 kb
Host smart-d315e948-e3c5-4265-bc2a-1f6557591ddc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208684644 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.4208684644
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.184927256
Short name T829
Test name
Test status
Simulation time 2803618491 ps
CPU time 8.9 seconds
Started Jan 25 02:44:59 PM PST 24
Finished Jan 25 02:45:45 PM PST 24
Peak memory 207252 kb
Host smart-6b406f68-8cb9-45be-9cec-71164989def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184927256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.184927256
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2032778821
Short name T377
Test name
Test status
Simulation time 336494237 ps
CPU time 3.69 seconds
Started Jan 25 02:45:19 PM PST 24
Finished Jan 25 02:45:56 PM PST 24
Peak memory 210380 kb
Host smart-3a0801e3-2ae7-4d1f-a146-0af1d3dd89cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032778821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2032778821
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1605703283
Short name T746
Test name
Test status
Simulation time 49931611 ps
CPU time 0.84 seconds
Started Jan 25 02:44:59 PM PST 24
Finished Jan 25 02:45:37 PM PST 24
Peak memory 205912 kb
Host smart-a701b01b-87f4-49b7-968a-ac55cdfb7af4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605703283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1605703283
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2467987755
Short name T851
Test name
Test status
Simulation time 74180394 ps
CPU time 3.85 seconds
Started Jan 25 02:44:59 PM PST 24
Finished Jan 25 02:45:41 PM PST 24
Peak memory 218272 kb
Host smart-68803caf-efef-4052-81b9-d7ce01ab5d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467987755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2467987755
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2031869821
Short name T900
Test name
Test status
Simulation time 57639110 ps
CPU time 1.78 seconds
Started Jan 25 02:44:59 PM PST 24
Finished Jan 25 02:45:39 PM PST 24
Peak memory 207832 kb
Host smart-c4c6c658-25a1-4e5a-ae80-08d10f918d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031869821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2031869821
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.415663843
Short name T266
Test name
Test status
Simulation time 181746635 ps
CPU time 4.3 seconds
Started Jan 25 02:44:58 PM PST 24
Finished Jan 25 02:45:40 PM PST 24
Peak memory 209668 kb
Host smart-96c093ea-a780-47eb-ab52-37fd315e614c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415663843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.415663843
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1917610571
Short name T727
Test name
Test status
Simulation time 431281895 ps
CPU time 4.65 seconds
Started Jan 25 02:44:58 PM PST 24
Finished Jan 25 02:45:40 PM PST 24
Peak memory 220288 kb
Host smart-df482712-6346-44c7-b63e-fed63ceae7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917610571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1917610571
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.734385796
Short name T253
Test name
Test status
Simulation time 230620941 ps
CPU time 6.51 seconds
Started Jan 25 02:44:58 PM PST 24
Finished Jan 25 02:45:42 PM PST 24
Peak memory 208980 kb
Host smart-716719eb-e8db-41af-972c-7cd75b1b0e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734385796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.734385796
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3190964862
Short name T995
Test name
Test status
Simulation time 659977239 ps
CPU time 3.1 seconds
Started Jan 25 02:44:53 PM PST 24
Finished Jan 25 02:45:31 PM PST 24
Peak memory 206720 kb
Host smart-7935147e-146b-4b95-99b1-dbdc4555ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190964862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3190964862
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.94550317
Short name T725
Test name
Test status
Simulation time 814264311 ps
CPU time 6.04 seconds
Started Jan 25 02:45:19 PM PST 24
Finished Jan 25 02:45:59 PM PST 24
Peak memory 208492 kb
Host smart-09635b58-e869-45e3-9383-3c23c4c523f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94550317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.94550317
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.968256549
Short name T843
Test name
Test status
Simulation time 42876016 ps
CPU time 2.41 seconds
Started Jan 25 02:44:53 PM PST 24
Finished Jan 25 02:45:30 PM PST 24
Peak memory 207860 kb
Host smart-ebe9b44b-3bb2-48f2-a332-3e00385db1f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968256549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.968256549
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2707254338
Short name T687
Test name
Test status
Simulation time 72507652 ps
CPU time 3.52 seconds
Started Jan 25 02:44:57 PM PST 24
Finished Jan 25 02:45:37 PM PST 24
Peak memory 208740 kb
Host smart-0bfb6bcb-c38b-40a5-9023-3f7fe1570c28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707254338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2707254338
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1443153127
Short name T350
Test name
Test status
Simulation time 97918537 ps
CPU time 1.87 seconds
Started Jan 25 02:44:58 PM PST 24
Finished Jan 25 02:45:37 PM PST 24
Peak memory 208064 kb
Host smart-0fe6871c-581f-45f6-b676-4aad79607a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443153127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1443153127
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1122692408
Short name T1007
Test name
Test status
Simulation time 115483391 ps
CPU time 3.25 seconds
Started Jan 25 02:44:53 PM PST 24
Finished Jan 25 02:45:31 PM PST 24
Peak memory 206800 kb
Host smart-7d614edf-1771-4a44-bda8-304eb0727bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122692408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1122692408
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.257342239
Short name T631
Test name
Test status
Simulation time 140772454 ps
CPU time 8.67 seconds
Started Jan 25 02:44:59 PM PST 24
Finished Jan 25 02:45:45 PM PST 24
Peak memory 222576 kb
Host smart-51c83f55-8b0c-436c-945a-a02d1ac6b1e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257342239 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.257342239
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.610396013
Short name T966
Test name
Test status
Simulation time 1019239854 ps
CPU time 5.33 seconds
Started Jan 25 02:44:56 PM PST 24
Finished Jan 25 02:45:39 PM PST 24
Peak memory 208412 kb
Host smart-abdd6899-5330-48ed-b8f4-9a56f819fa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610396013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.610396013
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.490998848
Short name T969
Test name
Test status
Simulation time 54645489 ps
CPU time 2.86 seconds
Started Jan 25 02:44:58 PM PST 24
Finished Jan 25 02:45:39 PM PST 24
Peak memory 209912 kb
Host smart-a43e4a82-9860-475c-99fc-af74a67a22ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490998848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.490998848
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1375023068
Short name T1045
Test name
Test status
Simulation time 59333370 ps
CPU time 3.46 seconds
Started Jan 25 02:46:38 PM PST 24
Finished Jan 25 02:47:24 PM PST 24
Peak memory 210096 kb
Host smart-af8f9143-ce8e-4918-a217-a73640c30b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375023068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1375023068
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2090730282
Short name T991
Test name
Test status
Simulation time 74769770 ps
CPU time 2.5 seconds
Started Jan 25 02:46:42 PM PST 24
Finished Jan 25 02:47:29 PM PST 24
Peak memory 218396 kb
Host smart-68bbbb23-5b2e-4698-bf8c-e7507a1c0bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090730282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2090730282
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2599696860
Short name T879
Test name
Test status
Simulation time 474815205 ps
CPU time 4.45 seconds
Started Jan 25 02:46:42 PM PST 24
Finished Jan 25 02:47:31 PM PST 24
Peak memory 219328 kb
Host smart-5c26169a-8cec-4241-926a-10d2771bd790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599696860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2599696860
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3597589776
Short name T255
Test name
Test status
Simulation time 109897295 ps
CPU time 4.92 seconds
Started Jan 25 02:46:42 PM PST 24
Finished Jan 25 02:47:32 PM PST 24
Peak memory 221876 kb
Host smart-72de52dc-595d-4c03-9ad1-64f46270b211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597589776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3597589776
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3713814159
Short name T7
Test name
Test status
Simulation time 66784110 ps
CPU time 2.56 seconds
Started Jan 25 02:46:41 PM PST 24
Finished Jan 25 02:47:28 PM PST 24
Peak memory 215072 kb
Host smart-1491c2aa-7641-48a6-b28c-e0f726a8e6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713814159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3713814159
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2499721648
Short name T669
Test name
Test status
Simulation time 5409777392 ps
CPU time 69.59 seconds
Started Jan 25 02:46:43 PM PST 24
Finished Jan 25 02:48:36 PM PST 24
Peak memory 209164 kb
Host smart-6edd6c10-bcdf-49c8-b600-b51f89c01fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499721648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2499721648
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3420494187
Short name T760
Test name
Test status
Simulation time 690731298 ps
CPU time 3.68 seconds
Started Jan 25 02:46:38 PM PST 24
Finished Jan 25 02:47:23 PM PST 24
Peak memory 208480 kb
Host smart-e0527e5a-213f-47fc-a823-9db9a9923e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420494187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3420494187
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.601791166
Short name T219
Test name
Test status
Simulation time 745755526 ps
CPU time 8.6 seconds
Started Jan 25 02:46:39 PM PST 24
Finished Jan 25 02:47:30 PM PST 24
Peak memory 208992 kb
Host smart-34450dd2-3783-44e7-8af1-1bce9372388a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601791166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.601791166
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3091472172
Short name T1068
Test name
Test status
Simulation time 99292604 ps
CPU time 2.6 seconds
Started Jan 25 02:46:42 PM PST 24
Finished Jan 25 02:47:29 PM PST 24
Peak memory 206772 kb
Host smart-2b045837-da4e-4f83-b0fd-2dd1eb7084d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091472172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3091472172
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2757683780
Short name T699
Test name
Test status
Simulation time 39205044 ps
CPU time 2.59 seconds
Started Jan 25 02:46:43 PM PST 24
Finished Jan 25 02:47:31 PM PST 24
Peak memory 208656 kb
Host smart-9bc78106-1a76-4bbf-80f9-ec2ad8aecb84
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757683780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2757683780
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1189474867
Short name T17
Test name
Test status
Simulation time 481659681 ps
CPU time 4.62 seconds
Started Jan 25 02:46:42 PM PST 24
Finished Jan 25 02:47:31 PM PST 24
Peak memory 208776 kb
Host smart-0abcae14-d347-4bd0-9ce3-d97d020b8a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189474867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1189474867
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1374612888
Short name T750
Test name
Test status
Simulation time 26235393 ps
CPU time 1.99 seconds
Started Jan 25 02:46:36 PM PST 24
Finished Jan 25 02:47:16 PM PST 24
Peak memory 208092 kb
Host smart-b12a5c52-ede5-4cca-a23d-6b784750b1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374612888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1374612888
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.619942349
Short name T931
Test name
Test status
Simulation time 3184887387 ps
CPU time 32.5 seconds
Started Jan 25 02:46:38 PM PST 24
Finished Jan 25 02:47:51 PM PST 24
Peak memory 216720 kb
Host smart-a4668723-c999-47aa-8879-3c4527f1911b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619942349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.619942349
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.722137206
Short name T849
Test name
Test status
Simulation time 1395340235 ps
CPU time 6.81 seconds
Started Jan 25 02:47:06 PM PST 24
Finished Jan 25 02:48:03 PM PST 24
Peak memory 222592 kb
Host smart-d5855c44-4d81-4750-9246-22f5d238f452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722137206 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.722137206
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3440407730
Short name T568
Test name
Test status
Simulation time 663749569 ps
CPU time 4.89 seconds
Started Jan 25 02:46:42 PM PST 24
Finished Jan 25 02:47:32 PM PST 24
Peak memory 209456 kb
Host smart-c163bec1-2b8e-4745-84eb-f0857053a6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440407730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3440407730
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2900570849
Short name T847
Test name
Test status
Simulation time 279497363 ps
CPU time 3.3 seconds
Started Jan 25 02:46:41 PM PST 24
Finished Jan 25 02:47:30 PM PST 24
Peak memory 210356 kb
Host smart-ee29499b-c182-4f92-8577-800f6df9f19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900570849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2900570849
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3617807867
Short name T714
Test name
Test status
Simulation time 9825544 ps
CPU time 0.9 seconds
Started Jan 25 02:47:11 PM PST 24
Finished Jan 25 02:48:01 PM PST 24
Peak memory 206084 kb
Host smart-a9042212-e3e6-4d4c-b405-f8cc115a90eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617807867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3617807867
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1883926476
Short name T789
Test name
Test status
Simulation time 22955795 ps
CPU time 1.45 seconds
Started Jan 25 02:47:09 PM PST 24
Finished Jan 25 02:48:00 PM PST 24
Peak memory 207812 kb
Host smart-d68614e4-61ff-4096-b340-aaff677759c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883926476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1883926476
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.143215297
Short name T63
Test name
Test status
Simulation time 86382390 ps
CPU time 4.25 seconds
Started Jan 25 02:47:09 PM PST 24
Finished Jan 25 02:48:03 PM PST 24
Peak memory 209824 kb
Host smart-3306440e-92e0-4189-841f-b9c341361619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143215297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.143215297
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3240639740
Short name T1035
Test name
Test status
Simulation time 82362970 ps
CPU time 3.46 seconds
Started Jan 25 02:46:56 PM PST 24
Finished Jan 25 02:47:48 PM PST 24
Peak memory 218120 kb
Host smart-d2dea823-2b56-4f22-abd2-c64a21bcd860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240639740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3240639740
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2477423284
Short name T119
Test name
Test status
Simulation time 1623625999 ps
CPU time 29.16 seconds
Started Jan 25 02:46:56 PM PST 24
Finished Jan 25 02:48:14 PM PST 24
Peak memory 208268 kb
Host smart-66b32149-14f3-44d6-9233-6acf80d0d07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477423284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2477423284
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.661481968
Short name T651
Test name
Test status
Simulation time 362752032 ps
CPU time 6.31 seconds
Started Jan 25 02:47:11 PM PST 24
Finished Jan 25 02:48:07 PM PST 24
Peak memory 208796 kb
Host smart-6a1d6fd5-ac4d-4f78-8d74-4c99f3f23b98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661481968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.661481968
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2308568406
Short name T654
Test name
Test status
Simulation time 738062827 ps
CPU time 20.81 seconds
Started Jan 25 02:47:03 PM PST 24
Finished Jan 25 02:48:15 PM PST 24
Peak memory 208000 kb
Host smart-6f21a5af-470b-44c6-9f92-0baadfbb830d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308568406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2308568406
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.221251514
Short name T596
Test name
Test status
Simulation time 401924039 ps
CPU time 3.04 seconds
Started Jan 25 02:47:03 PM PST 24
Finished Jan 25 02:47:56 PM PST 24
Peak memory 207004 kb
Host smart-4e1f4046-78ca-4c13-845c-a9a7280ab605
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221251514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.221251514
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1044737042
Short name T640
Test name
Test status
Simulation time 151243197 ps
CPU time 2.53 seconds
Started Jan 25 02:47:09 PM PST 24
Finished Jan 25 02:48:01 PM PST 24
Peak memory 215480 kb
Host smart-37343b98-18e2-4c02-916c-9d1bcaed9b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044737042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1044737042
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.948591064
Short name T629
Test name
Test status
Simulation time 248675877 ps
CPU time 2.12 seconds
Started Jan 25 02:46:58 PM PST 24
Finished Jan 25 02:47:50 PM PST 24
Peak memory 208544 kb
Host smart-c5fffbf3-958d-4041-9a1f-4a92a34eca6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948591064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.948591064
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2536148220
Short name T1038
Test name
Test status
Simulation time 3682200713 ps
CPU time 32.93 seconds
Started Jan 25 02:47:00 PM PST 24
Finished Jan 25 02:48:23 PM PST 24
Peak memory 208364 kb
Host smart-990f664d-a606-403f-80d4-527584fc5c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536148220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2536148220
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2851953423
Short name T769
Test name
Test status
Simulation time 129352189 ps
CPU time 1.94 seconds
Started Jan 25 02:47:04 PM PST 24
Finished Jan 25 02:47:56 PM PST 24
Peak memory 210276 kb
Host smart-eab98743-4407-4b81-8618-23b474098721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851953423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2851953423
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.293479250
Short name T839
Test name
Test status
Simulation time 115041008 ps
CPU time 0.87 seconds
Started Jan 25 02:46:59 PM PST 24
Finished Jan 25 02:47:49 PM PST 24
Peak memory 205820 kb
Host smart-e19cb7bc-d85f-4338-ad52-816aace895d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293479250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.293479250
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1393648714
Short name T227
Test name
Test status
Simulation time 1622522257 ps
CPU time 4.43 seconds
Started Jan 25 02:47:04 PM PST 24
Finished Jan 25 02:47:58 PM PST 24
Peak memory 209732 kb
Host smart-b2df3720-f453-4558-befa-79520665439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393648714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1393648714
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3252541150
Short name T323
Test name
Test status
Simulation time 2413828330 ps
CPU time 27.51 seconds
Started Jan 25 02:47:03 PM PST 24
Finished Jan 25 02:48:21 PM PST 24
Peak memory 218500 kb
Host smart-04f80022-aee4-4955-bed7-1d5c5fa786c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252541150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3252541150
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1591036855
Short name T747
Test name
Test status
Simulation time 135148192 ps
CPU time 2.69 seconds
Started Jan 25 02:47:11 PM PST 24
Finished Jan 25 02:48:03 PM PST 24
Peak memory 220360 kb
Host smart-5ec197f5-62f2-4398-982f-2504b0315880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591036855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1591036855
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1767706674
Short name T848
Test name
Test status
Simulation time 69858472 ps
CPU time 3.07 seconds
Started Jan 25 02:47:02 PM PST 24
Finished Jan 25 02:47:56 PM PST 24
Peak memory 207568 kb
Host smart-a4be9db1-00c2-426d-9442-7b7bd2f7d526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767706674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1767706674
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.793449315
Short name T75
Test name
Test status
Simulation time 121746062 ps
CPU time 2.35 seconds
Started Jan 25 02:47:00 PM PST 24
Finished Jan 25 02:47:52 PM PST 24
Peak memory 207144 kb
Host smart-659be066-ee23-4021-9528-d8ef344d9f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793449315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.793449315
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1372559197
Short name T1021
Test name
Test status
Simulation time 23869828 ps
CPU time 2 seconds
Started Jan 25 02:47:10 PM PST 24
Finished Jan 25 02:48:01 PM PST 24
Peak memory 208600 kb
Host smart-61c716b4-bbfd-4d12-92d3-dd8617c4b721
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372559197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1372559197
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2497141893
Short name T752
Test name
Test status
Simulation time 138065533 ps
CPU time 3.19 seconds
Started Jan 25 02:47:09 PM PST 24
Finished Jan 25 02:48:02 PM PST 24
Peak memory 207280 kb
Host smart-95dad268-129d-492b-8506-9b506c442cbd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497141893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2497141893
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.4216505567
Short name T916
Test name
Test status
Simulation time 692027978 ps
CPU time 17.5 seconds
Started Jan 25 02:47:02 PM PST 24
Finished Jan 25 02:48:10 PM PST 24
Peak memory 208588 kb
Host smart-29a7c001-37a1-4d85-863b-3c510d508bd2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216505567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4216505567
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3331678727
Short name T330
Test name
Test status
Simulation time 1820992691 ps
CPU time 19.85 seconds
Started Jan 25 02:47:09 PM PST 24
Finished Jan 25 02:48:18 PM PST 24
Peak memory 218252 kb
Host smart-90c1b3e3-3862-4654-a958-782fbfb6c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331678727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3331678727
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2782317701
Short name T1065
Test name
Test status
Simulation time 11917490739 ps
CPU time 54.93 seconds
Started Jan 25 02:47:07 PM PST 24
Finished Jan 25 02:48:51 PM PST 24
Peak memory 207944 kb
Host smart-d4ac8563-6c1f-4d55-8abe-46370b2244f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782317701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2782317701
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1301241741
Short name T1016
Test name
Test status
Simulation time 321784084 ps
CPU time 7.45 seconds
Started Jan 25 02:46:59 PM PST 24
Finished Jan 25 02:47:57 PM PST 24
Peak memory 216940 kb
Host smart-8507efda-d838-4f0a-8ba2-6e72b20aafc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301241741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1301241741
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3822961027
Short name T1003
Test name
Test status
Simulation time 3633654980 ps
CPU time 9.72 seconds
Started Jan 25 02:46:55 PM PST 24
Finished Jan 25 02:47:54 PM PST 24
Peak memory 208936 kb
Host smart-6f4adcf5-aa0f-4458-a749-c1a8b5d56cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822961027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3822961027
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1264970681
Short name T548
Test name
Test status
Simulation time 535468017 ps
CPU time 3.07 seconds
Started Jan 25 02:47:09 PM PST 24
Finished Jan 25 02:48:02 PM PST 24
Peak memory 210836 kb
Host smart-7cc6c4a8-c815-4a07-9529-dab134148b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264970681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1264970681
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.4184265637
Short name T891
Test name
Test status
Simulation time 58468526 ps
CPU time 0.73 seconds
Started Jan 25 02:47:09 PM PST 24
Finished Jan 25 02:48:00 PM PST 24
Peak memory 205744 kb
Host smart-ce22f185-f6cc-4b36-8026-2bbd9b504678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184265637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.4184265637
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2748090537
Short name T198
Test name
Test status
Simulation time 213757385 ps
CPU time 5.81 seconds
Started Jan 25 02:47:10 PM PST 24
Finished Jan 25 02:48:05 PM PST 24
Peak memory 210332 kb
Host smart-5e329d0d-c882-408c-b07c-cde0a882558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748090537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2748090537
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3774697264
Short name T1071
Test name
Test status
Simulation time 961358758 ps
CPU time 8.29 seconds
Started Jan 25 02:47:09 PM PST 24
Finished Jan 25 02:48:07 PM PST 24
Peak memory 208696 kb
Host smart-e33dcab4-a3dd-40a1-af50-61bd016866a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774697264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3774697264
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3587012720
Short name T814
Test name
Test status
Simulation time 111677185 ps
CPU time 4.38 seconds
Started Jan 25 02:47:11 PM PST 24
Finished Jan 25 02:48:05 PM PST 24
Peak memory 209168 kb
Host smart-49ae7311-8544-4bd9-b045-2c0d936333ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587012720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3587012720
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.485087728
Short name T195
Test name
Test status
Simulation time 170481416 ps
CPU time 4.37 seconds
Started Jan 25 02:47:00 PM PST 24
Finished Jan 25 02:47:55 PM PST 24
Peak memory 209912 kb
Host smart-3e82bc48-f3d1-4bb8-94d8-ba113d30293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485087728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.485087728
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3531572293
Short name T1058
Test name
Test status
Simulation time 336394733 ps
CPU time 2.07 seconds
Started Jan 25 02:47:09 PM PST 24
Finished Jan 25 02:48:01 PM PST 24
Peak memory 207496 kb
Host smart-88bb0753-85b6-446e-864b-63c4ccfdd994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531572293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3531572293
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.508165683
Short name T251
Test name
Test status
Simulation time 802910337 ps
CPU time 4.46 seconds
Started Jan 25 02:47:02 PM PST 24
Finished Jan 25 02:47:57 PM PST 24
Peak memory 208296 kb
Host smart-b4e8ee58-58b1-4f21-b679-e015f17e7e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508165683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.508165683
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.457049789
Short name T702
Test name
Test status
Simulation time 849968853 ps
CPU time 4.55 seconds
Started Jan 25 02:47:10 PM PST 24
Finished Jan 25 02:48:04 PM PST 24
Peak memory 208496 kb
Host smart-5f7dcfff-1798-4fbc-bab4-cc060bd1a39a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457049789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.457049789
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.712418385
Short name T946
Test name
Test status
Simulation time 3589281483 ps
CPU time 28.89 seconds
Started Jan 25 02:47:06 PM PST 24
Finished Jan 25 02:48:25 PM PST 24
Peak memory 208808 kb
Host smart-de69336f-1308-426d-95a8-27430c2cc735
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712418385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.712418385
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.605575472
Short name T565
Test name
Test status
Simulation time 47920624 ps
CPU time 2.47 seconds
Started Jan 25 02:47:02 PM PST 24
Finished Jan 25 02:47:55 PM PST 24
Peak memory 207020 kb
Host smart-27a27c4e-546a-4f96-b74f-289a84c84c9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605575472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.605575472
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.262481100
Short name T786
Test name
Test status
Simulation time 618196934 ps
CPU time 2.55 seconds
Started Jan 25 02:47:04 PM PST 24
Finished Jan 25 02:47:56 PM PST 24
Peak memory 208516 kb
Host smart-186760aa-c0ab-4031-9fb0-05e51ff03624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262481100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.262481100
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2994671523
Short name T938
Test name
Test status
Simulation time 1202853207 ps
CPU time 6.54 seconds
Started Jan 25 02:47:01 PM PST 24
Finished Jan 25 02:47:57 PM PST 24
Peak memory 206804 kb
Host smart-4c81eba0-3e4d-4c08-82e6-f80e6989717e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994671523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2994671523
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2114462862
Short name T182
Test name
Test status
Simulation time 190530350 ps
CPU time 7.21 seconds
Started Jan 25 02:47:03 PM PST 24
Finished Jan 25 02:48:01 PM PST 24
Peak memory 222676 kb
Host smart-f67bfde7-be71-4fdc-9726-66a857518065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114462862 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2114462862
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3935912900
Short name T942
Test name
Test status
Simulation time 141280489 ps
CPU time 2.82 seconds
Started Jan 25 02:47:05 PM PST 24
Finished Jan 25 02:47:58 PM PST 24
Peak memory 207336 kb
Host smart-4bbabb49-cf06-489f-bb60-04ecfef98b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935912900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3935912900
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.465605748
Short name T156
Test name
Test status
Simulation time 48442034 ps
CPU time 2.46 seconds
Started Jan 25 02:47:04 PM PST 24
Finished Jan 25 02:47:56 PM PST 24
Peak memory 210216 kb
Host smart-facc9151-2024-43fa-b781-cd88eb18e828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465605748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.465605748
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.4103278634
Short name T552
Test name
Test status
Simulation time 60108608 ps
CPU time 0.72 seconds
Started Jan 25 02:47:24 PM PST 24
Finished Jan 25 02:48:11 PM PST 24
Peak memory 205920 kb
Host smart-ec4794d7-70ec-4370-9a1f-9913e77e20e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103278634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4103278634
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2046111200
Short name T385
Test name
Test status
Simulation time 9804921529 ps
CPU time 100.31 seconds
Started Jan 25 02:47:27 PM PST 24
Finished Jan 25 02:49:52 PM PST 24
Peak memory 222108 kb
Host smart-31e03121-1f02-493f-9f9c-a0181a3975e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046111200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2046111200
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3458910164
Short name T637
Test name
Test status
Simulation time 157852623 ps
CPU time 2.46 seconds
Started Jan 25 02:47:24 PM PST 24
Finished Jan 25 02:48:12 PM PST 24
Peak memory 208424 kb
Host smart-ce719ef4-173b-406a-b251-96f62ae338a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458910164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3458910164
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3911878481
Short name T1025
Test name
Test status
Simulation time 262458093 ps
CPU time 4.85 seconds
Started Jan 25 02:47:22 PM PST 24
Finished Jan 25 02:48:13 PM PST 24
Peak memory 209764 kb
Host smart-a6b96fe7-09a8-46c3-81ad-ae68ce9a317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911878481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3911878481
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3521858477
Short name T34
Test name
Test status
Simulation time 168791353 ps
CPU time 3.11 seconds
Started Jan 25 02:47:39 PM PST 24
Finished Jan 25 02:48:26 PM PST 24
Peak memory 209368 kb
Host smart-1c1b19c6-3df4-4751-92c1-e969b3e14a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521858477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3521858477
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1551813277
Short name T581
Test name
Test status
Simulation time 323776397 ps
CPU time 3.97 seconds
Started Jan 25 02:47:30 PM PST 24
Finished Jan 25 02:48:18 PM PST 24
Peak memory 219952 kb
Host smart-8f5a7ad6-9601-4933-b566-fbef51462ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551813277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1551813277
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3832478475
Short name T352
Test name
Test status
Simulation time 129825653 ps
CPU time 5.61 seconds
Started Jan 25 02:47:18 PM PST 24
Finished Jan 25 02:48:11 PM PST 24
Peak memory 209604 kb
Host smart-20462ae3-5be5-400a-9efb-81398eb891a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832478475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3832478475
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1927619055
Short name T672
Test name
Test status
Simulation time 200499169 ps
CPU time 7.51 seconds
Started Jan 25 02:47:04 PM PST 24
Finished Jan 25 02:48:02 PM PST 24
Peak memory 207036 kb
Host smart-5ba39244-260a-44b7-bfa9-7c73d0f0131e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927619055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1927619055
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2418748310
Short name T783
Test name
Test status
Simulation time 86633291 ps
CPU time 3.72 seconds
Started Jan 25 02:47:23 PM PST 24
Finished Jan 25 02:48:13 PM PST 24
Peak memory 208760 kb
Host smart-46b04d72-27e9-4f68-ab76-98e4af6bff4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418748310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2418748310
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3759641391
Short name T621
Test name
Test status
Simulation time 205463835 ps
CPU time 2.92 seconds
Started Jan 25 02:47:11 PM PST 24
Finished Jan 25 02:48:03 PM PST 24
Peak memory 207156 kb
Host smart-7d608d95-ea46-4b54-93d6-1e54afd59033
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759641391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3759641391
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2469409156
Short name T1013
Test name
Test status
Simulation time 222099822 ps
CPU time 2.23 seconds
Started Jan 25 02:47:21 PM PST 24
Finished Jan 25 02:48:10 PM PST 24
Peak memory 206900 kb
Host smart-95e88bfa-e3f6-4fdb-ac35-09a479fe2a92
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469409156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2469409156
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.340657051
Short name T658
Test name
Test status
Simulation time 179708949 ps
CPU time 4.22 seconds
Started Jan 25 02:47:24 PM PST 24
Finished Jan 25 02:48:14 PM PST 24
Peak memory 209104 kb
Host smart-8d4c00f9-9d3d-47ce-86f9-f8d75fce13b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340657051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.340657051
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2394040814
Short name T375
Test name
Test status
Simulation time 813833371 ps
CPU time 7.54 seconds
Started Jan 25 02:47:04 PM PST 24
Finished Jan 25 02:48:02 PM PST 24
Peak memory 208752 kb
Host smart-adcd05fb-2964-472e-8a74-4f2bff4c761f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394040814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2394040814
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1780981262
Short name T757
Test name
Test status
Simulation time 128321020 ps
CPU time 3.6 seconds
Started Jan 25 02:47:26 PM PST 24
Finished Jan 25 02:48:14 PM PST 24
Peak memory 219716 kb
Host smart-3afcffa5-1a77-4a3f-a323-0810efa2072d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780981262 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1780981262
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3843511543
Short name T698
Test name
Test status
Simulation time 150232598 ps
CPU time 6.19 seconds
Started Jan 25 02:47:23 PM PST 24
Finished Jan 25 02:48:16 PM PST 24
Peak memory 218088 kb
Host smart-5b597774-a61b-40d2-a165-49a344aa1f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843511543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3843511543
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1688023020
Short name T808
Test name
Test status
Simulation time 43343366 ps
CPU time 1.84 seconds
Started Jan 25 02:47:30 PM PST 24
Finished Jan 25 02:48:16 PM PST 24
Peak memory 210064 kb
Host smart-bc62bcfd-1bdb-460e-8ab8-9301301afa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688023020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1688023020
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.60362260
Short name T571
Test name
Test status
Simulation time 43201575 ps
CPU time 0.81 seconds
Started Jan 25 02:47:26 PM PST 24
Finished Jan 25 02:48:12 PM PST 24
Peak memory 205848 kb
Host smart-0df61190-8577-4596-9a62-372c142ead05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60362260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.60362260
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.658336701
Short name T874
Test name
Test status
Simulation time 141937863 ps
CPU time 3.79 seconds
Started Jan 25 02:47:20 PM PST 24
Finished Jan 25 02:48:11 PM PST 24
Peak memory 222264 kb
Host smart-629632cd-5c12-4871-94e9-d48568682cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658336701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.658336701
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1109778042
Short name T706
Test name
Test status
Simulation time 577623377 ps
CPU time 5.99 seconds
Started Jan 25 02:47:21 PM PST 24
Finished Jan 25 02:48:14 PM PST 24
Peak memory 209680 kb
Host smart-c23e2f8d-9adb-4c65-a233-ca187f80b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109778042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1109778042
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2279138616
Short name T346
Test name
Test status
Simulation time 88278893 ps
CPU time 3.56 seconds
Started Jan 25 02:47:23 PM PST 24
Finished Jan 25 02:48:13 PM PST 24
Peak memory 218956 kb
Host smart-77768a5e-9d1d-4412-a521-fc8aa013d2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279138616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2279138616
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2655838382
Short name T975
Test name
Test status
Simulation time 105709388 ps
CPU time 3.54 seconds
Started Jan 25 02:47:40 PM PST 24
Finished Jan 25 02:48:26 PM PST 24
Peak memory 218788 kb
Host smart-227ef34e-d0a5-431f-835f-ad486a2b32af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655838382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2655838382
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.4136087175
Short name T1001
Test name
Test status
Simulation time 225696088 ps
CPU time 3.74 seconds
Started Jan 25 02:47:19 PM PST 24
Finished Jan 25 02:48:11 PM PST 24
Peak memory 209764 kb
Host smart-2c1814f4-9681-4e3c-b15b-63b14a64b539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136087175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4136087175
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3154089800
Short name T325
Test name
Test status
Simulation time 3160224493 ps
CPU time 59.37 seconds
Started Jan 25 02:47:20 PM PST 24
Finished Jan 25 02:49:06 PM PST 24
Peak memory 208620 kb
Host smart-580b471a-daad-42b1-927e-4ab76ea2bb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154089800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3154089800
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2327524930
Short name T583
Test name
Test status
Simulation time 87164667 ps
CPU time 3.23 seconds
Started Jan 25 02:47:38 PM PST 24
Finished Jan 25 02:48:25 PM PST 24
Peak memory 208712 kb
Host smart-8e750ae1-54e8-4d16-a7d6-17466afe6201
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327524930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2327524930
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.41835022
Short name T790
Test name
Test status
Simulation time 147109371 ps
CPU time 3.53 seconds
Started Jan 25 02:47:27 PM PST 24
Finished Jan 25 02:48:15 PM PST 24
Peak memory 206272 kb
Host smart-a5e9c27b-b9b4-41d6-8474-d89866f9128e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41835022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.41835022
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1611730939
Short name T178
Test name
Test status
Simulation time 86839940 ps
CPU time 4.12 seconds
Started Jan 25 02:47:24 PM PST 24
Finished Jan 25 02:48:14 PM PST 24
Peak memory 208764 kb
Host smart-97b7edcf-ab34-4eb8-accb-5acafabf594f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611730939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1611730939
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1001179837
Short name T171
Test name
Test status
Simulation time 648093676 ps
CPU time 17.36 seconds
Started Jan 25 02:47:23 PM PST 24
Finished Jan 25 02:48:27 PM PST 24
Peak memory 209108 kb
Host smart-5f95be93-55bf-4e2e-908e-5aa0ec4bc0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001179837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1001179837
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2416449368
Short name T902
Test name
Test status
Simulation time 124095863 ps
CPU time 2.18 seconds
Started Jan 25 02:47:21 PM PST 24
Finished Jan 25 02:48:11 PM PST 24
Peak memory 206704 kb
Host smart-df6ecd50-d567-42a6-bfe6-27118e175832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416449368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2416449368
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3923624188
Short name T945
Test name
Test status
Simulation time 89518241 ps
CPU time 2.87 seconds
Started Jan 25 02:47:24 PM PST 24
Finished Jan 25 02:48:13 PM PST 24
Peak memory 222504 kb
Host smart-1eb61b9f-0620-470c-8ed5-901a7b504a8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923624188 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3923624188
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.64222101
Short name T921
Test name
Test status
Simulation time 957465556 ps
CPU time 9.23 seconds
Started Jan 25 02:47:21 PM PST 24
Finished Jan 25 02:48:18 PM PST 24
Peak memory 214360 kb
Host smart-8270572f-bcb9-4932-8114-d76c7cea899a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64222101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.64222101
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.754820619
Short name T41
Test name
Test status
Simulation time 897300965 ps
CPU time 2.46 seconds
Started Jan 25 02:47:23 PM PST 24
Finished Jan 25 02:48:12 PM PST 24
Peak memory 210036 kb
Host smart-b30ec58b-995c-4ac5-853e-43bb997a69df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754820619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.754820619
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1164404724
Short name T904
Test name
Test status
Simulation time 151245404 ps
CPU time 0.68 seconds
Started Jan 25 02:47:57 PM PST 24
Finished Jan 25 02:48:34 PM PST 24
Peak memory 205916 kb
Host smart-f4caf152-0729-43b3-8556-ba7a44f5d455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164404724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1164404724
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2804119353
Short name T201
Test name
Test status
Simulation time 301321838 ps
CPU time 4.99 seconds
Started Jan 25 02:47:26 PM PST 24
Finished Jan 25 02:48:16 PM PST 24
Peak memory 214284 kb
Host smart-2db0df5b-7a8d-406d-9f33-1b91e929fd1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804119353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2804119353
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3466263266
Short name T9
Test name
Test status
Simulation time 326489232 ps
CPU time 3.99 seconds
Started Jan 25 03:04:33 PM PST 24
Finished Jan 25 03:04:49 PM PST 24
Peak memory 222312 kb
Host smart-2434ea3a-5bee-4e43-b5c5-f4cc63f70ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466263266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3466263266
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1114819867
Short name T816
Test name
Test status
Simulation time 303833809 ps
CPU time 2.94 seconds
Started Jan 25 02:47:20 PM PST 24
Finished Jan 25 02:48:10 PM PST 24
Peak memory 209732 kb
Host smart-f7191cf6-cf5a-4743-9e4c-c130ce61e80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114819867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1114819867
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.4041723921
Short name T213
Test name
Test status
Simulation time 3538012916 ps
CPU time 49.35 seconds
Started Jan 25 02:47:24 PM PST 24
Finished Jan 25 02:48:59 PM PST 24
Peak memory 222456 kb
Host smart-f5b1015f-39f3-423f-9da4-af3680155b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041723921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.4041723921
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.989005512
Short name T708
Test name
Test status
Simulation time 252810312 ps
CPU time 3.21 seconds
Started Jan 25 02:47:21 PM PST 24
Finished Jan 25 02:48:11 PM PST 24
Peak memory 222468 kb
Host smart-17b12126-d8c5-44d5-90e2-bdfbc5e89981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989005512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.989005512
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2236783196
Short name T999
Test name
Test status
Simulation time 2735528239 ps
CPU time 56.97 seconds
Started Jan 25 02:47:24 PM PST 24
Finished Jan 25 02:49:07 PM PST 24
Peak memory 208376 kb
Host smart-caf9b1c5-1b6c-47cd-9e9f-06c0356f3c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236783196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2236783196
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3873057548
Short name T700
Test name
Test status
Simulation time 102447812 ps
CPU time 2.69 seconds
Started Jan 25 02:47:39 PM PST 24
Finished Jan 25 02:48:25 PM PST 24
Peak memory 206984 kb
Host smart-ce458b7e-671f-45bf-b7ce-8b1ec6d9c1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873057548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3873057548
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.4087649803
Short name T936
Test name
Test status
Simulation time 244895986 ps
CPU time 3.06 seconds
Started Jan 25 02:47:20 PM PST 24
Finished Jan 25 02:48:10 PM PST 24
Peak memory 207112 kb
Host smart-56b69c96-492b-448f-9d90-4102981cba4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087649803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.4087649803
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.4221036611
Short name T766
Test name
Test status
Simulation time 339985667 ps
CPU time 5.23 seconds
Started Jan 25 02:47:21 PM PST 24
Finished Jan 25 02:48:13 PM PST 24
Peak memory 208120 kb
Host smart-515e64c7-9dbb-492b-b44c-c325ad79bedc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221036611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.4221036611
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3134192723
Short name T749
Test name
Test status
Simulation time 139876964 ps
CPU time 3.38 seconds
Started Jan 25 02:47:26 PM PST 24
Finished Jan 25 02:48:14 PM PST 24
Peak memory 208724 kb
Host smart-7f43222e-182b-42b4-b9e7-1372522af156
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134192723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3134192723
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1068527059
Short name T281
Test name
Test status
Simulation time 33829629 ps
CPU time 2.31 seconds
Started Jan 25 02:58:38 PM PST 24
Finished Jan 25 02:58:57 PM PST 24
Peak memory 214456 kb
Host smart-a371e715-49c2-44dd-bccc-4937f40b58cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068527059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1068527059
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.229648666
Short name T103
Test name
Test status
Simulation time 768366525 ps
CPU time 17.18 seconds
Started Jan 25 02:47:23 PM PST 24
Finished Jan 25 02:48:26 PM PST 24
Peak memory 208468 kb
Host smart-e7dc0e58-2f1f-4e7c-9769-b03ce3fd3f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229648666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.229648666
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2071026728
Short name T65
Test name
Test status
Simulation time 353977383 ps
CPU time 5.16 seconds
Started Jan 25 02:48:06 PM PST 24
Finished Jan 25 02:48:44 PM PST 24
Peak memory 218948 kb
Host smart-e0dbb314-e795-4f33-b9cd-eacb1a26d950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071026728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2071026728
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1733823354
Short name T58
Test name
Test status
Simulation time 222561138 ps
CPU time 8.62 seconds
Started Jan 25 04:59:30 PM PST 24
Finished Jan 25 04:59:48 PM PST 24
Peak memory 219860 kb
Host smart-fbe2a42a-8da9-4b03-bc0f-2d184b435bbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733823354 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1733823354
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.838768463
Short name T618
Test name
Test status
Simulation time 194183201 ps
CPU time 7.11 seconds
Started Jan 25 02:47:25 PM PST 24
Finished Jan 25 02:48:17 PM PST 24
Peak memory 208232 kb
Host smart-e7b7b60c-3b78-4ea7-8e5f-c5a67e44344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838768463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.838768463
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1726729818
Short name T378
Test name
Test status
Simulation time 56980565 ps
CPU time 2.44 seconds
Started Jan 25 03:04:42 PM PST 24
Finished Jan 25 03:04:58 PM PST 24
Peak memory 210000 kb
Host smart-c8886a37-e4a2-4fe7-b2c7-12122bf0fbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726729818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1726729818
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2862360304
Short name T566
Test name
Test status
Simulation time 37516931 ps
CPU time 0.87 seconds
Started Jan 25 03:05:46 PM PST 24
Finished Jan 25 03:05:49 PM PST 24
Peak memory 206084 kb
Host smart-2dea5de3-1dd4-4ab7-b218-46a02a6b9df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862360304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2862360304
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3659029749
Short name T598
Test name
Test status
Simulation time 257437680 ps
CPU time 4.02 seconds
Started Jan 25 02:47:58 PM PST 24
Finished Jan 25 02:48:38 PM PST 24
Peak memory 209612 kb
Host smart-bc22032f-a04a-4df3-a59b-ae8ddb5979e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659029749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3659029749
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3173679136
Short name T822
Test name
Test status
Simulation time 47944616 ps
CPU time 2.56 seconds
Started Jan 25 03:19:42 PM PST 24
Finished Jan 25 03:21:19 PM PST 24
Peak memory 209712 kb
Host smart-8e0aa0a2-27e4-4ee1-b130-d93268651afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173679136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3173679136
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3304619781
Short name T1074
Test name
Test status
Simulation time 191994032 ps
CPU time 4.5 seconds
Started Jan 25 03:04:42 PM PST 24
Finished Jan 25 03:05:00 PM PST 24
Peak memory 208536 kb
Host smart-989a1265-3b0f-4540-a40e-5ae795cf623b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304619781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3304619781
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.4142268074
Short name T976
Test name
Test status
Simulation time 717801958 ps
CPU time 5.33 seconds
Started Jan 25 02:48:06 PM PST 24
Finished Jan 25 02:48:44 PM PST 24
Peak memory 214272 kb
Host smart-fe4deca8-43c2-429c-8d25-3cee1fb40edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142268074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.4142268074
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.202882568
Short name T924
Test name
Test status
Simulation time 185543213 ps
CPU time 3.84 seconds
Started Jan 25 02:47:58 PM PST 24
Finished Jan 25 02:48:38 PM PST 24
Peak memory 209456 kb
Host smart-d443d7f3-2ad9-4600-bfa1-72e86680c1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202882568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.202882568
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3411083077
Short name T889
Test name
Test status
Simulation time 269796090 ps
CPU time 4.2 seconds
Started Jan 25 02:47:52 PM PST 24
Finished Jan 25 02:48:35 PM PST 24
Peak memory 218528 kb
Host smart-f125efb2-39b3-47f2-9a8f-a7d60f3853ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411083077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3411083077
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.229650981
Short name T210
Test name
Test status
Simulation time 127085018 ps
CPU time 4.53 seconds
Started Jan 25 03:46:43 PM PST 24
Finished Jan 25 03:47:51 PM PST 24
Peak memory 208144 kb
Host smart-8495b89a-e45f-46cf-99ba-fd2c7616560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229650981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.229650981
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.15955197
Short name T619
Test name
Test status
Simulation time 93045350 ps
CPU time 2.07 seconds
Started Jan 25 02:47:54 PM PST 24
Finished Jan 25 02:48:34 PM PST 24
Peak memory 208464 kb
Host smart-90e27e6c-5b72-472a-91a3-ec816ee64f21
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15955197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.15955197
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3199510400
Short name T263
Test name
Test status
Simulation time 208450846 ps
CPU time 2.68 seconds
Started Jan 25 02:47:57 PM PST 24
Finished Jan 25 02:48:37 PM PST 24
Peak memory 210040 kb
Host smart-e3da1ae4-8a88-4bcf-8289-1afec3f79f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199510400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3199510400
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.176858128
Short name T1034
Test name
Test status
Simulation time 59515758 ps
CPU time 2.67 seconds
Started Jan 25 02:48:06 PM PST 24
Finished Jan 25 02:48:41 PM PST 24
Peak memory 208256 kb
Host smart-67b85e28-5ea0-4d9c-b2e1-3bab24a8fa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176858128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.176858128
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1634083720
Short name T1061
Test name
Test status
Simulation time 7523970780 ps
CPU time 19.98 seconds
Started Jan 25 03:23:03 PM PST 24
Finished Jan 25 03:24:29 PM PST 24
Peak memory 215768 kb
Host smart-b54cdf7f-5fe7-484d-941e-6da96251e3cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634083720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1634083720
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1587630427
Short name T185
Test name
Test status
Simulation time 2761938811 ps
CPU time 22.2 seconds
Started Jan 25 05:11:34 PM PST 24
Finished Jan 25 05:11:57 PM PST 24
Peak memory 222604 kb
Host smart-703cbe26-82ff-46f6-bc21-26ec625fc150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587630427 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1587630427
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.4266909978
Short name T365
Test name
Test status
Simulation time 599663082 ps
CPU time 8.5 seconds
Started Jan 25 04:27:13 PM PST 24
Finished Jan 25 04:27:24 PM PST 24
Peak memory 209336 kb
Host smart-a5a3f890-011d-4f82-9115-e312b135b85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266909978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.4266909978
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1912591285
Short name T589
Test name
Test status
Simulation time 246786595 ps
CPU time 5.42 seconds
Started Jan 25 04:40:10 PM PST 24
Finished Jan 25 04:40:28 PM PST 24
Peak memory 210712 kb
Host smart-6278a30d-6d1d-4f68-af40-595f67b8839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912591285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1912591285
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.165693376
Short name T588
Test name
Test status
Simulation time 12187324 ps
CPU time 0.76 seconds
Started Jan 25 02:47:52 PM PST 24
Finished Jan 25 02:48:32 PM PST 24
Peak memory 205900 kb
Host smart-c5517502-dad1-4e23-ae5d-145e8e4b2d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165693376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.165693376
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3629841759
Short name T870
Test name
Test status
Simulation time 214946946 ps
CPU time 6.27 seconds
Started Jan 25 02:47:57 PM PST 24
Finished Jan 25 02:48:40 PM PST 24
Peak memory 209872 kb
Host smart-0a157b5f-a8f9-46e4-a8ae-7e6e97248130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629841759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3629841759
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3828840498
Short name T683
Test name
Test status
Simulation time 1705974989 ps
CPU time 8.51 seconds
Started Jan 25 04:46:29 PM PST 24
Finished Jan 25 04:46:39 PM PST 24
Peak memory 208912 kb
Host smart-29b95bd0-8642-4751-adf4-32df170e9e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828840498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3828840498
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.4036223208
Short name T283
Test name
Test status
Simulation time 381167003 ps
CPU time 4.37 seconds
Started Jan 25 02:47:56 PM PST 24
Finished Jan 25 02:48:38 PM PST 24
Peak memory 208092 kb
Host smart-44c5ed1c-24b3-42d3-8adb-934c4d751921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036223208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.4036223208
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.4011222178
Short name T66
Test name
Test status
Simulation time 415479010 ps
CPU time 7.06 seconds
Started Jan 25 03:06:29 PM PST 24
Finished Jan 25 03:06:38 PM PST 24
Peak memory 214360 kb
Host smart-d58fd171-bec2-4a5f-a83c-5e69a526436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011222178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.4011222178
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1167922786
Short name T57
Test name
Test status
Simulation time 93724478 ps
CPU time 2.49 seconds
Started Jan 25 02:48:03 PM PST 24
Finished Jan 25 02:48:39 PM PST 24
Peak memory 209384 kb
Host smart-8a3a4cda-a910-4887-b533-0bcb9ca05123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167922786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1167922786
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3845576503
Short name T641
Test name
Test status
Simulation time 418063215 ps
CPU time 5.86 seconds
Started Jan 25 03:47:23 PM PST 24
Finished Jan 25 03:48:32 PM PST 24
Peak memory 208876 kb
Host smart-2c2c513f-d45d-4918-bc14-ad6f28847f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845576503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3845576503
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.234582771
Short name T801
Test name
Test status
Simulation time 216659905 ps
CPU time 2.79 seconds
Started Jan 25 03:54:59 PM PST 24
Finished Jan 25 03:55:38 PM PST 24
Peak memory 206840 kb
Host smart-d7714a58-a89d-441c-987f-16e0ab3d627a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234582771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.234582771
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.4210118702
Short name T544
Test name
Test status
Simulation time 127839851 ps
CPU time 3.21 seconds
Started Jan 25 02:47:53 PM PST 24
Finished Jan 25 02:48:35 PM PST 24
Peak memory 206892 kb
Host smart-d9852c80-c5d4-47de-94f0-467cf1b4a076
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210118702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.4210118702
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3745351542
Short name T682
Test name
Test status
Simulation time 122271395 ps
CPU time 3.93 seconds
Started Jan 25 02:47:58 PM PST 24
Finished Jan 25 02:48:38 PM PST 24
Peak memory 208612 kb
Host smart-a72c131d-8b62-49c7-9803-54858902105a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745351542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3745351542
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2906719429
Short name T614
Test name
Test status
Simulation time 221818876 ps
CPU time 3.12 seconds
Started Jan 25 04:26:42 PM PST 24
Finished Jan 25 04:26:48 PM PST 24
Peak memory 208608 kb
Host smart-d847a561-b8be-4470-8d79-e7f87ac20817
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906719429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2906719429
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1805451263
Short name T582
Test name
Test status
Simulation time 724705872 ps
CPU time 2.73 seconds
Started Jan 25 02:48:06 PM PST 24
Finished Jan 25 02:48:41 PM PST 24
Peak memory 208448 kb
Host smart-61aaebab-2762-426c-8d76-539eaf4ab887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805451263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1805451263
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2435561519
Short name T1060
Test name
Test status
Simulation time 424498859 ps
CPU time 3.45 seconds
Started Jan 25 03:27:05 PM PST 24
Finished Jan 25 03:28:03 PM PST 24
Peak memory 208536 kb
Host smart-cefea14d-29d6-4473-b129-72fcd8b64307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435561519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2435561519
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2043042933
Short name T52
Test name
Test status
Simulation time 701482420 ps
CPU time 24.22 seconds
Started Jan 25 02:47:57 PM PST 24
Finished Jan 25 02:48:58 PM PST 24
Peak memory 216056 kb
Host smart-32c63cfe-4929-4453-9d82-8467093dccd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043042933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2043042933
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2840946195
Short name T1040
Test name
Test status
Simulation time 110153465 ps
CPU time 3.65 seconds
Started Jan 25 03:33:48 PM PST 24
Finished Jan 25 03:35:33 PM PST 24
Peak memory 222452 kb
Host smart-dca6c96f-fdb6-498e-8930-93a2e7af3106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840946195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2840946195
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3107014739
Short name T1009
Test name
Test status
Simulation time 127875604 ps
CPU time 2.96 seconds
Started Jan 25 05:20:39 PM PST 24
Finished Jan 25 05:20:44 PM PST 24
Peak memory 209808 kb
Host smart-381c82c3-0a46-42c6-a0f5-673b3846b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107014739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3107014739
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1099227329
Short name T625
Test name
Test status
Simulation time 49283463 ps
CPU time 0.88 seconds
Started Jan 25 02:48:24 PM PST 24
Finished Jan 25 02:48:49 PM PST 24
Peak memory 205940 kb
Host smart-cab2f8f7-a800-4125-ab67-3bd87c80fe53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099227329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1099227329
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3168648068
Short name T927
Test name
Test status
Simulation time 653053217 ps
CPU time 3.82 seconds
Started Jan 25 02:48:31 PM PST 24
Finished Jan 25 02:48:57 PM PST 24
Peak memory 219056 kb
Host smart-17763753-ae4f-4320-946b-0248ddb2e81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168648068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3168648068
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4217864508
Short name T59
Test name
Test status
Simulation time 1630990007 ps
CPU time 48.02 seconds
Started Jan 25 02:48:32 PM PST 24
Finished Jan 25 02:49:42 PM PST 24
Peak memory 214260 kb
Host smart-d606a600-5667-4413-9574-0a92b1fbd363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217864508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4217864508
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3654279426
Short name T82
Test name
Test status
Simulation time 101833745 ps
CPU time 5.3 seconds
Started Jan 25 02:48:23 PM PST 24
Finished Jan 25 02:48:53 PM PST 24
Peak memory 210592 kb
Host smart-eb8f3882-f274-49d6-a07f-3fcc9200c9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654279426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3654279426
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1557541429
Short name T1010
Test name
Test status
Simulation time 52498903 ps
CPU time 2.52 seconds
Started Jan 25 02:48:24 PM PST 24
Finished Jan 25 02:48:50 PM PST 24
Peak memory 209264 kb
Host smart-1ad81c08-3a59-4ee1-b5da-b71c42a3fd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557541429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1557541429
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2387889706
Short name T653
Test name
Test status
Simulation time 119817391 ps
CPU time 3.23 seconds
Started Jan 25 02:48:32 PM PST 24
Finished Jan 25 02:48:57 PM PST 24
Peak memory 209012 kb
Host smart-58a37f68-5175-4c97-842b-758cc1df61a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387889706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2387889706
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1410068378
Short name T218
Test name
Test status
Simulation time 804030036 ps
CPU time 20.26 seconds
Started Jan 25 02:57:43 PM PST 24
Finished Jan 25 02:58:06 PM PST 24
Peak memory 208420 kb
Host smart-0c78f818-f549-4204-bd37-701dc2dc5233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410068378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1410068378
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3088270486
Short name T877
Test name
Test status
Simulation time 128016848 ps
CPU time 2.42 seconds
Started Jan 25 02:48:24 PM PST 24
Finished Jan 25 02:48:50 PM PST 24
Peak memory 206848 kb
Host smart-6ebe5e16-30bd-4fe6-b964-4132eafb737b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088270486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3088270486
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3235962065
Short name T887
Test name
Test status
Simulation time 130700575 ps
CPU time 5.12 seconds
Started Jan 25 02:48:06 PM PST 24
Finished Jan 25 02:48:44 PM PST 24
Peak memory 208516 kb
Host smart-7fcaa677-0784-4afb-abab-a3b30925d7dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235962065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3235962065
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3058859656
Short name T857
Test name
Test status
Simulation time 1002076488 ps
CPU time 4.89 seconds
Started Jan 25 02:48:30 PM PST 24
Finished Jan 25 02:48:58 PM PST 24
Peak memory 206904 kb
Host smart-91c9fc9a-dffc-49f6-a2c3-d0a19251314b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058859656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3058859656
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2423106052
Short name T250
Test name
Test status
Simulation time 189932727 ps
CPU time 2.57 seconds
Started Jan 25 02:48:24 PM PST 24
Finished Jan 25 02:48:51 PM PST 24
Peak memory 208532 kb
Host smart-be77e07e-8e9b-46bc-bd1d-ed0a5916c035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423106052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2423106052
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3288425610
Short name T553
Test name
Test status
Simulation time 463098715 ps
CPU time 2.78 seconds
Started Jan 25 02:47:58 PM PST 24
Finished Jan 25 02:48:37 PM PST 24
Peak memory 206872 kb
Host smart-e9b55e2b-6c1f-4a04-a114-bcd9be9c9bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288425610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3288425610
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1596417954
Short name T295
Test name
Test status
Simulation time 1060500830 ps
CPU time 15.91 seconds
Started Jan 25 02:48:32 PM PST 24
Finished Jan 25 02:49:10 PM PST 24
Peak memory 215844 kb
Host smart-6d4bddb6-e28e-488e-82c3-a2c9c9bc6ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596417954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1596417954
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2174381093
Short name T389
Test name
Test status
Simulation time 605430403 ps
CPU time 4.47 seconds
Started Jan 25 02:48:30 PM PST 24
Finished Jan 25 02:48:58 PM PST 24
Peak memory 218692 kb
Host smart-1b1a8679-dcdb-4ee3-8651-bf0ec53b814e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174381093 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2174381093
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2388116259
Short name T994
Test name
Test status
Simulation time 39360239 ps
CPU time 2.95 seconds
Started Jan 25 02:48:25 PM PST 24
Finished Jan 25 02:48:52 PM PST 24
Peak memory 208244 kb
Host smart-bb3fa728-e969-44d4-b496-ce1c246cb06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388116259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2388116259
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3690703836
Short name T794
Test name
Test status
Simulation time 44085802 ps
CPU time 2.65 seconds
Started Jan 25 02:48:30 PM PST 24
Finished Jan 25 02:48:56 PM PST 24
Peak memory 209772 kb
Host smart-d8041a55-a7c9-4993-9bf3-134770b9d084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690703836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3690703836
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2258842038
Short name T652
Test name
Test status
Simulation time 16386196 ps
CPU time 0.76 seconds
Started Jan 25 02:45:49 PM PST 24
Finished Jan 25 02:46:13 PM PST 24
Peak memory 205824 kb
Host smart-9dfd92d2-d8a4-4ea0-9741-ea6bebd131ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258842038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2258842038
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1061384168
Short name T616
Test name
Test status
Simulation time 195424197 ps
CPU time 3.77 seconds
Started Jan 25 02:45:00 PM PST 24
Finished Jan 25 02:45:41 PM PST 24
Peak memory 221620 kb
Host smart-eef09391-b78b-4ccd-9c0d-a7a8a1fa9f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061384168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1061384168
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.440343232
Short name T958
Test name
Test status
Simulation time 106378651 ps
CPU time 2.07 seconds
Started Jan 25 02:45:02 PM PST 24
Finished Jan 25 02:45:42 PM PST 24
Peak memory 209428 kb
Host smart-393cd4b7-a7c9-4041-99e8-1b244db504a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440343232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.440343232
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1727028298
Short name T344
Test name
Test status
Simulation time 955536194 ps
CPU time 5.96 seconds
Started Jan 25 02:44:58 PM PST 24
Finished Jan 25 02:45:42 PM PST 24
Peak memory 222472 kb
Host smart-c7c476d9-e783-4cd9-8187-0fe6f39a9068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727028298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1727028298
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2210505062
Short name T235
Test name
Test status
Simulation time 348130275 ps
CPU time 4.28 seconds
Started Jan 25 02:45:00 PM PST 24
Finished Jan 25 02:45:42 PM PST 24
Peak memory 222392 kb
Host smart-f104c0f1-a891-4b17-9675-e71d7213d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210505062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2210505062
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.514223962
Short name T248
Test name
Test status
Simulation time 536128822 ps
CPU time 3.31 seconds
Started Jan 25 02:45:00 PM PST 24
Finished Jan 25 02:45:41 PM PST 24
Peak memory 209544 kb
Host smart-d8a08343-5784-45b6-bea5-9856b0ace0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514223962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.514223962
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3202226659
Short name T726
Test name
Test status
Simulation time 1289515826 ps
CPU time 5.28 seconds
Started Jan 25 02:45:03 PM PST 24
Finished Jan 25 02:45:45 PM PST 24
Peak memory 209092 kb
Host smart-abdc576e-9ca0-42ae-b874-871c5a3f114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202226659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3202226659
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.512509456
Short name T14
Test name
Test status
Simulation time 1193878963 ps
CPU time 28.37 seconds
Started Jan 25 02:45:33 PM PST 24
Finished Jan 25 02:46:29 PM PST 24
Peak memory 243828 kb
Host smart-78ce5559-dd8c-4b90-8387-2dedb5c9cde7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512509456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.512509456
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3918615769
Short name T592
Test name
Test status
Simulation time 103879202 ps
CPU time 3.31 seconds
Started Jan 25 02:45:02 PM PST 24
Finished Jan 25 02:45:43 PM PST 24
Peak memory 207428 kb
Host smart-96b4edc8-b800-416b-adca-ed0d006a7c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918615769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3918615769
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1903527047
Short name T564
Test name
Test status
Simulation time 535875903 ps
CPU time 4.25 seconds
Started Jan 25 02:45:03 PM PST 24
Finished Jan 25 02:45:44 PM PST 24
Peak memory 208460 kb
Host smart-8bfad509-6e26-4d82-bfdf-7aeb0c8e9d04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903527047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1903527047
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4048981873
Short name T247
Test name
Test status
Simulation time 234158740 ps
CPU time 3.32 seconds
Started Jan 25 02:44:57 PM PST 24
Finished Jan 25 02:45:38 PM PST 24
Peak memory 208800 kb
Host smart-49107776-e362-462d-8ee8-f11e1fa9e444
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048981873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4048981873
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2435913908
Short name T610
Test name
Test status
Simulation time 30020942 ps
CPU time 2.18 seconds
Started Jan 25 02:44:59 PM PST 24
Finished Jan 25 02:45:39 PM PST 24
Peak memory 208800 kb
Host smart-f2753b67-4655-46ac-9a7c-be8462ab8c22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435913908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2435913908
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2475270042
Short name T939
Test name
Test status
Simulation time 335091539 ps
CPU time 3.16 seconds
Started Jan 25 02:45:37 PM PST 24
Finished Jan 25 02:46:07 PM PST 24
Peak memory 209508 kb
Host smart-a7bf1343-603b-4b92-a2dd-b6698461bc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475270042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2475270042
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.558282546
Short name T689
Test name
Test status
Simulation time 147048928 ps
CPU time 2.25 seconds
Started Jan 25 02:44:56 PM PST 24
Finished Jan 25 02:45:36 PM PST 24
Peak memory 206512 kb
Host smart-2550c238-6cef-465e-83fb-0f48ac09c913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558282546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.558282546
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1929377657
Short name T824
Test name
Test status
Simulation time 357232850 ps
CPU time 4.16 seconds
Started Jan 25 02:45:00 PM PST 24
Finished Jan 25 02:45:42 PM PST 24
Peak memory 208796 kb
Host smart-183f3054-5d97-4e1a-befc-04c4adb91a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929377657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1929377657
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3947090551
Short name T33
Test name
Test status
Simulation time 311740187 ps
CPU time 3.32 seconds
Started Jan 25 02:45:34 PM PST 24
Finished Jan 25 02:46:05 PM PST 24
Peak memory 209988 kb
Host smart-b822f168-57a8-47bf-a567-0d51ab61a0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947090551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3947090551
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.85106705
Short name T634
Test name
Test status
Simulation time 51150098 ps
CPU time 0.76 seconds
Started Jan 25 02:49:02 PM PST 24
Finished Jan 25 02:49:16 PM PST 24
Peak memory 205920 kb
Host smart-0aca2585-4c36-48da-bb71-8d3baf84467e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85106705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.85106705
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.4106930111
Short name T265
Test name
Test status
Simulation time 113454416 ps
CPU time 3.96 seconds
Started Jan 25 02:48:30 PM PST 24
Finished Jan 25 02:48:57 PM PST 24
Peak memory 215060 kb
Host smart-d215c015-53a7-4c2b-9557-21e9d07477d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106930111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.4106930111
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4276520356
Short name T711
Test name
Test status
Simulation time 152183290 ps
CPU time 3.19 seconds
Started Jan 25 02:48:33 PM PST 24
Finished Jan 25 02:48:58 PM PST 24
Peak memory 214272 kb
Host smart-8998cce1-439c-4333-9bef-b6330ea37b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276520356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4276520356
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.4217633095
Short name T836
Test name
Test status
Simulation time 26582457645 ps
CPU time 152.43 seconds
Started Jan 25 02:48:32 PM PST 24
Finished Jan 25 02:51:26 PM PST 24
Peak memory 209732 kb
Host smart-2de839d6-a98f-45db-a288-80cdba10c329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217633095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.4217633095
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2667509245
Short name T256
Test name
Test status
Simulation time 261677732 ps
CPU time 6.26 seconds
Started Jan 25 02:48:57 PM PST 24
Finished Jan 25 02:49:15 PM PST 24
Peak memory 214148 kb
Host smart-5509173a-876f-498d-953e-d4440b622dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667509245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2667509245
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1134461318
Short name T713
Test name
Test status
Simulation time 116032086 ps
CPU time 3.79 seconds
Started Jan 25 02:48:34 PM PST 24
Finished Jan 25 02:49:01 PM PST 24
Peak memory 214360 kb
Host smart-e6de0277-998b-4996-b7a5-caeb397dc29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134461318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1134461318
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1782972860
Short name T925
Test name
Test status
Simulation time 454919555 ps
CPU time 12.57 seconds
Started Jan 25 02:48:29 PM PST 24
Finished Jan 25 02:49:05 PM PST 24
Peak memory 209008 kb
Host smart-819b7311-494e-45e2-b9a2-6df85575e0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782972860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1782972860
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.568095778
Short name T863
Test name
Test status
Simulation time 142565844 ps
CPU time 5.32 seconds
Started Jan 25 02:48:32 PM PST 24
Finished Jan 25 02:49:00 PM PST 24
Peak memory 208368 kb
Host smart-90121277-18d7-40b4-9bc2-e6ed5b914832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568095778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.568095778
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3157677760
Short name T177
Test name
Test status
Simulation time 167972430 ps
CPU time 2.48 seconds
Started Jan 25 02:48:26 PM PST 24
Finished Jan 25 02:48:53 PM PST 24
Peak memory 206844 kb
Host smart-9fc25447-5615-437e-a78c-0fcab12d10f9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157677760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3157677760
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1133752380
Short name T215
Test name
Test status
Simulation time 23038231 ps
CPU time 1.97 seconds
Started Jan 25 02:48:31 PM PST 24
Finished Jan 25 02:48:55 PM PST 24
Peak memory 207760 kb
Host smart-335b7c25-f86f-4778-9d59-9d57c2529fa2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133752380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1133752380
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.891875835
Short name T659
Test name
Test status
Simulation time 22145914 ps
CPU time 1.85 seconds
Started Jan 25 02:48:32 PM PST 24
Finished Jan 25 02:48:56 PM PST 24
Peak memory 206848 kb
Host smart-99e68352-ce56-4943-bdc3-c59d8f3d118a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891875835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.891875835
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1209321052
Short name T751
Test name
Test status
Simulation time 98070602 ps
CPU time 2.69 seconds
Started Jan 25 02:48:59 PM PST 24
Finished Jan 25 02:49:14 PM PST 24
Peak memory 218024 kb
Host smart-3d19d7aa-2928-40d2-92dd-ea9702380294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209321052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1209321052
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3882607626
Short name T663
Test name
Test status
Simulation time 169155440 ps
CPU time 2.43 seconds
Started Jan 25 02:48:25 PM PST 24
Finished Jan 25 02:48:51 PM PST 24
Peak memory 206912 kb
Host smart-f8c104b7-8b3d-47a9-9889-dfe75b972518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882607626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3882607626
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.4069661454
Short name T67
Test name
Test status
Simulation time 7621025966 ps
CPU time 52.3 seconds
Started Jan 25 02:49:07 PM PST 24
Finished Jan 25 02:50:13 PM PST 24
Peak memory 215536 kb
Host smart-cf46efba-95ac-41a3-8f9a-5986a44a664e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069661454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.4069661454
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1609566215
Short name T615
Test name
Test status
Simulation time 1332719646 ps
CPU time 6.29 seconds
Started Jan 25 02:49:07 PM PST 24
Finished Jan 25 02:49:27 PM PST 24
Peak memory 222548 kb
Host smart-4c34099e-ba0f-425f-8205-0a5b896ff05f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609566215 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1609566215
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3128035463
Short name T335
Test name
Test status
Simulation time 228145070 ps
CPU time 3.04 seconds
Started Jan 25 02:48:22 PM PST 24
Finished Jan 25 02:48:50 PM PST 24
Peak memory 209360 kb
Host smart-11a9ba4f-1a47-4919-bf3f-fd312b249806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128035463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3128035463
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.857452903
Short name T152
Test name
Test status
Simulation time 75251614 ps
CPU time 2.06 seconds
Started Jan 25 02:48:54 PM PST 24
Finished Jan 25 02:49:10 PM PST 24
Peak memory 210516 kb
Host smart-00b54da0-b552-4b76-86c7-1efd9265bf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857452903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.857452903
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.237610826
Short name T761
Test name
Test status
Simulation time 7953822 ps
CPU time 0.7 seconds
Started Jan 25 02:49:07 PM PST 24
Finished Jan 25 02:49:21 PM PST 24
Peak memory 205828 kb
Host smart-969e8260-a460-4bf8-9a90-45ba0d987599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237610826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.237610826
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3796872652
Short name T381
Test name
Test status
Simulation time 264335695 ps
CPU time 13.94 seconds
Started Jan 25 02:48:53 PM PST 24
Finished Jan 25 02:49:21 PM PST 24
Peak memory 215488 kb
Host smart-9508a05f-9bec-45f0-84d1-da5bb1b7079d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796872652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3796872652
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2406826835
Short name T609
Test name
Test status
Simulation time 94555201 ps
CPU time 1.89 seconds
Started Jan 25 02:49:03 PM PST 24
Finished Jan 25 02:49:19 PM PST 24
Peak memory 209600 kb
Host smart-6458a4a9-d0d8-4b40-b56f-8295c3d04b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406826835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2406826835
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3387119932
Short name T913
Test name
Test status
Simulation time 349166907 ps
CPU time 6.15 seconds
Started Jan 25 02:49:05 PM PST 24
Finished Jan 25 02:49:25 PM PST 24
Peak memory 219464 kb
Host smart-33e00a1c-8c06-40b2-915e-95a824c369eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387119932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3387119932
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.4092661222
Short name T278
Test name
Test status
Simulation time 746528415 ps
CPU time 7.66 seconds
Started Jan 25 02:49:04 PM PST 24
Finished Jan 25 02:49:26 PM PST 24
Peak memory 214144 kb
Host smart-306b6496-3f43-46c6-906f-35b075a5accd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092661222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.4092661222
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3464893581
Short name T51
Test name
Test status
Simulation time 950221202 ps
CPU time 5.53 seconds
Started Jan 25 02:49:02 PM PST 24
Finished Jan 25 02:49:21 PM PST 24
Peak memory 219632 kb
Host smart-747acc4e-b6eb-4dee-82bf-cf9f4897c463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464893581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3464893581
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2884179692
Short name T207
Test name
Test status
Simulation time 151010869 ps
CPU time 2.7 seconds
Started Jan 25 02:49:05 PM PST 24
Finished Jan 25 02:49:21 PM PST 24
Peak memory 206788 kb
Host smart-3da3b59f-1bfe-4092-aa9d-345c877f1fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884179692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2884179692
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2815125154
Short name T911
Test name
Test status
Simulation time 43118806 ps
CPU time 2.22 seconds
Started Jan 25 02:48:59 PM PST 24
Finished Jan 25 02:49:13 PM PST 24
Peak memory 208252 kb
Host smart-ac01b22a-81d1-4a6b-9b48-cd8f2d8ebb4f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815125154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2815125154
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1070309552
Short name T811
Test name
Test status
Simulation time 90761804 ps
CPU time 3.71 seconds
Started Jan 25 02:48:59 PM PST 24
Finished Jan 25 02:49:15 PM PST 24
Peak memory 208608 kb
Host smart-11e63a95-c49b-4e6e-a037-319376e1280e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070309552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1070309552
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1233245254
Short name T675
Test name
Test status
Simulation time 55561375 ps
CPU time 2.97 seconds
Started Jan 25 02:49:02 PM PST 24
Finished Jan 25 02:49:18 PM PST 24
Peak memory 206920 kb
Host smart-49e4df04-fa3b-4bb9-92f7-823a9b831da5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233245254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1233245254
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3596308488
Short name T1056
Test name
Test status
Simulation time 1700433929 ps
CPU time 10.93 seconds
Started Jan 25 02:49:07 PM PST 24
Finished Jan 25 02:49:32 PM PST 24
Peak memory 209760 kb
Host smart-c2786d98-090e-44b5-9d14-2b0d930c1825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596308488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3596308488
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2100385634
Short name T593
Test name
Test status
Simulation time 647114344 ps
CPU time 4.62 seconds
Started Jan 25 02:49:07 PM PST 24
Finished Jan 25 02:49:26 PM PST 24
Peak memory 208500 kb
Host smart-d05fe040-ad14-4ae7-a6e5-b93a20174018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100385634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2100385634
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2411965111
Short name T294
Test name
Test status
Simulation time 3847034068 ps
CPU time 40.78 seconds
Started Jan 25 02:49:02 PM PST 24
Finished Jan 25 02:49:56 PM PST 24
Peak memory 216564 kb
Host smart-0f591b55-dd6c-484f-9ed0-70c987968230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411965111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2411965111
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.1800865208
Short name T98
Test name
Test status
Simulation time 483399837 ps
CPU time 2.93 seconds
Started Jan 25 02:48:54 PM PST 24
Finished Jan 25 02:49:11 PM PST 24
Peak memory 222580 kb
Host smart-e3844c17-132d-4490-bc53-72bfb865a66c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800865208 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.1800865208
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.952001898
Short name T269
Test name
Test status
Simulation time 246180597 ps
CPU time 3.75 seconds
Started Jan 25 02:49:05 PM PST 24
Finished Jan 25 02:49:22 PM PST 24
Peak memory 209328 kb
Host smart-6f6ecc5d-7850-4549-a2a9-42dfd7c96c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952001898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.952001898
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1071339429
Short name T967
Test name
Test status
Simulation time 673081049 ps
CPU time 2.31 seconds
Started Jan 25 02:49:08 PM PST 24
Finished Jan 25 02:49:25 PM PST 24
Peak memory 210240 kb
Host smart-d1177cd7-d175-48dc-8b68-729d837e449d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071339429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1071339429
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3492518244
Short name T753
Test name
Test status
Simulation time 110667436 ps
CPU time 0.75 seconds
Started Jan 25 02:49:02 PM PST 24
Finished Jan 25 02:49:16 PM PST 24
Peak memory 205924 kb
Host smart-85a3c4e4-7a0a-4664-b163-c2df1df15990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492518244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3492518244
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1011143992
Short name T273
Test name
Test status
Simulation time 118343869 ps
CPU time 2.57 seconds
Started Jan 25 02:49:00 PM PST 24
Finished Jan 25 02:49:15 PM PST 24
Peak memory 214272 kb
Host smart-e201210b-2fb9-48da-8069-09a02099cffd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011143992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1011143992
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1648217501
Short name T985
Test name
Test status
Simulation time 799970300 ps
CPU time 4.64 seconds
Started Jan 25 02:48:55 PM PST 24
Finished Jan 25 02:49:13 PM PST 24
Peak memory 208360 kb
Host smart-938f8e50-dcdd-42f8-be08-6bc2d0e4ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648217501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1648217501
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2168090869
Short name T738
Test name
Test status
Simulation time 854717615 ps
CPU time 21.17 seconds
Started Jan 25 02:49:07 PM PST 24
Finished Jan 25 02:49:41 PM PST 24
Peak memory 214344 kb
Host smart-51c4ae94-3435-4b6f-8e20-5e38b4d717ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168090869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2168090869
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.4116003064
Short name T360
Test name
Test status
Simulation time 5241263211 ps
CPU time 61.74 seconds
Started Jan 25 02:49:03 PM PST 24
Finished Jan 25 02:50:18 PM PST 24
Peak memory 222400 kb
Host smart-637a0300-874e-43dd-9faa-29005ed4c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116003064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.4116003064
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1164250794
Short name T765
Test name
Test status
Simulation time 104607293 ps
CPU time 3.36 seconds
Started Jan 25 02:49:02 PM PST 24
Finished Jan 25 02:49:18 PM PST 24
Peak memory 206096 kb
Host smart-a75239b4-5a40-4b6c-b7cd-61b932af6707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164250794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1164250794
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.468093365
Short name T748
Test name
Test status
Simulation time 613843537 ps
CPU time 3.95 seconds
Started Jan 25 02:49:07 PM PST 24
Finished Jan 25 02:49:25 PM PST 24
Peak memory 207864 kb
Host smart-c323d5da-8424-48b3-904b-07cf21def0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468093365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.468093365
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.123786267
Short name T947
Test name
Test status
Simulation time 118765174 ps
CPU time 2.25 seconds
Started Jan 25 02:49:04 PM PST 24
Finished Jan 25 02:49:20 PM PST 24
Peak memory 206628 kb
Host smart-abc74d2a-7a4c-4456-b7b5-d100cf70ab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123786267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.123786267
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2071281220
Short name T655
Test name
Test status
Simulation time 187760077 ps
CPU time 5.4 seconds
Started Jan 25 02:49:04 PM PST 24
Finished Jan 25 02:49:24 PM PST 24
Peak memory 207612 kb
Host smart-3dcab563-dd25-4cdb-aab5-f3ab96896c67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071281220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2071281220
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1435886700
Short name T690
Test name
Test status
Simulation time 121290972 ps
CPU time 4.14 seconds
Started Jan 25 02:48:59 PM PST 24
Finished Jan 25 02:49:16 PM PST 24
Peak memory 207896 kb
Host smart-c91f3157-4b1a-40a8-9c9d-bab295a881ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435886700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1435886700
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.200039174
Short name T282
Test name
Test status
Simulation time 28647617 ps
CPU time 2.16 seconds
Started Jan 25 02:48:59 PM PST 24
Finished Jan 25 02:49:14 PM PST 24
Peak memory 208648 kb
Host smart-564be980-2d1a-4ada-b40a-cf5e1578ea82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200039174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.200039174
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3001093592
Short name T1006
Test name
Test status
Simulation time 336165340 ps
CPU time 2.55 seconds
Started Jan 25 02:49:02 PM PST 24
Finished Jan 25 02:49:18 PM PST 24
Peak memory 208080 kb
Host smart-848853c7-5dd7-4442-bb2a-e82f6c29fb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001093592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3001093592
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1566217806
Short name T560
Test name
Test status
Simulation time 104506847 ps
CPU time 3.55 seconds
Started Jan 25 02:49:02 PM PST 24
Finished Jan 25 02:49:19 PM PST 24
Peak memory 206764 kb
Host smart-c4135932-3ff6-4ba0-add3-33f9648d8f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566217806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1566217806
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3259995695
Short name T820
Test name
Test status
Simulation time 1258048731 ps
CPU time 12.48 seconds
Started Jan 25 02:49:03 PM PST 24
Finished Jan 25 02:49:29 PM PST 24
Peak memory 206684 kb
Host smart-55300e89-f470-4ebe-80c2-beccb3d529a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259995695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3259995695
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2575229787
Short name T271
Test name
Test status
Simulation time 183459269 ps
CPU time 5.45 seconds
Started Jan 25 02:48:53 PM PST 24
Finished Jan 25 02:49:12 PM PST 24
Peak memory 207776 kb
Host smart-68d17ad5-fbb9-4f62-870f-ce274b4c33f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575229787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2575229787
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.397991230
Short name T36
Test name
Test status
Simulation time 121603489 ps
CPU time 1.99 seconds
Started Jan 25 02:49:04 PM PST 24
Finished Jan 25 02:49:20 PM PST 24
Peak memory 210560 kb
Host smart-48ae520a-0582-4abe-9246-9e3d6196df78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397991230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.397991230
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.939316450
Short name T102
Test name
Test status
Simulation time 156998275 ps
CPU time 0.76 seconds
Started Jan 25 02:49:28 PM PST 24
Finished Jan 25 02:49:48 PM PST 24
Peak memory 205852 kb
Host smart-7def1e88-4316-4849-95f3-7fde2bad9973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939316450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.939316450
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3763692534
Short name T384
Test name
Test status
Simulation time 152905421 ps
CPU time 2.48 seconds
Started Jan 25 02:49:07 PM PST 24
Finished Jan 25 02:49:23 PM PST 24
Peak memory 214256 kb
Host smart-28ec5f03-f07a-45df-9e18-3c038a3a931b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3763692534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3763692534
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.665568302
Short name T72
Test name
Test status
Simulation time 266236422 ps
CPU time 4.32 seconds
Started Jan 25 02:49:07 PM PST 24
Finished Jan 25 02:49:25 PM PST 24
Peak memory 218064 kb
Host smart-9d06657a-e2f1-483e-9991-faeb658edf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665568302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.665568302
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4108850264
Short name T285
Test name
Test status
Simulation time 226995610 ps
CPU time 3.79 seconds
Started Jan 25 02:49:25 PM PST 24
Finished Jan 25 02:49:47 PM PST 24
Peak memory 214252 kb
Host smart-829e5e8a-4cc4-46b1-a6b9-fcc97d440f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108850264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4108850264
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1027506811
Short name T950
Test name
Test status
Simulation time 117399079 ps
CPU time 4.63 seconds
Started Jan 25 02:49:36 PM PST 24
Finished Jan 25 02:50:06 PM PST 24
Peak memory 210800 kb
Host smart-dafcfdb8-c0c8-47f0-85a0-671c1461ac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027506811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1027506811
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2532096076
Short name T53
Test name
Test status
Simulation time 48653771 ps
CPU time 2.44 seconds
Started Jan 25 02:49:34 PM PST 24
Finished Jan 25 02:50:00 PM PST 24
Peak memory 215292 kb
Host smart-9d8ccf24-0682-4d87-83a1-8665441dadca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532096076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2532096076
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3771233020
Short name T296
Test name
Test status
Simulation time 388605360 ps
CPU time 5.2 seconds
Started Jan 25 02:49:04 PM PST 24
Finished Jan 25 02:49:23 PM PST 24
Peak memory 206600 kb
Host smart-000d2e91-5350-4236-9644-1e7723c74f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771233020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3771233020
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2303274369
Short name T948
Test name
Test status
Simulation time 470392990 ps
CPU time 2.87 seconds
Started Jan 25 02:49:18 PM PST 24
Finished Jan 25 02:49:37 PM PST 24
Peak memory 206852 kb
Host smart-55930ac2-18c3-47bc-bf68-b54eac935516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303274369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2303274369
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2467934796
Short name T656
Test name
Test status
Simulation time 811596832 ps
CPU time 6.92 seconds
Started Jan 25 02:49:02 PM PST 24
Finished Jan 25 02:49:22 PM PST 24
Peak memory 208300 kb
Host smart-eeb81b69-4822-4d71-acb5-eb34f85da280
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467934796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2467934796
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3544898571
Short name T795
Test name
Test status
Simulation time 57114661 ps
CPU time 2.21 seconds
Started Jan 25 02:49:00 PM PST 24
Finished Jan 25 02:49:15 PM PST 24
Peak memory 206852 kb
Host smart-6bcdf09a-f041-45d4-8984-7d202d8aa49e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544898571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3544898571
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3739838755
Short name T1027
Test name
Test status
Simulation time 25191677 ps
CPU time 1.94 seconds
Started Jan 25 02:49:07 PM PST 24
Finished Jan 25 02:49:23 PM PST 24
Peak memory 207568 kb
Host smart-61b126af-88dc-42dd-8a00-abdfd61e83b8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739838755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3739838755
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1016178807
Short name T1000
Test name
Test status
Simulation time 3740834884 ps
CPU time 33.56 seconds
Started Jan 25 02:49:04 PM PST 24
Finished Jan 25 02:49:51 PM PST 24
Peak memory 208412 kb
Host smart-46f7ddab-1287-4496-9e50-52b3cb25172c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016178807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1016178807
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.933014480
Short name T220
Test name
Test status
Simulation time 2173826522 ps
CPU time 68.4 seconds
Started Jan 25 02:49:34 PM PST 24
Finished Jan 25 02:51:06 PM PST 24
Peak memory 219692 kb
Host smart-05b06610-b8ba-4efb-9ec7-6ddb856a3e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933014480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.933014480
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3832160720
Short name T1052
Test name
Test status
Simulation time 301489088 ps
CPU time 3.76 seconds
Started Jan 25 02:49:33 PM PST 24
Finished Jan 25 02:49:59 PM PST 24
Peak memory 210672 kb
Host smart-e2737076-7e14-4051-a77a-0dbf2b8d3de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832160720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3832160720
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3651541861
Short name T846
Test name
Test status
Simulation time 25937400 ps
CPU time 1.12 seconds
Started Jan 25 02:49:26 PM PST 24
Finished Jan 25 02:49:47 PM PST 24
Peak memory 206272 kb
Host smart-577816c4-1307-44cb-b2d7-8845cb0447e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651541861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3651541861
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.358677394
Short name T1064
Test name
Test status
Simulation time 71882561 ps
CPU time 4.42 seconds
Started Jan 25 02:49:30 PM PST 24
Finished Jan 25 02:49:56 PM PST 24
Peak memory 214240 kb
Host smart-8d2957ae-3e45-4835-8d0d-107d96e1b037
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=358677394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.358677394
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3477080490
Short name T880
Test name
Test status
Simulation time 300077653 ps
CPU time 5.58 seconds
Started Jan 25 02:49:23 PM PST 24
Finished Jan 25 02:49:46 PM PST 24
Peak memory 214624 kb
Host smart-92911290-dcb0-4594-bd93-026d0b5d7e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477080490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3477080490
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2554574365
Short name T71
Test name
Test status
Simulation time 54058937 ps
CPU time 2.58 seconds
Started Jan 25 02:49:27 PM PST 24
Finished Jan 25 02:49:48 PM PST 24
Peak memory 214384 kb
Host smart-7fd71b37-d16b-48ba-bd2b-830721731505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554574365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2554574365
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.4285045671
Short name T1030
Test name
Test status
Simulation time 85884649 ps
CPU time 3.58 seconds
Started Jan 25 02:49:29 PM PST 24
Finished Jan 25 02:49:53 PM PST 24
Peak memory 214880 kb
Host smart-656255c1-8745-498c-be4f-0f56b4fceec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285045671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.4285045671
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.4293459989
Short name T733
Test name
Test status
Simulation time 1545676344 ps
CPU time 8.07 seconds
Started Jan 25 02:49:29 PM PST 24
Finished Jan 25 02:49:57 PM PST 24
Peak memory 214180 kb
Host smart-cd10b21b-4236-4ea5-a54c-419af7c8f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293459989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.4293459989
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.4147713242
Short name T691
Test name
Test status
Simulation time 350802661 ps
CPU time 9.9 seconds
Started Jan 25 02:49:35 PM PST 24
Finished Jan 25 02:50:11 PM PST 24
Peak memory 208924 kb
Host smart-5fcc62f4-4927-46cc-aa76-f9902af859ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147713242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.4147713242
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1962738914
Short name T287
Test name
Test status
Simulation time 791547990 ps
CPU time 5.14 seconds
Started Jan 25 02:49:33 PM PST 24
Finished Jan 25 02:50:00 PM PST 24
Peak memory 208612 kb
Host smart-952f6e12-24bd-4a17-8ad1-ce754567296a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962738914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1962738914
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1211923584
Short name T209
Test name
Test status
Simulation time 438512578 ps
CPU time 3.93 seconds
Started Jan 25 02:49:32 PM PST 24
Finished Jan 25 02:49:57 PM PST 24
Peak memory 208552 kb
Host smart-04f47f4b-a124-480a-9998-25d9c1be4bb4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211923584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1211923584
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.651900666
Short name T704
Test name
Test status
Simulation time 254019931 ps
CPU time 3.78 seconds
Started Jan 25 02:49:26 PM PST 24
Finished Jan 25 02:49:50 PM PST 24
Peak memory 208016 kb
Host smart-dba4b54c-04ac-4b3e-8592-328613054e5c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651900666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.651900666
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3969217971
Short name T607
Test name
Test status
Simulation time 222847820 ps
CPU time 2.78 seconds
Started Jan 25 02:49:29 PM PST 24
Finished Jan 25 02:49:52 PM PST 24
Peak memory 208664 kb
Host smart-fce0418b-1848-4168-bcbc-b3960495557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969217971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3969217971
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3366393033
Short name T572
Test name
Test status
Simulation time 86843468 ps
CPU time 3.39 seconds
Started Jan 25 02:49:33 PM PST 24
Finished Jan 25 02:49:58 PM PST 24
Peak memory 208296 kb
Host smart-2ae123b8-e132-4034-9ea6-755a02ab7767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366393033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3366393033
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.377796102
Short name T199
Test name
Test status
Simulation time 244745312 ps
CPU time 10.45 seconds
Started Jan 25 02:49:25 PM PST 24
Finished Jan 25 02:49:54 PM PST 24
Peak memory 219924 kb
Host smart-e31b4d42-53fc-4cbc-b3bb-a8df70c95e92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377796102 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.377796102
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2635578406
Short name T712
Test name
Test status
Simulation time 289492876 ps
CPU time 9.69 seconds
Started Jan 25 02:49:34 PM PST 24
Finished Jan 25 02:50:08 PM PST 24
Peak memory 208488 kb
Host smart-ab8df282-ff4f-45d0-b88d-7e97a8f2b051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635578406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2635578406
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1151193851
Short name T543
Test name
Test status
Simulation time 54578178 ps
CPU time 1.5 seconds
Started Jan 25 02:49:26 PM PST 24
Finished Jan 25 02:49:47 PM PST 24
Peak memory 209936 kb
Host smart-c43f7464-8622-44c3-a3b9-4110e207c796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151193851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1151193851
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1132807278
Short name T556
Test name
Test status
Simulation time 18279468 ps
CPU time 0.8 seconds
Started Jan 25 02:49:33 PM PST 24
Finished Jan 25 02:49:55 PM PST 24
Peak memory 205864 kb
Host smart-f4bdc62e-c398-4820-8e72-3a1ab3968b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132807278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1132807278
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1423392894
Short name T676
Test name
Test status
Simulation time 68710155 ps
CPU time 1.83 seconds
Started Jan 25 02:49:23 PM PST 24
Finished Jan 25 02:49:43 PM PST 24
Peak memory 209036 kb
Host smart-857987f5-85c6-464f-aae6-b76944c198a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423392894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1423392894
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2483335721
Short name T290
Test name
Test status
Simulation time 70593308 ps
CPU time 3.49 seconds
Started Jan 25 02:49:26 PM PST 24
Finished Jan 25 02:49:49 PM PST 24
Peak memory 214288 kb
Host smart-2599b677-8b83-4fb1-acf1-2043131363c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483335721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2483335721
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2505802361
Short name T963
Test name
Test status
Simulation time 61832096 ps
CPU time 3.81 seconds
Started Jan 25 02:49:31 PM PST 24
Finished Jan 25 02:49:56 PM PST 24
Peak memory 210196 kb
Host smart-4e9f341d-1cdd-49aa-913b-0faa3b4cbfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505802361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2505802361
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1023657886
Short name T767
Test name
Test status
Simulation time 232484602 ps
CPU time 2.39 seconds
Started Jan 25 02:49:34 PM PST 24
Finished Jan 25 02:50:00 PM PST 24
Peak memory 209136 kb
Host smart-93d425a9-66cc-46df-92f5-ea637ea0657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023657886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1023657886
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.958569427
Short name T576
Test name
Test status
Simulation time 142429234 ps
CPU time 5.24 seconds
Started Jan 25 02:49:32 PM PST 24
Finished Jan 25 02:49:58 PM PST 24
Peak memory 209240 kb
Host smart-54a1bd39-8196-4ed0-b229-e05a2285b57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958569427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.958569427
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.298104533
Short name T99
Test name
Test status
Simulation time 4129579053 ps
CPU time 22.78 seconds
Started Jan 25 02:49:36 PM PST 24
Finished Jan 25 02:50:24 PM PST 24
Peak memory 208516 kb
Host smart-fbe47129-4a7d-4d28-9ce2-51354b56e6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298104533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.298104533
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2080746258
Short name T951
Test name
Test status
Simulation time 25657753 ps
CPU time 1.82 seconds
Started Jan 25 02:49:33 PM PST 24
Finished Jan 25 02:49:57 PM PST 24
Peak memory 206892 kb
Host smart-22e337ab-44b9-42d8-95f7-698269adf2f4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080746258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2080746258
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2575357742
Short name T591
Test name
Test status
Simulation time 57683131 ps
CPU time 2.75 seconds
Started Jan 25 02:49:23 PM PST 24
Finished Jan 25 02:49:44 PM PST 24
Peak memory 206696 kb
Host smart-fdb4e17f-34e7-481c-8244-d7d2ea3f1e3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575357742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2575357742
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.4285568829
Short name T179
Test name
Test status
Simulation time 53879061 ps
CPU time 2.97 seconds
Started Jan 25 02:49:32 PM PST 24
Finished Jan 25 02:49:56 PM PST 24
Peak memory 208372 kb
Host smart-2ec916f3-0db5-42b8-821a-047a4a4092fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285568829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4285568829
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1809248318
Short name T342
Test name
Test status
Simulation time 607562321 ps
CPU time 2.99 seconds
Started Jan 25 02:49:26 PM PST 24
Finished Jan 25 02:49:48 PM PST 24
Peak memory 209748 kb
Host smart-7e13dc9f-166c-4b1a-89a9-593f546c3f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809248318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1809248318
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2024676801
Short name T906
Test name
Test status
Simulation time 103733251 ps
CPU time 2.62 seconds
Started Jan 25 02:49:34 PM PST 24
Finished Jan 25 02:50:01 PM PST 24
Peak memory 206720 kb
Host smart-c6b6a896-88bd-4e80-a652-df0b77aa915f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024676801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2024676801
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.4237185689
Short name T97
Test name
Test status
Simulation time 1076452924 ps
CPU time 35.61 seconds
Started Jan 25 02:49:34 PM PST 24
Finished Jan 25 02:50:33 PM PST 24
Peak memory 222068 kb
Host smart-b1627c84-604d-487e-b7d4-b895762d2ede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237185689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4237185689
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1909870427
Short name T597
Test name
Test status
Simulation time 710607025 ps
CPU time 11.33 seconds
Started Jan 25 02:49:30 PM PST 24
Finished Jan 25 02:50:01 PM PST 24
Peak memory 222588 kb
Host smart-a283f0f9-4b9c-470a-ac6b-ca4fce6a40a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909870427 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1909870427
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1176999392
Short name T223
Test name
Test status
Simulation time 117304874 ps
CPU time 4.54 seconds
Started Jan 25 02:49:36 PM PST 24
Finished Jan 25 02:50:06 PM PST 24
Peak memory 209268 kb
Host smart-f15b3f58-8001-4544-a669-1dd003c92537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176999392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1176999392
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3964579335
Short name T105
Test name
Test status
Simulation time 61579592 ps
CPU time 2.21 seconds
Started Jan 25 02:49:34 PM PST 24
Finished Jan 25 02:50:00 PM PST 24
Peak memory 210336 kb
Host smart-ae537c81-91d6-4e33-a2fb-7fa3be02c652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964579335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3964579335
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.771870067
Short name T755
Test name
Test status
Simulation time 61537485 ps
CPU time 0.72 seconds
Started Jan 25 02:49:40 PM PST 24
Finished Jan 25 02:50:06 PM PST 24
Peak memory 205900 kb
Host smart-39b7d27d-be4f-4e92-9716-9b351c932368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771870067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.771870067
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1019895068
Short name T399
Test name
Test status
Simulation time 180126514 ps
CPU time 3.22 seconds
Started Jan 25 02:49:29 PM PST 24
Finished Jan 25 02:49:52 PM PST 24
Peak memory 214908 kb
Host smart-c1d89e36-08cf-478d-bc18-42e68eb53983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019895068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1019895068
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.503641207
Short name T642
Test name
Test status
Simulation time 660714159 ps
CPU time 4.55 seconds
Started Jan 25 02:49:31 PM PST 24
Finished Jan 25 02:49:57 PM PST 24
Peak memory 222776 kb
Host smart-a804ae42-6063-43aa-aa7f-02f585991501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503641207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.503641207
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3683841575
Short name T944
Test name
Test status
Simulation time 231014831 ps
CPU time 3.79 seconds
Started Jan 25 02:49:30 PM PST 24
Finished Jan 25 02:49:54 PM PST 24
Peak memory 206876 kb
Host smart-3fadd7c4-e87c-4d92-b7cf-76a2168ec09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683841575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3683841575
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.792855443
Short name T923
Test name
Test status
Simulation time 954340953 ps
CPU time 11.27 seconds
Started Jan 25 02:49:35 PM PST 24
Finished Jan 25 02:50:12 PM PST 24
Peak memory 209564 kb
Host smart-ca256b06-b46d-4eee-92cf-4968066a4089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792855443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.792855443
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1532385778
Short name T882
Test name
Test status
Simulation time 108696710 ps
CPU time 5.79 seconds
Started Jan 25 02:49:30 PM PST 24
Finished Jan 25 02:49:56 PM PST 24
Peak memory 214268 kb
Host smart-9b1c8771-970f-400a-8050-24739f527e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532385778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1532385778
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1514439782
Short name T693
Test name
Test status
Simulation time 290608631 ps
CPU time 3.93 seconds
Started Jan 25 02:49:36 PM PST 24
Finished Jan 25 02:50:05 PM PST 24
Peak memory 209016 kb
Host smart-67563992-3dd6-473c-a5d2-eca074c7ec7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514439782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1514439782
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.574891531
Short name T628
Test name
Test status
Simulation time 132463414 ps
CPU time 2.43 seconds
Started Jan 25 02:49:31 PM PST 24
Finished Jan 25 02:49:54 PM PST 24
Peak memory 206728 kb
Host smart-f97850f5-5e04-4354-b6f8-11219a31502d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574891531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.574891531
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.92759469
Short name T1042
Test name
Test status
Simulation time 632303017 ps
CPU time 4.38 seconds
Started Jan 25 02:49:29 PM PST 24
Finished Jan 25 02:49:53 PM PST 24
Peak memory 206756 kb
Host smart-98d1b7cc-e407-422b-8fc4-08df71c8a4e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92759469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.92759469
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2316767024
Short name T667
Test name
Test status
Simulation time 118256140 ps
CPU time 4.72 seconds
Started Jan 25 02:49:30 PM PST 24
Finished Jan 25 02:49:55 PM PST 24
Peak memory 208588 kb
Host smart-b186704c-5e29-47d6-b86d-7bd2ab68a420
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316767024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2316767024
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2442977523
Short name T1055
Test name
Test status
Simulation time 231119524 ps
CPU time 7.9 seconds
Started Jan 25 02:49:30 PM PST 24
Finished Jan 25 02:49:58 PM PST 24
Peak memory 207956 kb
Host smart-259e1635-ff56-4c65-96e7-f6096da9a69b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442977523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2442977523
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1799623450
Short name T587
Test name
Test status
Simulation time 52536295 ps
CPU time 2.66 seconds
Started Jan 25 02:49:31 PM PST 24
Finished Jan 25 02:49:55 PM PST 24
Peak memory 209456 kb
Host smart-2fb4d26b-5377-4992-9f1c-0ca2d67c3c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799623450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1799623450
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2197238225
Short name T922
Test name
Test status
Simulation time 133691630 ps
CPU time 2 seconds
Started Jan 25 02:49:32 PM PST 24
Finished Jan 25 02:49:56 PM PST 24
Peak memory 208504 kb
Host smart-7d6aff99-7e9b-41ff-ba09-5debec407685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197238225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2197238225
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1576262321
Short name T941
Test name
Test status
Simulation time 460282288 ps
CPU time 9.53 seconds
Started Jan 25 02:49:35 PM PST 24
Finished Jan 25 02:50:10 PM PST 24
Peak memory 220304 kb
Host smart-7ce688be-f71a-4ac1-9bcc-759c9f4df176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576262321 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1576262321
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.307669863
Short name T823
Test name
Test status
Simulation time 456926408 ps
CPU time 9.14 seconds
Started Jan 25 02:49:34 PM PST 24
Finished Jan 25 02:50:07 PM PST 24
Peak memory 208188 kb
Host smart-c7376022-3ab1-439a-b624-619e89532996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307669863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.307669863
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.628163693
Short name T779
Test name
Test status
Simulation time 45817009 ps
CPU time 2.6 seconds
Started Jan 25 02:49:29 PM PST 24
Finished Jan 25 02:49:51 PM PST 24
Peak memory 210020 kb
Host smart-333839ba-8a47-42fc-8bf5-7997a024ec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628163693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.628163693
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.922709409
Short name T661
Test name
Test status
Simulation time 25087591 ps
CPU time 0.7 seconds
Started Jan 25 02:49:49 PM PST 24
Finished Jan 25 02:50:13 PM PST 24
Peak memory 205916 kb
Host smart-2d635936-4783-490e-816c-5007432904ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922709409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.922709409
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4263069796
Short name T110
Test name
Test status
Simulation time 54077787 ps
CPU time 3.47 seconds
Started Jan 25 02:49:37 PM PST 24
Finished Jan 25 02:50:07 PM PST 24
Peak memory 222460 kb
Host smart-85f21a6a-ce04-46f1-8e9c-742f3c7f6ea6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263069796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4263069796
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3508750891
Short name T299
Test name
Test status
Simulation time 436686800 ps
CPU time 4.26 seconds
Started Jan 25 02:49:36 PM PST 24
Finished Jan 25 02:50:06 PM PST 24
Peak memory 218152 kb
Host smart-6f1e51eb-db1d-400e-9e3b-8c6d27d5208e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508750891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3508750891
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2957762211
Short name T929
Test name
Test status
Simulation time 686052720 ps
CPU time 5.59 seconds
Started Jan 25 02:49:40 PM PST 24
Finished Jan 25 02:50:11 PM PST 24
Peak memory 207892 kb
Host smart-dbea86cd-acd4-462c-95c6-e1a6e011a3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957762211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2957762211
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3543321099
Short name T1037
Test name
Test status
Simulation time 776215766 ps
CPU time 27.92 seconds
Started Jan 25 02:49:24 PM PST 24
Finished Jan 25 02:50:11 PM PST 24
Peak memory 222564 kb
Host smart-53c2d2ee-a11a-4469-9027-5f1b97cb35d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543321099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3543321099
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_random.2133564042
Short name T388
Test name
Test status
Simulation time 317696920 ps
CPU time 7.44 seconds
Started Jan 25 02:49:41 PM PST 24
Finished Jan 25 02:50:13 PM PST 24
Peak memory 208456 kb
Host smart-190ca632-bf7d-4535-ab09-dd7c1686e3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133564042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2133564042
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.808597757
Short name T604
Test name
Test status
Simulation time 3401570237 ps
CPU time 12.9 seconds
Started Jan 25 02:49:35 PM PST 24
Finished Jan 25 02:50:13 PM PST 24
Peak memory 208496 kb
Host smart-2c95d176-4559-4f77-a8ee-6cec4559e034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808597757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.808597757
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1436372139
Short name T231
Test name
Test status
Simulation time 230266170 ps
CPU time 2.87 seconds
Started Jan 25 02:49:29 PM PST 24
Finished Jan 25 02:49:52 PM PST 24
Peak memory 208724 kb
Host smart-8dbadc00-a532-4a81-899d-e779c6557e8c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436372139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1436372139
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.270687661
Short name T869
Test name
Test status
Simulation time 37807686 ps
CPU time 1.71 seconds
Started Jan 25 02:49:29 PM PST 24
Finished Jan 25 02:49:51 PM PST 24
Peak memory 206416 kb
Host smart-11e055d6-8e22-4cf5-b575-31f7902eefde
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270687661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.270687661
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4154929218
Short name T763
Test name
Test status
Simulation time 176710513 ps
CPU time 3.44 seconds
Started Jan 25 02:49:31 PM PST 24
Finished Jan 25 02:49:55 PM PST 24
Peak memory 206808 kb
Host smart-0e7b9294-db24-47e3-8810-dafd6508e3c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154929218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4154929218
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.435338713
Short name T1059
Test name
Test status
Simulation time 207039253 ps
CPU time 2.59 seconds
Started Jan 25 02:49:28 PM PST 24
Finished Jan 25 02:49:50 PM PST 24
Peak memory 209412 kb
Host smart-c5d16b28-6c32-4826-9aa9-d4b9d96bc83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435338713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.435338713
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3088215821
Short name T1053
Test name
Test status
Simulation time 220528203 ps
CPU time 4.49 seconds
Started Jan 25 02:49:39 PM PST 24
Finished Jan 25 02:50:08 PM PST 24
Peak memory 208132 kb
Host smart-6f7af734-9282-4d1e-b50b-b7b2bad0d2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088215821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3088215821
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2619636887
Short name T194
Test name
Test status
Simulation time 1167995874 ps
CPU time 19.21 seconds
Started Jan 25 02:49:43 PM PST 24
Finished Jan 25 02:50:27 PM PST 24
Peak memory 216616 kb
Host smart-181e6cf0-df39-4ace-a8b7-8efa0d4b35df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619636887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2619636887
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2278800917
Short name T962
Test name
Test status
Simulation time 691228430 ps
CPU time 4.35 seconds
Started Jan 25 02:49:50 PM PST 24
Finished Jan 25 02:50:17 PM PST 24
Peak memory 222488 kb
Host smart-0cfedbeb-e6e3-4f50-9bea-bcdff7ee553f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278800917 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2278800917
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3333071282
Short name T987
Test name
Test status
Simulation time 246412649 ps
CPU time 5.78 seconds
Started Jan 25 02:49:33 PM PST 24
Finished Jan 25 02:50:01 PM PST 24
Peak memory 209760 kb
Host smart-8aff80a7-9211-4e0f-9a20-58765ea8528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333071282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3333071282
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.4155911411
Short name T785
Test name
Test status
Simulation time 57866384 ps
CPU time 2.56 seconds
Started Jan 25 02:49:51 PM PST 24
Finished Jan 25 02:50:17 PM PST 24
Peak memory 209784 kb
Host smart-fbf442de-eb13-4cef-967e-202e39d4e3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155911411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.4155911411
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3631949831
Short name T586
Test name
Test status
Simulation time 39299514 ps
CPU time 1.01 seconds
Started Jan 25 02:49:51 PM PST 24
Finished Jan 25 02:50:15 PM PST 24
Peak memory 205428 kb
Host smart-9d79403d-313e-4171-88f5-6652d6beb0c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631949831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3631949831
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3506548515
Short name T386
Test name
Test status
Simulation time 33558958 ps
CPU time 2.71 seconds
Started Jan 25 02:49:46 PM PST 24
Finished Jan 25 02:50:12 PM PST 24
Peak memory 214356 kb
Host smart-29a76cd8-bd48-4413-8da6-04b341db36b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3506548515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3506548515
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1476183288
Short name T594
Test name
Test status
Simulation time 786083988 ps
CPU time 5.16 seconds
Started Jan 25 02:49:48 PM PST 24
Finished Jan 25 02:50:17 PM PST 24
Peak memory 207416 kb
Host smart-2e34d4a7-4e14-4c20-b869-5c94a76c2126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476183288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1476183288
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3961332835
Short name T328
Test name
Test status
Simulation time 385810908 ps
CPU time 3.56 seconds
Started Jan 25 02:49:54 PM PST 24
Finished Jan 25 02:50:22 PM PST 24
Peak memory 209732 kb
Host smart-2eebeb6f-3888-431c-a9fa-7a13df6cacc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961332835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3961332835
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3349528174
Short name T853
Test name
Test status
Simulation time 597876464 ps
CPU time 4.18 seconds
Started Jan 25 02:49:53 PM PST 24
Finished Jan 25 02:50:21 PM PST 24
Peak memory 220044 kb
Host smart-19777021-7f86-49a5-a99e-8b2a82634c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349528174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3349528174
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2676575052
Short name T318
Test name
Test status
Simulation time 217230683 ps
CPU time 5.22 seconds
Started Jan 25 02:49:52 PM PST 24
Finished Jan 25 02:50:20 PM PST 24
Peak memory 207736 kb
Host smart-5f4b8b88-e1ac-4573-895b-9ae5ad97885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676575052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2676575052
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.943865831
Short name T612
Test name
Test status
Simulation time 218243288 ps
CPU time 2.27 seconds
Started Jan 25 02:49:55 PM PST 24
Finished Jan 25 02:50:23 PM PST 24
Peak memory 206840 kb
Host smart-d4edec72-99dd-4490-a080-6e98c7c31369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943865831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.943865831
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1353654392
Short name T694
Test name
Test status
Simulation time 267375686 ps
CPU time 2.87 seconds
Started Jan 25 02:49:51 PM PST 24
Finished Jan 25 02:50:18 PM PST 24
Peak memory 206828 kb
Host smart-2d4c3378-9f61-415c-8dbd-4cf4b31d4081
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353654392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1353654392
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1952467770
Short name T1048
Test name
Test status
Simulation time 513183404 ps
CPU time 9.89 seconds
Started Jan 25 02:49:52 PM PST 24
Finished Jan 25 02:50:26 PM PST 24
Peak memory 208596 kb
Host smart-9ea24c66-6c20-42da-ba25-89a44f6afb50
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952467770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1952467770
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.985750221
Short name T574
Test name
Test status
Simulation time 243330823 ps
CPU time 2.82 seconds
Started Jan 25 02:49:46 PM PST 24
Finished Jan 25 02:50:12 PM PST 24
Peak memory 208692 kb
Host smart-5e8167fa-a099-4955-a1fb-e014c6502932
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985750221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.985750221
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1427689449
Short name T1076
Test name
Test status
Simulation time 153590524 ps
CPU time 2.33 seconds
Started Jan 25 02:49:49 PM PST 24
Finished Jan 25 02:50:14 PM PST 24
Peak memory 208168 kb
Host smart-dce25d7f-9634-462f-a0b0-a25d2e89fad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427689449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1427689449
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2401391231
Short name T608
Test name
Test status
Simulation time 524039143 ps
CPU time 3.83 seconds
Started Jan 25 02:49:47 PM PST 24
Finished Jan 25 02:50:14 PM PST 24
Peak memory 206956 kb
Host smart-a057d0c9-72d2-4ef8-8e20-d2696076bfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401391231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2401391231
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3936436845
Short name T840
Test name
Test status
Simulation time 7450738361 ps
CPU time 26.08 seconds
Started Jan 25 02:49:49 PM PST 24
Finished Jan 25 02:50:38 PM PST 24
Peak memory 215208 kb
Host smart-68a7163d-113c-4ea0-99d4-d3008e547e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936436845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3936436845
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1843633757
Short name T912
Test name
Test status
Simulation time 167432200 ps
CPU time 4.64 seconds
Started Jan 25 02:49:48 PM PST 24
Finished Jan 25 02:50:16 PM PST 24
Peak memory 207364 kb
Host smart-6cc78937-9beb-4216-9412-20e603fa65b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843633757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1843633757
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.48924882
Short name T981
Test name
Test status
Simulation time 59540359 ps
CPU time 1.69 seconds
Started Jan 25 02:49:50 PM PST 24
Finished Jan 25 02:50:15 PM PST 24
Peak memory 210136 kb
Host smart-3f0923fd-9dfd-4e3a-93e1-5a0586985265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48924882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.48924882
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.4210390419
Short name T76
Test name
Test status
Simulation time 9248929 ps
CPU time 0.69 seconds
Started Jan 25 02:49:53 PM PST 24
Finished Jan 25 02:50:17 PM PST 24
Peak memory 205908 kb
Host smart-bdac6662-d894-412c-9c37-56302d49a75a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210390419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.4210390419
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3815982571
Short name T896
Test name
Test status
Simulation time 1704419498 ps
CPU time 5.27 seconds
Started Jan 25 02:50:07 PM PST 24
Finished Jan 25 02:50:36 PM PST 24
Peak memory 214356 kb
Host smart-e8dd0712-d35a-4b60-943c-cfd24e7309b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815982571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3815982571
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2710589139
Short name T585
Test name
Test status
Simulation time 209950834 ps
CPU time 8.13 seconds
Started Jan 25 02:49:55 PM PST 24
Finished Jan 25 02:50:29 PM PST 24
Peak memory 214228 kb
Host smart-bf97b8dc-15e7-47e2-91e2-25f06b480ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710589139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2710589139
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1360759868
Short name T635
Test name
Test status
Simulation time 120095792 ps
CPU time 3.46 seconds
Started Jan 25 02:49:54 PM PST 24
Finished Jan 25 02:50:21 PM PST 24
Peak memory 222440 kb
Host smart-cb3e5865-cce4-4fea-a07a-1c1676388a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360759868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1360759868
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4008178236
Short name T317
Test name
Test status
Simulation time 49640588 ps
CPU time 3.52 seconds
Started Jan 25 02:49:55 PM PST 24
Finished Jan 25 02:50:24 PM PST 24
Peak memory 207716 kb
Host smart-df674837-84a7-4ed9-8f3b-f335d0534783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008178236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4008178236
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.994410207
Short name T104
Test name
Test status
Simulation time 169839196 ps
CPU time 2.89 seconds
Started Jan 25 02:49:58 PM PST 24
Finished Jan 25 02:50:26 PM PST 24
Peak memory 206604 kb
Host smart-183a6a0d-211d-4db0-9706-3e5b28fa3e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994410207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.994410207
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1646862413
Short name T868
Test name
Test status
Simulation time 162980533 ps
CPU time 2.47 seconds
Started Jan 25 02:50:01 PM PST 24
Finished Jan 25 02:50:27 PM PST 24
Peak memory 206860 kb
Host smart-9ab12462-de9d-48ad-a08b-29042f24ac51
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646862413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1646862413
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4171179268
Short name T348
Test name
Test status
Simulation time 39707611 ps
CPU time 2.57 seconds
Started Jan 25 02:49:59 PM PST 24
Finished Jan 25 02:50:26 PM PST 24
Peak memory 208480 kb
Host smart-8317c5b8-8f13-4855-ae30-d6e937ac79b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171179268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4171179268
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1935704281
Short name T971
Test name
Test status
Simulation time 631779154 ps
CPU time 14.41 seconds
Started Jan 25 02:50:01 PM PST 24
Finished Jan 25 02:50:39 PM PST 24
Peak memory 207812 kb
Host smart-0937db92-f1d5-4eb9-84fb-7934b055b876
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935704281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1935704281
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3152647609
Short name T737
Test name
Test status
Simulation time 85523843 ps
CPU time 2.25 seconds
Started Jan 25 02:50:08 PM PST 24
Finished Jan 25 02:50:33 PM PST 24
Peak memory 217536 kb
Host smart-102af4c7-3b9a-41d5-a71c-724c664ae3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152647609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3152647609
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2753981509
Short name T561
Test name
Test status
Simulation time 424016654 ps
CPU time 8.13 seconds
Started Jan 25 02:49:51 PM PST 24
Finished Jan 25 02:50:22 PM PST 24
Peak memory 208152 kb
Host smart-3df6003e-ca06-4540-a8ce-8432c70f7b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753981509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2753981509
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2562010920
Short name T186
Test name
Test status
Simulation time 1504117759 ps
CPU time 10.67 seconds
Started Jan 25 02:50:06 PM PST 24
Finished Jan 25 02:50:40 PM PST 24
Peak memory 221464 kb
Host smart-5897f92f-3349-45dc-9c3a-a91a3062b27d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562010920 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2562010920
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1273234978
Short name T252
Test name
Test status
Simulation time 127777783 ps
CPU time 5.88 seconds
Started Jan 25 02:49:56 PM PST 24
Finished Jan 25 02:50:27 PM PST 24
Peak memory 210188 kb
Host smart-828a8fd6-424c-4585-8049-d95d699504fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273234978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1273234978
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1982002538
Short name T815
Test name
Test status
Simulation time 57428764 ps
CPU time 0.77 seconds
Started Jan 25 02:45:51 PM PST 24
Finished Jan 25 02:46:15 PM PST 24
Peak memory 205916 kb
Host smart-6eea2459-ccf3-41a5-9086-34f8fde422d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982002538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1982002538
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2328834739
Short name T39
Test name
Test status
Simulation time 404851760 ps
CPU time 7.62 seconds
Started Jan 25 02:45:42 PM PST 24
Finished Jan 25 02:46:14 PM PST 24
Peak memory 218316 kb
Host smart-415b7c4a-b3d5-438c-ab81-127a624f5535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328834739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2328834739
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3490379245
Short name T1012
Test name
Test status
Simulation time 24365356 ps
CPU time 1.76 seconds
Started Jan 25 02:45:41 PM PST 24
Finished Jan 25 02:46:08 PM PST 24
Peak memory 207320 kb
Host smart-003f1a7b-a9fb-41f2-aa5a-93f026d10290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490379245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3490379245
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.411128754
Short name T855
Test name
Test status
Simulation time 594309371 ps
CPU time 6.6 seconds
Started Jan 25 02:45:32 PM PST 24
Finished Jan 25 02:46:07 PM PST 24
Peak memory 214204 kb
Host smart-24b100ed-c5d4-4b5f-83c6-32463a037925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411128754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.411128754
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1719275497
Short name T301
Test name
Test status
Simulation time 59812634 ps
CPU time 3.65 seconds
Started Jan 25 02:45:35 PM PST 24
Finished Jan 25 02:46:06 PM PST 24
Peak memory 210704 kb
Host smart-00b0ff95-5ece-41de-8327-2d134e22c761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719275497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1719275497
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_random.656781732
Short name T174
Test name
Test status
Simulation time 856896389 ps
CPU time 5.03 seconds
Started Jan 25 02:45:42 PM PST 24
Finished Jan 25 02:46:12 PM PST 24
Peak memory 207000 kb
Host smart-b2246e29-1a02-46a3-93cb-ceb6ca7c1443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656781732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.656781732
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3304361181
Short name T13
Test name
Test status
Simulation time 610745442 ps
CPU time 14.3 seconds
Started Jan 25 02:45:43 PM PST 24
Finished Jan 25 02:46:22 PM PST 24
Peak memory 233376 kb
Host smart-67f2e07c-c55e-46f3-8ecf-4feb399ac447
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304361181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3304361181
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.890517437
Short name T729
Test name
Test status
Simulation time 1368055322 ps
CPU time 9.05 seconds
Started Jan 25 02:45:41 PM PST 24
Finished Jan 25 02:46:16 PM PST 24
Peak memory 207940 kb
Host smart-942f1711-7620-4fb4-852c-9e866ff7d86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890517437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.890517437
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.97868584
Short name T986
Test name
Test status
Simulation time 271007721 ps
CPU time 4.72 seconds
Started Jan 25 02:45:49 PM PST 24
Finished Jan 25 02:46:17 PM PST 24
Peak memory 206648 kb
Host smart-8c1ab5d6-3a03-4abc-85c8-b1da01bcee38
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97868584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.97868584
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2594489540
Short name T228
Test name
Test status
Simulation time 1839331292 ps
CPU time 39.61 seconds
Started Jan 25 02:45:49 PM PST 24
Finished Jan 25 02:46:53 PM PST 24
Peak memory 207800 kb
Host smart-2429b3e7-c8c3-492b-a9ab-4df23904ce46
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594489540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2594489540
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2044877266
Short name T1075
Test name
Test status
Simulation time 21744531 ps
CPU time 1.83 seconds
Started Jan 25 02:45:40 PM PST 24
Finished Jan 25 02:46:08 PM PST 24
Peak memory 206824 kb
Host smart-d2b7d40d-a91d-46be-82bc-687bc6679faa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044877266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2044877266
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2236757213
Short name T1017
Test name
Test status
Simulation time 148501620 ps
CPU time 2.47 seconds
Started Jan 25 02:45:34 PM PST 24
Finished Jan 25 02:46:04 PM PST 24
Peak memory 218300 kb
Host smart-7647165d-2160-44b0-b866-c9e745676f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236757213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2236757213
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3961775907
Short name T862
Test name
Test status
Simulation time 117148368 ps
CPU time 1.78 seconds
Started Jan 25 02:45:40 PM PST 24
Finished Jan 25 02:46:08 PM PST 24
Peak memory 206820 kb
Host smart-59ec4f04-63c0-4699-8d0e-0d3a93008936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961775907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3961775907
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1048140438
Short name T300
Test name
Test status
Simulation time 253410717 ps
CPU time 13.55 seconds
Started Jan 25 02:45:43 PM PST 24
Finished Jan 25 02:46:21 PM PST 24
Peak memory 216196 kb
Host smart-0c6a857d-d89f-4f62-a598-d4cc34fb7440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048140438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1048140438
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1323208436
Short name T838
Test name
Test status
Simulation time 784388964 ps
CPU time 6.67 seconds
Started Jan 25 02:45:43 PM PST 24
Finished Jan 25 02:46:14 PM PST 24
Peak memory 219052 kb
Host smart-5bc0cb1c-86fe-4a8f-93f7-091dee88b387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323208436 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.1323208436
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2253597856
Short name T630
Test name
Test status
Simulation time 167602200 ps
CPU time 2.96 seconds
Started Jan 25 02:45:41 PM PST 24
Finished Jan 25 02:46:09 PM PST 24
Peak memory 207204 kb
Host smart-8938e1bf-7c5b-40d8-82f7-62035999c678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253597856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2253597856
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2686656806
Short name T866
Test name
Test status
Simulation time 46422122 ps
CPU time 1.79 seconds
Started Jan 25 02:45:32 PM PST 24
Finished Jan 25 02:46:02 PM PST 24
Peak memory 209696 kb
Host smart-fa8c35fd-d08c-4eda-8684-b872d2ad8f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686656806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2686656806
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3484476801
Short name T935
Test name
Test status
Simulation time 11208422 ps
CPU time 0.69 seconds
Started Jan 25 02:50:28 PM PST 24
Finished Jan 25 02:50:41 PM PST 24
Peak memory 205908 kb
Host smart-6fab0a61-4337-4b21-942d-ce63d156ad50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484476801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3484476801
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.4266247315
Short name T122
Test name
Test status
Simulation time 55662079 ps
CPU time 3.45 seconds
Started Jan 25 02:49:50 PM PST 24
Finished Jan 25 02:50:16 PM PST 24
Peak memory 214236 kb
Host smart-fbd1119c-6fda-47d1-badc-b62cde5f4d25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4266247315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4266247315
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3781674818
Short name T1018
Test name
Test status
Simulation time 321196802 ps
CPU time 3.3 seconds
Started Jan 25 02:49:54 PM PST 24
Finished Jan 25 02:50:21 PM PST 24
Peak memory 214044 kb
Host smart-2ef68674-40c5-406a-833c-911ab20ebf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781674818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3781674818
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1757936687
Short name T309
Test name
Test status
Simulation time 96785788 ps
CPU time 2.73 seconds
Started Jan 25 02:49:49 PM PST 24
Finished Jan 25 02:50:15 PM PST 24
Peak memory 207396 kb
Host smart-a23c51f8-0ce6-4a59-80b6-520dc82d86a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757936687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1757936687
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1959966946
Short name T1020
Test name
Test status
Simulation time 47345093 ps
CPU time 2.75 seconds
Started Jan 25 02:49:50 PM PST 24
Finished Jan 25 02:50:16 PM PST 24
Peak memory 207952 kb
Host smart-8d7c2c07-2e48-4c55-9593-6c8d171148eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959966946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1959966946
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3632260325
Short name T276
Test name
Test status
Simulation time 293878430 ps
CPU time 4.3 seconds
Started Jan 25 02:49:54 PM PST 24
Finished Jan 25 02:50:22 PM PST 24
Peak memory 211012 kb
Host smart-34431ac6-4b68-45f6-9fd2-d45acc561ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632260325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3632260325
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.519013679
Short name T861
Test name
Test status
Simulation time 119919099 ps
CPU time 1.46 seconds
Started Jan 25 02:49:49 PM PST 24
Finished Jan 25 02:50:14 PM PST 24
Peak memory 205984 kb
Host smart-68060b9d-3d3b-4d95-be24-226fb96d700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519013679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.519013679
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1302298149
Short name T214
Test name
Test status
Simulation time 146469460 ps
CPU time 6.47 seconds
Started Jan 25 02:49:45 PM PST 24
Finished Jan 25 02:50:15 PM PST 24
Peak memory 214288 kb
Host smart-7798598d-bd20-421c-bcb5-7ecc31aa890a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302298149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1302298149
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2748562764
Short name T259
Test name
Test status
Simulation time 53486636 ps
CPU time 3.01 seconds
Started Jan 25 02:49:57 PM PST 24
Finished Jan 25 02:50:25 PM PST 24
Peak memory 208744 kb
Host smart-561ae9df-5c4b-4760-8ccb-b7f0089fde6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748562764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2748562764
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3986320406
Short name T884
Test name
Test status
Simulation time 140258590 ps
CPU time 4.57 seconds
Started Jan 25 02:49:49 PM PST 24
Finished Jan 25 02:50:17 PM PST 24
Peak memory 208864 kb
Host smart-d3ff7124-69fe-4976-ab1c-e4db86faec01
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986320406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3986320406
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.4132122518
Short name T18
Test name
Test status
Simulation time 81927847 ps
CPU time 2.01 seconds
Started Jan 25 02:49:59 PM PST 24
Finished Jan 25 02:50:26 PM PST 24
Peak memory 206872 kb
Host smart-34d91220-6cf8-4789-ad25-b99ff498f81f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132122518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.4132122518
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2958148010
Short name T623
Test name
Test status
Simulation time 433183191 ps
CPU time 4.02 seconds
Started Jan 25 02:49:57 PM PST 24
Finished Jan 25 02:50:26 PM PST 24
Peak memory 206668 kb
Host smart-da080a99-32cc-4fae-92fe-d130d8080081
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958148010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2958148010
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1998097390
Short name T731
Test name
Test status
Simulation time 115125995 ps
CPU time 2.78 seconds
Started Jan 25 02:49:49 PM PST 24
Finished Jan 25 02:50:15 PM PST 24
Peak memory 209748 kb
Host smart-fc956d71-72ac-48b5-b62c-29f4a146176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998097390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1998097390
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1710319026
Short name T721
Test name
Test status
Simulation time 870026970 ps
CPU time 8.44 seconds
Started Jan 25 02:49:49 PM PST 24
Finished Jan 25 02:50:21 PM PST 24
Peak memory 208596 kb
Host smart-a8a23018-c89f-4c42-b6fd-4154d47a176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710319026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1710319026
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1385001126
Short name T74
Test name
Test status
Simulation time 2331601633 ps
CPU time 23.53 seconds
Started Jan 25 02:49:56 PM PST 24
Finished Jan 25 02:50:45 PM PST 24
Peak memory 217116 kb
Host smart-8d8fbb6f-c330-4f03-ac79-a97e34867e56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385001126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1385001126
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2188944816
Short name T188
Test name
Test status
Simulation time 791187162 ps
CPU time 14.14 seconds
Started Jan 25 02:49:51 PM PST 24
Finished Jan 25 02:50:28 PM PST 24
Peak memory 222596 kb
Host smart-e407ebcf-3dad-4b04-9538-7c20af3a00c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188944816 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2188944816
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1834121365
Short name T297
Test name
Test status
Simulation time 1299715922 ps
CPU time 36.89 seconds
Started Jan 25 02:49:49 PM PST 24
Finished Jan 25 02:50:49 PM PST 24
Peak memory 218196 kb
Host smart-5dbeeda3-c747-4875-a1fc-4dd40f57f77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834121365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1834121365
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.254317358
Short name T735
Test name
Test status
Simulation time 13112751 ps
CPU time 0.88 seconds
Started Jan 25 02:50:36 PM PST 24
Finished Jan 25 02:50:49 PM PST 24
Peak memory 206112 kb
Host smart-a9c12edf-4019-4b8b-8f65-de2f99728b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254317358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.254317358
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2837735588
Short name T10
Test name
Test status
Simulation time 4213568252 ps
CPU time 72.33 seconds
Started Jan 25 02:50:34 PM PST 24
Finished Jan 25 02:51:59 PM PST 24
Peak memory 226060 kb
Host smart-1807f143-8b87-4aab-bd93-2c14c523e08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837735588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2837735588
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1557034856
Short name T960
Test name
Test status
Simulation time 480940961 ps
CPU time 3.48 seconds
Started Jan 25 02:50:30 PM PST 24
Finished Jan 25 02:50:45 PM PST 24
Peak memory 214448 kb
Host smart-3f5e3d0b-d2d7-4516-ba16-fcbcfbecdc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557034856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1557034856
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.424906987
Short name T771
Test name
Test status
Simulation time 297599529 ps
CPU time 2.63 seconds
Started Jan 25 02:50:32 PM PST 24
Finished Jan 25 02:50:47 PM PST 24
Peak memory 209140 kb
Host smart-b1d7dc74-35cd-4353-af68-980caf25a863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424906987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.424906987
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2896827326
Short name T232
Test name
Test status
Simulation time 827866214 ps
CPU time 6.29 seconds
Started Jan 25 02:50:27 PM PST 24
Finished Jan 25 02:50:45 PM PST 24
Peak memory 222284 kb
Host smart-0b0973e5-f6ec-4c2f-9989-4331bb42a09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896827326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2896827326
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1045520159
Short name T45
Test name
Test status
Simulation time 242230996 ps
CPU time 5.31 seconds
Started Jan 25 02:50:28 PM PST 24
Finished Jan 25 02:50:45 PM PST 24
Peak memory 210360 kb
Host smart-082f0f7c-4cce-49bb-9b12-f77c9bcb9375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045520159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1045520159
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3522608231
Short name T954
Test name
Test status
Simulation time 356971121 ps
CPU time 4.27 seconds
Started Jan 25 02:50:28 PM PST 24
Finished Jan 25 02:50:44 PM PST 24
Peak memory 218232 kb
Host smart-53e6af8c-cb2a-4fe9-80b6-106524ceacaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522608231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3522608231
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3965568787
Short name T812
Test name
Test status
Simulation time 37302100 ps
CPU time 2.61 seconds
Started Jan 25 02:50:34 PM PST 24
Finished Jan 25 02:50:49 PM PST 24
Peak memory 206384 kb
Host smart-9298ab5c-2683-4d61-aeb6-94a55f607bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965568787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3965568787
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1176237476
Short name T80
Test name
Test status
Simulation time 429630626 ps
CPU time 5.12 seconds
Started Jan 25 02:50:33 PM PST 24
Finished Jan 25 02:50:50 PM PST 24
Peak memory 206812 kb
Host smart-c8eca0f3-836a-4cde-ab65-59e7191bce71
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176237476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1176237476
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3224868748
Short name T1039
Test name
Test status
Simulation time 36469185 ps
CPU time 2.37 seconds
Started Jan 25 02:50:28 PM PST 24
Finished Jan 25 02:50:42 PM PST 24
Peak memory 206904 kb
Host smart-e18b4df9-ff70-49e5-a057-73a8f4a690f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224868748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3224868748
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2821947170
Short name T573
Test name
Test status
Simulation time 41499213 ps
CPU time 2.8 seconds
Started Jan 25 02:50:25 PM PST 24
Finished Jan 25 02:50:40 PM PST 24
Peak memory 208572 kb
Host smart-84f5e4cd-fbf1-4e03-8770-e9e71e5f0d01
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821947170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2821947170
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.822701983
Short name T1070
Test name
Test status
Simulation time 177561442 ps
CPU time 5.93 seconds
Started Jan 25 02:50:34 PM PST 24
Finished Jan 25 02:50:52 PM PST 24
Peak memory 215788 kb
Host smart-dd864c8f-1a64-4a99-b7a6-55aa2a2e82d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822701983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.822701983
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3186247850
Short name T744
Test name
Test status
Simulation time 214953999 ps
CPU time 2.77 seconds
Started Jan 25 02:50:25 PM PST 24
Finished Jan 25 02:50:40 PM PST 24
Peak memory 206752 kb
Host smart-e2bb3d8d-a300-49d6-8c11-5a3513a88763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186247850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3186247850
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2093256426
Short name T859
Test name
Test status
Simulation time 477941215 ps
CPU time 13.27 seconds
Started Jan 25 02:50:27 PM PST 24
Finished Jan 25 02:50:52 PM PST 24
Peak memory 215772 kb
Host smart-9c76b4d3-8a57-4172-acef-9ea69e758618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093256426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2093256426
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1547512762
Short name T2
Test name
Test status
Simulation time 852952743 ps
CPU time 5.96 seconds
Started Jan 25 02:50:36 PM PST 24
Finished Jan 25 02:50:54 PM PST 24
Peak memory 222512 kb
Host smart-5abf32a0-7d3e-47ac-9116-483fc8205960
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547512762 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1547512762
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1455972113
Short name T78
Test name
Test status
Simulation time 163944286 ps
CPU time 5.83 seconds
Started Jan 25 02:50:34 PM PST 24
Finished Jan 25 02:50:52 PM PST 24
Peak memory 208072 kb
Host smart-7854d700-3518-4469-afe6-f1d3e30f06e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455972113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1455972113
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3981391165
Short name T772
Test name
Test status
Simulation time 160630548 ps
CPU time 3.15 seconds
Started Jan 25 02:50:29 PM PST 24
Finished Jan 25 02:50:44 PM PST 24
Peak memory 211048 kb
Host smart-eef09c89-180d-439b-8aac-23d3938a59f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981391165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3981391165
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3278754852
Short name T562
Test name
Test status
Simulation time 34925470 ps
CPU time 0.8 seconds
Started Jan 25 02:50:29 PM PST 24
Finished Jan 25 02:50:41 PM PST 24
Peak memory 205928 kb
Host smart-8e2ea470-9eae-4f67-94d5-bd2ce7420b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278754852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3278754852
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1632433064
Short name T1044
Test name
Test status
Simulation time 280851769 ps
CPU time 2.48 seconds
Started Jan 25 02:50:28 PM PST 24
Finished Jan 25 02:50:42 PM PST 24
Peak memory 214260 kb
Host smart-cda3b640-0b62-4429-af82-cbb57360676a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1632433064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1632433064
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1831150483
Short name T943
Test name
Test status
Simulation time 96398709 ps
CPU time 2.41 seconds
Started Jan 25 02:50:31 PM PST 24
Finished Jan 25 02:50:45 PM PST 24
Peak memory 209172 kb
Host smart-0ad2f7a6-2f14-4f2e-b85f-6d6cc29c018a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831150483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1831150483
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3264035490
Short name T64
Test name
Test status
Simulation time 65138399 ps
CPU time 1.89 seconds
Started Jan 25 02:50:26 PM PST 24
Finished Jan 25 02:50:40 PM PST 24
Peak memory 214280 kb
Host smart-011feeb4-b20f-457c-a168-0afbccc113c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264035490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3264035490
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3354640379
Short name T856
Test name
Test status
Simulation time 631125604 ps
CPU time 6.46 seconds
Started Jan 25 02:50:32 PM PST 24
Finished Jan 25 02:50:50 PM PST 24
Peak memory 219564 kb
Host smart-c1b98c2d-012c-4679-b743-8a9b25aacd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354640379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3354640379
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2560648035
Short name T172
Test name
Test status
Simulation time 391435237 ps
CPU time 11.33 seconds
Started Jan 25 02:50:36 PM PST 24
Finished Jan 25 02:50:59 PM PST 24
Peak memory 215284 kb
Host smart-8465ef18-5f69-4751-872b-a08efd500c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560648035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2560648035
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3415799723
Short name T602
Test name
Test status
Simulation time 738766004 ps
CPU time 3.73 seconds
Started Jan 25 02:50:31 PM PST 24
Finished Jan 25 02:50:47 PM PST 24
Peak memory 214264 kb
Host smart-c10ffe52-e006-432d-8234-482c31ccd3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415799723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3415799723
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.4081107654
Short name T703
Test name
Test status
Simulation time 734223978 ps
CPU time 3.17 seconds
Started Jan 25 02:50:31 PM PST 24
Finished Jan 25 02:50:46 PM PST 24
Peak memory 207612 kb
Host smart-558b0478-2755-4b88-a576-05bff4a49659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081107654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.4081107654
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4129330375
Short name T332
Test name
Test status
Simulation time 64963528 ps
CPU time 3.16 seconds
Started Jan 25 02:50:27 PM PST 24
Finished Jan 25 02:50:42 PM PST 24
Peak memory 208120 kb
Host smart-be79fcd6-5bc7-4ec1-b523-9529ad94ee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129330375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4129330375
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.96033298
Short name T803
Test name
Test status
Simulation time 309291231 ps
CPU time 3.5 seconds
Started Jan 25 02:50:33 PM PST 24
Finished Jan 25 02:50:49 PM PST 24
Peak memory 208760 kb
Host smart-629364af-d8d1-4457-919c-c8def7ec187b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96033298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.96033298
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.67279852
Short name T819
Test name
Test status
Simulation time 177557076 ps
CPU time 3 seconds
Started Jan 25 02:50:28 PM PST 24
Finished Jan 25 02:50:42 PM PST 24
Peak memory 207064 kb
Host smart-442a197e-8dd8-4048-8734-d37b9ee6da8d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67279852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.67279852
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.760830039
Short name T804
Test name
Test status
Simulation time 59995012 ps
CPU time 2.21 seconds
Started Jan 25 02:50:28 PM PST 24
Finished Jan 25 02:50:42 PM PST 24
Peak memory 206704 kb
Host smart-0bff15fe-105c-40e4-ab17-71c1c0c575ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760830039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.760830039
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1892298465
Short name T959
Test name
Test status
Simulation time 28350787 ps
CPU time 1.29 seconds
Started Jan 25 02:50:27 PM PST 24
Finished Jan 25 02:50:40 PM PST 24
Peak memory 207056 kb
Host smart-fc7ab2b8-bdb1-469e-a788-7125826f4cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892298465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1892298465
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1335144445
Short name T835
Test name
Test status
Simulation time 1486219330 ps
CPU time 6.96 seconds
Started Jan 25 02:50:33 PM PST 24
Finished Jan 25 02:50:53 PM PST 24
Peak memory 207960 kb
Host smart-c8903824-5d38-4a6f-8619-a404dc7003cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335144445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1335144445
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1889660627
Short name T650
Test name
Test status
Simulation time 5267539208 ps
CPU time 8.7 seconds
Started Jan 25 02:50:26 PM PST 24
Finished Jan 25 02:50:47 PM PST 24
Peak memory 223272 kb
Host smart-57216450-cb60-4486-afcb-d7c3116defb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889660627 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1889660627
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1532224079
Short name T723
Test name
Test status
Simulation time 33213363 ps
CPU time 2.52 seconds
Started Jan 25 02:50:31 PM PST 24
Finished Jan 25 02:50:45 PM PST 24
Peak memory 208012 kb
Host smart-cbb1c724-7aae-4e7d-974b-7d675a3edb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532224079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1532224079
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2846652895
Short name T681
Test name
Test status
Simulation time 131973741 ps
CPU time 3.11 seconds
Started Jan 25 02:50:30 PM PST 24
Finished Jan 25 02:50:44 PM PST 24
Peak memory 209860 kb
Host smart-dc0bad0a-8787-4b5c-85fc-49dcd73c89ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846652895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2846652895
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.4084072856
Short name T996
Test name
Test status
Simulation time 10655075 ps
CPU time 0.82 seconds
Started Jan 25 02:51:01 PM PST 24
Finished Jan 25 02:51:10 PM PST 24
Peak memory 205924 kb
Host smart-076e1bee-b1d1-4863-b593-1b5f3113087e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084072856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4084072856
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.755991371
Short name T268
Test name
Test status
Simulation time 68340461 ps
CPU time 4.75 seconds
Started Jan 25 02:50:34 PM PST 24
Finished Jan 25 02:50:51 PM PST 24
Peak memory 213816 kb
Host smart-898158da-6bf1-4e25-b7b7-450f31630449
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755991371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.755991371
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2558052115
Short name T776
Test name
Test status
Simulation time 118691315 ps
CPU time 5.36 seconds
Started Jan 25 02:50:59 PM PST 24
Finished Jan 25 02:51:13 PM PST 24
Peak memory 222764 kb
Host smart-5b846192-bf66-44ea-90cd-60af1418a3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558052115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2558052115
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1113245577
Short name T584
Test name
Test status
Simulation time 121247183 ps
CPU time 3.72 seconds
Started Jan 25 02:50:52 PM PST 24
Finished Jan 25 02:51:00 PM PST 24
Peak memory 217484 kb
Host smart-f87baaaa-1864-4d2e-a2e5-0342cea393e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113245577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1113245577
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1645204285
Short name T787
Test name
Test status
Simulation time 437782976 ps
CPU time 5.3 seconds
Started Jan 25 02:50:54 PM PST 24
Finished Jan 25 02:51:04 PM PST 24
Peak memory 208780 kb
Host smart-8c1b41c6-5e63-43aa-be25-f3f244c22630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645204285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1645204285
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2269321391
Short name T258
Test name
Test status
Simulation time 229357558 ps
CPU time 3.93 seconds
Started Jan 25 02:50:53 PM PST 24
Finished Jan 25 02:51:01 PM PST 24
Peak memory 214224 kb
Host smart-d9219384-40e5-4bbb-b39f-ceb17d119b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269321391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2269321391
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.262973577
Short name T813
Test name
Test status
Simulation time 663744095 ps
CPU time 4.72 seconds
Started Jan 25 02:51:12 PM PST 24
Finished Jan 25 02:51:21 PM PST 24
Peak memory 220164 kb
Host smart-0b6914ae-08e8-4aee-ac4c-d669e11c97ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262973577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.262973577
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3129729434
Short name T1024
Test name
Test status
Simulation time 160346136 ps
CPU time 3.05 seconds
Started Jan 25 02:50:34 PM PST 24
Finished Jan 25 02:50:50 PM PST 24
Peak memory 214304 kb
Host smart-50696a76-a7f8-4954-b2a3-c4ba2bf93db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129729434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3129729434
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1700432448
Short name T354
Test name
Test status
Simulation time 751777175 ps
CPU time 5.84 seconds
Started Jan 25 02:50:30 PM PST 24
Finished Jan 25 02:50:47 PM PST 24
Peak memory 208328 kb
Host smart-5b50c6e6-b32b-4ce4-b49d-afd068c5a230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700432448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1700432448
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.5437372
Short name T626
Test name
Test status
Simulation time 46228265 ps
CPU time 2.5 seconds
Started Jan 25 02:50:33 PM PST 24
Finished Jan 25 02:50:48 PM PST 24
Peak memory 208216 kb
Host smart-722d4b63-20f9-4fa5-974e-0bb4b6f91c8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5437372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.5437372
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1631733255
Short name T322
Test name
Test status
Simulation time 29026206 ps
CPU time 2 seconds
Started Jan 25 02:50:29 PM PST 24
Finished Jan 25 02:50:42 PM PST 24
Peak memory 208260 kb
Host smart-8d0229c1-a375-46f7-b826-41cd51ccea5b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631733255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1631733255
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3525587323
Short name T547
Test name
Test status
Simulation time 51286634 ps
CPU time 2.27 seconds
Started Jan 25 02:50:29 PM PST 24
Finished Jan 25 02:50:43 PM PST 24
Peak memory 206732 kb
Host smart-032eed3a-acef-476a-82ed-b7e61b07f431
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525587323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3525587323
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1837406293
Short name T599
Test name
Test status
Simulation time 53728935 ps
CPU time 2.43 seconds
Started Jan 25 02:51:00 PM PST 24
Finished Jan 25 02:51:11 PM PST 24
Peak memory 214292 kb
Host smart-46700293-9430-426f-91b9-05b96fa42b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837406293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1837406293
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2750605614
Short name T932
Test name
Test status
Simulation time 777290624 ps
CPU time 7.76 seconds
Started Jan 25 02:50:26 PM PST 24
Finished Jan 25 02:50:46 PM PST 24
Peak memory 207176 kb
Host smart-8f9bbc84-efeb-49b4-a7a8-8b148fa56bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750605614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2750605614
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1026914377
Short name T705
Test name
Test status
Simulation time 352247081 ps
CPU time 4.11 seconds
Started Jan 25 02:51:00 PM PST 24
Finished Jan 25 02:51:13 PM PST 24
Peak memory 222492 kb
Host smart-62b3ab37-fe42-49b0-be8b-8b29450f65ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026914377 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1026914377
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2387077334
Short name T222
Test name
Test status
Simulation time 1167384407 ps
CPU time 8.34 seconds
Started Jan 25 02:50:57 PM PST 24
Finished Jan 25 02:51:12 PM PST 24
Peak memory 214364 kb
Host smart-f04edfe2-5fc7-4222-bc29-e60cf25d56f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387077334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2387077334
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.471071517
Short name T867
Test name
Test status
Simulation time 33160758 ps
CPU time 1.93 seconds
Started Jan 25 02:50:53 PM PST 24
Finished Jan 25 02:50:59 PM PST 24
Peak memory 208340 kb
Host smart-06871147-3dcf-46b9-8160-f826f4796314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471071517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.471071517
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2347266606
Short name T952
Test name
Test status
Simulation time 35413071 ps
CPU time 0.81 seconds
Started Jan 25 02:50:55 PM PST 24
Finished Jan 25 02:51:01 PM PST 24
Peak memory 205844 kb
Host smart-bd7d6c2d-41ef-45db-8196-d0e3f45af49f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347266606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2347266606
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2086045456
Short name T394
Test name
Test status
Simulation time 4936595338 ps
CPU time 137.66 seconds
Started Jan 25 02:51:01 PM PST 24
Finished Jan 25 02:53:27 PM PST 24
Peak memory 222560 kb
Host smart-b28e50ce-f2b0-4add-b71d-1488b01e03f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2086045456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2086045456
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1670137687
Short name T49
Test name
Test status
Simulation time 107504154 ps
CPU time 1.82 seconds
Started Jan 25 02:50:54 PM PST 24
Finished Jan 25 02:51:00 PM PST 24
Peak memory 207712 kb
Host smart-bcf5b1a6-09b4-489f-a5bf-7e9cdd0d40a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670137687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1670137687
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.366159757
Short name T605
Test name
Test status
Simulation time 3337568779 ps
CPU time 58.04 seconds
Started Jan 25 02:51:01 PM PST 24
Finished Jan 25 02:52:07 PM PST 24
Peak memory 222472 kb
Host smart-9b12f258-c0cc-44a5-8632-2598c81854ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366159757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.366159757
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1831516123
Short name T937
Test name
Test status
Simulation time 52219409 ps
CPU time 1.66 seconds
Started Jan 25 02:51:00 PM PST 24
Finished Jan 25 02:51:10 PM PST 24
Peak memory 214924 kb
Host smart-02a68c4b-fe7a-4966-aadb-0d43c2147c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831516123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1831516123
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2524785552
Short name T742
Test name
Test status
Simulation time 4332113976 ps
CPU time 43.09 seconds
Started Jan 25 02:50:59 PM PST 24
Finished Jan 25 02:51:51 PM PST 24
Peak memory 218472 kb
Host smart-e834adfd-7e6d-4eec-b5ad-a4f9a894fabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524785552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2524785552
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1625085688
Short name T788
Test name
Test status
Simulation time 140923027 ps
CPU time 2.75 seconds
Started Jan 25 02:51:00 PM PST 24
Finished Jan 25 02:51:11 PM PST 24
Peak memory 208400 kb
Host smart-d9b285ef-221d-4045-be24-89be2f998e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625085688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1625085688
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2118743841
Short name T773
Test name
Test status
Simulation time 41596071 ps
CPU time 2.75 seconds
Started Jan 25 02:50:57 PM PST 24
Finished Jan 25 02:51:06 PM PST 24
Peak memory 209032 kb
Host smart-6adad2f3-b224-4dd9-89f9-5a313cd894f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118743841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2118743841
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3718060644
Short name T644
Test name
Test status
Simulation time 77776800 ps
CPU time 3.61 seconds
Started Jan 25 02:50:58 PM PST 24
Finished Jan 25 02:51:08 PM PST 24
Peak memory 207044 kb
Host smart-cdb6dbd0-15d9-46b4-92d4-79921fb39c3a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718060644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3718060644
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.440326729
Short name T627
Test name
Test status
Simulation time 4550764434 ps
CPU time 60.48 seconds
Started Jan 25 02:51:00 PM PST 24
Finished Jan 25 02:52:09 PM PST 24
Peak memory 207824 kb
Host smart-67d7520f-aa42-4c51-a292-47474d9c9cdf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440326729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.440326729
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3676240163
Short name T638
Test name
Test status
Simulation time 34882370 ps
CPU time 1.83 seconds
Started Jan 25 02:50:58 PM PST 24
Finished Jan 25 02:51:06 PM PST 24
Peak memory 208336 kb
Host smart-7cd53b29-dfab-4561-9b31-caa27faae9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676240163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3676240163
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1229786309
Short name T692
Test name
Test status
Simulation time 890618177 ps
CPU time 9.17 seconds
Started Jan 25 02:50:58 PM PST 24
Finished Jan 25 02:51:14 PM PST 24
Peak memory 208336 kb
Host smart-d338e089-1640-4b04-8bf8-a7ff8c20e9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229786309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1229786309
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3709677486
Short name T187
Test name
Test status
Simulation time 172564808 ps
CPU time 5.15 seconds
Started Jan 25 02:50:54 PM PST 24
Finished Jan 25 02:51:04 PM PST 24
Peak memory 222516 kb
Host smart-7824864f-8c13-4c6f-94ba-916200ecfd16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709677486 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3709677486
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2567698205
Short name T826
Test name
Test status
Simulation time 696747136 ps
CPU time 7.71 seconds
Started Jan 25 02:51:03 PM PST 24
Finished Jan 25 02:51:18 PM PST 24
Peak memory 207404 kb
Host smart-c62eb3f7-63b9-45d5-809d-c56fa85b55f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567698205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2567698205
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2613113932
Short name T1011
Test name
Test status
Simulation time 157486393 ps
CPU time 6.17 seconds
Started Jan 25 02:50:53 PM PST 24
Finished Jan 25 02:51:03 PM PST 24
Peak memory 210444 kb
Host smart-af7d9ea4-347e-49f4-ab03-f69a9a804e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613113932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2613113932
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.514298790
Short name T740
Test name
Test status
Simulation time 11329044 ps
CPU time 0.7 seconds
Started Jan 25 02:51:02 PM PST 24
Finished Jan 25 02:51:11 PM PST 24
Peak memory 205920 kb
Host smart-70fff0d4-09e6-4726-af80-6ad273f6b2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514298790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.514298790
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1739670538
Short name T1002
Test name
Test status
Simulation time 1793115323 ps
CPU time 7.11 seconds
Started Jan 25 02:50:58 PM PST 24
Finished Jan 25 02:51:11 PM PST 24
Peak memory 214204 kb
Host smart-6c566c15-622d-4b37-a400-3f8e92e64f2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739670538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1739670538
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2904376225
Short name T22
Test name
Test status
Simulation time 53637950 ps
CPU time 3.59 seconds
Started Jan 25 02:50:56 PM PST 24
Finished Jan 25 02:51:05 PM PST 24
Peak memory 214636 kb
Host smart-4d2c78b1-428b-4274-a678-641e298895c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904376225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2904376225
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.4083442754
Short name T203
Test name
Test status
Simulation time 667886083 ps
CPU time 5.16 seconds
Started Jan 25 02:51:03 PM PST 24
Finished Jan 25 02:51:16 PM PST 24
Peak memory 207220 kb
Host smart-96d3e7fd-8789-491b-80c9-a1e3fe7bc791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083442754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.4083442754
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.834199791
Short name T684
Test name
Test status
Simulation time 318774386 ps
CPU time 6.59 seconds
Started Jan 25 02:51:00 PM PST 24
Finished Jan 25 02:51:15 PM PST 24
Peak memory 209528 kb
Host smart-cffd444a-7505-495f-9ff9-f65c66f801a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834199791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.834199791
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3066318426
Short name T233
Test name
Test status
Simulation time 7672214544 ps
CPU time 81.05 seconds
Started Jan 25 02:50:59 PM PST 24
Finished Jan 25 02:52:29 PM PST 24
Peak memory 220784 kb
Host smart-eb3e14a6-a649-4253-931b-b9a4e8a2079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066318426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3066318426
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_random.3649095577
Short name T800
Test name
Test status
Simulation time 251276684 ps
CPU time 4.86 seconds
Started Jan 25 02:50:57 PM PST 24
Finished Jan 25 02:51:08 PM PST 24
Peak memory 218176 kb
Host smart-2bcb5a6c-f3cb-4aa9-874f-32e883437cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649095577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3649095577
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1691943801
Short name T768
Test name
Test status
Simulation time 64746009 ps
CPU time 3.15 seconds
Started Jan 25 02:51:00 PM PST 24
Finished Jan 25 02:51:12 PM PST 24
Peak memory 208288 kb
Host smart-d0f2e889-4040-4348-ac22-56c9bf79a68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691943801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1691943801
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2798655507
Short name T643
Test name
Test status
Simulation time 56147955 ps
CPU time 2.89 seconds
Started Jan 25 02:50:58 PM PST 24
Finished Jan 25 02:51:07 PM PST 24
Peak memory 207996 kb
Host smart-ff2b8623-d5de-48ac-8272-09858a2baba9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798655507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2798655507
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2545543512
Short name T841
Test name
Test status
Simulation time 79163832 ps
CPU time 3.69 seconds
Started Jan 25 02:50:55 PM PST 24
Finished Jan 25 02:51:03 PM PST 24
Peak memory 208644 kb
Host smart-379b3523-8def-4d10-be9c-32e89c26b774
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545543512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2545543512
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3744058990
Short name T734
Test name
Test status
Simulation time 368713166 ps
CPU time 2.41 seconds
Started Jan 25 02:50:57 PM PST 24
Finished Jan 25 02:51:05 PM PST 24
Peak memory 206728 kb
Host smart-398d7853-0140-4b30-a670-8c45dc2fb9af
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744058990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3744058990
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.57955936
Short name T647
Test name
Test status
Simulation time 205971240 ps
CPU time 4.62 seconds
Started Jan 25 02:50:58 PM PST 24
Finished Jan 25 02:51:09 PM PST 24
Peak memory 210268 kb
Host smart-15dc8c30-bf34-4123-8523-162e76e1a98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57955936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.57955936
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1519717533
Short name T79
Test name
Test status
Simulation time 185672759 ps
CPU time 3.13 seconds
Started Jan 25 02:51:03 PM PST 24
Finished Jan 25 02:51:14 PM PST 24
Peak memory 206596 kb
Host smart-f3675ace-804e-4e61-bc0c-7c6f262650c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519717533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1519717533
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2741038353
Short name T286
Test name
Test status
Simulation time 2602004912 ps
CPU time 64 seconds
Started Jan 25 02:51:13 PM PST 24
Finished Jan 25 02:52:21 PM PST 24
Peak memory 214856 kb
Host smart-8e8ac5f8-16ed-44d5-a9ef-9c816a35fcf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741038353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2741038353
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3997553539
Short name T274
Test name
Test status
Simulation time 118116252 ps
CPU time 5.29 seconds
Started Jan 25 02:51:00 PM PST 24
Finished Jan 25 02:51:14 PM PST 24
Peak memory 209928 kb
Host smart-617b986c-4de0-4f57-802e-b6c26924d011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997553539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3997553539
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.316151721
Short name T632
Test name
Test status
Simulation time 249780903 ps
CPU time 1.91 seconds
Started Jan 25 02:51:00 PM PST 24
Finished Jan 25 02:51:11 PM PST 24
Peak memory 209836 kb
Host smart-f7db2bfe-a128-4478-91fa-c734039d582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316151721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.316151721
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2005943809
Short name T620
Test name
Test status
Simulation time 57661996 ps
CPU time 0.69 seconds
Started Jan 25 02:51:42 PM PST 24
Finished Jan 25 02:52:00 PM PST 24
Peak memory 205896 kb
Host smart-f5b8e0c8-f6bd-4472-8ebe-b759eb3ea35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005943809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2005943809
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.371998971
Short name T392
Test name
Test status
Simulation time 69727914 ps
CPU time 4.6 seconds
Started Jan 25 02:50:56 PM PST 24
Finished Jan 25 02:51:06 PM PST 24
Peak memory 214320 kb
Host smart-f75b83c5-cf6d-4be0-abe4-e157dfb99fef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371998971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.371998971
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3553705846
Short name T38
Test name
Test status
Simulation time 111364220 ps
CPU time 1.7 seconds
Started Jan 25 02:51:32 PM PST 24
Finished Jan 25 02:51:47 PM PST 24
Peak memory 209408 kb
Host smart-aff47805-5773-43d8-a6a0-31e2bfbb1ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553705846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3553705846
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3929686772
Short name T387
Test name
Test status
Simulation time 83070403 ps
CPU time 3.49 seconds
Started Jan 25 02:51:13 PM PST 24
Finished Jan 25 02:51:21 PM PST 24
Peak memory 214272 kb
Host smart-b471a7b4-bbf3-4a75-88be-3c25ae78d3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929686772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3929686772
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2755352886
Short name T894
Test name
Test status
Simulation time 55684796 ps
CPU time 4.04 seconds
Started Jan 25 02:51:26 PM PST 24
Finished Jan 25 02:51:33 PM PST 24
Peak memory 219972 kb
Host smart-1f6f747e-d5a4-4100-85d7-24755bbd5b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755352886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2755352886
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3753289940
Short name T827
Test name
Test status
Simulation time 81972578 ps
CPU time 3.95 seconds
Started Jan 25 02:51:32 PM PST 24
Finished Jan 25 02:51:50 PM PST 24
Peak memory 222360 kb
Host smart-bee38504-174b-4548-908e-f93eb1efd39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753289940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3753289940
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.4186166112
Short name T1062
Test name
Test status
Simulation time 403301844 ps
CPU time 5.49 seconds
Started Jan 25 02:50:57 PM PST 24
Finished Jan 25 02:51:09 PM PST 24
Peak memory 214224 kb
Host smart-f19ae5d3-b0bc-48d5-9857-e83345c08e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186166112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.4186166112
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.784151851
Short name T337
Test name
Test status
Simulation time 74369200 ps
CPU time 1.79 seconds
Started Jan 25 02:50:57 PM PST 24
Finished Jan 25 02:51:05 PM PST 24
Peak memory 206764 kb
Host smart-dc926f56-eb3d-4501-b1df-ace151368052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784151851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.784151851
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3644763719
Short name T842
Test name
Test status
Simulation time 69151786 ps
CPU time 3.1 seconds
Started Jan 25 02:51:02 PM PST 24
Finished Jan 25 02:51:13 PM PST 24
Peak memory 206880 kb
Host smart-9025d05c-eddd-4df1-b158-97fc95200c0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644763719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3644763719
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2316861205
Short name T370
Test name
Test status
Simulation time 158600617 ps
CPU time 3.08 seconds
Started Jan 25 02:51:03 PM PST 24
Finished Jan 25 02:51:14 PM PST 24
Peak memory 206868 kb
Host smart-ff590dca-149a-4bfd-bea6-e11479726e14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316861205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2316861205
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3671828425
Short name T578
Test name
Test status
Simulation time 71089311 ps
CPU time 2.46 seconds
Started Jan 25 02:50:57 PM PST 24
Finished Jan 25 02:51:05 PM PST 24
Peak memory 206636 kb
Host smart-fac374d2-8e16-4031-9443-40e56f4c797c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671828425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3671828425
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.206822541
Short name T668
Test name
Test status
Simulation time 61831300 ps
CPU time 3.06 seconds
Started Jan 25 02:51:40 PM PST 24
Finished Jan 25 02:51:58 PM PST 24
Peak memory 209552 kb
Host smart-5e43041a-5143-4a94-8d0d-f074f1f8e5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206822541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.206822541
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3779328270
Short name T545
Test name
Test status
Simulation time 438474846 ps
CPU time 3.07 seconds
Started Jan 25 02:50:58 PM PST 24
Finished Jan 25 02:51:09 PM PST 24
Peak memory 208784 kb
Host smart-ae8b21cc-c6b6-4ff9-bcce-53ca6c4daff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779328270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3779328270
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1322623396
Short name T697
Test name
Test status
Simulation time 179593985 ps
CPU time 11.28 seconds
Started Jan 25 02:51:24 PM PST 24
Finished Jan 25 02:51:39 PM PST 24
Peak memory 222704 kb
Host smart-d14d741c-73b2-42fa-8056-ae29367f225d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322623396 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1322623396
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2026559540
Short name T624
Test name
Test status
Simulation time 112642945 ps
CPU time 4.88 seconds
Started Jan 25 02:51:30 PM PST 24
Finished Jan 25 02:51:50 PM PST 24
Peak memory 218448 kb
Host smart-92d7b967-7323-4658-9157-5d2080a27006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026559540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2026559540
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.612940499
Short name T160
Test name
Test status
Simulation time 66125627 ps
CPU time 2.12 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:52:09 PM PST 24
Peak memory 209808 kb
Host smart-6f5557b7-9d35-4259-b975-c01902910b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612940499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.612940499
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3454917078
Short name T91
Test name
Test status
Simulation time 13599880 ps
CPU time 0.98 seconds
Started Jan 25 02:51:31 PM PST 24
Finished Jan 25 02:51:47 PM PST 24
Peak memory 205980 kb
Host smart-0604c71a-9dab-4709-a351-74c6a0b8ebde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454917078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3454917078
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4239957904
Short name T1033
Test name
Test status
Simulation time 635204841 ps
CPU time 31.23 seconds
Started Jan 25 02:51:40 PM PST 24
Finished Jan 25 02:52:26 PM PST 24
Peak memory 214180 kb
Host smart-aaf09969-dd0a-43d0-8e35-bfdb920681c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4239957904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4239957904
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1834000996
Short name T992
Test name
Test status
Simulation time 248050485 ps
CPU time 8.57 seconds
Started Jan 25 02:51:24 PM PST 24
Finished Jan 25 02:51:35 PM PST 24
Peak memory 214616 kb
Host smart-d7a4ad1a-c3ca-4245-933c-f9b7545eba5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834000996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1834000996
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2513680659
Short name T919
Test name
Test status
Simulation time 1719158880 ps
CPU time 8.71 seconds
Started Jan 25 02:51:46 PM PST 24
Finished Jan 25 02:52:13 PM PST 24
Peak memory 208476 kb
Host smart-6a17b204-d34b-4b3d-8e80-dd22f743db8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513680659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2513680659
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2748916308
Short name T260
Test name
Test status
Simulation time 542124442 ps
CPU time 5.85 seconds
Started Jan 25 02:51:30 PM PST 24
Finished Jan 25 02:51:51 PM PST 24
Peak memory 219260 kb
Host smart-5d0b08b6-8bc6-48f5-958a-d16b065bf85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748916308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2748916308
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2699959511
Short name T279
Test name
Test status
Simulation time 589220029 ps
CPU time 4.28 seconds
Started Jan 25 02:51:41 PM PST 24
Finished Jan 25 02:52:00 PM PST 24
Peak memory 211296 kb
Host smart-b42916f7-4155-4523-8bdd-5f67d1a79f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699959511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2699959511
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3058529592
Short name T893
Test name
Test status
Simulation time 98195669 ps
CPU time 3 seconds
Started Jan 25 02:51:47 PM PST 24
Finished Jan 25 02:52:08 PM PST 24
Peak memory 208872 kb
Host smart-849084cb-fd94-432b-b1d7-e77a25f85ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058529592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3058529592
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1894470039
Short name T321
Test name
Test status
Simulation time 1493605845 ps
CPU time 3.91 seconds
Started Jan 25 02:51:26 PM PST 24
Finished Jan 25 02:51:33 PM PST 24
Peak memory 208888 kb
Host smart-54ba29b8-36e5-45b7-b253-96692e0ba25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894470039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1894470039
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3126268329
Short name T677
Test name
Test status
Simulation time 139082827 ps
CPU time 3.36 seconds
Started Jan 25 02:51:42 PM PST 24
Finished Jan 25 02:52:03 PM PST 24
Peak memory 208132 kb
Host smart-2660a005-4460-48e9-b3c6-21cac20f73b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126268329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3126268329
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3669661995
Short name T355
Test name
Test status
Simulation time 1130988140 ps
CPU time 11.91 seconds
Started Jan 25 02:51:27 PM PST 24
Finished Jan 25 02:51:45 PM PST 24
Peak memory 208744 kb
Host smart-b271a3f9-83b6-46c5-9469-4d5e57e656bc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669661995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3669661995
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3659946775
Short name T968
Test name
Test status
Simulation time 53378964 ps
CPU time 2.58 seconds
Started Jan 25 02:51:23 PM PST 24
Finished Jan 25 02:51:27 PM PST 24
Peak memory 206872 kb
Host smart-475de3f0-7316-4173-8537-63bd79ad36e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659946775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3659946775
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1024737928
Short name T858
Test name
Test status
Simulation time 9139889060 ps
CPU time 64.34 seconds
Started Jan 25 02:51:26 PM PST 24
Finished Jan 25 02:52:33 PM PST 24
Peak memory 208124 kb
Host smart-e371c985-81c7-4a31-b8eb-69abd6b4bbd3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024737928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1024737928
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1076206804
Short name T793
Test name
Test status
Simulation time 297468960 ps
CPU time 3.25 seconds
Started Jan 25 02:51:40 PM PST 24
Finished Jan 25 02:51:58 PM PST 24
Peak memory 218104 kb
Host smart-d3bbbc22-5c95-4648-8f5f-a3d7ea90d706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076206804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1076206804
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2141087414
Short name T1
Test name
Test status
Simulation time 384344836 ps
CPU time 5.09 seconds
Started Jan 25 02:51:46 PM PST 24
Finished Jan 25 02:52:09 PM PST 24
Peak memory 208028 kb
Host smart-609a9614-cd16-42fa-b2bf-b26ef0201443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141087414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2141087414
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.717488372
Short name T998
Test name
Test status
Simulation time 285881958 ps
CPU time 10.48 seconds
Started Jan 25 02:51:43 PM PST 24
Finished Jan 25 02:52:12 PM PST 24
Peak memory 214980 kb
Host smart-8f3ea268-31a9-4356-bea9-f12e7f24e796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717488372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.717488372
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3468830645
Short name T35
Test name
Test status
Simulation time 545697458 ps
CPU time 4.83 seconds
Started Jan 25 02:51:30 PM PST 24
Finished Jan 25 02:51:50 PM PST 24
Peak memory 207620 kb
Host smart-2a4cf634-e640-4b0e-8030-530b98f132f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468830645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3468830645
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.4287260895
Short name T551
Test name
Test status
Simulation time 3671902086 ps
CPU time 14.09 seconds
Started Jan 25 02:51:29 PM PST 24
Finished Jan 25 02:52:00 PM PST 24
Peak memory 211568 kb
Host smart-5dc565d2-6424-4c98-ba0f-200db4c36830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287260895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.4287260895
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1380491274
Short name T974
Test name
Test status
Simulation time 9797834 ps
CPU time 0.76 seconds
Started Jan 25 02:51:30 PM PST 24
Finished Jan 25 02:51:46 PM PST 24
Peak memory 205868 kb
Host smart-cd5e47cb-e334-4581-8670-a46997ecc3b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380491274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1380491274
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3109604681
Short name T208
Test name
Test status
Simulation time 393198497 ps
CPU time 10.21 seconds
Started Jan 25 02:51:40 PM PST 24
Finished Jan 25 02:52:05 PM PST 24
Peak memory 214652 kb
Host smart-f02d030c-4fba-4089-a8c6-d2fa9fb38867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109604681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3109604681
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1741233212
Short name T183
Test name
Test status
Simulation time 1041796883 ps
CPU time 14.38 seconds
Started Jan 25 02:51:24 PM PST 24
Finished Jan 25 02:51:40 PM PST 24
Peak memory 222676 kb
Host smart-e504357f-9e67-487c-a8cc-e39ec97fa61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741233212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1741233212
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3497371649
Short name T871
Test name
Test status
Simulation time 342174786 ps
CPU time 1.66 seconds
Started Jan 25 02:51:42 PM PST 24
Finished Jan 25 02:52:01 PM PST 24
Peak memory 207220 kb
Host smart-f6371ee0-c1d6-4706-8b5c-111b3af6bbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497371649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3497371649
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.4128444663
Short name T234
Test name
Test status
Simulation time 2134138697 ps
CPU time 28.71 seconds
Started Jan 25 02:51:33 PM PST 24
Finished Jan 25 02:52:14 PM PST 24
Peak memory 222404 kb
Host smart-6b6de10f-7b08-4e30-b4ca-dfc9ef139963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128444663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.4128444663
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.4006536058
Short name T844
Test name
Test status
Simulation time 91541502 ps
CPU time 4.28 seconds
Started Jan 25 02:51:32 PM PST 24
Finished Jan 25 02:51:50 PM PST 24
Peak memory 219272 kb
Host smart-28f4a081-9bfa-49d7-ade5-d0b8d945b5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006536058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.4006536058
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1521150618
Short name T569
Test name
Test status
Simulation time 6867518034 ps
CPU time 79.85 seconds
Started Jan 25 02:51:45 PM PST 24
Finished Jan 25 02:53:23 PM PST 24
Peak memory 222464 kb
Host smart-43613281-bf26-4b12-935f-33c9755368d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521150618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1521150618
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.205777103
Short name T865
Test name
Test status
Simulation time 31563021435 ps
CPU time 61.87 seconds
Started Jan 25 02:51:31 PM PST 24
Finished Jan 25 02:52:47 PM PST 24
Peak memory 208528 kb
Host smart-824c68fa-207d-4791-81dc-b70f96661da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205777103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.205777103
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3018026641
Short name T550
Test name
Test status
Simulation time 125609867 ps
CPU time 2.38 seconds
Started Jan 25 02:51:30 PM PST 24
Finished Jan 25 02:51:48 PM PST 24
Peak memory 206808 kb
Host smart-31083a8e-c7cc-4c0d-a3e7-b571d62d7efd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018026641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3018026641
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2849565677
Short name T680
Test name
Test status
Simulation time 57456104 ps
CPU time 3.03 seconds
Started Jan 25 02:51:31 PM PST 24
Finished Jan 25 02:51:49 PM PST 24
Peak memory 208740 kb
Host smart-f4fd255f-aa95-4429-8bc3-1abb4e3e6fee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849565677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2849565677
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1040697211
Short name T872
Test name
Test status
Simulation time 222883652 ps
CPU time 3.21 seconds
Started Jan 25 02:51:32 PM PST 24
Finished Jan 25 02:51:49 PM PST 24
Peak memory 206708 kb
Host smart-0dfb92c1-6c43-489a-b5d1-d68e896dfa51
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040697211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1040697211
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1645355177
Short name T1019
Test name
Test status
Simulation time 196047529 ps
CPU time 2.52 seconds
Started Jan 25 02:51:32 PM PST 24
Finished Jan 25 02:51:48 PM PST 24
Peak memory 209648 kb
Host smart-20fc7ec2-879b-4edc-a483-372cf059121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645355177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1645355177
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2764678551
Short name T611
Test name
Test status
Simulation time 154613576 ps
CPU time 2.77 seconds
Started Jan 25 02:51:46 PM PST 24
Finished Jan 25 02:52:07 PM PST 24
Peak memory 206868 kb
Host smart-9fdb9690-b4d4-4ee7-b0df-e0e19564957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764678551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2764678551
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3231180541
Short name T1023
Test name
Test status
Simulation time 1966230724 ps
CPU time 23.35 seconds
Started Jan 25 02:51:32 PM PST 24
Finished Jan 25 02:52:09 PM PST 24
Peak memory 216860 kb
Host smart-88871ac4-12b1-4918-b173-7c902b75fb5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231180541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3231180541
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1932041796
Short name T674
Test name
Test status
Simulation time 156335156 ps
CPU time 4.75 seconds
Started Jan 25 02:51:46 PM PST 24
Finished Jan 25 02:52:09 PM PST 24
Peak memory 222464 kb
Host smart-b1730639-b84e-442f-9298-235bf273448b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932041796 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1932041796
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.129635793
Short name T688
Test name
Test status
Simulation time 257869099 ps
CPU time 7.56 seconds
Started Jan 25 02:51:26 PM PST 24
Finished Jan 25 02:51:37 PM PST 24
Peak memory 214420 kb
Host smart-b9f1ef14-cfbb-4193-ac76-30563d17255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129635793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.129635793
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3690145581
Short name T679
Test name
Test status
Simulation time 63787461 ps
CPU time 2.15 seconds
Started Jan 25 02:51:30 PM PST 24
Finished Jan 25 02:51:48 PM PST 24
Peak memory 210044 kb
Host smart-5e939c46-186e-40f9-aa38-b0a58182184f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690145581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3690145581
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.459766684
Short name T837
Test name
Test status
Simulation time 55646603 ps
CPU time 0.78 seconds
Started Jan 25 02:51:45 PM PST 24
Finished Jan 25 02:52:04 PM PST 24
Peak memory 205912 kb
Host smart-a4625673-ffcc-47c7-9979-dfb17b24edcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459766684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.459766684
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.668829703
Short name T1047
Test name
Test status
Simulation time 521189930 ps
CPU time 5 seconds
Started Jan 25 02:51:50 PM PST 24
Finished Jan 25 02:52:14 PM PST 24
Peak memory 209236 kb
Host smart-1a154b58-b5db-4b59-8bc1-bc5c0a582ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668829703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.668829703
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.948025779
Short name T242
Test name
Test status
Simulation time 1155945262 ps
CPU time 14.16 seconds
Started Jan 25 02:51:46 PM PST 24
Finished Jan 25 02:52:18 PM PST 24
Peak memory 218240 kb
Host smart-f1a5eee5-0330-43a3-a71a-594e4de593ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948025779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.948025779
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2133164119
Short name T372
Test name
Test status
Simulation time 893486101 ps
CPU time 4.85 seconds
Started Jan 25 02:51:46 PM PST 24
Finished Jan 25 02:52:09 PM PST 24
Peak memory 208284 kb
Host smart-c4caf12f-00db-4ff9-9064-7af5b84d103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133164119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2133164119
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.4148612036
Short name T934
Test name
Test status
Simulation time 92152037 ps
CPU time 2.63 seconds
Started Jan 25 02:51:31 PM PST 24
Finished Jan 25 02:51:48 PM PST 24
Peak memory 222324 kb
Host smart-fd3e8316-5023-4be6-ab68-97122c05ccf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148612036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.4148612036
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1819897452
Short name T338
Test name
Test status
Simulation time 1228079860 ps
CPU time 8.95 seconds
Started Jan 25 02:51:41 PM PST 24
Finished Jan 25 02:52:05 PM PST 24
Peak memory 208212 kb
Host smart-e37ea072-7b6c-4fb0-985f-430c07f9ded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819897452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1819897452
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1532118705
Short name T298
Test name
Test status
Simulation time 5481716540 ps
CPU time 49.16 seconds
Started Jan 25 02:51:28 PM PST 24
Finished Jan 25 02:52:26 PM PST 24
Peak memory 209220 kb
Host smart-d8cd24ca-72e5-4b07-9734-4f750bb9086a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532118705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1532118705
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1144614175
Short name T964
Test name
Test status
Simulation time 340832214 ps
CPU time 5.7 seconds
Started Jan 25 02:51:42 PM PST 24
Finished Jan 25 02:52:05 PM PST 24
Peak memory 208712 kb
Host smart-7c3dbe8f-c755-498d-b9e0-431b012f3f0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144614175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1144614175
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.908510661
Short name T557
Test name
Test status
Simulation time 510052884 ps
CPU time 7.08 seconds
Started Jan 25 02:51:50 PM PST 24
Finished Jan 25 02:52:16 PM PST 24
Peak memory 207820 kb
Host smart-e685df79-15e5-4bfa-b8cc-0b10185e407d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908510661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.908510661
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.624827984
Short name T1029
Test name
Test status
Simulation time 5787483320 ps
CPU time 23.47 seconds
Started Jan 25 02:51:28 PM PST 24
Finished Jan 25 02:52:03 PM PST 24
Peak memory 208720 kb
Host smart-4cd28aac-e3c0-4dde-92da-83fce940c8bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624827984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.624827984
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2504325624
Short name T883
Test name
Test status
Simulation time 115601590 ps
CPU time 2.17 seconds
Started Jan 25 02:51:45 PM PST 24
Finished Jan 25 02:52:05 PM PST 24
Peak memory 208620 kb
Host smart-b78bab8e-42f3-420f-a702-9649aebd660b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504325624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2504325624
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.4203691806
Short name T660
Test name
Test status
Simulation time 850940125 ps
CPU time 18 seconds
Started Jan 25 02:51:42 PM PST 24
Finished Jan 25 02:52:19 PM PST 24
Peak memory 208124 kb
Host smart-bb37d7cf-9506-493d-9750-9e3134668016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203691806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.4203691806
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1295200409
Short name T270
Test name
Test status
Simulation time 1485610485 ps
CPU time 21.08 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:52:29 PM PST 24
Peak memory 214856 kb
Host smart-6a508d97-b061-4f27-bd9f-9d1673a7905d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295200409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1295200409
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1442755713
Short name T329
Test name
Test status
Simulation time 475350468 ps
CPU time 8.62 seconds
Started Jan 25 02:51:25 PM PST 24
Finished Jan 25 02:51:37 PM PST 24
Peak memory 219408 kb
Host smart-a459a470-da1c-4348-b3fb-7ff1c0768bb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442755713 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1442755713
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1433254002
Short name T784
Test name
Test status
Simulation time 102026487 ps
CPU time 3.58 seconds
Started Jan 25 02:51:23 PM PST 24
Finished Jan 25 02:51:28 PM PST 24
Peak memory 208176 kb
Host smart-43dff3d4-1524-4c59-92e5-e86bde730880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433254002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1433254002
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.4119391906
Short name T567
Test name
Test status
Simulation time 129615125 ps
CPU time 2 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:52:09 PM PST 24
Peak memory 210168 kb
Host smart-8ed4593f-dd14-4d52-924e-d622cd4a046e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119391906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4119391906
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1843233894
Short name T92
Test name
Test status
Simulation time 49980293 ps
CPU time 0.89 seconds
Started Jan 25 02:45:49 PM PST 24
Finished Jan 25 02:46:14 PM PST 24
Peak memory 205832 kb
Host smart-474b79a0-2d15-41ac-b5fc-c0a2d285c8f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843233894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1843233894
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1498799941
Short name T1031
Test name
Test status
Simulation time 520221965 ps
CPU time 4.42 seconds
Started Jan 25 02:45:49 PM PST 24
Finished Jan 25 02:46:17 PM PST 24
Peak memory 214200 kb
Host smart-3670c72a-f0e0-44e3-bec8-c8d259621248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498799941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1498799941
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1613720406
Short name T20
Test name
Test status
Simulation time 298575345 ps
CPU time 4.41 seconds
Started Jan 25 02:45:34 PM PST 24
Finished Jan 25 02:46:06 PM PST 24
Peak memory 208988 kb
Host smart-3cf454e0-cb27-4853-99a0-1f42989caf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613720406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1613720406
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2339623412
Short name T990
Test name
Test status
Simulation time 74440376 ps
CPU time 1.59 seconds
Started Jan 25 02:45:52 PM PST 24
Finished Jan 25 02:46:16 PM PST 24
Peak memory 208520 kb
Host smart-66b8d131-a4de-4e3b-ab25-c78ecaa3e42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339623412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2339623412
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1586120301
Short name T345
Test name
Test status
Simulation time 79841319 ps
CPU time 3.78 seconds
Started Jan 25 02:45:35 PM PST 24
Finished Jan 25 02:46:06 PM PST 24
Peak memory 219128 kb
Host smart-b03c649c-71c6-4efe-92d6-b25588182e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586120301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1586120301
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1661630058
Short name T886
Test name
Test status
Simulation time 356758600 ps
CPU time 7.04 seconds
Started Jan 25 02:45:40 PM PST 24
Finished Jan 25 02:46:13 PM PST 24
Peak memory 208872 kb
Host smart-aad3eb1e-5708-4e04-a364-de040a0ed060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661630058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1661630058
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.415202498
Short name T1015
Test name
Test status
Simulation time 280779908 ps
CPU time 7.91 seconds
Started Jan 25 02:45:41 PM PST 24
Finished Jan 25 02:46:14 PM PST 24
Peak memory 208972 kb
Host smart-9ce09197-5f09-4650-9dee-6b67d34b3367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415202498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.415202498
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1778616268
Short name T12
Test name
Test status
Simulation time 1237984291 ps
CPU time 9.81 seconds
Started Jan 25 02:45:49 PM PST 24
Finished Jan 25 02:46:23 PM PST 24
Peak memory 230376 kb
Host smart-bfee8252-43c7-4fb6-8e71-81b97de78f3a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778616268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1778616268
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1046605427
Short name T895
Test name
Test status
Simulation time 121729040 ps
CPU time 2.43 seconds
Started Jan 25 02:45:41 PM PST 24
Finished Jan 25 02:46:09 PM PST 24
Peak memory 208768 kb
Host smart-f1429d16-54c6-4e17-9ecd-10cb549a6401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046605427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1046605427
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.4044443458
Short name T577
Test name
Test status
Simulation time 98310173 ps
CPU time 1.98 seconds
Started Jan 25 02:45:34 PM PST 24
Finished Jan 25 02:46:04 PM PST 24
Peak memory 206888 kb
Host smart-4de7b892-a455-45c2-b2bc-92d1c95ed916
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044443458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.4044443458
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2037584
Short name T830
Test name
Test status
Simulation time 1152285967 ps
CPU time 14.98 seconds
Started Jan 25 02:45:42 PM PST 24
Finished Jan 25 02:46:22 PM PST 24
Peak memory 208008 kb
Host smart-df245fff-fd07-40cb-bd0a-8f9a6c6b5de6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2037584
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2813706889
Short name T371
Test name
Test status
Simulation time 40883067 ps
CPU time 2.83 seconds
Started Jan 25 02:45:41 PM PST 24
Finished Jan 25 02:46:10 PM PST 24
Peak memory 208512 kb
Host smart-df316e3f-7d06-41ef-ad20-7e1427a1479e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813706889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2813706889
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1816492624
Short name T993
Test name
Test status
Simulation time 346082036 ps
CPU time 2.74 seconds
Started Jan 25 02:45:51 PM PST 24
Finished Jan 25 02:46:17 PM PST 24
Peak memory 207016 kb
Host smart-c0031d01-52a4-485b-a810-d531e8938e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816492624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1816492624
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1436303222
Short name T875
Test name
Test status
Simulation time 53717120 ps
CPU time 2.71 seconds
Started Jan 25 02:45:43 PM PST 24
Finished Jan 25 02:46:10 PM PST 24
Peak memory 206824 kb
Host smart-baae735d-a451-4254-9567-135ca5b49404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436303222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1436303222
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.751243111
Short name T96
Test name
Test status
Simulation time 99791442 ps
CPU time 7 seconds
Started Jan 25 02:45:42 PM PST 24
Finished Jan 25 02:46:14 PM PST 24
Peak memory 222668 kb
Host smart-75a87439-1f23-4cd7-a2ca-64d2fcf42668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751243111 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.751243111
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2851151464
Short name T606
Test name
Test status
Simulation time 1606558510 ps
CPU time 37.65 seconds
Started Jan 25 02:45:41 PM PST 24
Finished Jan 25 02:46:44 PM PST 24
Peak memory 208588 kb
Host smart-48d90611-f2f1-4507-93e4-ee138247d28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851151464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2851151464
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3166126135
Short name T743
Test name
Test status
Simulation time 134527597 ps
CPU time 1.92 seconds
Started Jan 25 02:45:41 PM PST 24
Finished Jan 25 02:46:08 PM PST 24
Peak memory 210124 kb
Host smart-0acea422-bc2a-42c0-8162-7ba661800470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166126135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3166126135
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1990123555
Short name T1028
Test name
Test status
Simulation time 31591887 ps
CPU time 0.79 seconds
Started Jan 25 02:51:49 PM PST 24
Finished Jan 25 02:52:09 PM PST 24
Peak memory 206084 kb
Host smart-ca9b6c85-61b9-4d76-b713-5aa1b9ff4694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990123555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1990123555
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1039104801
Short name T180
Test name
Test status
Simulation time 457671621 ps
CPU time 7.24 seconds
Started Jan 25 02:51:37 PM PST 24
Finished Jan 25 02:51:57 PM PST 24
Peak memory 214520 kb
Host smart-7389dba6-9d92-4d93-b727-127078490fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039104801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1039104801
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.920468342
Short name T1066
Test name
Test status
Simulation time 2374726003 ps
CPU time 6.52 seconds
Started Jan 25 02:51:26 PM PST 24
Finished Jan 25 02:51:40 PM PST 24
Peak memory 208612 kb
Host smart-ee9759bb-327a-4043-85e7-ae1e71638ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920468342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.920468342
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.623032988
Short name T720
Test name
Test status
Simulation time 4259240619 ps
CPU time 12.09 seconds
Started Jan 25 02:51:37 PM PST 24
Finished Jan 25 02:52:00 PM PST 24
Peak memory 214332 kb
Host smart-a17fd21b-2dbe-473e-bd77-41fefcdb3262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623032988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.623032988
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3018666762
Short name T237
Test name
Test status
Simulation time 285234329 ps
CPU time 11.2 seconds
Started Jan 25 02:51:49 PM PST 24
Finished Jan 25 02:52:20 PM PST 24
Peak memory 211424 kb
Host smart-d95909f2-010a-4cdb-a92d-a743f5d9c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018666762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3018666762
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1527680053
Short name T796
Test name
Test status
Simulation time 123679472 ps
CPU time 1.64 seconds
Started Jan 25 02:51:40 PM PST 24
Finished Jan 25 02:51:57 PM PST 24
Peak memory 206004 kb
Host smart-ecf27711-8c7a-4240-98ba-cd075309867e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527680053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1527680053
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3822900725
Short name T333
Test name
Test status
Simulation time 232900795 ps
CPU time 5.74 seconds
Started Jan 25 02:51:37 PM PST 24
Finished Jan 25 02:51:54 PM PST 24
Peak memory 210216 kb
Host smart-23ada74c-0972-405b-b227-ceeb8e82607c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822900725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3822900725
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.491924689
Short name T791
Test name
Test status
Simulation time 45044318 ps
CPU time 2.63 seconds
Started Jan 25 02:51:45 PM PST 24
Finished Jan 25 02:52:06 PM PST 24
Peak memory 206716 kb
Host smart-8f260cb0-9fa7-4d47-bd10-5683d911e03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491924689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.491924689
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1880170366
Short name T873
Test name
Test status
Simulation time 21945544 ps
CPU time 1.94 seconds
Started Jan 25 02:51:38 PM PST 24
Finished Jan 25 02:51:53 PM PST 24
Peak memory 206828 kb
Host smart-a0c27615-cf22-435b-9060-79b38f5a461f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880170366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1880170366
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3910551835
Short name T876
Test name
Test status
Simulation time 77084763 ps
CPU time 2.98 seconds
Started Jan 25 02:51:45 PM PST 24
Finished Jan 25 02:52:06 PM PST 24
Peak memory 206804 kb
Host smart-dc6a83e9-4658-4902-9f76-4e6e7f7e6e17
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910551835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3910551835
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2139604283
Short name T639
Test name
Test status
Simulation time 118724280 ps
CPU time 2.3 seconds
Started Jan 25 02:51:36 PM PST 24
Finished Jan 25 02:51:49 PM PST 24
Peak memory 206768 kb
Host smart-15652620-43e0-409f-9ca2-2d8fff0d8ba1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139604283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2139604283
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1909381308
Short name T739
Test name
Test status
Simulation time 382949278 ps
CPU time 5.72 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:52:13 PM PST 24
Peak memory 209868 kb
Host smart-dd26d24d-8048-4e18-bcb5-f010785b5130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909381308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1909381308
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2640007151
Short name T1063
Test name
Test status
Simulation time 529390783 ps
CPU time 3.36 seconds
Started Jan 25 02:51:45 PM PST 24
Finished Jan 25 02:52:07 PM PST 24
Peak memory 208272 kb
Host smart-78077d06-0aa2-4165-9b67-0f5aad3f9dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640007151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2640007151
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1619568556
Short name T373
Test name
Test status
Simulation time 298425123 ps
CPU time 6.75 seconds
Started Jan 25 02:51:37 PM PST 24
Finished Jan 25 02:51:57 PM PST 24
Peak memory 214240 kb
Host smart-5083d111-445d-418d-af41-faeb1bbc5eed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619568556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1619568556
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.261807317
Short name T928
Test name
Test status
Simulation time 143723051 ps
CPU time 8.12 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:52:15 PM PST 24
Peak memory 222804 kb
Host smart-18361b91-ef92-491f-8c08-f2ccd6f99950
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261807317 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.261807317
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2976377784
Short name T933
Test name
Test status
Simulation time 1229057569 ps
CPU time 21.88 seconds
Started Jan 25 02:51:38 PM PST 24
Finished Jan 25 02:52:13 PM PST 24
Peak memory 209104 kb
Host smart-62656340-0e5a-49fa-8122-2eb78ce76bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976377784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2976377784
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1412761875
Short name T799
Test name
Test status
Simulation time 92846456 ps
CPU time 3.84 seconds
Started Jan 25 02:51:49 PM PST 24
Finished Jan 25 02:52:13 PM PST 24
Peak memory 210000 kb
Host smart-364f0bcd-41d6-4abf-a5bb-5f4a88764f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412761875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1412761875
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.131425962
Short name T401
Test name
Test status
Simulation time 18398268 ps
CPU time 0.75 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:52:25 PM PST 24
Peak memory 205896 kb
Host smart-f1c0a4e8-38c3-48b3-ad83-5b50f9423d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131425962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.131425962
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1389353991
Short name T395
Test name
Test status
Simulation time 2524561539 ps
CPU time 128.76 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:54:17 PM PST 24
Peak memory 215456 kb
Host smart-b90c6c55-69a3-4185-a683-2ac3b9acb3e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1389353991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1389353991
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2672823588
Short name T1032
Test name
Test status
Simulation time 400918615 ps
CPU time 3.21 seconds
Started Jan 25 02:52:10 PM PST 24
Finished Jan 25 02:52:29 PM PST 24
Peak memory 219376 kb
Host smart-61a79ee4-bc66-4560-bbd7-b739c8e7182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672823588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2672823588
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3719141618
Short name T340
Test name
Test status
Simulation time 125412537 ps
CPU time 3.28 seconds
Started Jan 25 02:51:29 PM PST 24
Finished Jan 25 02:51:48 PM PST 24
Peak memory 209244 kb
Host smart-02b62d4d-7b39-4734-a9ca-412fb3b11e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719141618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3719141618
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2710203576
Short name T88
Test name
Test status
Simulation time 213768853 ps
CPU time 3.73 seconds
Started Jan 25 02:52:09 PM PST 24
Finished Jan 25 02:52:29 PM PST 24
Peak memory 208596 kb
Host smart-085825c9-383c-4cec-8590-05ef659afeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710203576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2710203576
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1264192037
Short name T87
Test name
Test status
Simulation time 38257439 ps
CPU time 2.62 seconds
Started Jan 25 02:52:04 PM PST 24
Finished Jan 25 02:52:24 PM PST 24
Peak memory 208904 kb
Host smart-30b13dc1-0c4e-4919-b3d9-c8bb7f3d892c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264192037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1264192037
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1315974298
Short name T908
Test name
Test status
Simulation time 56140320 ps
CPU time 2.94 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:52:11 PM PST 24
Peak memory 214344 kb
Host smart-3aff31ea-0370-482c-82a8-bc1bba03e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315974298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1315974298
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3984714314
Short name T636
Test name
Test status
Simulation time 276603418 ps
CPU time 7.23 seconds
Started Jan 25 02:51:30 PM PST 24
Finished Jan 25 02:51:53 PM PST 24
Peak memory 208912 kb
Host smart-14d3a06e-6427-45cb-8b05-3f5650f5a695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984714314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3984714314
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.842522626
Short name T834
Test name
Test status
Simulation time 50114953 ps
CPU time 2.61 seconds
Started Jan 25 02:51:25 PM PST 24
Finished Jan 25 02:51:31 PM PST 24
Peak memory 206756 kb
Host smart-f2405f5d-e900-4679-a224-8044fea2e105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842522626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.842522626
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3979194525
Short name T369
Test name
Test status
Simulation time 365704549 ps
CPU time 9.2 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:52:17 PM PST 24
Peak memory 209152 kb
Host smart-7a3e5eb3-47e5-4d7a-a977-3c283c2322b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979194525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3979194525
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3280694892
Short name T745
Test name
Test status
Simulation time 21789673 ps
CPU time 1.88 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:52:09 PM PST 24
Peak memory 207068 kb
Host smart-0bc6e2a2-c6e5-48bd-b0a9-64e7d9931bca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280694892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3280694892
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.202094951
Short name T1043
Test name
Test status
Simulation time 50815168 ps
CPU time 2.76 seconds
Started Jan 25 02:51:30 PM PST 24
Finished Jan 25 02:51:48 PM PST 24
Peak memory 206712 kb
Host smart-5b8c897c-690a-4d0d-883e-8762fd1ef7aa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202094951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.202094951
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.550259022
Short name T549
Test name
Test status
Simulation time 50268287 ps
CPU time 2.43 seconds
Started Jan 25 02:52:11 PM PST 24
Finished Jan 25 02:52:29 PM PST 24
Peak memory 207016 kb
Host smart-0e4975d1-69b7-44dc-8a08-c544c2eaa421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550259022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.550259022
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2597337459
Short name T732
Test name
Test status
Simulation time 1281416967 ps
CPU time 27.8 seconds
Started Jan 25 02:51:48 PM PST 24
Finished Jan 25 02:52:35 PM PST 24
Peak memory 208116 kb
Host smart-7773fc84-799d-40f7-9f4c-b417bfe657f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597337459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2597337459
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1298278927
Short name T347
Test name
Test status
Simulation time 7893988321 ps
CPU time 238.32 seconds
Started Jan 25 02:52:10 PM PST 24
Finished Jan 25 02:56:24 PM PST 24
Peak memory 219156 kb
Host smart-226b6a3c-780c-4a46-b97d-425fba8e9eb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298278927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1298278927
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.469633339
Short name T245
Test name
Test status
Simulation time 607201743 ps
CPU time 14.85 seconds
Started Jan 25 02:52:11 PM PST 24
Finished Jan 25 02:52:41 PM PST 24
Peak memory 222568 kb
Host smart-13e65bcd-f444-46f6-8ccd-0afba6b8d95f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469633339 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.469633339
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2710637121
Short name T782
Test name
Test status
Simulation time 138332203 ps
CPU time 5.54 seconds
Started Jan 25 02:51:44 PM PST 24
Finished Jan 25 02:52:08 PM PST 24
Peak memory 208648 kb
Host smart-2b63e0f0-f9bf-4af4-93fa-ff3ef62229bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710637121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2710637121
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1522040745
Short name T955
Test name
Test status
Simulation time 1346022274 ps
CPU time 6.42 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:52:28 PM PST 24
Peak memory 210880 kb
Host smart-6410e71e-a4e8-428f-88e7-f20a6ab40e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522040745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1522040745
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.4048273718
Short name T579
Test name
Test status
Simulation time 13461684 ps
CPU time 0.76 seconds
Started Jan 25 02:52:03 PM PST 24
Finished Jan 25 02:52:21 PM PST 24
Peak memory 205880 kb
Host smart-af0575cb-04a0-4303-af79-ba02c3bd212e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048273718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.4048273718
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3785297695
Short name T379
Test name
Test status
Simulation time 52085677 ps
CPU time 3.78 seconds
Started Jan 25 02:52:10 PM PST 24
Finished Jan 25 02:52:29 PM PST 24
Peak memory 214252 kb
Host smart-ba780975-4441-439d-aa6b-4e98be1337fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3785297695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3785297695
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3853771101
Short name T818
Test name
Test status
Simulation time 106864411 ps
CPU time 3.21 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:52:25 PM PST 24
Peak memory 220552 kb
Host smart-7b589c8c-399c-4f39-8624-1b4b53a2057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853771101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3853771101
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2102343581
Short name T356
Test name
Test status
Simulation time 21258485407 ps
CPU time 28.76 seconds
Started Jan 25 02:52:10 PM PST 24
Finished Jan 25 02:52:55 PM PST 24
Peak memory 209604 kb
Host smart-0de7184a-362f-4732-af2d-fe2b72a0fb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102343581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2102343581
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.438301469
Short name T326
Test name
Test status
Simulation time 1911941428 ps
CPU time 7.8 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:52:30 PM PST 24
Peak memory 214140 kb
Host smart-485e6602-ef12-4d64-8908-710400f0fba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438301469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.438301469
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1376397710
Short name T90
Test name
Test status
Simulation time 94924403 ps
CPU time 2.86 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:52:25 PM PST 24
Peak memory 211632 kb
Host smart-772ddcaa-f96c-42ad-8cb9-0dfbc0e815f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376397710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1376397710
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1572726318
Short name T192
Test name
Test status
Simulation time 310098424 ps
CPU time 2.63 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:52:26 PM PST 24
Peak memory 216596 kb
Host smart-1179498d-12b7-431f-ba3f-52a91e0f0ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572726318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1572726318
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2693276720
Short name T603
Test name
Test status
Simulation time 97099925 ps
CPU time 3.17 seconds
Started Jan 25 02:52:09 PM PST 24
Finished Jan 25 02:52:28 PM PST 24
Peak memory 208156 kb
Host smart-89ccd269-32d6-4afa-a5a1-a6a2e2dfb078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693276720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2693276720
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2262219696
Short name T758
Test name
Test status
Simulation time 119996358 ps
CPU time 4.43 seconds
Started Jan 25 02:52:15 PM PST 24
Finished Jan 25 02:52:37 PM PST 24
Peak memory 206960 kb
Host smart-bd059bda-eade-4fe7-9b68-dee3de4c75aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262219696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2262219696
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1131553855
Short name T622
Test name
Test status
Simulation time 1927083948 ps
CPU time 48.77 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:53:11 PM PST 24
Peak memory 208316 kb
Host smart-b8dd6f85-695d-4f7c-a3db-4f836d7928db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131553855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1131553855
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1559858159
Short name T204
Test name
Test status
Simulation time 44990958 ps
CPU time 2.41 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:52:25 PM PST 24
Peak memory 207288 kb
Host smart-f3b4c544-2472-4605-888f-9a12deb82e8a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559858159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1559858159
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.4089097063
Short name T554
Test name
Test status
Simulation time 34831948 ps
CPU time 2.37 seconds
Started Jan 25 02:52:09 PM PST 24
Finished Jan 25 02:52:27 PM PST 24
Peak memory 206832 kb
Host smart-3fbaa2c7-ce0b-4d64-86bb-bc6b4b90e807
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089097063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.4089097063
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3880784889
Short name T315
Test name
Test status
Simulation time 102837571 ps
CPU time 2.11 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:52:24 PM PST 24
Peak memory 207920 kb
Host smart-51b2e8cd-a0ab-466f-a07e-5e0b33cca70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880784889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3880784889
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.521020796
Short name T940
Test name
Test status
Simulation time 453477781 ps
CPU time 3.85 seconds
Started Jan 25 02:52:09 PM PST 24
Finished Jan 25 02:52:28 PM PST 24
Peak memory 208636 kb
Host smart-e75787a1-af44-4be5-b739-39efc9aee9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521020796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.521020796
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3847470186
Short name T314
Test name
Test status
Simulation time 781834562 ps
CPU time 19.76 seconds
Started Jan 25 02:52:09 PM PST 24
Finished Jan 25 02:52:44 PM PST 24
Peak memory 220292 kb
Host smart-b0d5b30b-e85b-4f9b-bc8b-341f298ed765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847470186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3847470186
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2382671488
Short name T304
Test name
Test status
Simulation time 26843736480 ps
CPU time 43.2 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:53:05 PM PST 24
Peak memory 214424 kb
Host smart-81c3616e-213a-47bb-9227-bf30523ec328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382671488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2382671488
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1907537558
Short name T821
Test name
Test status
Simulation time 2658739100 ps
CPU time 12.05 seconds
Started Jan 25 02:52:04 PM PST 24
Finished Jan 25 02:52:34 PM PST 24
Peak memory 211292 kb
Host smart-f6a3a86c-51af-4035-8ed1-73ee4249a16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907537558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1907537558
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.296100491
Short name T558
Test name
Test status
Simulation time 14380594 ps
CPU time 0.96 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:52:25 PM PST 24
Peak memory 206292 kb
Host smart-bd124cfb-ce35-41ea-a921-019f466b0f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296100491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.296100491
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2108152370
Short name T391
Test name
Test status
Simulation time 196437686 ps
CPU time 3.85 seconds
Started Jan 25 02:52:06 PM PST 24
Finished Jan 25 02:52:27 PM PST 24
Peak memory 214316 kb
Host smart-48ed7c5f-64fd-468d-9657-46b4a9f628f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108152370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2108152370
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3697698648
Short name T798
Test name
Test status
Simulation time 80118419 ps
CPU time 2.23 seconds
Started Jan 25 02:52:11 PM PST 24
Finished Jan 25 02:52:29 PM PST 24
Peak memory 208808 kb
Host smart-b2959fd1-d66a-4f6d-8c4b-1c4632839511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697698648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3697698648
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3816159731
Short name T305
Test name
Test status
Simulation time 376453907 ps
CPU time 8.04 seconds
Started Jan 25 02:52:03 PM PST 24
Finished Jan 25 02:52:28 PM PST 24
Peak memory 219928 kb
Host smart-b8f0958b-bde2-467f-836e-04fa84d76708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816159731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3816159731
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1129229935
Short name T40
Test name
Test status
Simulation time 170277154 ps
CPU time 6.54 seconds
Started Jan 25 02:52:11 PM PST 24
Finished Jan 25 02:52:33 PM PST 24
Peak memory 210344 kb
Host smart-ee023243-47d8-434f-aef5-5aceace60bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129229935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1129229935
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4248831583
Short name T953
Test name
Test status
Simulation time 72616193 ps
CPU time 4.71 seconds
Started Jan 25 02:52:10 PM PST 24
Finished Jan 25 02:52:30 PM PST 24
Peak memory 222424 kb
Host smart-ddfb66cc-f405-4113-9521-bb210a6576ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248831583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4248831583
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.997200894
Short name T775
Test name
Test status
Simulation time 441729509 ps
CPU time 8.26 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:52:31 PM PST 24
Peak memory 208116 kb
Host smart-c9c6f7ad-b37f-4035-95c9-4bbe95a9f9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997200894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.997200894
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3608668740
Short name T357
Test name
Test status
Simulation time 749498471 ps
CPU time 23.56 seconds
Started Jan 25 02:52:09 PM PST 24
Finished Jan 25 02:52:48 PM PST 24
Peak memory 208432 kb
Host smart-61e74a9f-44b5-4366-95f5-6e2f71fa4a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608668740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3608668740
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2683823961
Short name T308
Test name
Test status
Simulation time 53880890 ps
CPU time 2.16 seconds
Started Jan 25 02:52:01 PM PST 24
Finished Jan 25 02:52:20 PM PST 24
Peak memory 208496 kb
Host smart-20fdde16-ef13-4daa-9abd-86c42c571ed6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683823961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2683823961
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.301192233
Short name T728
Test name
Test status
Simulation time 166871250 ps
CPU time 3.9 seconds
Started Jan 25 02:52:11 PM PST 24
Finished Jan 25 02:52:30 PM PST 24
Peak memory 208636 kb
Host smart-ede07a4e-173b-42a3-b4ac-8d50d5142348
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301192233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.301192233
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3366710651
Short name T970
Test name
Test status
Simulation time 284642239 ps
CPU time 4.59 seconds
Started Jan 25 02:52:06 PM PST 24
Finished Jan 25 02:52:27 PM PST 24
Peak memory 206712 kb
Host smart-e645087b-ca61-4dae-99cd-f5646ae2ffdd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366710651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3366710651
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2575328115
Short name T852
Test name
Test status
Simulation time 180946815 ps
CPU time 2.67 seconds
Started Jan 25 02:52:10 PM PST 24
Finished Jan 25 02:52:28 PM PST 24
Peak memory 213672 kb
Host smart-688d8648-683b-4bd9-a34b-d3d6dbfb4c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575328115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2575328115
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2931239288
Short name T1072
Test name
Test status
Simulation time 8134131220 ps
CPU time 41.57 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:53:06 PM PST 24
Peak memory 207768 kb
Host smart-7e86fec1-e9cc-4716-ac5a-1e5e8d954e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931239288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2931239288
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.936925489
Short name T173
Test name
Test status
Simulation time 836223905 ps
CPU time 5.92 seconds
Started Jan 25 02:52:15 PM PST 24
Finished Jan 25 02:52:38 PM PST 24
Peak memory 209184 kb
Host smart-35162431-ca99-4d80-9920-bae351a241c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936925489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.936925489
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2744076022
Short name T903
Test name
Test status
Simulation time 422712008 ps
CPU time 6.95 seconds
Started Jan 25 02:52:02 PM PST 24
Finished Jan 25 02:52:25 PM PST 24
Peak memory 222604 kb
Host smart-136a27e0-e28b-47ec-8d8d-237e0bdefa10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744076022 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2744076022
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2390046281
Short name T854
Test name
Test status
Simulation time 373606643 ps
CPU time 3.09 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:52:25 PM PST 24
Peak memory 218096 kb
Host smart-df2a5edc-794d-45c8-9a52-ce699f0c7dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390046281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2390046281
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3304618376
Short name T888
Test name
Test status
Simulation time 68242255 ps
CPU time 2.27 seconds
Started Jan 25 02:52:11 PM PST 24
Finished Jan 25 02:52:29 PM PST 24
Peak memory 210044 kb
Host smart-6692f558-aec0-468a-99ca-1553ba37874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304618376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3304618376
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2444555424
Short name T666
Test name
Test status
Simulation time 27974986 ps
CPU time 0.77 seconds
Started Jan 25 02:52:11 PM PST 24
Finished Jan 25 02:52:28 PM PST 24
Peak memory 205920 kb
Host smart-917856fd-d17c-44b1-8e60-a62aa959e754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444555424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2444555424
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2453779667
Short name T396
Test name
Test status
Simulation time 4195615572 ps
CPU time 65.96 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:53:30 PM PST 24
Peak memory 215308 kb
Host smart-ae9e333e-6d15-4a0c-8605-d87480a4db2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453779667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2453779667
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.507757123
Short name T878
Test name
Test status
Simulation time 112563831 ps
CPU time 3.96 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:52:28 PM PST 24
Peak memory 223056 kb
Host smart-0278d639-8e02-4535-848f-7257edc80f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507757123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.507757123
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1392977334
Short name T671
Test name
Test status
Simulation time 54242943 ps
CPU time 2.47 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:52:24 PM PST 24
Peak memory 207764 kb
Host smart-c6fa8806-bbc4-4625-a522-8151aa57f6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392977334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1392977334
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.261219738
Short name T23
Test name
Test status
Simulation time 207381071 ps
CPU time 6.9 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:52:31 PM PST 24
Peak memory 218392 kb
Host smart-01623bba-a277-4c43-8503-937d7c6d8198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261219738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.261219738
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1418217766
Short name T196
Test name
Test status
Simulation time 68990249 ps
CPU time 2.61 seconds
Started Jan 25 02:52:10 PM PST 24
Finished Jan 25 02:52:28 PM PST 24
Peak memory 209556 kb
Host smart-7b1cb1fa-bb67-4d10-89ed-78b31bd0758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418217766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1418217766
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3378148422
Short name T695
Test name
Test status
Simulation time 273526743 ps
CPU time 7.82 seconds
Started Jan 25 02:52:02 PM PST 24
Finished Jan 25 02:52:27 PM PST 24
Peak memory 207184 kb
Host smart-d22b0dfd-55d2-4803-8b2f-61fe388c4a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378148422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3378148422
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1716109783
Short name T175
Test name
Test status
Simulation time 539449741 ps
CPU time 8.12 seconds
Started Jan 25 02:52:05 PM PST 24
Finished Jan 25 02:52:30 PM PST 24
Peak memory 208516 kb
Host smart-ae629c8c-91e3-44af-9b60-6a77ea4a6774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716109783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1716109783
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3818555491
Short name T965
Test name
Test status
Simulation time 360118018 ps
CPU time 3.21 seconds
Started Jan 25 02:52:09 PM PST 24
Finished Jan 25 02:52:28 PM PST 24
Peak memory 206856 kb
Host smart-e0adcc37-79c8-44b4-aa76-1dc665ae0458
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818555491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3818555491
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3903768755
Short name T685
Test name
Test status
Simulation time 908285182 ps
CPU time 32.41 seconds
Started Jan 25 02:52:09 PM PST 24
Finished Jan 25 02:52:57 PM PST 24
Peak memory 208828 kb
Host smart-fcca5aac-50bf-4c01-be54-5fec6fdd14ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903768755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3903768755
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3378014118
Short name T225
Test name
Test status
Simulation time 187841539 ps
CPU time 2.67 seconds
Started Jan 25 02:52:11 PM PST 24
Finished Jan 25 02:52:30 PM PST 24
Peak memory 206704 kb
Host smart-55fb8409-3a98-471a-b4e0-31159fc9afec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378014118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3378014118
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.820529471
Short name T673
Test name
Test status
Simulation time 109292481 ps
CPU time 4.2 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:52:28 PM PST 24
Peak memory 208472 kb
Host smart-6bff51ff-b339-42bf-a46d-ac1bec4a1fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820529471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.820529471
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1353345692
Short name T982
Test name
Test status
Simulation time 39870152 ps
CPU time 1.64 seconds
Started Jan 25 02:52:06 PM PST 24
Finished Jan 25 02:52:25 PM PST 24
Peak memory 206708 kb
Host smart-4b4f3448-85e4-4a31-9645-da55b82bdac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353345692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1353345692
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1284907934
Short name T224
Test name
Test status
Simulation time 2746404445 ps
CPU time 27.17 seconds
Started Jan 25 02:52:13 PM PST 24
Finished Jan 25 02:52:57 PM PST 24
Peak memory 216768 kb
Host smart-5e180fac-b743-449c-bee9-af59bbe685b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284907934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1284907934
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3970022344
Short name T980
Test name
Test status
Simulation time 175512785 ps
CPU time 2.82 seconds
Started Jan 25 02:52:07 PM PST 24
Finished Jan 25 02:52:26 PM PST 24
Peak memory 222860 kb
Host smart-1279c3a8-fd74-44f5-8154-2ace7d910a14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970022344 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3970022344
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.4239729096
Short name T1049
Test name
Test status
Simulation time 1276443834 ps
CPU time 3.89 seconds
Started Jan 25 02:52:01 PM PST 24
Finished Jan 25 02:52:22 PM PST 24
Peak memory 207344 kb
Host smart-39daf4a4-a8e7-48ba-9d5c-88188d85c507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239729096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.4239729096
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1828704805
Short name T701
Test name
Test status
Simulation time 118709686 ps
CPU time 2.57 seconds
Started Jan 25 02:52:10 PM PST 24
Finished Jan 25 02:52:28 PM PST 24
Peak memory 210108 kb
Host smart-55002f67-7d72-4519-a51f-16cc86e68c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828704805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1828704805
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2958576174
Short name T909
Test name
Test status
Simulation time 11233950 ps
CPU time 0.75 seconds
Started Jan 25 02:52:49 PM PST 24
Finished Jan 25 02:53:04 PM PST 24
Peak memory 205916 kb
Host smart-6a03f378-6c5e-4ae7-97b0-055593ee8c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958576174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2958576174
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3350780262
Short name T336
Test name
Test status
Simulation time 206003146 ps
CPU time 4.09 seconds
Started Jan 25 02:52:14 PM PST 24
Finished Jan 25 02:52:34 PM PST 24
Peak memory 214292 kb
Host smart-6684054e-b8db-4e50-b496-ff4ef52a3fb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350780262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3350780262
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1611386562
Short name T29
Test name
Test status
Simulation time 79691380 ps
CPU time 3.16 seconds
Started Jan 25 02:52:39 PM PST 24
Finished Jan 25 02:52:51 PM PST 24
Peak memory 214300 kb
Host smart-cc8ff5c3-a6d2-4213-9bcb-f0becaacdc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611386562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1611386562
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2943998961
Short name T678
Test name
Test status
Simulation time 45533275 ps
CPU time 1.62 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:52:26 PM PST 24
Peak memory 207480 kb
Host smart-0647e27c-cd40-4375-a686-87ae24c37c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943998961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2943998961
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3849282195
Short name T374
Test name
Test status
Simulation time 334756493 ps
CPU time 4.46 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:52:29 PM PST 24
Peak memory 209188 kb
Host smart-9bbf0abe-d43b-41b8-b818-bd798e287ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849282195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3849282195
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.514298007
Short name T262
Test name
Test status
Simulation time 382779757 ps
CPU time 5.05 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:52:29 PM PST 24
Peak memory 210144 kb
Host smart-45d16d07-57c4-4a48-9b06-b770deb02404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514298007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.514298007
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3413925054
Short name T809
Test name
Test status
Simulation time 57129006 ps
CPU time 3.53 seconds
Started Jan 25 02:52:09 PM PST 24
Finished Jan 25 02:52:29 PM PST 24
Peak memory 209924 kb
Host smart-b58958d2-6aa2-441a-8c52-5e0eb367cdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413925054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3413925054
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.18438572
Short name T1054
Test name
Test status
Simulation time 2309154871 ps
CPU time 16.1 seconds
Started Jan 25 02:52:11 PM PST 24
Finished Jan 25 02:52:43 PM PST 24
Peak memory 209148 kb
Host smart-b4eae81b-9eaa-487d-91d9-042d3c0c2b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18438572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.18438572
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.806010486
Short name T244
Test name
Test status
Simulation time 270835197 ps
CPU time 10.06 seconds
Started Jan 25 02:52:14 PM PST 24
Finished Jan 25 02:52:40 PM PST 24
Peak memory 208728 kb
Host smart-5f213918-7294-4ada-b543-e337283dccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806010486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.806010486
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.989769010
Short name T832
Test name
Test status
Simulation time 138284444 ps
CPU time 4.43 seconds
Started Jan 25 02:52:10 PM PST 24
Finished Jan 25 02:52:30 PM PST 24
Peak memory 208680 kb
Host smart-dd815fb7-7852-4b5b-901d-e29ee366a74b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989769010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.989769010
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.4252339059
Short name T288
Test name
Test status
Simulation time 195401475 ps
CPU time 2.72 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:52:27 PM PST 24
Peak memory 208552 kb
Host smart-1800c81a-cd14-4e43-b31f-a32cf8a8754b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252339059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.4252339059
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3688293725
Short name T864
Test name
Test status
Simulation time 299943174 ps
CPU time 2 seconds
Started Jan 25 02:52:14 PM PST 24
Finished Jan 25 02:52:32 PM PST 24
Peak memory 206688 kb
Host smart-8d4da1ea-2468-47d0-89f6-3eff8a72c4a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688293725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3688293725
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1781184932
Short name T291
Test name
Test status
Simulation time 25751337 ps
CPU time 1.98 seconds
Started Jan 25 02:52:01 PM PST 24
Finished Jan 25 02:52:20 PM PST 24
Peak memory 214344 kb
Host smart-ad4260fa-68d4-48e1-9775-cb6d6e370358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781184932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1781184932
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1517345586
Short name T662
Test name
Test status
Simulation time 233009702 ps
CPU time 5.32 seconds
Started Jan 25 02:52:10 PM PST 24
Finished Jan 25 02:52:31 PM PST 24
Peak memory 207184 kb
Host smart-a2ed0b06-7eff-4165-b800-cfdbdcbd791c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517345586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1517345586
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2719954597
Short name T70
Test name
Test status
Simulation time 3155551843 ps
CPU time 29.29 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:38 PM PST 24
Peak memory 215672 kb
Host smart-cd5221f0-8ccc-4739-8d99-6a120cb879c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719954597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2719954597
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3768287953
Short name T972
Test name
Test status
Simulation time 107542946 ps
CPU time 4.56 seconds
Started Jan 25 03:28:29 PM PST 24
Finished Jan 25 03:29:45 PM PST 24
Peak memory 222512 kb
Host smart-0b9c7f6e-d0a1-4989-9a26-454b6207e5ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768287953 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3768287953
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.203764622
Short name T366
Test name
Test status
Simulation time 1549277920 ps
CPU time 15.22 seconds
Started Jan 25 02:52:08 PM PST 24
Finished Jan 25 02:52:39 PM PST 24
Peak memory 213488 kb
Host smart-f7b491ef-9d55-43f0-a988-155c7c208bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203764622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.203764622
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1592166136
Short name T722
Test name
Test status
Simulation time 568133425 ps
CPU time 4.18 seconds
Started Jan 25 02:51:59 PM PST 24
Finished Jan 25 02:52:20 PM PST 24
Peak memory 210160 kb
Host smart-72917f75-dc4a-4d8f-932d-352ef868cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592166136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1592166136
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3271108680
Short name T770
Test name
Test status
Simulation time 23311683 ps
CPU time 0.71 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:09 PM PST 24
Peak memory 205840 kb
Host smart-da544c59-d6c0-4683-9ef7-07e2476feb22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271108680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3271108680
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3789284906
Short name T806
Test name
Test status
Simulation time 106837675 ps
CPU time 3.1 seconds
Started Jan 25 02:52:49 PM PST 24
Finished Jan 25 02:53:06 PM PST 24
Peak memory 222536 kb
Host smart-2db69bea-1b90-4a68-989e-916bc2377508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3789284906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3789284906
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1584742589
Short name T193
Test name
Test status
Simulation time 1096946407 ps
CPU time 12.38 seconds
Started Jan 25 05:09:51 PM PST 24
Finished Jan 25 05:10:05 PM PST 24
Peak memory 209208 kb
Host smart-ad1ae47c-a84d-40e7-bb80-de06bb70d953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584742589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1584742589
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.290510465
Short name T334
Test name
Test status
Simulation time 163305444 ps
CPU time 2.33 seconds
Started Jan 25 02:52:49 PM PST 24
Finished Jan 25 02:53:05 PM PST 24
Peak memory 208860 kb
Host smart-ede99ce8-a1bc-4a25-b9d8-ef064b901b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290510465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.290510465
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.600494458
Short name T327
Test name
Test status
Simulation time 709439482 ps
CPU time 4.56 seconds
Started Jan 25 02:52:53 PM PST 24
Finished Jan 25 02:53:15 PM PST 24
Peak memory 209504 kb
Host smart-06e71578-1651-4f88-a456-b744c07dddc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600494458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.600494458
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1322316720
Short name T280
Test name
Test status
Simulation time 257754225 ps
CPU time 3.24 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:14 PM PST 24
Peak memory 209532 kb
Host smart-e5f5c72b-6771-4a33-9914-52f00033f9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322316720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1322316720
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3171333101
Short name T306
Test name
Test status
Simulation time 230988559 ps
CPU time 4.17 seconds
Started Jan 25 03:55:25 PM PST 24
Finished Jan 25 03:55:59 PM PST 24
Peak memory 209716 kb
Host smart-a1c18760-ff2e-414b-b8b0-07a8f5174504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171333101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3171333101
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.983884704
Short name T1057
Test name
Test status
Simulation time 1110001638 ps
CPU time 6.98 seconds
Started Jan 25 02:52:57 PM PST 24
Finished Jan 25 02:53:21 PM PST 24
Peak memory 218348 kb
Host smart-389c4383-f64b-4b59-a171-bf5abd539697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983884704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.983884704
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.4153138615
Short name T915
Test name
Test status
Simulation time 236112029 ps
CPU time 2.76 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:12 PM PST 24
Peak memory 207300 kb
Host smart-6300b54f-e1cb-43c1-b7fa-bd12fc6b895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153138615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.4153138615
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2116638086
Short name T898
Test name
Test status
Simulation time 384014294 ps
CPU time 3.92 seconds
Started Jan 25 02:52:43 PM PST 24
Finished Jan 25 02:52:54 PM PST 24
Peak memory 208648 kb
Host smart-073fe98b-753c-4f28-99c3-7b479188bfeb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116638086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2116638086
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.137713
Short name T319
Test name
Test status
Simulation time 23367866 ps
CPU time 1.98 seconds
Started Jan 25 02:52:43 PM PST 24
Finished Jan 25 02:52:53 PM PST 24
Peak memory 206696 kb
Host smart-f4b939dd-9ea4-4c91-9761-c69b47073e27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.137713
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2675265800
Short name T580
Test name
Test status
Simulation time 826865260 ps
CPU time 6.01 seconds
Started Jan 25 02:52:41 PM PST 24
Finished Jan 25 02:52:55 PM PST 24
Peak memory 207904 kb
Host smart-ba38fa92-66d7-45db-8315-f64caa1443ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675265800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2675265800
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.664615544
Short name T717
Test name
Test status
Simulation time 276552617 ps
CPU time 2.52 seconds
Started Jan 25 02:52:43 PM PST 24
Finished Jan 25 02:52:52 PM PST 24
Peak memory 208352 kb
Host smart-3604b290-346b-4002-ba58-7da99770b3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664615544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.664615544
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2765786379
Short name T77
Test name
Test status
Simulation time 254291583 ps
CPU time 3 seconds
Started Jan 25 03:12:15 PM PST 24
Finished Jan 25 03:12:18 PM PST 24
Peak memory 208336 kb
Host smart-e89b4956-473d-415e-8a16-40d03f8109df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765786379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2765786379
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2139420188
Short name T367
Test name
Test status
Simulation time 201746947 ps
CPU time 9.5 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:20 PM PST 24
Peak memory 215476 kb
Host smart-010639f3-fc3c-4cf7-ac5d-80d5d21a83ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139420188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2139420188
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3315011290
Short name T139
Test name
Test status
Simulation time 210716643 ps
CPU time 3.53 seconds
Started Jan 25 02:52:53 PM PST 24
Finished Jan 25 02:53:14 PM PST 24
Peak memory 217720 kb
Host smart-97948c09-31fe-4905-8b7a-e7f4993ee717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315011290 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3315011290
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1468693644
Short name T956
Test name
Test status
Simulation time 829299374 ps
CPU time 8.81 seconds
Started Jan 25 02:52:50 PM PST 24
Finished Jan 25 02:53:13 PM PST 24
Peak memory 209416 kb
Host smart-3ea7f03b-c193-45bb-b03f-54c2245d4eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468693644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1468693644
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3683706763
Short name T56
Test name
Test status
Simulation time 331655798 ps
CPU time 7.45 seconds
Started Jan 25 02:52:57 PM PST 24
Finished Jan 25 02:53:22 PM PST 24
Peak memory 210940 kb
Host smart-935334ed-eb6b-4a49-958d-5bc32648018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683706763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3683706763
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1048998919
Short name T93
Test name
Test status
Simulation time 75169671 ps
CPU time 0.88 seconds
Started Jan 25 02:52:51 PM PST 24
Finished Jan 25 02:53:09 PM PST 24
Peak memory 205900 kb
Host smart-d32990bf-24ef-4478-8749-cf2c91319cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048998919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1048998919
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2375073924
Short name T351
Test name
Test status
Simulation time 82984569 ps
CPU time 4.88 seconds
Started Jan 25 02:52:53 PM PST 24
Finished Jan 25 02:53:16 PM PST 24
Peak memory 215120 kb
Host smart-9b3835de-8974-460c-a3f1-7c7243dde50f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375073924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2375073924
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3915959080
Short name T613
Test name
Test status
Simulation time 35667668 ps
CPU time 2.15 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:13 PM PST 24
Peak memory 209068 kb
Host smart-a56eeddb-058a-4a29-aabf-659b471b042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915959080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3915959080
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3681755145
Short name T825
Test name
Test status
Simulation time 2087233586 ps
CPU time 30.38 seconds
Started Jan 25 04:56:24 PM PST 24
Finished Jan 25 04:57:06 PM PST 24
Peak memory 209504 kb
Host smart-30b1be16-4b9c-4ac9-88d6-24645598079d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681755145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3681755145
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.308936821
Short name T393
Test name
Test status
Simulation time 89425059 ps
CPU time 2.64 seconds
Started Jan 25 02:52:44 PM PST 24
Finished Jan 25 02:52:54 PM PST 24
Peak memory 214288 kb
Host smart-5d4271bc-6fbb-4284-b25a-2c5759b7851c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308936821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.308936821
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3736219622
Short name T774
Test name
Test status
Simulation time 559075154 ps
CPU time 4.73 seconds
Started Jan 25 03:52:50 PM PST 24
Finished Jan 25 03:53:16 PM PST 24
Peak memory 209184 kb
Host smart-42a6c997-e93e-4e45-8797-082018529770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736219622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3736219622
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.846048625
Short name T845
Test name
Test status
Simulation time 58759108 ps
CPU time 3.07 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:14 PM PST 24
Peak memory 207608 kb
Host smart-e3aa6cbf-06f0-4ac8-8f92-c26de14c5e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846048625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.846048625
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4107254973
Short name T973
Test name
Test status
Simulation time 139668626 ps
CPU time 2.76 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:12 PM PST 24
Peak memory 207084 kb
Host smart-cad6f100-9aed-4b6a-bf6a-d780c345b407
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107254973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4107254973
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3830191880
Short name T920
Test name
Test status
Simulation time 138380268 ps
CPU time 1.74 seconds
Started Jan 25 02:52:43 PM PST 24
Finished Jan 25 02:52:52 PM PST 24
Peak memory 206820 kb
Host smart-733978ce-1db2-4658-8000-69fd2196d59b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830191880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3830191880
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1666099499
Short name T807
Test name
Test status
Simulation time 319702593 ps
CPU time 2.99 seconds
Started Jan 25 02:52:41 PM PST 24
Finished Jan 25 02:52:52 PM PST 24
Peak memory 207512 kb
Host smart-9cde4140-5100-4578-aa5e-41cb33514520
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666099499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1666099499
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.376842053
Short name T989
Test name
Test status
Simulation time 3406884368 ps
CPU time 27.17 seconds
Started Jan 25 02:52:43 PM PST 24
Finished Jan 25 02:53:17 PM PST 24
Peak memory 208656 kb
Host smart-04d095ac-cf91-40ec-9ece-f816cdaebc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376842053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.376842053
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3274234741
Short name T648
Test name
Test status
Simulation time 764972340 ps
CPU time 14.97 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:26 PM PST 24
Peak memory 208032 kb
Host smart-0e157a7a-8e7b-4807-b220-3ea7e6b7b572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274234741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3274234741
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1336350725
Short name T1051
Test name
Test status
Simulation time 2643234403 ps
CPU time 20.68 seconds
Started Jan 25 02:52:53 PM PST 24
Finished Jan 25 02:53:31 PM PST 24
Peak memory 222568 kb
Host smart-c1485c3a-4ab2-4b59-83b9-7b3032d512a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336350725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1336350725
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1568119628
Short name T905
Test name
Test status
Simulation time 136730065 ps
CPU time 8.56 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:19 PM PST 24
Peak memory 222848 kb
Host smart-fc5d5c69-7680-4325-9cc8-9ae91b77935f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568119628 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1568119628
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2296299727
Short name T4
Test name
Test status
Simulation time 226508928 ps
CPU time 6.15 seconds
Started Jan 25 02:52:57 PM PST 24
Finished Jan 25 02:53:20 PM PST 24
Peak memory 209244 kb
Host smart-d33ce526-3e83-4085-ae3e-735e6ce89037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296299727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2296299727
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1855537143
Short name T778
Test name
Test status
Simulation time 50621228 ps
CPU time 2.78 seconds
Started Jan 25 03:22:04 PM PST 24
Finished Jan 25 03:23:32 PM PST 24
Peak memory 210220 kb
Host smart-f86e8580-a989-41dd-bfd0-628f0f191307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855537143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1855537143
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.498434366
Short name T892
Test name
Test status
Simulation time 56345557 ps
CPU time 0.82 seconds
Started Jan 25 02:58:58 PM PST 24
Finished Jan 25 02:59:13 PM PST 24
Peak memory 206044 kb
Host smart-9f5210e0-a9cc-4ca9-aaf5-75e671e427af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498434366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.498434366
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.683030464
Short name T398
Test name
Test status
Simulation time 56245461 ps
CPU time 3.85 seconds
Started Jan 25 02:52:49 PM PST 24
Finished Jan 25 02:53:07 PM PST 24
Peak memory 222436 kb
Host smart-3bfad3c1-6cd3-460f-bb62-2d89a38f7826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=683030464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.683030464
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2964760381
Short name T1067
Test name
Test status
Simulation time 426658734 ps
CPU time 8.88 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:20 PM PST 24
Peak memory 210268 kb
Host smart-dfdde195-1558-4b8f-afdb-57047367b425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964760381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2964760381
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1415519637
Short name T649
Test name
Test status
Simulation time 100458225 ps
CPU time 2.99 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:14 PM PST 24
Peak memory 213496 kb
Host smart-442fae04-cce0-4e89-bf59-dd58573f4209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415519637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1415519637
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.939347425
Short name T696
Test name
Test status
Simulation time 272395142 ps
CPU time 8.85 seconds
Started Jan 25 02:52:53 PM PST 24
Finished Jan 25 02:53:20 PM PST 24
Peak memory 209300 kb
Host smart-48a0ab94-3495-4449-96e4-6e650dc27a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939347425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.939347425
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2876824460
Short name T257
Test name
Test status
Simulation time 232163289 ps
CPU time 8.65 seconds
Started Jan 25 02:52:53 PM PST 24
Finished Jan 25 02:53:19 PM PST 24
Peak memory 210000 kb
Host smart-bc842ffa-0bdc-4eb2-af43-9d96be9b049d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876824460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2876824460
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3921592307
Short name T633
Test name
Test status
Simulation time 1154064910 ps
CPU time 4.13 seconds
Started Jan 25 02:52:51 PM PST 24
Finished Jan 25 02:53:11 PM PST 24
Peak memory 209248 kb
Host smart-6989f5af-7bdb-4d9d-afc8-1902e59e3a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921592307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3921592307
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.686292694
Short name T570
Test name
Test status
Simulation time 139623394 ps
CPU time 2.74 seconds
Started Jan 25 04:08:24 PM PST 24
Finished Jan 25 04:08:37 PM PST 24
Peak memory 207492 kb
Host smart-c2f24c31-4730-4664-b4be-0be31851ec25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686292694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.686292694
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1635599392
Short name T664
Test name
Test status
Simulation time 340743948 ps
CPU time 3.74 seconds
Started Jan 25 03:36:03 PM PST 24
Finished Jan 25 03:37:29 PM PST 24
Peak memory 208360 kb
Host smart-9072bb04-051e-4975-a7fc-9a548d76fa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635599392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1635599392
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1620420389
Short name T756
Test name
Test status
Simulation time 302744795 ps
CPU time 5.09 seconds
Started Jan 25 02:52:53 PM PST 24
Finished Jan 25 02:53:16 PM PST 24
Peak memory 207816 kb
Host smart-96aa7ad7-f764-413c-a0fd-ba20cb99b666
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620420389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1620420389
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3971694415
Short name T730
Test name
Test status
Simulation time 270645492 ps
CPU time 3.64 seconds
Started Jan 25 02:52:53 PM PST 24
Finished Jan 25 02:53:14 PM PST 24
Peak memory 207068 kb
Host smart-15c0afd1-0f3f-4ee0-a601-754c3a7df3b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971694415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3971694415
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1802797625
Short name T901
Test name
Test status
Simulation time 657232317 ps
CPU time 5.6 seconds
Started Jan 25 02:52:53 PM PST 24
Finished Jan 25 02:53:16 PM PST 24
Peak memory 208488 kb
Host smart-fd6cae05-8993-486c-b2de-9cf718f15a76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802797625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1802797625
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3108844868
Short name T19
Test name
Test status
Simulation time 121563011 ps
CPU time 3.73 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:14 PM PST 24
Peak memory 214192 kb
Host smart-4754bfcf-3e92-4385-9b84-168642ec5702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108844868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3108844868
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1501535352
Short name T657
Test name
Test status
Simulation time 50579969 ps
CPU time 2.2 seconds
Started Jan 25 05:18:17 PM PST 24
Finished Jan 25 05:18:27 PM PST 24
Peak memory 208716 kb
Host smart-52ff3367-5e7c-4a9f-9c2f-d9846cf4a39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501535352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1501535352
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4262470942
Short name T229
Test name
Test status
Simulation time 2389300069 ps
CPU time 22.45 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:33 PM PST 24
Peak memory 222508 kb
Host smart-6d318fff-dcc4-4dc4-ae6d-ffcd0703472c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262470942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4262470942
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1473987897
Short name T777
Test name
Test status
Simulation time 792155657 ps
CPU time 6.21 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:17 PM PST 24
Peak memory 209872 kb
Host smart-a482c644-8f92-4644-a1c2-c15ecd776e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473987897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1473987897
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1918000887
Short name T100
Test name
Test status
Simulation time 69922163 ps
CPU time 3.15 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:13 PM PST 24
Peak memory 210164 kb
Host smart-7b643b63-194e-4d02-b096-f65015eee4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918000887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1918000887
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3146658075
Short name T555
Test name
Test status
Simulation time 23485759 ps
CPU time 0.8 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:11 PM PST 24
Peak memory 205804 kb
Host smart-9240f23e-aac7-45a6-8521-1c7cab5a651f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146658075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3146658075
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1174932110
Short name T719
Test name
Test status
Simulation time 175773567 ps
CPU time 3.31 seconds
Started Jan 25 03:55:02 PM PST 24
Finished Jan 25 03:55:41 PM PST 24
Peak memory 214292 kb
Host smart-ed23aaa6-c396-40fa-833e-4ddde3e96e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174932110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1174932110
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1022835230
Short name T211
Test name
Test status
Simulation time 236867694 ps
CPU time 3.02 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:14 PM PST 24
Peak memory 209516 kb
Host smart-b84ecc22-e60c-4bfe-869f-a1d591f067a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022835230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1022835230
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.383943456
Short name T324
Test name
Test status
Simulation time 308555869 ps
CPU time 9.69 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:20 PM PST 24
Peak memory 210272 kb
Host smart-fa9067bb-976d-4632-822b-acba28ba6b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383943456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.383943456
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.586686473
Short name T62
Test name
Test status
Simulation time 77380907 ps
CPU time 3.31 seconds
Started Jan 25 03:04:33 PM PST 24
Finished Jan 25 03:04:48 PM PST 24
Peak memory 216372 kb
Host smart-858db265-1e4b-48c9-9d30-9dd8f8b9d06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586686473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.586686473
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2944953128
Short name T1077
Test name
Test status
Simulation time 839579182 ps
CPU time 10.23 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:21 PM PST 24
Peak memory 206904 kb
Host smart-ff29902d-d718-42c6-b065-cab4a979faa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944953128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2944953128
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.4286472034
Short name T575
Test name
Test status
Simulation time 135907525 ps
CPU time 3.01 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:12 PM PST 24
Peak memory 208608 kb
Host smart-4470fe44-fdb3-42d3-8e0c-72ec99dd3460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286472034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.4286472034
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4026839593
Short name T961
Test name
Test status
Simulation time 117001383 ps
CPU time 2.36 seconds
Started Jan 25 02:52:54 PM PST 24
Finished Jan 25 02:53:13 PM PST 24
Peak memory 206736 kb
Host smart-eb93b9c8-5fcc-4216-b290-1953bfe546ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026839593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4026839593
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3492134496
Short name T997
Test name
Test status
Simulation time 1186554660 ps
CPU time 16.34 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:27 PM PST 24
Peak memory 208688 kb
Host smart-3608a809-afef-4524-ba0b-db4ce6c4ea0e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492134496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3492134496
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.744683192
Short name T665
Test name
Test status
Simulation time 36625107 ps
CPU time 2.51 seconds
Started Jan 25 05:05:56 PM PST 24
Finished Jan 25 05:06:00 PM PST 24
Peak memory 206880 kb
Host smart-9f6a5830-cdf9-4414-a554-a849f6e00f4c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744683192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.744683192
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1035283693
Short name T1008
Test name
Test status
Simulation time 522502189 ps
CPU time 4.28 seconds
Started Jan 25 02:52:52 PM PST 24
Finished Jan 25 02:53:15 PM PST 24
Peak memory 208000 kb
Host smart-69d3d372-868e-4026-9cdc-0610d79f03f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035283693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1035283693
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2958643334
Short name T988
Test name
Test status
Simulation time 55014947 ps
CPU time 2.8 seconds
Started Jan 25 03:35:30 PM PST 24
Finished Jan 25 03:36:55 PM PST 24
Peak memory 206800 kb
Host smart-97fd7a9f-bc5c-4ff5-9d05-3e500db1b3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958643334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2958643334
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2376102122
Short name T95
Test name
Test status
Simulation time 1065236564 ps
CPU time 5.73 seconds
Started Jan 25 06:24:59 PM PST 24
Finished Jan 25 06:25:08 PM PST 24
Peak memory 215460 kb
Host smart-948ae774-2b03-4460-aa0e-02d0c68df0d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376102122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2376102122
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3672567694
Short name T94
Test name
Test status
Simulation time 67007468 ps
CPU time 3.11 seconds
Started Jan 25 03:41:57 PM PST 24
Finished Jan 25 03:43:17 PM PST 24
Peak memory 222516 kb
Host smart-857fd621-9ec7-4d64-b610-eda2e0966ff0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672567694 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3672567694
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2157817897
Short name T716
Test name
Test status
Simulation time 100637234 ps
CPU time 5.08 seconds
Started Jan 25 05:06:33 PM PST 24
Finished Jan 25 05:06:42 PM PST 24
Peak memory 214276 kb
Host smart-9a064e06-ecb5-4056-a074-b91b1af3146f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157817897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2157817897
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1107381992
Short name T55
Test name
Test status
Simulation time 546865305 ps
CPU time 2.98 seconds
Started Jan 25 04:31:13 PM PST 24
Finished Jan 25 04:31:24 PM PST 24
Peak memory 209848 kb
Host smart-81e56142-5b9c-4e25-9d98-b5f6a504e4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107381992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1107381992
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1783946368
Short name T890
Test name
Test status
Simulation time 18609753 ps
CPU time 0.84 seconds
Started Jan 25 02:46:10 PM PST 24
Finished Jan 25 02:46:28 PM PST 24
Peak memory 205860 kb
Host smart-2efd0851-ffb5-49b5-a8e6-6aa7ed983f51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783946368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1783946368
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3169576405
Short name T27
Test name
Test status
Simulation time 3436966096 ps
CPU time 13.75 seconds
Started Jan 25 02:46:05 PM PST 24
Finished Jan 25 02:46:39 PM PST 24
Peak memory 222804 kb
Host smart-5d62c0e9-9fa2-4ea2-8e48-44b08a16536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169576405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3169576405
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.275719779
Short name T860
Test name
Test status
Simulation time 71238348 ps
CPU time 2.31 seconds
Started Jan 25 02:45:49 PM PST 24
Finished Jan 25 02:46:15 PM PST 24
Peak memory 209272 kb
Host smart-0eeeefbe-4639-459d-b493-180e95e5089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275719779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.275719779
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.379613234
Short name T25
Test name
Test status
Simulation time 88620454 ps
CPU time 2.86 seconds
Started Jan 25 02:45:43 PM PST 24
Finished Jan 25 02:46:11 PM PST 24
Peak memory 218116 kb
Host smart-b2648b60-9572-42c0-9772-535adb7c817a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379613234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.379613234
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2586446218
Short name T239
Test name
Test status
Simulation time 65617135 ps
CPU time 4.12 seconds
Started Jan 25 02:46:10 PM PST 24
Finished Jan 25 02:46:31 PM PST 24
Peak memory 211256 kb
Host smart-8d9777cf-6996-4b8c-bec0-e7b33c2abe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586446218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2586446218
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3060732859
Short name T718
Test name
Test status
Simulation time 225347328 ps
CPU time 5.88 seconds
Started Jan 25 02:45:51 PM PST 24
Finished Jan 25 02:46:20 PM PST 24
Peak memory 209804 kb
Host smart-0cc484d6-79a8-4648-a281-c2085f6a2568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060732859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3060732859
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3579006127
Short name T595
Test name
Test status
Simulation time 286369257 ps
CPU time 9.26 seconds
Started Jan 25 02:45:40 PM PST 24
Finished Jan 25 02:46:15 PM PST 24
Peak memory 209076 kb
Host smart-3216987f-de53-4761-b547-5c64eb95268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579006127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3579006127
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3133709574
Short name T957
Test name
Test status
Simulation time 444415043 ps
CPU time 6.95 seconds
Started Jan 25 02:45:42 PM PST 24
Finished Jan 25 02:46:14 PM PST 24
Peak memory 206748 kb
Host smart-1ca003e5-8411-490d-8e6a-9e477ec81509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133709574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3133709574
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2593411898
Short name T101
Test name
Test status
Simulation time 532277902 ps
CPU time 2.43 seconds
Started Jan 25 02:45:48 PM PST 24
Finished Jan 25 02:46:14 PM PST 24
Peak memory 206800 kb
Host smart-5f1b8bdb-0d4f-4c5f-983a-0138914d5691
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593411898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2593411898
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2101785764
Short name T559
Test name
Test status
Simulation time 536603754 ps
CPU time 7.05 seconds
Started Jan 25 02:45:49 PM PST 24
Finished Jan 25 02:46:20 PM PST 24
Peak memory 208532 kb
Host smart-633a46be-86f3-4257-be34-8780087f9e0c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101785764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2101785764
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.148636383
Short name T917
Test name
Test status
Simulation time 211709287 ps
CPU time 2.98 seconds
Started Jan 25 02:45:49 PM PST 24
Finished Jan 25 02:46:15 PM PST 24
Peak memory 206736 kb
Host smart-cfae4bda-4c7a-4c3f-8b38-c3c13c24ee66
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148636383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.148636383
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.333317173
Short name T885
Test name
Test status
Simulation time 150169300 ps
CPU time 2.7 seconds
Started Jan 25 02:46:10 PM PST 24
Finished Jan 25 02:46:30 PM PST 24
Peak memory 217904 kb
Host smart-480b62e4-2f44-4da5-bc08-7f2ce947bd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333317173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.333317173
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2695079104
Short name T918
Test name
Test status
Simulation time 82719790 ps
CPU time 3.33 seconds
Started Jan 25 02:45:42 PM PST 24
Finished Jan 25 02:46:10 PM PST 24
Peak memory 208400 kb
Host smart-818f167a-5c41-49d3-a267-cad8cbf6e9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695079104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2695079104
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3939248962
Short name T741
Test name
Test status
Simulation time 224349325 ps
CPU time 4.66 seconds
Started Jan 25 02:45:36 PM PST 24
Finished Jan 25 02:46:07 PM PST 24
Peak memory 207480 kb
Host smart-f8d13686-d685-49f8-9823-47b1243f9de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939248962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3939248962
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.847293666
Short name T158
Test name
Test status
Simulation time 128099017 ps
CPU time 2.28 seconds
Started Jan 25 02:46:17 PM PST 24
Finished Jan 25 02:46:34 PM PST 24
Peak memory 209952 kb
Host smart-efef6236-a6f3-4eae-8198-d85741a5296d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847293666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.847293666
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2424881351
Short name T910
Test name
Test status
Simulation time 12160806 ps
CPU time 0.88 seconds
Started Jan 25 02:46:17 PM PST 24
Finished Jan 25 02:46:32 PM PST 24
Peak memory 205840 kb
Host smart-ac4c4d8f-e3a8-4088-a198-ab4bf30711ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424881351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2424881351
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.398578677
Short name T382
Test name
Test status
Simulation time 81166925 ps
CPU time 4.58 seconds
Started Jan 25 02:46:10 PM PST 24
Finished Jan 25 02:46:31 PM PST 24
Peak memory 214236 kb
Host smart-0ab4cf0a-4e6c-4ed3-8edb-c4a84a3a8fa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=398578677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.398578677
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3338556370
Short name T30
Test name
Test status
Simulation time 78753213 ps
CPU time 3.03 seconds
Started Jan 25 02:46:29 PM PST 24
Finished Jan 25 02:47:01 PM PST 24
Peak memory 209140 kb
Host smart-5b91447a-d673-41d4-8969-47db5c784008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338556370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3338556370
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1536983196
Short name T850
Test name
Test status
Simulation time 216773949 ps
CPU time 2.11 seconds
Started Jan 25 02:46:12 PM PST 24
Finished Jan 25 02:46:30 PM PST 24
Peak memory 218092 kb
Host smart-3388adfd-ad80-463d-af1d-07b330469a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536983196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1536983196
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3190597196
Short name T81
Test name
Test status
Simulation time 354533795 ps
CPU time 11.95 seconds
Started Jan 25 02:46:10 PM PST 24
Finished Jan 25 02:46:39 PM PST 24
Peak memory 208996 kb
Host smart-7b30d944-18c6-4bff-b3d8-ca128f7e0d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190597196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3190597196
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3813026384
Short name T261
Test name
Test status
Simulation time 207713847 ps
CPU time 6.08 seconds
Started Jan 25 02:46:08 PM PST 24
Finished Jan 25 02:46:32 PM PST 24
Peak memory 210972 kb
Host smart-7b5f2ee5-dee3-4104-9f40-92076330bc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813026384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3813026384
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.106284201
Short name T881
Test name
Test status
Simulation time 147117589 ps
CPU time 2.15 seconds
Started Jan 25 02:46:20 PM PST 24
Finished Jan 25 02:46:35 PM PST 24
Peak memory 209768 kb
Host smart-b2bd7f64-0dc1-40de-8f46-0ac9301eccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106284201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.106284201
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1151358907
Short name T978
Test name
Test status
Simulation time 115206239 ps
CPU time 3.43 seconds
Started Jan 25 02:46:16 PM PST 24
Finished Jan 25 02:46:33 PM PST 24
Peak memory 217816 kb
Host smart-305401b7-b871-450d-8322-308874372468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151358907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1151358907
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.783067936
Short name T311
Test name
Test status
Simulation time 48521061 ps
CPU time 2.25 seconds
Started Jan 25 02:46:11 PM PST 24
Finished Jan 25 02:46:29 PM PST 24
Peak memory 206644 kb
Host smart-301b869a-bde6-45d4-a333-6de66ec98b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783067936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.783067936
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3630413782
Short name T724
Test name
Test status
Simulation time 691189425 ps
CPU time 5.34 seconds
Started Jan 25 02:46:16 PM PST 24
Finished Jan 25 02:46:35 PM PST 24
Peak memory 208344 kb
Host smart-2ec61043-6ee3-419d-8cd3-15c9be704e83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630413782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3630413782
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.4136518982
Short name T1041
Test name
Test status
Simulation time 530111067 ps
CPU time 6.31 seconds
Started Jan 25 02:46:15 PM PST 24
Finished Jan 25 02:46:36 PM PST 24
Peak memory 208600 kb
Host smart-4fb25e61-9c57-4a24-846d-711a135415d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136518982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.4136518982
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2403354794
Short name T563
Test name
Test status
Simulation time 197318137 ps
CPU time 4.95 seconds
Started Jan 25 02:46:19 PM PST 24
Finished Jan 25 02:46:38 PM PST 24
Peak memory 208492 kb
Host smart-de2977fe-2243-4b90-a378-c6600e8b39cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403354794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2403354794
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.975602330
Short name T312
Test name
Test status
Simulation time 551827699 ps
CPU time 10.72 seconds
Started Jan 25 02:46:17 PM PST 24
Finished Jan 25 02:46:42 PM PST 24
Peak memory 208968 kb
Host smart-b16916cf-29e3-4b4f-83c2-bd56397728c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975602330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.975602330
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3404643464
Short name T15
Test name
Test status
Simulation time 14894447192 ps
CPU time 76.59 seconds
Started Jan 25 02:46:08 PM PST 24
Finished Jan 25 02:47:43 PM PST 24
Peak memory 208160 kb
Host smart-191a08a9-9777-4610-b086-2cd728505113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404643464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3404643464
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2724823439
Short name T230
Test name
Test status
Simulation time 4150443285 ps
CPU time 33.23 seconds
Started Jan 25 02:46:17 PM PST 24
Finished Jan 25 02:47:05 PM PST 24
Peak memory 222492 kb
Host smart-9e71e71c-236f-492b-9c0f-ad0b24511f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724823439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2724823439
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1132214639
Short name T899
Test name
Test status
Simulation time 76105945 ps
CPU time 2.92 seconds
Started Jan 25 02:46:09 PM PST 24
Finished Jan 25 02:46:29 PM PST 24
Peak memory 217984 kb
Host smart-2cdd7d1c-7551-4b10-add9-461b14e6f718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132214639 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1132214639
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3878857713
Short name T764
Test name
Test status
Simulation time 7733111970 ps
CPU time 81.14 seconds
Started Jan 25 02:46:05 PM PST 24
Finished Jan 25 02:47:46 PM PST 24
Peak memory 222440 kb
Host smart-39b4670e-006a-49f4-bd52-0447d3c6e900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878857713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3878857713
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3040600279
Short name T833
Test name
Test status
Simulation time 533246819 ps
CPU time 2.06 seconds
Started Jan 25 02:46:13 PM PST 24
Finished Jan 25 02:46:30 PM PST 24
Peak memory 210460 kb
Host smart-5da6ee30-ef31-487e-a309-9a8657cfd48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040600279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3040600279
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.4194973267
Short name T802
Test name
Test status
Simulation time 67237813 ps
CPU time 0.98 seconds
Started Jan 25 02:46:09 PM PST 24
Finished Jan 25 02:46:28 PM PST 24
Peak memory 205824 kb
Host smart-bf69a836-3133-416a-85e1-2208f7b21613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194973267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4194973267
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1954364079
Short name T397
Test name
Test status
Simulation time 578361975 ps
CPU time 16.2 seconds
Started Jan 25 02:46:13 PM PST 24
Finished Jan 25 02:46:44 PM PST 24
Peak memory 214292 kb
Host smart-8e4265a0-1ce2-463a-878b-0cad7d68a072
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954364079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1954364079
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2104487168
Short name T190
Test name
Test status
Simulation time 56018889 ps
CPU time 3.54 seconds
Started Jan 25 02:46:17 PM PST 24
Finished Jan 25 02:46:35 PM PST 24
Peak memory 209728 kb
Host smart-87ef40b2-ee67-41e1-8725-dc166e06bdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104487168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2104487168
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2273645587
Short name T1026
Test name
Test status
Simulation time 59123694 ps
CPU time 2.78 seconds
Started Jan 25 02:46:17 PM PST 24
Finished Jan 25 02:46:34 PM PST 24
Peak memory 218264 kb
Host smart-a4791d2b-0a78-455e-ae4c-928c7090969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273645587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2273645587
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1798860778
Short name T1005
Test name
Test status
Simulation time 1393703891 ps
CPU time 10.47 seconds
Started Jan 25 02:46:15 PM PST 24
Finished Jan 25 02:46:40 PM PST 24
Peak memory 209620 kb
Host smart-0ff8ab13-71b9-4b4a-9321-c193d6b3b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798860778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1798860778
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.506691626
Short name T1014
Test name
Test status
Simulation time 164758029 ps
CPU time 6.6 seconds
Started Jan 25 02:46:18 PM PST 24
Finished Jan 25 02:46:39 PM PST 24
Peak memory 214124 kb
Host smart-464cf8b7-91a6-4092-b8d0-05028f6eaae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506691626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.506691626
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3570503992
Short name T780
Test name
Test status
Simulation time 144397176 ps
CPU time 5.44 seconds
Started Jan 25 02:46:19 PM PST 24
Finished Jan 25 02:46:38 PM PST 24
Peak memory 219900 kb
Host smart-0e038145-d221-44f1-a269-b653f1ab514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570503992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3570503992
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1757583726
Short name T206
Test name
Test status
Simulation time 964927915 ps
CPU time 24.78 seconds
Started Jan 25 02:46:18 PM PST 24
Finished Jan 25 02:46:57 PM PST 24
Peak memory 208940 kb
Host smart-b7cc544e-9cee-4c67-b402-a06ca1d823d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757583726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1757583726
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2144022859
Short name T1022
Test name
Test status
Simulation time 149103614 ps
CPU time 2.88 seconds
Started Jan 25 02:46:19 PM PST 24
Finished Jan 25 02:46:36 PM PST 24
Peak memory 206780 kb
Host smart-41a25488-3b1d-4352-b4dd-d3dbb8a4fda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144022859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2144022859
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2105273001
Short name T546
Test name
Test status
Simulation time 725897128 ps
CPU time 5.54 seconds
Started Jan 25 02:46:15 PM PST 24
Finished Jan 25 02:46:35 PM PST 24
Peak memory 208560 kb
Host smart-e1e43ef1-9678-40c3-8f48-62ca8325ce94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105273001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2105273001
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2614678552
Short name T1036
Test name
Test status
Simulation time 487543203 ps
CPU time 5.78 seconds
Started Jan 25 02:46:13 PM PST 24
Finished Jan 25 02:46:34 PM PST 24
Peak memory 206952 kb
Host smart-8b8e70a0-6c6d-4501-8033-ff9670be972a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614678552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2614678552
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.662858286
Short name T617
Test name
Test status
Simulation time 62818251 ps
CPU time 3.24 seconds
Started Jan 25 02:46:08 PM PST 24
Finished Jan 25 02:46:30 PM PST 24
Peak memory 206748 kb
Host smart-f58421e9-370a-450e-a5ae-73238d6803f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662858286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.662858286
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3265383870
Short name T267
Test name
Test status
Simulation time 67670474 ps
CPU time 3.06 seconds
Started Jan 25 02:46:16 PM PST 24
Finished Jan 25 02:46:33 PM PST 24
Peak memory 209156 kb
Host smart-1b91674b-0451-4a61-9865-be17a7cb85a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265383870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3265383870
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2905239879
Short name T897
Test name
Test status
Simulation time 559512595 ps
CPU time 15.7 seconds
Started Jan 25 02:46:10 PM PST 24
Finished Jan 25 02:46:42 PM PST 24
Peak memory 207752 kb
Host smart-6b0647c0-d578-4530-b220-fd3d2a9e1102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905239879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2905239879
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3025043076
Short name T50
Test name
Test status
Simulation time 834630471 ps
CPU time 24.08 seconds
Started Jan 25 02:46:13 PM PST 24
Finished Jan 25 02:46:52 PM PST 24
Peak memory 214244 kb
Host smart-75ae1e71-218a-4f47-b3fd-35e2bb82fc55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025043076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3025043076
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1009608040
Short name T600
Test name
Test status
Simulation time 385455455 ps
CPU time 2.65 seconds
Started Jan 25 02:46:10 PM PST 24
Finished Jan 25 02:46:29 PM PST 24
Peak memory 214332 kb
Host smart-f6a60009-d888-41e3-b5a5-369413cb0976
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009608040 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1009608040
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1988836768
Short name T275
Test name
Test status
Simulation time 242707402 ps
CPU time 4.34 seconds
Started Jan 25 02:46:17 PM PST 24
Finished Jan 25 02:46:36 PM PST 24
Peak memory 210400 kb
Host smart-ade889ee-cd30-4a05-9249-28a3b36a578f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988836768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1988836768
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1944545
Short name T670
Test name
Test status
Simulation time 19801664 ps
CPU time 0.72 seconds
Started Jan 25 02:46:39 PM PST 24
Finished Jan 25 02:47:23 PM PST 24
Peak memory 205856 kb
Host smart-f53a5ed2-6168-4aff-aff5-b54bb41dd372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1944545
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2739972774
Short name T383
Test name
Test status
Simulation time 274755800 ps
CPU time 14.03 seconds
Started Jan 25 02:47:02 PM PST 24
Finished Jan 25 02:48:07 PM PST 24
Peak memory 214228 kb
Host smart-bdc59dcc-5696-4a88-9c57-bb80c0b0a601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2739972774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2739972774
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.758806891
Short name T645
Test name
Test status
Simulation time 186027911 ps
CPU time 6.49 seconds
Started Jan 25 02:46:37 PM PST 24
Finished Jan 25 02:47:24 PM PST 24
Peak memory 210100 kb
Host smart-8943ee9a-a363-4852-85c1-c925c58f208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758806891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.758806891
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3260539656
Short name T1050
Test name
Test status
Simulation time 80526527 ps
CPU time 3.78 seconds
Started Jan 25 02:46:36 PM PST 24
Finished Jan 25 02:47:18 PM PST 24
Peak memory 209708 kb
Host smart-a785014e-649f-43ba-97fe-78508704ab1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260539656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3260539656
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.478286254
Short name T86
Test name
Test status
Simulation time 64936871 ps
CPU time 3.81 seconds
Started Jan 25 02:46:34 PM PST 24
Finished Jan 25 02:47:11 PM PST 24
Peak memory 214368 kb
Host smart-b1176605-d2e8-4ded-b932-975c002dabea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478286254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.478286254
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_random.2060566121
Short name T715
Test name
Test status
Simulation time 46000624058 ps
CPU time 98.32 seconds
Started Jan 25 02:46:34 PM PST 24
Finished Jan 25 02:48:48 PM PST 24
Peak memory 210408 kb
Host smart-31c7f82e-59dd-4c84-9ee8-f7440cd24409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060566121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2060566121
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.23652040
Short name T977
Test name
Test status
Simulation time 153402105 ps
CPU time 2.58 seconds
Started Jan 25 02:46:42 PM PST 24
Finished Jan 25 02:47:29 PM PST 24
Peak memory 208600 kb
Host smart-3ce48695-90c2-49ee-9e40-34e634d19325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23652040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.23652040
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2739376199
Short name T320
Test name
Test status
Simulation time 552401932 ps
CPU time 4.03 seconds
Started Jan 25 02:46:39 PM PST 24
Finished Jan 25 02:47:26 PM PST 24
Peak memory 206832 kb
Host smart-28c30c79-42b8-4929-ad56-846b5bb39129
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739376199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2739376199
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1447988177
Short name T828
Test name
Test status
Simulation time 601673972 ps
CPU time 20.1 seconds
Started Jan 25 02:46:38 PM PST 24
Finished Jan 25 02:47:39 PM PST 24
Peak memory 207804 kb
Host smart-bb76090a-522e-40ab-a5e4-8a614f7c6be0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447988177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1447988177
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.376205899
Short name T907
Test name
Test status
Simulation time 393012928 ps
CPU time 3.12 seconds
Started Jan 25 02:46:42 PM PST 24
Finished Jan 25 02:47:30 PM PST 24
Peak memory 206820 kb
Host smart-06a7b77e-aa97-4421-a28d-4ceb852baacb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376205899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.376205899
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.713690748
Short name T817
Test name
Test status
Simulation time 33804575 ps
CPU time 2.05 seconds
Started Jan 25 02:46:34 PM PST 24
Finished Jan 25 02:47:11 PM PST 24
Peak memory 208864 kb
Host smart-f6e17ebc-9da3-4799-8e1e-9b44412878d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713690748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.713690748
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1578102171
Short name T1004
Test name
Test status
Simulation time 42640596 ps
CPU time 2.22 seconds
Started Jan 25 02:46:16 PM PST 24
Finished Jan 25 02:46:33 PM PST 24
Peak memory 206800 kb
Host smart-87e8e7cc-6570-4b34-b8af-2921b1efe5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578102171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1578102171
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.691320451
Short name T797
Test name
Test status
Simulation time 82160509 ps
CPU time 3.63 seconds
Started Jan 25 02:46:37 PM PST 24
Finished Jan 25 02:47:20 PM PST 24
Peak memory 218856 kb
Host smart-d35b2de2-6070-4deb-ba3c-fc95fa3aafd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691320451 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.691320451
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.293065464
Short name T339
Test name
Test status
Simulation time 388734070 ps
CPU time 3.43 seconds
Started Jan 25 02:46:36 PM PST 24
Finished Jan 25 02:47:16 PM PST 24
Peak memory 209092 kb
Host smart-58a61181-e021-40e4-8d13-6b0daf2df4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293065464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.293065464
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1181233815
Short name T831
Test name
Test status
Simulation time 98472343 ps
CPU time 2.92 seconds
Started Jan 25 02:46:42 PM PST 24
Finished Jan 25 02:47:30 PM PST 24
Peak memory 210476 kb
Host smart-5749dd73-d3a5-4e34-ba0c-e28a44213d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181233815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1181233815
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.976059950
Short name T710
Test name
Test status
Simulation time 16939352 ps
CPU time 0.72 seconds
Started Jan 25 02:46:40 PM PST 24
Finished Jan 25 02:47:25 PM PST 24
Peak memory 205808 kb
Host smart-f8fa8625-abad-4bdf-8220-3dbdf7beca2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976059950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.976059950
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2023158691
Short name T289
Test name
Test status
Simulation time 50288725 ps
CPU time 3.53 seconds
Started Jan 25 02:46:40 PM PST 24
Finished Jan 25 02:47:28 PM PST 24
Peak memory 215284 kb
Host smart-2620fd07-1a15-403d-9c10-a1fd52da60a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023158691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2023158691
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3431244971
Short name T984
Test name
Test status
Simulation time 1621152385 ps
CPU time 6.88 seconds
Started Jan 25 02:46:41 PM PST 24
Finished Jan 25 02:47:31 PM PST 24
Peak memory 209792 kb
Host smart-e31e9408-2518-4d1e-812f-8cc18ce72e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431244971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3431244971
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3919956115
Short name T914
Test name
Test status
Simulation time 32425669 ps
CPU time 2.13 seconds
Started Jan 25 02:46:52 PM PST 24
Finished Jan 25 02:47:42 PM PST 24
Peak memory 209420 kb
Host smart-aa5ccfe3-59cc-40d2-9558-2d55dcc5e678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919956115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3919956115
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2394891121
Short name T810
Test name
Test status
Simulation time 58822784 ps
CPU time 3.44 seconds
Started Jan 25 02:46:40 PM PST 24
Finished Jan 25 02:47:28 PM PST 24
Peak memory 208916 kb
Host smart-28b0f017-8a4d-4b6b-ab76-a665ae830ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394891121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2394891121
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.590684033
Short name T303
Test name
Test status
Simulation time 605760365 ps
CPU time 4.26 seconds
Started Jan 25 02:46:36 PM PST 24
Finished Jan 25 02:47:19 PM PST 24
Peak memory 222408 kb
Host smart-e4d56f25-d67f-49e1-9d5d-1a9453f8c2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590684033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.590684033
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2331255016
Short name T805
Test name
Test status
Simulation time 375816583 ps
CPU time 4.79 seconds
Started Jan 25 02:46:38 PM PST 24
Finished Jan 25 02:47:24 PM PST 24
Peak memory 210064 kb
Host smart-215f608b-10e2-4897-bdde-fb3e7f5479f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331255016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2331255016
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1590102541
Short name T1073
Test name
Test status
Simulation time 456949991 ps
CPU time 10.92 seconds
Started Jan 25 02:46:39 PM PST 24
Finished Jan 25 02:47:33 PM PST 24
Peak memory 206792 kb
Host smart-7c3cb5ae-180c-48db-90bd-cbfd9fd4447f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590102541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1590102541
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.428409141
Short name T979
Test name
Test status
Simulation time 118422432 ps
CPU time 3.06 seconds
Started Jan 25 02:46:41 PM PST 24
Finished Jan 25 02:47:29 PM PST 24
Peak memory 208436 kb
Host smart-bef7d743-968a-4f15-af1b-dc1c2e343b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428409141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.428409141
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.4176994303
Short name T709
Test name
Test status
Simulation time 162052238 ps
CPU time 4.98 seconds
Started Jan 25 02:46:41 PM PST 24
Finished Jan 25 02:47:31 PM PST 24
Peak memory 208796 kb
Host smart-12e39683-b1b6-406b-b1ee-4134da71c46b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176994303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.4176994303
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1495429140
Short name T590
Test name
Test status
Simulation time 1982171595 ps
CPU time 61.35 seconds
Started Jan 25 02:46:36 PM PST 24
Finished Jan 25 02:48:16 PM PST 24
Peak memory 209080 kb
Host smart-02928735-601f-49e2-89af-5942bc90965b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495429140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1495429140
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.772999359
Short name T759
Test name
Test status
Simulation time 147484714 ps
CPU time 2.69 seconds
Started Jan 25 02:46:39 PM PST 24
Finished Jan 25 02:47:24 PM PST 24
Peak memory 208676 kb
Host smart-3b52afd3-8494-4b39-9b6d-8ef0d66ea356
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772999359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.772999359
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1783873471
Short name T762
Test name
Test status
Simulation time 2822353112 ps
CPU time 8.1 seconds
Started Jan 25 02:46:37 PM PST 24
Finished Jan 25 02:47:25 PM PST 24
Peak memory 208108 kb
Host smart-199c5195-a688-44ee-8b6c-a735ba3d044b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783873471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1783873471
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1977543170
Short name T646
Test name
Test status
Simulation time 36305302 ps
CPU time 2.33 seconds
Started Jan 25 02:46:42 PM PST 24
Finished Jan 25 02:47:29 PM PST 24
Peak memory 206612 kb
Host smart-74795a30-ad0c-401e-ba86-3349c7055dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977543170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1977543170
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3473076166
Short name T368
Test name
Test status
Simulation time 275319375 ps
CPU time 7.46 seconds
Started Jan 25 02:46:41 PM PST 24
Finished Jan 25 02:47:33 PM PST 24
Peak memory 220100 kb
Host smart-3f6db6b1-f460-4a69-8c48-79ee8d71ea26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473076166 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3473076166
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3161277458
Short name T1046
Test name
Test status
Simulation time 213442771 ps
CPU time 4.07 seconds
Started Jan 25 02:46:43 PM PST 24
Finished Jan 25 02:47:31 PM PST 24
Peak memory 208092 kb
Host smart-af4dc1dd-5165-4f78-bc49-445f440c4b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161277458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3161277458
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3560341460
Short name T983
Test name
Test status
Simulation time 48150974 ps
CPU time 2.19 seconds
Started Jan 25 02:46:38 PM PST 24
Finished Jan 25 02:47:24 PM PST 24
Peak memory 210868 kb
Host smart-38bd89f1-5c3f-4f7e-962d-72a7054d902c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560341460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3560341460
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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