Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	81	1			T1	1		T4	1		T25	1
auto[OpGenId]	16	1			T8	1		T199	1		T200	1
auto[OpGenSwOut]	29	1			T14	1		T201	1		T202	1
auto[OpGenHwOut]	27	1			T5	1		T199	1		T202	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1903	1			T1	5		T4	2		T14	2
auto[StInit]	153	1			T14	2		T25	1		T92	1
auto[StCreatorRootKey]	56	1			T4	1		T41	1		T39	1
auto[StOwnerIntKey]	35	1			T13	1		T14	1		T53	1
auto[StOwnerKey]	26	1			T35	1		T29	1		T36	1
auto[StDisabled]	395	1			T1	10		T4	5		T41	14
auto[StInvalid]	45	1			T22	1		T34	1		T24	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3536

1

T1

15

T2

1

T3

1

auto[1]

153

1

T1

1

T4

1

T14

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1882	1			T1	5		T4	2		T14	2
auto[StReset]	auto[1]	21	1			T27	1		T140	1		T203	1
auto[StInit]	auto[0]	72	1			T14	2		T92	1		T42	1
auto[StInit]	auto[1]	81	1			T25	1		T5	1		T50	1
auto[StCreatorRootKey]	auto[0]	33	1			T39	1		T105	1		T51	1
auto[StCreatorRootKey]	auto[1]	23	1			T4	1		T41	1		T42	1
auto[StOwnerIntKey]	auto[0]	23	1			T13	1		T53	1		T54	1
auto[StOwnerIntKey]	auto[1]	12	1			T14	1		T204	1		T65	1
auto[StOwnerKey]	auto[0]	17	1			T35	1		T29	1		T36	1
auto[StOwnerKey]	auto[1]	9	1			T60	1		T62	2		T205	1
auto[StDisabled]	auto[0]	388	1			T1	9		T4	5		T41	14
auto[StDisabled]	auto[1]	7	1			T1	1		T199	1		T206	1
auto[StInvalid]	auto[0]	45	1			T22	1		T34	1		T24	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut]]	--	--	2
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	20	1			T27	1		T203	1		T137	1
auto[StReset]	auto[OpGenHwOut]	1	1			T140	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	34	1			T25	1		T50	1		T207	1
auto[StInit]	auto[OpGenId]	12	1			T8	1		T200	1		T208	1
auto[StInit]	auto[OpGenSwOut]	16	1			T201	1		T37	1		T209	2
auto[StInit]	auto[OpGenHwOut]	19	1			T5	1		T202	1		T43	1
auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T4	1		T41	1		T42	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T210	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T202	1		T211	1		T138	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T199	1		T212	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T213	1		T214	1		T215	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T204	1		T216	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T14	1		T65	1		T217	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T218	1		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	5	1			T60	1		T205	1		T216	2
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T62	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	3	1			T62	1		T219	1		T220	1
auto[StDisabled]	auto[OpAdvance]	4	1			T1	1		T72	1		T221	1
auto[StDisabled]	auto[OpGenId]	1	1			T199	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	1	1			T215	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	1	1			T206	1		-	-		-	-