Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11336

1

T1

72

T2

8

T3

18

auto[Attestation]

7775

1

T1

50

T2

17

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2813	1			T1	15		T2	4		T4	22
auto[Aes]	3312	1			T1	23		T2	4		T3	23
auto[Kmac]	3456	1			T1	22		T2	4		T4	23
auto[Otbn]	3529	1			T1	18		T2	7		T4	18

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7681	1			T1	65		T2	8		T3	8
auto[OpGenId]	6001	1			T1	44		T2	6		T4	39
auto[OpGenSwOut]	6020	1			T1	49		T2	9		T4	41
auto[OpGenHwOut]	7090	1			T1	29		T2	10		T3	23
auto[OpDisable]	134	1			T1	2		T45	1		T46	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10027

1

T1

74

T2

16

T3

8

auto[OpDoneFail]

16899

1

T1

115

T2

17

T3

23

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6343	1			T1	47		T2	1		T3	16
auto[StInit]	4139	1			T1	21		T2	2		T3	2
auto[StCreatorRootKey]	2989	1			T1	21		T2	5		T3	2
auto[StOwnerIntKey]	2575	1			T1	17		T2	4		T3	2
auto[StOwnerKey]	2331	1			T1	16		T2	5		T3	2
auto[StDisabled]	7526	1			T1	67		T2	16		T3	7
auto[StInvalid]	1023	1			T22	20		T34	27		T24	11

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	332	1			T1	2		T4	4		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	117	1			T1	1		T4	3		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	97	1			T13	2		T15	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	77	1			T12	1		T183	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T4	1		T17	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	205	1			T1	1		T4	3		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	27	1			T34	2		T24	1		T90	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	280	1			T1	6		T4	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	101	1			T23	1		T115	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	75	1			T4	1		T15	1		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	68	1			T184	1		T183	1		T185	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	62	1			T1	1		T186	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	214	1			T1	4		T4	3		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	34	1			T22	2		T34	2		T81	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	311	1			T1	2		T4	3		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	128	1			T1	1		T79	1		T186	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T1	1		T4	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	64	1			T1	1		T4	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T1	1		T4	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	207	1			T1	2		T2	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	45	1			T22	1		T83	1		T90	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	373	1			T1	2		T4	2		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	109	1			T46	1		T41	2		T42	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	78	1			T1	2		T184	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	54	1			T40	1		T41	3		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	57	1			T1	1		T2	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	180	1			T1	1		T2	2		T4	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	37	1			T34	1		T83	2		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	73	1			T1	1		T4	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	122	1			T1	1		T12	2		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	87	1			T40	1		T184	1		T187	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	52	1			T17	1		T188	1		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T4	1		T41	2		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	183	1			T1	3		T2	2		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	35	1			T22	1		T34	1		T83	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	78	1			T1	3		T41	2		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	106	1			T4	1		T15	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	86	1			T1	1		T4	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	69	1			T2	1		T41	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	52	1			T184	1		T115	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	203	1			T1	1		T4	1		T41	7
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	39	1			T24	1		T91	1		T190	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	77	1			T1	2		T41	5		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	103	1			T1	1		T17	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T1	2		T183	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	77	1			T4	1		T13	1		T186	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	63	1			T1	1		T2	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	219	1			T1	2		T4	3		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	28	1			T22	1		T34	3		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	60	1			T1	1		T41	4		T59	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	126	1			T15	1		T23	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T15	1		T184	1		T41	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T1	1		T4	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	57	1			T41	1		T42	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	188	1			T2	1		T4	2		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	33	1			T22	1		T34	2		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	292	1			T1	2		T4	1		T191	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	108	1			T4	1		T23	1		T183	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	68	1			T15	1		T45	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T4	1		T78	1		T127	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	162	1			T1	1		T4	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	33	1			T22	2		T34	1		T83	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	430	1			T3	15		T12	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	131	1			T4	2		T15	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	86	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	94	1			T1	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	96	1			T12	1		T40	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	262	1			T1	1		T2	1		T3	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	22	1			T22	1		T34	1		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	427	1			T4	1		T12	3		T13	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	145	1			T1	1		T4	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T4	1		T193	1		T194	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	81	1			T4	1		T194	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	81	1			T1	1		T4	1		T193	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	263	1			T4	2		T40	1		T193	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	34	1			T34	1		T190	2		T195	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	525	1			T1	2		T4	2		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	124	1			T16	1		T17	1		T123	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	109	1			T1	1		T4	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T1	2		T4	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	80	1			T4	1		T184	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	285	1			T1	2		T4	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	37	1			T34	1		T24	1		T83	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	38	1			T4	1		T41	3		T59	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	120	1			T127	1		T196	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	67	1			T13	1		T14	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	58	1			T4	1		T15	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	40	1			T4	1		T99	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	160	1			T1	2		T2	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	35	1			T34	1		T83	1		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	46	1			T14	1		T59	1		T83	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	124	1			T1	1		T3	1		T23	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	100	1			T3	1		T4	2		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	75	1			T1	1		T4	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	82	1			T3	1		T12	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	274	1			T1	2		T2	1		T3	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	23	1			T83	1		T91	1		T190	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	44	1			T1	2		T22	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	133	1			T1	1		T4	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T4	1		T191	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T2	1		T17	1		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	83	1			T2	1		T41	1		T185	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	292	1			T1	1		T4	3		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	34	1			T22	2		T91	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	38	1			T59	2		T83	1		T112	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	127	1			T2	1		T79	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	137	1			T2	2		T16	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	74	1			T123	1		T183	3		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	81	1			T16	1		T123	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	276	1			T1	3		T4	2		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	39	1			T34	2		T91	1		T195	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	212	1			T4	1		T12	1		T13	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	699	1			T1	4		T4	10		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	193	1			T1	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	641	1			T1	10		T4	4		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	186	1			T1	3		T4	2		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	707	1			T1	5		T2	1		T4	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	175	1			T1	3		T2	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	713	1			T1	3		T2	2		T4	6
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	180	1			T17	1		T40	1		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	428	1			T1	5		T2	2		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	191	1			T1	1		T2	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	442	1			T1	4		T4	2		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	206	1			T1	3		T2	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	438	1			T1	5		T4	3		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	184	1			T1	1		T4	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	425	1			T1	1		T2	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	166	1			T1	1		T2	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	610	1			T1	3		T4	3		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	266	1			T1	2		T2	1		T3	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	855	1			T1	1		T2	1		T3	17
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	258	1			T1	1		T4	3		T193	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	883	1			T1	1		T4	4		T12	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	277	1			T1	3		T4	4		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	983	1			T1	4		T4	3		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	148	1			T4	2		T13	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	370	1			T1	2		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	241	1			T1	1		T3	2		T4	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	483	1			T1	3		T2	1		T3	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	258	1			T2	2		T4	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	520	1			T1	4		T4	5		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	286	1			T2	2		T16	2		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	486	1			T1	3		T2	1		T4	2