Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30956

1

T1

218

T2

34

T3

36

auto[1]

270

1

T2

14

T115

9

T99

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30965	1			T1	218		T2	35		T3	36
auto[134217728:268435455]	10	1			T307	1		T222	1		T414	1
auto[268435456:402653183]	6	1			T409	1		T336	2		T415	1
auto[402653184:536870911]	9	1			T2	1		T115	2		T416	1
auto[536870912:671088639]	4	1			T317	1		T417	1		T297	1
auto[671088640:805306367]	7	1			T295	1		T317	1		T336	1
auto[805306368:939524095]	9	1			T2	1		T115	1		T307	2
auto[939524096:1073741823]	7	1			T115	1		T222	1		T278	1
auto[1073741824:1207959551]	5	1			T276	1		T295	1		T253	1
auto[1207959552:1342177279]	5	1			T307	1		T409	1		T418	1
auto[1342177280:1476395007]	8	1			T115	1		T295	1		T303	1
auto[1476395008:1610612735]	13	1			T2	1		T280	1		T419	1
auto[1610612736:1744830463]	10	1			T2	1		T99	1		T280	2
auto[1744830464:1879048191]	10	1			T2	3		T280	2		T390	1
auto[1879048192:2013265919]	10	1			T115	1		T99	1		T248	1
auto[2013265920:2147483647]	5	1			T2	1		T255	1		T223	1
auto[2147483648:2281701375]	6	1			T248	1		T253	1		T255	1
auto[2281701376:2415919103]	12	1			T2	2		T115	1		T250	1
auto[2415919104:2550136831]	13	1			T230	1		T418	1		T276	1
auto[2550136832:2684354559]	8	1			T280	2		T248	1		T394	1
auto[2684354560:2818572287]	6	1			T317	1		T308	1		T417	1
auto[2818572288:2952790015]	8	1			T307	1		T255	1		T416	1
auto[2952790016:3087007743]	10	1			T115	1		T307	2		T414	1
auto[3087007744:3221225471]	9	1			T280	1		T250	1		T222	1
auto[3221225472:3355443199]	15	1			T99	1		T230	1		T307	1
auto[3355443200:3489660927]	11	1			T307	1		T409	1		T278	2
auto[3489660928:3623878655]	10	1			T2	1		T390	1		T283	1
auto[3623878656:3758096383]	10	1			T2	1		T250	1		T276	1
auto[3758096384:3892314111]	5	1			T222	2		T288	1		T415	1
auto[3892314112:4026531839]	6	1			T419	1		T295	1		T317	1
auto[4026531840:4160749567]	7	1			T248	1		T286	2		T416	1
auto[4160749568:4294967295]	7	1			T2	1		T390	1		T409	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30956	1			T1	218		T2	34		T3	36
auto[0:134217727]	auto[1]	9	1			T2	1		T115	1		T280	1
auto[134217728:268435455]	auto[1]	10	1			T307	1		T222	1		T414	1
auto[268435456:402653183]	auto[1]	6	1			T409	1		T336	2		T415	1
auto[402653184:536870911]	auto[1]	9	1			T2	1		T115	2		T416	1
auto[536870912:671088639]	auto[1]	4	1			T317	1		T417	1		T297	1
auto[671088640:805306367]	auto[1]	7	1			T295	1		T317	1		T336	1
auto[805306368:939524095]	auto[1]	9	1			T2	1		T115	1		T307	2
auto[939524096:1073741823]	auto[1]	7	1			T115	1		T222	1		T278	1
auto[1073741824:1207959551]	auto[1]	5	1			T276	1		T295	1		T253	1
auto[1207959552:1342177279]	auto[1]	5	1			T307	1		T409	1		T418	1
auto[1342177280:1476395007]	auto[1]	8	1			T115	1		T295	1		T303	1
auto[1476395008:1610612735]	auto[1]	13	1			T2	1		T280	1		T419	1
auto[1610612736:1744830463]	auto[1]	10	1			T2	1		T99	1		T280	2
auto[1744830464:1879048191]	auto[1]	10	1			T2	3		T280	2		T390	1
auto[1879048192:2013265919]	auto[1]	10	1			T115	1		T99	1		T248	1
auto[2013265920:2147483647]	auto[1]	5	1			T2	1		T255	1		T223	1
auto[2147483648:2281701375]	auto[1]	6	1			T248	1		T253	1		T255	1
auto[2281701376:2415919103]	auto[1]	12	1			T2	2		T115	1		T250	1
auto[2415919104:2550136831]	auto[1]	13	1			T230	1		T418	1		T276	1
auto[2550136832:2684354559]	auto[1]	8	1			T280	2		T248	1		T394	1
auto[2684354560:2818572287]	auto[1]	6	1			T317	1		T308	1		T417	1
auto[2818572288:2952790015]	auto[1]	8	1			T307	1		T255	1		T416	1
auto[2952790016:3087007743]	auto[1]	10	1			T115	1		T307	2		T414	1
auto[3087007744:3221225471]	auto[1]	9	1			T280	1		T250	1		T222	1
auto[3221225472:3355443199]	auto[1]	15	1			T99	1		T230	1		T307	1
auto[3355443200:3489660927]	auto[1]	11	1			T307	1		T409	1		T278	2
auto[3489660928:3623878655]	auto[1]	10	1			T2	1		T390	1		T283	1
auto[3623878656:3758096383]	auto[1]	10	1			T2	1		T250	1		T276	1
auto[3758096384:3892314111]	auto[1]	5	1			T222	2		T288	1		T415	1
auto[3892314112:4026531839]	auto[1]	6	1			T419	1		T295	1		T317	1
auto[4026531840:4160749567]	auto[1]	7	1			T248	1		T286	2		T416	1
auto[4160749568:4294967295]	auto[1]	7	1			T2	1		T390	1		T409	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1472

1

T1

4

T2

2

T4

13

auto[1]

1739

1

T1

10

T2

2

T4

13

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T4	2		T40	1		T189	1
auto[134217728:268435455]	101	1			T1	2		T15	1		T45	1
auto[268435456:402653183]	86	1			T4	1		T41	1		T59	2
auto[402653184:536870911]	98	1			T1	3		T4	2		T17	1
auto[536870912:671088639]	106	1			T1	2		T4	1		T46	1
auto[671088640:805306367]	104	1			T1	1		T4	2		T12	1
auto[805306368:939524095]	97	1			T12	1		T25	1		T41	1
auto[939524096:1073741823]	82	1			T17	1		T22	1		T23	1
auto[1073741824:1207959551]	108	1			T40	1		T46	1		T41	1
auto[1207959552:1342177279]	106	1			T2	1		T189	1		T42	1
auto[1342177280:1476395007]	90	1			T1	1		T4	1		T15	1
auto[1476395008:1610612735]	96	1			T4	1		T13	2		T15	1
auto[1610612736:1744830463]	104	1			T13	1		T34	2		T127	1
auto[1744830464:1879048191]	92	1			T4	2		T15	1		T42	1
auto[1879048192:2013265919]	90	1			T1	1		T12	1		T22	2
auto[2013265920:2147483647]	117	1			T1	1		T4	1		T184	1
auto[2147483648:2281701375]	106	1			T41	2		T420	1		T59	2
auto[2281701376:2415919103]	92	1			T1	1		T4	1		T22	1
auto[2415919104:2550136831]	98	1			T4	1		T13	1		T45	1
auto[2550136832:2684354559]	104	1			T2	1		T4	1		T13	1
auto[2684354560:2818572287]	102	1			T4	1		T22	1		T183	1
auto[2818572288:2952790015]	122	1			T4	2		T13	1		T15	2
auto[2952790016:3087007743]	121	1			T13	1		T17	2		T79	1
auto[3087007744:3221225471]	115	1			T2	1		T4	1		T12	1
auto[3221225472:3355443199]	88	1			T2	1		T15	1		T226	1
auto[3355443200:3489660927]	87	1			T45	1		T382	1		T36	1
auto[3489660928:3623878655]	96	1			T1	1		T4	2		T41	1
auto[3623878656:3758096383]	101	1			T196	1		T42	4		T59	2
auto[3758096384:3892314111]	94	1			T1	1		T4	4		T79	1
auto[3892314112:4026531839]	112	1			T41	1		T196	1		T42	2
auto[4026531840:4160749567]	104	1			T79	1		T23	1		T41	3
auto[4160749568:4294967295]	90	1			T12	1		T41	1		T42	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T4	1		T40	1		T42	1
auto[0:134217727]	auto[1]	49	1			T4	1		T189	1		T42	3
auto[134217728:268435455]	auto[0]	45	1			T1	1		T41	1		T66	1
auto[134217728:268435455]	auto[1]	56	1			T1	1		T15	1		T45	1
auto[268435456:402653183]	auto[0]	36	1			T4	1		T59	1		T83	1
auto[268435456:402653183]	auto[1]	50	1			T41	1		T59	1		T91	2
auto[402653184:536870911]	auto[0]	41	1			T4	2		T82	1		T83	2
auto[402653184:536870911]	auto[1]	57	1			T1	3		T17	1		T184	1
auto[536870912:671088639]	auto[0]	49	1			T4	1		T46	1		T41	1
auto[536870912:671088639]	auto[1]	57	1			T1	2		T42	1		T5	1
auto[671088640:805306367]	auto[0]	45	1			T1	1		T4	1		T22	1
auto[671088640:805306367]	auto[1]	59	1			T4	1		T12	1		T41	2
auto[805306368:939524095]	auto[0]	42	1			T12	1		T25	1		T421	1
auto[805306368:939524095]	auto[1]	55	1			T41	1		T66	1		T59	2
auto[939524096:1073741823]	auto[0]	33	1			T41	1		T59	1		T190	1
auto[939524096:1073741823]	auto[1]	49	1			T17	1		T22	1		T23	1
auto[1073741824:1207959551]	auto[0]	44	1			T46	1		T41	1		T82	1
auto[1073741824:1207959551]	auto[1]	64	1			T40	1		T42	1		T177	1
auto[1207959552:1342177279]	auto[0]	46	1			T2	1		T189	1		T42	1
auto[1207959552:1342177279]	auto[1]	60	1			T382	1		T59	2		T177	1
auto[1342177280:1476395007]	auto[0]	38	1			T15	1		T17	1		T127	1
auto[1342177280:1476395007]	auto[1]	52	1			T1	1		T4	1		T58	1
auto[1476395008:1610612735]	auto[0]	38	1			T15	1		T22	1		T41	1
auto[1476395008:1610612735]	auto[1]	58	1			T4	1		T13	2		T41	1
auto[1610612736:1744830463]	auto[0]	52	1			T13	1		T34	2		T42	1
auto[1610612736:1744830463]	auto[1]	52	1			T127	1		T420	1		T422	1
auto[1744830464:1879048191]	auto[0]	52	1			T4	2		T15	1		T42	1
auto[1744830464:1879048191]	auto[1]	40	1			T422	1		T294	1		T59	1
auto[1879048192:2013265919]	auto[0]	47	1			T22	2		T190	1		T230	1
auto[1879048192:2013265919]	auto[1]	43	1			T1	1		T12	1		T42	1
auto[2013265920:2147483647]	auto[0]	54	1			T1	1		T42	2		T82	1
auto[2013265920:2147483647]	auto[1]	63	1			T4	1		T184	1		T41	1
auto[2147483648:2281701375]	auto[0]	48	1			T41	2		T50	1		T60	1
auto[2147483648:2281701375]	auto[1]	58	1			T420	1		T59	2		T228	1
auto[2281701376:2415919103]	auto[0]	41	1			T4	1		T22	1		T46	1
auto[2281701376:2415919103]	auto[1]	51	1			T1	1		T184	1		T41	1
auto[2415919104:2550136831]	auto[0]	48	1			T4	1		T58	1		T42	1
auto[2415919104:2550136831]	auto[1]	50	1			T13	1		T45	1		T226	1
auto[2550136832:2684354559]	auto[0]	52	1			T13	1		T15	1		T79	1
auto[2550136832:2684354559]	auto[1]	52	1			T2	1		T4	1		T41	1
auto[2684354560:2818572287]	auto[0]	48	1			T22	1		T63	1		T177	1
auto[2684354560:2818572287]	auto[1]	54	1			T4	1		T183	1		T41	1
auto[2818572288:2952790015]	auto[0]	56	1			T15	1		T63	1		T59	1
auto[2818572288:2952790015]	auto[1]	66	1			T4	2		T13	1		T15	1
auto[2952790016:3087007743]	auto[0]	62	1			T13	1		T50	2		T89	1
auto[2952790016:3087007743]	auto[1]	59	1			T17	2		T79	1		T40	1
auto[3087007744:3221225471]	auto[0]	45	1			T4	1		T12	1		T15	2
auto[3087007744:3221225471]	auto[1]	70	1			T2	1		T25	1		T41	1
auto[3221225472:3355443199]	auto[0]	37	1			T2	1		T41	1		T89	1
auto[3221225472:3355443199]	auto[1]	51	1			T15	1		T226	1		T58	1
auto[3355443200:3489660927]	auto[0]	41	1			T177	1		T60	1		T273	1
auto[3355443200:3489660927]	auto[1]	46	1			T45	1		T382	1		T36	1
auto[3489660928:3623878655]	auto[0]	45	1			T1	1		T4	2		T59	1
auto[3489660928:3623878655]	auto[1]	51	1			T41	1		T58	1		T42	3
auto[3623878656:3758096383]	auto[0]	49	1			T42	1		T59	1		T421	1
auto[3623878656:3758096383]	auto[1]	52	1			T196	1		T42	3		T59	1
auto[3758096384:3892314111]	auto[0]	40	1			T79	1		T83	1		T177	1
auto[3758096384:3892314111]	auto[1]	54	1			T1	1		T4	4		T115	1
auto[3892314112:4026531839]	auto[0]	46	1			T41	1		T42	1		T82	1
auto[3892314112:4026531839]	auto[1]	66	1			T196	1		T42	1		T27	1
auto[4026531840:4160749567]	auto[0]	52	1			T23	1		T41	1		T42	2
auto[4026531840:4160749567]	auto[1]	52	1			T79	1		T41	2		T227	1
auto[4160749568:4294967295]	auto[0]	47	1			T12	1		T41	1		T63	1
auto[4160749568:4294967295]	auto[1]	43	1			T42	1		T5	1		T59	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1499

1

T1

4

T2

1

T4

14

auto[1]

1708

1

T1

10

T2

3

T4

12

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	123	1			T1	1		T13	2		T17	1
auto[134217728:268435455]	113	1			T4	1		T79	1		T40	1
auto[268435456:402653183]	117	1			T4	1		T12	1		T13	1
auto[402653184:536870911]	93	1			T12	1		T15	1		T46	1
auto[536870912:671088639]	85	1			T2	1		T12	1		T13	1
auto[671088640:805306367]	101	1			T4	3		T15	1		T45	1
auto[805306368:939524095]	88	1			T4	1		T79	2		T41	1
auto[939524096:1073741823]	82	1			T1	1		T4	2		T41	1
auto[1073741824:1207959551]	109	1			T12	1		T15	3		T17	1
auto[1207959552:1342177279]	118	1			T1	1		T2	1		T184	1
auto[1342177280:1476395007]	95	1			T1	1		T12	1		T15	1
auto[1476395008:1610612735]	83	1			T41	1		T42	1		T63	1
auto[1610612736:1744830463]	124	1			T4	2		T34	1		T42	1
auto[1744830464:1879048191]	110	1			T17	1		T22	1		T41	1
auto[1879048192:2013265919]	104	1			T15	1		T22	2		T41	1
auto[2013265920:2147483647]	98	1			T22	1		T422	1		T59	2
auto[2147483648:2281701375]	109	1			T4	1		T40	1		T41	1
auto[2281701376:2415919103]	91	1			T4	2		T22	1		T41	1
auto[2415919104:2550136831]	85	1			T4	1		T22	1		T46	1
auto[2550136832:2684354559]	98	1			T4	2		T15	1		T17	1
auto[2684354560:2818572287]	87	1			T1	1		T45	1		T41	1
auto[2818572288:2952790015]	105	1			T1	1		T23	1		T59	2
auto[2952790016:3087007743]	108	1			T4	1		T13	1		T17	1
auto[3087007744:3221225471]	91	1			T13	1		T22	1		T25	1
auto[3221225472:3355443199]	100	1			T1	1		T2	1		T196	1
auto[3355443200:3489660927]	80	1			T4	1		T226	1		T41	1
auto[3489660928:3623878655]	96	1			T1	1		T4	2		T45	1
auto[3623878656:3758096383]	89	1			T13	1		T22	1		T41	1
auto[3758096384:3892314111]	114	1			T4	3		T15	1		T41	1
auto[3892314112:4026531839]	114	1			T1	5		T4	1		T25	1
auto[4026531840:4160749567]	93	1			T1	1		T2	1		T79	1
auto[4160749568:4294967295]	104	1			T4	2		T15	1		T40	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	69	1			T13	1		T46	1		T41	1
auto[0:134217727]	auto[1]	54	1			T1	1		T13	1		T17	1
auto[134217728:268435455]	auto[0]	50	1			T42	1		T59	1		T50	1
auto[134217728:268435455]	auto[1]	63	1			T4	1		T79	1		T40	1
auto[268435456:402653183]	auto[0]	42	1			T12	1		T41	1		T42	1
auto[268435456:402653183]	auto[1]	75	1			T4	1		T13	1		T41	1
auto[402653184:536870911]	auto[0]	48	1			T12	1		T46	1		T41	1
auto[402653184:536870911]	auto[1]	45	1			T15	1		T227	1		T300	1
auto[536870912:671088639]	auto[0]	45	1			T12	1		T189	1		T243	1
auto[536870912:671088639]	auto[1]	40	1			T2	1		T13	1		T26	1
auto[671088640:805306367]	auto[0]	49	1			T4	3		T15	1		T83	1
auto[671088640:805306367]	auto[1]	52	1			T45	1		T184	1		T189	1
auto[805306368:939524095]	auto[0]	43	1			T4	1		T42	1		T243	1
auto[805306368:939524095]	auto[1]	45	1			T79	2		T41	1		T42	1
auto[939524096:1073741823]	auto[0]	42	1			T4	1		T41	1		T63	1
auto[939524096:1073741823]	auto[1]	40	1			T1	1		T4	1		T42	5
auto[1073741824:1207959551]	auto[0]	54	1			T12	1		T15	2		T183	1
auto[1073741824:1207959551]	auto[1]	55	1			T15	1		T17	1		T41	2
auto[1207959552:1342177279]	auto[0]	50	1			T34	1		T42	1		T50	2
auto[1207959552:1342177279]	auto[1]	68	1			T1	1		T2	1		T184	1
auto[1342177280:1476395007]	auto[0]	44	1			T1	1		T12	1		T15	1
auto[1342177280:1476395007]	auto[1]	51	1			T184	1		T58	1		T42	3
auto[1476395008:1610612735]	auto[0]	27	1			T63	1		T83	1		T207	1
auto[1476395008:1610612735]	auto[1]	56	1			T41	1		T42	1		T50	1
auto[1610612736:1744830463]	auto[0]	55	1			T4	1		T42	1		T59	2
auto[1610612736:1744830463]	auto[1]	69	1			T4	1		T34	1		T344	1
auto[1744830464:1879048191]	auto[0]	43	1			T22	1		T41	1		T50	1
auto[1744830464:1879048191]	auto[1]	67	1			T17	1		T82	1		T59	2
auto[1879048192:2013265919]	auto[0]	54	1			T15	1		T22	2		T41	1
auto[1879048192:2013265919]	auto[1]	50	1			T173	1		T99	1		T190	1
auto[2013265920:2147483647]	auto[0]	52	1			T22	1		T50	1		T177	1
auto[2013265920:2147483647]	auto[1]	46	1			T422	1		T59	2		T36	1
auto[2147483648:2281701375]	auto[0]	48	1			T4	1		T40	1		T58	1
auto[2147483648:2281701375]	auto[1]	61	1			T41	1		T227	1		T189	1
auto[2281701376:2415919103]	auto[0]	34	1			T22	1		T41	1		T42	1
auto[2281701376:2415919103]	auto[1]	57	1			T4	2		T420	1		T42	1
auto[2415919104:2550136831]	auto[0]	44	1			T4	1		T46	1		T420	1
auto[2415919104:2550136831]	auto[1]	41	1			T22	1		T41	1		T58	1
auto[2550136832:2684354559]	auto[0]	39	1			T4	1		T15	1		T197	1
auto[2550136832:2684354559]	auto[1]	59	1			T4	1		T17	1		T41	1
auto[2684354560:2818572287]	auto[0]	44	1			T227	1		T42	2		T59	1
auto[2684354560:2818572287]	auto[1]	43	1			T1	1		T45	1		T41	1
auto[2818572288:2952790015]	auto[0]	40	1			T23	1		T59	1		T331	1
auto[2818572288:2952790015]	auto[1]	65	1			T1	1		T59	1		T83	1
auto[2952790016:3087007743]	auto[0]	59	1			T4	1		T13	1		T127	1
auto[2952790016:3087007743]	auto[1]	49	1			T17	1		T58	1		T273	1
auto[3087007744:3221225471]	auto[0]	50	1			T22	1		T42	1		T59	1
auto[3087007744:3221225471]	auto[1]	41	1			T13	1		T25	1		T41	1
auto[3221225472:3355443199]	auto[0]	49	1			T2	1		T196	1		T58	1
auto[3221225472:3355443199]	auto[1]	51	1			T1	1		T59	1		T50	1
auto[3355443200:3489660927]	auto[0]	37	1			T41	1		T42	1		T136	1
auto[3355443200:3489660927]	auto[1]	43	1			T4	1		T226	1		T42	1
auto[3489660928:3623878655]	auto[0]	39	1			T4	1		T23	1		T5	1
auto[3489660928:3623878655]	auto[1]	57	1			T1	1		T4	1		T45	1
auto[3623878656:3758096383]	auto[0]	40	1			T13	1		T22	1		T50	2
auto[3623878656:3758096383]	auto[1]	49	1			T41	1		T59	1		T173	1
auto[3758096384:3892314111]	auto[0]	60	1			T4	1		T41	1		T82	1
auto[3758096384:3892314111]	auto[1]	54	1			T4	2		T15	1		T59	1
auto[3892314112:4026531839]	auto[0]	57	1			T1	2		T25	1		T23	1
auto[3892314112:4026531839]	auto[1]	57	1			T1	3		T4	1		T189	1
auto[4026531840:4160749567]	auto[0]	41	1			T1	1		T79	1		T22	1
auto[4026531840:4160749567]	auto[1]	52	1			T2	1		T41	1		T58	1
auto[4160749568:4294967295]	auto[0]	51	1			T4	2		T15	1		T42	1
auto[4160749568:4294967295]	auto[1]	53	1			T40	1		T226	1		T115	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1512

1

T1

7

T2

1

T4

15

auto[1]

1692

1

T1

7

T2

3

T4

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	81	1			T1	2		T17	1		T45	1
auto[134217728:268435455]	97	1			T15	1		T41	1		T196	1
auto[268435456:402653183]	100	1			T1	1		T46	1		T41	1
auto[402653184:536870911]	105	1			T1	1		T4	2		T22	1
auto[536870912:671088639]	113	1			T4	1		T22	1		T422	1
auto[671088640:805306367]	113	1			T1	1		T2	1		T22	1
auto[805306368:939524095]	100	1			T1	1		T4	1		T420	2
auto[939524096:1073741823]	93	1			T1	1		T12	1		T41	1
auto[1073741824:1207959551]	108	1			T4	2		T17	1		T79	1
auto[1207959552:1342177279]	89	1			T40	1		T25	1		T189	1
auto[1342177280:1476395007]	110	1			T4	1		T25	1		T41	1
auto[1476395008:1610612735]	98	1			T4	1		T12	1		T41	2
auto[1610612736:1744830463]	116	1			T127	1		T41	1		T42	3
auto[1744830464:1879048191]	106	1			T1	2		T4	2		T13	2
auto[1879048192:2013265919]	94	1			T4	1		T15	1		T41	1
auto[2013265920:2147483647]	90	1			T15	1		T226	1		T41	2
auto[2147483648:2281701375]	95	1			T1	1		T13	1		T17	1
auto[2281701376:2415919103]	100	1			T4	2		T13	1		T184	1
auto[2415919104:2550136831]	102	1			T2	1		T15	1		T45	1
auto[2550136832:2684354559]	86	1			T4	1		T17	1		T42	1
auto[2684354560:2818572287]	106	1			T4	1		T15	2		T66	1
auto[2818572288:2952790015]	108	1			T15	1		T23	1		T41	1
auto[2952790016:3087007743]	78	1			T15	1		T40	1		T184	1
auto[3087007744:3221225471]	105	1			T4	2		T12	1		T22	1
auto[3221225472:3355443199]	107	1			T12	1		T13	1		T79	1
auto[3355443200:3489660927]	103	1			T4	3		T79	1		T22	1
auto[3489660928:3623878655]	96	1			T1	1		T4	1		T46	1
auto[3623878656:3758096383]	108	1			T2	1		T4	2		T13	1
auto[3758096384:3892314111]	113	1			T1	2		T2	1		T4	1
auto[3892314112:4026531839]	88	1			T4	1		T196	1		T42	1
auto[4026531840:4160749567]	99	1			T1	1		T15	1		T41	1
auto[4160749568:4294967295]	97	1			T4	1		T17	1		T22	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	40	1			T34	2		T42	1		T173	1
auto[0:134217727]	auto[1]	41	1			T1	2		T17	1		T45	1
auto[134217728:268435455]	auto[0]	50	1			T15	1		T58	1		T83	1
auto[134217728:268435455]	auto[1]	47	1			T41	1		T196	1		T63	1
auto[268435456:402653183]	auto[0]	45	1			T1	1		T46	1		T50	1
auto[268435456:402653183]	auto[1]	55	1			T41	1		T294	1		T50	1
auto[402653184:536870911]	auto[0]	53	1			T1	1		T4	2		T22	1
auto[402653184:536870911]	auto[1]	52	1			T115	2		T41	1		T5	1
auto[536870912:671088639]	auto[0]	55	1			T4	1		T22	1		T177	1
auto[536870912:671088639]	auto[1]	58	1			T422	1		T59	3		T136	1
auto[671088640:805306367]	auto[0]	51	1			T22	1		T42	2		T59	1
auto[671088640:805306367]	auto[1]	62	1			T1	1		T2	1		T41	1
auto[805306368:939524095]	auto[0]	46	1			T1	1		T4	1		T420	1
auto[805306368:939524095]	auto[1]	54	1			T420	1		T227	1		T42	2
auto[939524096:1073741823]	auto[0]	47	1			T12	1		T41	1		T59	1
auto[939524096:1073741823]	auto[1]	46	1			T1	1		T294	1		T83	1
auto[1073741824:1207959551]	auto[0]	54	1			T4	1		T17	1		T41	2
auto[1073741824:1207959551]	auto[1]	54	1			T4	1		T79	1		T41	2
auto[1207959552:1342177279]	auto[0]	47	1			T40	1		T42	2		T82	1
auto[1207959552:1342177279]	auto[1]	42	1			T25	1		T189	1		T42	1
auto[1342177280:1476395007]	auto[0]	55	1			T25	1		T41	1		T58	1
auto[1342177280:1476395007]	auto[1]	55	1			T4	1		T227	1		T189	1
auto[1476395008:1610612735]	auto[0]	41	1			T4	1		T12	1		T41	1
auto[1476395008:1610612735]	auto[1]	57	1			T41	1		T42	2		T82	1
auto[1610612736:1744830463]	auto[0]	42	1			T127	1		T83	1		T421	1
auto[1610612736:1744830463]	auto[1]	74	1			T41	1		T42	3		T27	1
auto[1744830464:1879048191]	auto[0]	56	1			T1	1		T4	1		T13	1
auto[1744830464:1879048191]	auto[1]	50	1			T1	1		T4	1		T13	1
auto[1879048192:2013265919]	auto[0]	43	1			T207	1		T60	1		T423	1
auto[1879048192:2013265919]	auto[1]	51	1			T4	1		T15	1		T41	1
auto[2013265920:2147483647]	auto[0]	48	1			T15	1		T41	1		T50	1
auto[2013265920:2147483647]	auto[1]	42	1			T226	1		T41	1		T42	1
auto[2147483648:2281701375]	auto[0]	40	1			T13	1		T22	1		T196	1
auto[2147483648:2281701375]	auto[1]	55	1			T1	1		T17	1		T79	1
auto[2281701376:2415919103]	auto[0]	44	1			T4	2		T13	1		T127	1
auto[2281701376:2415919103]	auto[1]	56	1			T184	1		T226	1		T41	1
auto[2415919104:2550136831]	auto[0]	48	1			T22	1		T42	1		T59	1
auto[2415919104:2550136831]	auto[1]	54	1			T2	1		T15	1		T45	1
auto[2550136832:2684354559]	auto[0]	36	1			T17	1		T177	1		T230	1
auto[2550136832:2684354559]	auto[1]	50	1			T4	1		T42	1		T59	1
auto[2684354560:2818572287]	auto[0]	53	1			T4	1		T15	1		T66	1
auto[2684354560:2818572287]	auto[1]	53	1			T15	1		T42	1		T24	1
auto[2818572288:2952790015]	auto[0]	57	1			T15	1		T41	1		T42	2
auto[2818572288:2952790015]	auto[1]	51	1			T23	1		T66	1		T63	1
auto[2952790016:3087007743]	auto[0]	36	1			T15	1		T41	1		T189	1
auto[2952790016:3087007743]	auto[1]	42	1			T40	1		T184	1		T41	1
auto[3087007744:3221225471]	auto[0]	47	1			T83	1		T51	1		T207	1
auto[3087007744:3221225471]	auto[1]	58	1			T4	2		T12	1		T22	1
auto[3221225472:3355443199]	auto[0]	55	1			T12	1		T79	1		T23	1
auto[3221225472:3355443199]	auto[1]	52	1			T13	1		T40	1		T45	1
auto[3355443200:3489660927]	auto[0]	43	1			T4	2		T79	1		T22	1
auto[3355443200:3489660927]	auto[1]	60	1			T4	1		T184	1		T41	1
auto[3489660928:3623878655]	auto[0]	38	1			T1	1		T4	1		T46	1
auto[3489660928:3623878655]	auto[1]	58	1			T41	1		T58	1		T382	1
auto[3623878656:3758096383]	auto[0]	57	1			T2	1		T4	2		T41	1
auto[3623878656:3758096383]	auto[1]	51	1			T13	1		T42	1		T294	1
auto[3758096384:3892314111]	auto[0]	56	1			T1	1		T12	1		T13	1
auto[3758096384:3892314111]	auto[1]	57	1			T1	1		T2	1		T4	1
auto[3892314112:4026531839]	auto[0]	43	1			T42	1		T59	1		T89	1
auto[3892314112:4026531839]	auto[1]	45	1			T4	1		T196	1		T59	1
auto[4026531840:4160749567]	auto[0]	49	1			T1	1		T15	1		T83	1
auto[4026531840:4160749567]	auto[1]	50	1			T41	1		T58	2		T227	1
auto[4160749568:4294967295]	auto[0]	37	1			T22	1		T50	1		T190	1
auto[4160749568:4294967295]	auto[1]	60	1			T4	1		T17	1		T41	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1505

1

T1

4

T2

2

T4

12

auto[1]

1699

1

T1

10

T2

2

T4

14

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T79	1		T115	1		T41	4
auto[134217728:268435455]	115	1			T1	1		T12	1		T15	1
auto[268435456:402653183]	93	1			T1	1		T4	1		T12	1
auto[402653184:536870911]	120	1			T4	2		T46	1		T227	1
auto[536870912:671088639]	103	1			T127	1		T42	1		T59	1
auto[671088640:805306367]	102	1			T2	1		T4	2		T59	1
auto[805306368:939524095]	93	1			T1	1		T4	1		T12	1
auto[939524096:1073741823]	99	1			T1	1		T13	1		T15	1
auto[1073741824:1207959551]	122	1			T4	1		T12	1		T41	1
auto[1207959552:1342177279]	96	1			T1	1		T4	2		T15	2
auto[1342177280:1476395007]	99	1			T22	1		T41	1		T42	1
auto[1476395008:1610612735]	101	1			T4	2		T13	1		T17	2
auto[1610612736:1744830463]	94	1			T4	2		T25	1		T183	1
auto[1744830464:1879048191]	94	1			T2	1		T12	1		T184	1
auto[1879048192:2013265919]	102	1			T41	2		T58	1		T63	2
auto[2013265920:2147483647]	95	1			T1	1		T4	1		T25	1
auto[2147483648:2281701375]	100	1			T4	1		T17	1		T22	2
auto[2281701376:2415919103]	91	1			T1	1		T2	1		T4	2
auto[2415919104:2550136831]	99	1			T4	1		T13	1		T15	1
auto[2550136832:2684354559]	107	1			T1	1		T15	1		T40	2
auto[2684354560:2818572287]	107	1			T1	1		T40	1		T41	1
auto[2818572288:2952790015]	100	1			T4	2		T23	1		T34	1
auto[2952790016:3087007743]	102	1			T4	1		T184	1		T226	1
auto[3087007744:3221225471]	102	1			T14	1		T184	1		T189	1
auto[3221225472:3355443199]	99	1			T4	1		T13	1		T23	1
auto[3355443200:3489660927]	101	1			T1	1		T4	1		T15	1
auto[3489660928:3623878655]	113	1			T4	1		T23	1		T41	1
auto[3623878656:3758096383]	82	1			T17	1		T79	1		T420	1
auto[3758096384:3892314111]	95	1			T41	2		T196	1		T189	1
auto[3892314112:4026531839]	89	1			T1	2		T2	1		T13	1
auto[4026531840:4160749567]	106	1			T1	1		T4	1		T15	3
auto[4160749568:4294967295]	89	1			T1	1		T4	1		T66	1