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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4358 1 T1 20 T2 6 T4 26
auto[1] 2052 1 T1 8 T2 2 T4 26



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 234 1 T4 4 T79 2 T22 2
auto[134217728:268435455] 206 1 T1 2 T15 4 T82 2
auto[268435456:402653183] 174 1 T115 2 T41 6 T42 2
auto[402653184:536870911] 238 1 T1 4 T4 4 T22 4
auto[536870912:671088639] 170 1 T4 4 T23 2 T59 2
auto[671088640:805306367] 186 1 T4 2 T12 2 T13 2
auto[805306368:939524095] 188 1 T4 2 T17 2 T22 2
auto[939524096:1073741823] 178 1 T4 4 T15 2 T40 2
auto[1073741824:1207959551] 230 1 T1 2 T4 4 T13 2
auto[1207959552:1342177279] 208 1 T1 2 T2 2 T4 4
auto[1342177280:1476395007] 220 1 T1 2 T22 2 T41 4
auto[1476395008:1610612735] 198 1 T79 2 T40 2 T45 2
auto[1610612736:1744830463] 202 1 T2 2 T4 8 T184 2
auto[1744830464:1879048191] 194 1 T1 2 T45 2 T226 2
auto[1879048192:2013265919] 172 1 T4 2 T420 2 T42 4
auto[2013265920:2147483647] 228 1 T4 2 T12 2 T13 2
auto[2147483648:2281701375] 200 1 T23 2 T41 6 T58 4
auto[2281701376:2415919103] 228 1 T1 2 T13 2 T14 2
auto[2415919104:2550136831] 192 1 T1 2 T42 4 T59 4
auto[2550136832:2684354559] 208 1 T1 2 T12 4 T13 2
auto[2684354560:2818572287] 196 1 T4 2 T45 2 T127 2
auto[2818572288:2952790015] 208 1 T2 2 T4 2 T13 2
auto[2952790016:3087007743] 194 1 T4 2 T15 2 T17 4
auto[3087007744:3221225471] 216 1 T1 4 T2 2 T42 2
auto[3221225472:3355443199] 196 1 T1 2 T15 2 T41 2
auto[3355443200:3489660927] 194 1 T4 2 T12 2 T41 4
auto[3489660928:3623878655] 182 1 T4 2 T79 2 T23 2
auto[3623878656:3758096383] 206 1 T1 2 T15 2 T25 2
auto[3758096384:3892314111] 204 1 T15 2 T26 2 T226 2
auto[3892314112:4026531839] 170 1 T13 2 T15 2 T41 2
auto[4026531840:4160749567] 204 1 T66 2 T382 2 T50 4
auto[4160749568:4294967295] 186 1 T4 2 T22 2 T41 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 168 1 T4 4 T79 2 T22 2
auto[0:134217727] auto[1] 66 1 T184 2 T24 2 T59 2
auto[134217728:268435455] auto[0] 166 1 T1 2 T15 4 T82 2
auto[134217728:268435455] auto[1] 40 1 T50 2 T60 2 T347 2
auto[268435456:402653183] auto[0] 114 1 T41 4 T42 2 T422 2
auto[268435456:402653183] auto[1] 60 1 T115 2 T41 2 T199 2
auto[402653184:536870911] auto[0] 162 1 T1 2 T22 2 T382 2
auto[402653184:536870911] auto[1] 76 1 T1 2 T4 4 T22 2
auto[536870912:671088639] auto[0] 130 1 T4 4 T23 2 T59 2
auto[536870912:671088639] auto[1] 40 1 T177 2 T56 2 T206 2
auto[671088640:805306367] auto[0] 118 1 T13 2 T41 2 T189 2
auto[671088640:805306367] auto[1] 68 1 T4 2 T12 2 T63 2
auto[805306368:939524095] auto[0] 128 1 T17 2 T22 2 T34 2
auto[805306368:939524095] auto[1] 60 1 T4 2 T199 2 T103 2
auto[939524096:1073741823] auto[0] 118 1 T4 4 T15 2 T58 2
auto[939524096:1073741823] auto[1] 60 1 T40 2 T41 2 T59 2
auto[1073741824:1207959551] auto[0] 158 1 T1 2 T4 4 T13 2
auto[1073741824:1207959551] auto[1] 72 1 T42 6 T27 2 T270 2
auto[1207959552:1342177279] auto[0] 150 1 T1 2 T4 2 T41 2
auto[1207959552:1342177279] auto[1] 58 1 T2 2 T4 2 T17 2
auto[1342177280:1476395007] auto[0] 146 1 T1 2 T22 2 T196 2
auto[1342177280:1476395007] auto[1] 74 1 T41 4 T227 2 T5 2
auto[1476395008:1610612735] auto[0] 138 1 T79 2 T40 2 T196 2
auto[1476395008:1610612735] auto[1] 60 1 T45 2 T41 2 T50 2
auto[1610612736:1744830463] auto[0] 148 1 T2 2 T4 4 T196 2
auto[1610612736:1744830463] auto[1] 54 1 T4 4 T184 2 T41 2
auto[1744830464:1879048191] auto[0] 116 1 T1 2 T45 2 T226 2
auto[1744830464:1879048191] auto[1] 78 1 T42 2 T5 2 T63 2
auto[1879048192:2013265919] auto[0] 110 1 T420 2 T42 2 T294 2
auto[1879048192:2013265919] auto[1] 62 1 T4 2 T42 2 T29 2
auto[2013265920:2147483647] auto[0] 166 1 T12 2 T13 2 T15 2
auto[2013265920:2147483647] auto[1] 62 1 T4 2 T40 2 T41 2
auto[2147483648:2281701375] auto[0] 140 1 T23 2 T41 4 T58 4
auto[2147483648:2281701375] auto[1] 60 1 T41 2 T42 2 T201 2
auto[2281701376:2415919103] auto[0] 160 1 T13 2 T22 2 T59 4
auto[2281701376:2415919103] auto[1] 68 1 T1 2 T14 2 T100 2
auto[2415919104:2550136831] auto[0] 122 1 T1 2 T42 2 T59 4
auto[2415919104:2550136831] auto[1] 70 1 T42 2 T51 2 T56 2
auto[2550136832:2684354559] auto[0] 128 1 T1 2 T12 4 T13 2
auto[2550136832:2684354559] auto[1] 80 1 T184 2 T42 2 T51 2
auto[2684354560:2818572287] auto[0] 124 1 T4 2 T127 2 T196 2
auto[2684354560:2818572287] auto[1] 72 1 T45 2 T41 2 T42 2
auto[2818572288:2952790015] auto[0] 138 1 T2 2 T13 2 T41 2
auto[2818572288:2952790015] auto[1] 70 1 T4 2 T79 2 T115 2
auto[2952790016:3087007743] auto[0] 124 1 T4 2 T15 2 T17 2
auto[2952790016:3087007743] auto[1] 70 1 T17 2 T22 2 T34 2
auto[3087007744:3221225471] auto[0] 134 1 T2 2 T59 2 T177 2
auto[3087007744:3221225471] auto[1] 82 1 T1 4 T42 2 T422 2
auto[3221225472:3355443199] auto[0] 140 1 T1 2 T15 2 T41 2
auto[3221225472:3355443199] auto[1] 56 1 T42 4 T173 2 T81 2
auto[3355443200:3489660927] auto[0] 120 1 T12 2 T42 2 T422 2
auto[3355443200:3489660927] auto[1] 74 1 T4 2 T41 4 T42 2
auto[3489660928:3623878655] auto[0] 120 1 T79 2 T23 2 T46 2
auto[3489660928:3623878655] auto[1] 62 1 T4 2 T5 2 T207 2
auto[3623878656:3758096383] auto[0] 140 1 T1 2 T15 2 T66 2
auto[3623878656:3758096383] auto[1] 66 1 T25 2 T41 2 T424 2
auto[3758096384:3892314111] auto[0] 152 1 T15 2 T226 2 T46 2
auto[3758096384:3892314111] auto[1] 52 1 T26 2 T41 4 T42 2
auto[3892314112:4026531839] auto[0] 118 1 T13 2 T15 2 T58 2
auto[3892314112:4026531839] auto[1] 52 1 T41 2 T420 2 T99 2
auto[4026531840:4160749567] auto[0] 144 1 T66 2 T382 2 T50 2
auto[4026531840:4160749567] auto[1] 60 1 T50 2 T427 2 T32 2
auto[4160749568:4294967295] auto[0] 118 1 T22 2 T41 2 T58 2
auto[4160749568:4294967295] auto[1] 68 1 T4 2 T189 2 T59 2

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