Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2892

1

T1

13

T2

4

T4

22

auto[1]

273

1

T2

10

T115

7

T99

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T1	3		T2	1		T45	1
auto[134217728:268435455]	106	1			T4	1		T79	1		T115	1
auto[268435456:402653183]	105	1			T1	1		T2	1		T4	2
auto[402653184:536870911]	101	1			T2	1		T127	1		T227	1
auto[536870912:671088639]	98	1			T4	2		T45	1		T184	1
auto[671088640:805306367]	105	1			T2	1		T115	1		T41	2
auto[805306368:939524095]	100	1			T4	2		T40	1		T41	1
auto[939524096:1073741823]	106	1			T2	1		T15	1		T34	2
auto[1073741824:1207959551]	94	1			T2	2		T15	1		T46	1
auto[1207959552:1342177279]	99	1			T1	1		T17	1		T23	1
auto[1342177280:1476395007]	103	1			T4	1		T12	1		T13	1
auto[1476395008:1610612735]	89	1			T4	1		T13	1		T17	1
auto[1610612736:1744830463]	83	1			T1	1		T4	2		T22	1
auto[1744830464:1879048191]	85	1			T1	2		T41	1		T58	1
auto[1879048192:2013265919]	111	1			T2	1		T22	1		T41	1
auto[2013265920:2147483647]	102	1			T2	1		T184	1		T25	1
auto[2147483648:2281701375]	90	1			T4	1		T17	1		T22	1
auto[2281701376:2415919103]	105	1			T1	1		T2	2		T4	2
auto[2415919104:2550136831]	101	1			T12	1		T40	1		T41	1
auto[2550136832:2684354559]	101	1			T2	1		T13	1		T15	1
auto[2684354560:2818572287]	93	1			T14	1		T23	1		T189	1
auto[2818572288:2952790015]	90	1			T1	1		T15	1		T25	1
auto[2952790016:3087007743]	106	1			T4	1		T184	1		T58	1
auto[3087007744:3221225471]	101	1			T4	1		T66	1		T82	1
auto[3221225472:3355443199]	82	1			T4	2		T15	2		T63	1
auto[3355443200:3489660927]	102	1			T2	1		T4	1		T15	1
auto[3489660928:3623878655]	98	1			T12	1		T15	1		T22	1
auto[3623878656:3758096383]	91	1			T4	1		T12	1		T41	1
auto[3758096384:3892314111]	99	1			T1	2		T13	1		T79	1
auto[3892314112:4026531839]	97	1			T1	1		T2	1		T4	1
auto[4026531840:4160749567]	97	1			T40	1		T115	1		T24	1
auto[4160749568:4294967295]	105	1			T4	1		T12	1		T45	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	109	1			T1	3		T45	1		T127	1
auto[0:134217727]	auto[1]	11	1			T2	1		T280	1		T419	1
auto[134217728:268435455]	auto[0]	98	1			T4	1		T79	1		T50	2
auto[134217728:268435455]	auto[1]	8	1			T115	1		T280	1		T222	1
auto[268435456:402653183]	auto[0]	98	1			T1	1		T2	1		T4	2
auto[268435456:402653183]	auto[1]	7	1			T115	1		T283	1		T414	1
auto[402653184:536870911]	auto[0]	91	1			T127	1		T227	1		T42	2
auto[402653184:536870911]	auto[1]	10	1			T2	1		T409	1		T418	1
auto[536870912:671088639]	auto[0]	91	1			T4	2		T45	1		T184	1
auto[536870912:671088639]	auto[1]	7	1			T280	1		T307	1		T295	1
auto[671088640:805306367]	auto[0]	96	1			T115	1		T41	2		T42	4
auto[671088640:805306367]	auto[1]	9	1			T2	1		T409	1		T253	1
auto[805306368:939524095]	auto[0]	93	1			T4	2		T40	1		T41	1
auto[805306368:939524095]	auto[1]	7	1			T295	1		T317	1		T288	2
auto[939524096:1073741823]	auto[0]	93	1			T15	1		T34	2		T226	1
auto[939524096:1073741823]	auto[1]	13	1			T2	1		T307	1		T409	1
auto[1073741824:1207959551]	auto[0]	84	1			T15	1		T46	1		T41	1
auto[1073741824:1207959551]	auto[1]	10	1			T2	2		T222	1		T248	1
auto[1207959552:1342177279]	auto[0]	91	1			T1	1		T17	1		T23	1
auto[1207959552:1342177279]	auto[1]	8	1			T115	1		T283	1		T222	1
auto[1342177280:1476395007]	auto[0]	96	1			T4	1		T12	1		T13	1
auto[1342177280:1476395007]	auto[1]	7	1			T115	1		T230	1		T307	1
auto[1476395008:1610612735]	auto[0]	86	1			T4	1		T13	1		T17	1
auto[1476395008:1610612735]	auto[1]	3	1			T307	1		T288	1		T429	1
auto[1610612736:1744830463]	auto[0]	76	1			T1	1		T4	2		T22	1
auto[1610612736:1744830463]	auto[1]	7	1			T307	1		T248	1		T317	1
auto[1744830464:1879048191]	auto[0]	77	1			T1	2		T41	1		T58	1
auto[1744830464:1879048191]	auto[1]	8	1			T99	1		T283	1		T248	1
auto[1879048192:2013265919]	auto[0]	105	1			T2	1		T22	1		T41	1
auto[1879048192:2013265919]	auto[1]	6	1			T283	1		T276	1		T253	1
auto[2013265920:2147483647]	auto[0]	94	1			T2	1		T184	1		T25	1
auto[2013265920:2147483647]	auto[1]	8	1			T390	1		T414	1		T317	2
auto[2147483648:2281701375]	auto[0]	84	1			T4	1		T17	1		T22	1
auto[2147483648:2281701375]	auto[1]	6	1			T283	1		T409	1		T295	1
auto[2281701376:2415919103]	auto[0]	94	1			T1	1		T4	2		T15	1
auto[2281701376:2415919103]	auto[1]	11	1			T2	2		T307	1		T409	1
auto[2415919104:2550136831]	auto[0]	89	1			T12	1		T40	1		T41	1
auto[2415919104:2550136831]	auto[1]	12	1			T307	1		T283	1		T409	1
auto[2550136832:2684354559]	auto[0]	91	1			T13	1		T15	1		T22	1
auto[2550136832:2684354559]	auto[1]	10	1			T2	1		T419	1		T222	2
auto[2684354560:2818572287]	auto[0]	88	1			T14	1		T23	1		T189	1
auto[2684354560:2818572287]	auto[1]	5	1			T390	1		T222	1		T224	1
auto[2818572288:2952790015]	auto[0]	76	1			T1	1		T15	1		T25	1
auto[2818572288:2952790015]	auto[1]	14	1			T115	1		T230	1		T248	1
auto[2952790016:3087007743]	auto[0]	97	1			T4	1		T184	1		T58	1
auto[2952790016:3087007743]	auto[1]	9	1			T307	1		T250	1		T222	3
auto[3087007744:3221225471]	auto[0]	96	1			T4	1		T66	1		T82	1
auto[3087007744:3221225471]	auto[1]	5	1			T248	1		T276	1		T224	1
auto[3221225472:3355443199]	auto[0]	77	1			T4	2		T15	2		T63	1
auto[3221225472:3355443199]	auto[1]	5	1			T283	1		T253	1		T381	1
auto[3355443200:3489660927]	auto[0]	90	1			T2	1		T4	1		T15	1
auto[3355443200:3489660927]	auto[1]	12	1			T115	1		T390	1		T222	1
auto[3489660928:3623878655]	auto[0]	86	1			T12	1		T15	1		T22	1
auto[3489660928:3623878655]	auto[1]	12	1			T230	1		T307	1		T390	1
auto[3623878656:3758096383]	auto[0]	79	1			T4	1		T12	1		T41	1
auto[3623878656:3758096383]	auto[1]	12	1			T280	1		T307	1		T248	1
auto[3758096384:3892314111]	auto[0]	91	1			T1	2		T13	1		T79	1
auto[3758096384:3892314111]	auto[1]	8	1			T230	1		T250	1		T248	1
auto[3892314112:4026531839]	auto[0]	87	1			T1	1		T4	1		T13	1
auto[3892314112:4026531839]	auto[1]	10	1			T2	1		T248	1		T295	1
auto[4026531840:4160749567]	auto[0]	89	1			T40	1		T24	1		T136	1
auto[4026531840:4160749567]	auto[1]	8	1			T115	1		T280	1		T283	1
auto[4160749568:4294967295]	auto[0]	100	1			T4	1		T12	1		T45	1
auto[4160749568:4294967295]	auto[1]	5	1			T283	1		T222	1		T317	1