Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4242

1

T1

20

T4

36

T12

8

auto[1]

2178

1

T1

8

T2

8

T4

16

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	200	1			T4	4		T13	2		T15	2
auto[134217728:268435455]	232	1			T1	2		T2	2		T4	2
auto[268435456:402653183]	226	1			T4	4		T12	2		T41	2
auto[402653184:536870911]	196	1			T1	2		T23	2		T41	2
auto[536870912:671088639]	202	1			T1	4		T13	2		T42	4
auto[671088640:805306367]	232	1			T12	2		T45	2		T22	4
auto[805306368:939524095]	224	1			T12	2		T17	2		T22	2
auto[939524096:1073741823]	176	1			T1	4		T23	2		T189	2
auto[1073741824:1207959551]	188	1			T4	2		T127	2		T41	4
auto[1207959552:1342177279]	184	1			T4	2		T41	4		T227	4
auto[1342177280:1476395007]	207	1			T4	2		T23	2		T127	2
auto[1476395008:1610612735]	166	1			T2	2		T4	2		T15	2
auto[1610612736:1744830463]	220	1			T4	2		T17	2		T41	4
auto[1744830464:1879048191]	204	1			T4	2		T13	2		T17	2
auto[1879048192:2013265919]	240	1			T13	2		T15	4		T184	2
auto[2013265920:2147483647]	194	1			T1	2		T4	2		T45	2
auto[2147483648:2281701375]	216	1			T1	2		T79	2		T22	2
auto[2281701376:2415919103]	198	1			T1	2		T4	4		T13	2
auto[2415919104:2550136831]	192	1			T79	2		T46	2		T41	2
auto[2550136832:2684354559]	176	1			T4	2		T40	2		T22	2
auto[2684354560:2818572287]	186	1			T1	2		T15	4		T22	2
auto[2818572288:2952790015]	168	1			T1	2		T17	2		T22	4
auto[2952790016:3087007743]	162	1			T196	2		T58	2		T42	4
auto[3087007744:3221225471]	194	1			T1	2		T4	2		T12	2
auto[3221225472:3355443199]	190	1			T184	2		T183	2		T42	6
auto[3355443200:3489660927]	224	1			T2	2		T15	4		T41	4
auto[3489660928:3623878655]	206	1			T4	4		T41	2		T58	2
auto[3623878656:3758096383]	214	1			T1	2		T4	2		T40	2
auto[3758096384:3892314111]	181	1			T4	2		T12	2		T13	2
auto[3892314112:4026531839]	234	1			T1	2		T4	2		T15	2
auto[4026531840:4160749567]	214	1			T4	8		T13	2		T41	6
auto[4160749568:4294967295]	174	1			T2	2		T4	2		T226	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	126	1			T13	2		T15	2		T59	2
auto[0:134217727]	auto[1]	74	1			T4	4		T91	2		T101	2
auto[134217728:268435455]	auto[0]	152	1			T1	2		T4	2		T40	2
auto[134217728:268435455]	auto[1]	80	1			T2	2		T14	2		T15	2
auto[268435456:402653183]	auto[0]	168	1			T4	4		T41	2		T42	2
auto[268435456:402653183]	auto[1]	58	1			T12	2		T91	2		T199	4
auto[402653184:536870911]	auto[0]	130	1			T23	2		T41	2		T59	2
auto[402653184:536870911]	auto[1]	66	1			T1	2		T82	2		T59	2
auto[536870912:671088639]	auto[0]	140	1			T1	2		T13	2		T42	4
auto[536870912:671088639]	auto[1]	62	1			T1	2		T5	2		T199	2
auto[671088640:805306367]	auto[0]	150	1			T12	2		T46	2		T41	2
auto[671088640:805306367]	auto[1]	82	1			T45	2		T22	4		T41	2
auto[805306368:939524095]	auto[0]	152	1			T12	2		T22	2		T42	6
auto[805306368:939524095]	auto[1]	72	1			T17	2		T41	2		T269	2
auto[939524096:1073741823]	auto[0]	120	1			T1	4		T189	2		T42	2
auto[939524096:1073741823]	auto[1]	56	1			T23	2		T206	4		T367	2
auto[1073741824:1207959551]	auto[0]	130	1			T4	2		T196	2		T50	6
auto[1073741824:1207959551]	auto[1]	58	1			T127	2		T41	4		T254	2
auto[1207959552:1342177279]	auto[0]	124	1			T4	2		T41	2		T227	4
auto[1207959552:1342177279]	auto[1]	60	1			T41	2		T59	2		T177	2
auto[1342177280:1476395007]	auto[0]	128	1			T4	2		T23	2		T46	2
auto[1342177280:1476395007]	auto[1]	79	1			T127	2		T42	2		T50	2
auto[1476395008:1610612735]	auto[0]	104	1			T4	2		T15	2		T79	2
auto[1476395008:1610612735]	auto[1]	62	1			T2	2		T66	2		T105	2
auto[1610612736:1744830463]	auto[0]	140	1			T4	2		T58	2		T42	2
auto[1610612736:1744830463]	auto[1]	80	1			T17	2		T41	4		T42	6
auto[1744830464:1879048191]	auto[0]	120	1			T13	2		T22	2		T243	2
auto[1744830464:1879048191]	auto[1]	84	1			T4	2		T17	2		T25	2
auto[1879048192:2013265919]	auto[0]	154	1			T13	2		T15	2		T196	2
auto[1879048192:2013265919]	auto[1]	86	1			T15	2		T184	2		T27	2
auto[2013265920:2147483647]	auto[0]	126	1			T1	2		T115	2		T41	4
auto[2013265920:2147483647]	auto[1]	68	1			T4	2		T45	2		T42	2
auto[2147483648:2281701375]	auto[0]	146	1			T1	2		T79	2		T22	2
auto[2147483648:2281701375]	auto[1]	70	1			T25	2		T41	4		T50	2
auto[2281701376:2415919103]	auto[0]	122	1			T4	2		T13	2		T17	2
auto[2281701376:2415919103]	auto[1]	76	1			T1	2		T4	2		T45	2
auto[2415919104:2550136831]	auto[0]	130	1			T79	2		T41	2		T42	2
auto[2415919104:2550136831]	auto[1]	62	1			T46	2		T177	2		T254	2
auto[2550136832:2684354559]	auto[0]	114	1			T66	2		T82	2		T59	2
auto[2550136832:2684354559]	auto[1]	62	1			T4	2		T40	2		T22	2
auto[2684354560:2818572287]	auto[0]	132	1			T1	2		T15	4		T22	2
auto[2684354560:2818572287]	auto[1]	54	1			T59	2		T50	2		T61	2
auto[2818572288:2952790015]	auto[0]	98	1			T1	2		T17	2		T22	4
auto[2818572288:2952790015]	auto[1]	70	1			T115	2		T66	2		T42	2
auto[2952790016:3087007743]	auto[0]	106	1			T196	2		T84	2		T197	2
auto[2952790016:3087007743]	auto[1]	56	1			T58	2		T42	4		T50	2
auto[3087007744:3221225471]	auto[0]	128	1			T1	2		T4	2		T12	2
auto[3087007744:3221225471]	auto[1]	66	1			T422	2		T82	2		T300	2
auto[3221225472:3355443199]	auto[0]	120	1			T42	4		T177	2		T136	2
auto[3221225472:3355443199]	auto[1]	70	1			T184	2		T183	2		T42	2
auto[3355443200:3489660927]	auto[0]	144	1			T15	4		T41	2		T42	2
auto[3355443200:3489660927]	auto[1]	80	1			T2	2		T41	2		T5	2
auto[3489660928:3623878655]	auto[0]	136	1			T4	2		T41	2		T58	2
auto[3489660928:3623878655]	auto[1]	70	1			T4	2		T382	2		T421	2
auto[3623878656:3758096383]	auto[0]	156	1			T1	2		T4	2		T40	2
auto[3623878656:3758096383]	auto[1]	58	1			T420	2		T59	2		T400	2
auto[3758096384:3892314111]	auto[0]	124	1			T4	2		T12	2		T13	2
auto[3758096384:3892314111]	auto[1]	57	1			T50	2		T173	2		T203	3
auto[3892314112:4026531839]	auto[0]	172	1			T4	2		T15	2		T41	2
auto[3892314112:4026531839]	auto[1]	62	1			T1	2		T34	2		T42	2
auto[4026531840:4160749567]	auto[0]	124	1			T4	8		T13	2		T41	4
auto[4026531840:4160749567]	auto[1]	90	1			T41	2		T50	2		T230	2
auto[4160749568:4294967295]	auto[0]	126	1			T41	4		T59	2		T50	4
auto[4160749568:4294967295]	auto[1]	48	1			T2	2		T4	2		T226	2