Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.85 99.10 98.07 98.52 100.00 99.19 98.41 91.68


Total test records in report: 1076
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T1009 /workspace/coverage/default/28.keymgr_sideload_protect.1252819901 Feb 01 03:54:07 PM PST 24 Feb 01 03:54:14 PM PST 24 88299142 ps
T1010 /workspace/coverage/default/44.keymgr_kmac_rsp_err.2595679169 Feb 01 03:55:14 PM PST 24 Feb 01 03:55:34 PM PST 24 2646725043 ps
T1011 /workspace/coverage/default/11.keymgr_direct_to_disabled.795732721 Feb 01 03:47:29 PM PST 24 Feb 01 03:48:14 PM PST 24 98713406 ps
T392 /workspace/coverage/default/32.keymgr_kmac_rsp_err.1759752242 Feb 01 03:54:40 PM PST 24 Feb 01 03:54:50 PM PST 24 307944721 ps
T1012 /workspace/coverage/default/5.keymgr_sideload_otbn.1482438052 Feb 01 03:45:05 PM PST 24 Feb 01 03:45:40 PM PST 24 243561878 ps
T1013 /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1830153853 Feb 01 03:53:36 PM PST 24 Feb 01 03:54:07 PM PST 24 6721932380 ps
T1014 /workspace/coverage/default/17.keymgr_random.871539733 Feb 01 03:47:19 PM PST 24 Feb 01 03:48:01 PM PST 24 124499534 ps
T1015 /workspace/coverage/default/11.keymgr_kmac_rsp_err.2802965030 Feb 01 03:46:55 PM PST 24 Feb 01 03:48:26 PM PST 24 1727618029 ps
T1016 /workspace/coverage/default/29.keymgr_sideload_otbn.2640755444 Feb 01 03:53:37 PM PST 24 Feb 01 03:53:52 PM PST 24 544570977 ps
T1017 /workspace/coverage/default/35.keymgr_sideload_otbn.3070690753 Feb 01 03:54:01 PM PST 24 Feb 01 03:54:09 PM PST 24 264461442 ps
T1018 /workspace/coverage/default/28.keymgr_direct_to_disabled.2906582634 Feb 01 03:54:56 PM PST 24 Feb 01 03:55:05 PM PST 24 49363401 ps
T1019 /workspace/coverage/default/49.keymgr_sideload_protect.4100615966 Feb 01 03:55:13 PM PST 24 Feb 01 03:55:26 PM PST 24 192702267 ps
T1020 /workspace/coverage/default/22.keymgr_hwsw_invalid_input.642708710 Feb 01 03:48:11 PM PST 24 Feb 01 03:49:10 PM PST 24 118308804 ps
T1021 /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1952271181 Feb 01 03:47:44 PM PST 24 Feb 01 03:48:38 PM PST 24 48379392 ps
T1022 /workspace/coverage/default/9.keymgr_sideload_aes.3495604193 Feb 01 03:45:48 PM PST 24 Feb 01 03:47:10 PM PST 24 6779987276 ps
T1023 /workspace/coverage/default/48.keymgr_alert_test.1496885136 Feb 01 03:55:35 PM PST 24 Feb 01 03:55:44 PM PST 24 16347115 ps
T1024 /workspace/coverage/default/35.keymgr_cfg_regwen.3940470814 Feb 01 03:54:19 PM PST 24 Feb 01 03:54:26 PM PST 24 71881276 ps
T1025 /workspace/coverage/default/36.keymgr_smoke.1036690773 Feb 01 03:54:56 PM PST 24 Feb 01 03:55:07 PM PST 24 250588429 ps
T1026 /workspace/coverage/default/41.keymgr_sideload_protect.2650765969 Feb 01 03:56:13 PM PST 24 Feb 01 03:56:30 PM PST 24 3530714403 ps
T1027 /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.882263895 Feb 01 03:52:17 PM PST 24 Feb 01 03:52:35 PM PST 24 491978191 ps
T1028 /workspace/coverage/default/8.keymgr_sideload.1974478262 Feb 01 03:45:50 PM PST 24 Feb 01 03:46:48 PM PST 24 254763352 ps
T1029 /workspace/coverage/default/27.keymgr_cfg_regwen.1044422678 Feb 01 03:53:44 PM PST 24 Feb 01 03:53:56 PM PST 24 41630231 ps
T1030 /workspace/coverage/default/4.keymgr_alert_test.3067350291 Feb 01 03:45:10 PM PST 24 Feb 01 03:45:45 PM PST 24 17698472 ps
T1031 /workspace/coverage/default/10.keymgr_sideload.1955528496 Feb 01 03:46:10 PM PST 24 Feb 01 03:47:49 PM PST 24 2658761395 ps
T141 /workspace/coverage/default/6.keymgr_custom_cm.2867949175 Feb 01 03:45:39 PM PST 24 Feb 01 03:46:34 PM PST 24 94215759 ps
T341 /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1747919839 Feb 01 03:47:59 PM PST 24 Feb 01 03:49:59 PM PST 24 19907213393 ps
T1032 /workspace/coverage/default/49.keymgr_sideload.1482125097 Feb 01 03:54:15 PM PST 24 Feb 01 03:54:24 PM PST 24 128540041 ps
T1033 /workspace/coverage/default/37.keymgr_alert_test.2667137247 Feb 01 03:54:56 PM PST 24 Feb 01 03:55:04 PM PST 24 17081622 ps
T1034 /workspace/coverage/default/48.keymgr_direct_to_disabled.946367380 Feb 01 03:55:14 PM PST 24 Feb 01 03:55:26 PM PST 24 135163630 ps
T1035 /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3237364835 Feb 01 03:55:13 PM PST 24 Feb 01 03:55:26 PM PST 24 527637224 ps
T217 /workspace/coverage/default/7.keymgr_stress_all.3579927804 Feb 01 03:47:48 PM PST 24 Feb 01 03:49:03 PM PST 24 5666119011 ps
T1036 /workspace/coverage/default/29.keymgr_sideload.2137701104 Feb 01 03:50:35 PM PST 24 Feb 01 03:51:38 PM PST 24 533823343 ps
T1037 /workspace/coverage/default/3.keymgr_sideload_aes.3250928000 Feb 01 03:44:54 PM PST 24 Feb 01 03:45:24 PM PST 24 151831341 ps
T1038 /workspace/coverage/default/13.keymgr_sideload.502490278 Feb 01 03:47:25 PM PST 24 Feb 01 03:48:09 PM PST 24 121704117 ps
T1039 /workspace/coverage/default/38.keymgr_sideload_protect.1711173579 Feb 01 03:54:58 PM PST 24 Feb 01 03:55:08 PM PST 24 32105970 ps
T1040 /workspace/coverage/default/6.keymgr_random.1743601878 Feb 01 03:47:28 PM PST 24 Feb 01 03:48:22 PM PST 24 432656764 ps
T1041 /workspace/coverage/default/20.keymgr_sw_invalid_input.2016871361 Feb 01 03:47:48 PM PST 24 Feb 01 03:49:24 PM PST 24 2450134447 ps
T1042 /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2481598779 Feb 01 03:54:56 PM PST 24 Feb 01 03:55:07 PM PST 24 111081555 ps
T1043 /workspace/coverage/default/18.keymgr_sideload_protect.33831123 Feb 01 03:47:25 PM PST 24 Feb 01 03:48:11 PM PST 24 145116718 ps
T49 /workspace/coverage/default/30.keymgr_stress_all.2227153371 Feb 01 03:54:56 PM PST 24 Feb 01 03:55:46 PM PST 24 1969179166 ps
T1044 /workspace/coverage/default/18.keymgr_smoke.1229307457 Feb 01 03:48:29 PM PST 24 Feb 01 03:49:29 PM PST 24 3325008601 ps
T1045 /workspace/coverage/default/47.keymgr_sideload_kmac.2151123240 Feb 01 03:54:55 PM PST 24 Feb 01 03:55:06 PM PST 24 171975899 ps
T1046 /workspace/coverage/default/12.keymgr_lc_disable.1167120735 Feb 01 03:47:27 PM PST 24 Feb 01 03:48:11 PM PST 24 71089683 ps
T1047 /workspace/coverage/default/1.keymgr_sideload_otbn.3522713468 Feb 01 03:46:01 PM PST 24 Feb 01 03:47:03 PM PST 24 378376729 ps
T1048 /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3220779077 Feb 01 03:48:42 PM PST 24 Feb 01 03:49:35 PM PST 24 46170626 ps
T343 /workspace/coverage/default/36.keymgr_hwsw_invalid_input.654268777 Feb 01 03:53:38 PM PST 24 Feb 01 03:53:53 PM PST 24 42995220 ps
T1049 /workspace/coverage/default/16.keymgr_custom_cm.367045187 Feb 01 03:47:23 PM PST 24 Feb 01 03:48:07 PM PST 24 352030796 ps
T1050 /workspace/coverage/default/2.keymgr_direct_to_disabled.1198631736 Feb 01 03:44:30 PM PST 24 Feb 01 03:45:02 PM PST 24 726198434 ps
T1051 /workspace/coverage/default/1.keymgr_sideload_aes.3715455841 Feb 01 03:44:23 PM PST 24 Feb 01 03:44:55 PM PST 24 86829123 ps
T1052 /workspace/coverage/default/28.keymgr_sideload_otbn.1306607325 Feb 01 03:51:17 PM PST 24 Feb 01 03:52:29 PM PST 24 2838526886 ps
T1053 /workspace/coverage/default/28.keymgr_sw_invalid_input.938014014 Feb 01 03:54:56 PM PST 24 Feb 01 03:55:06 PM PST 24 80151241 ps
T314 /workspace/coverage/default/8.keymgr_stress_all.4169178805 Feb 01 03:45:35 PM PST 24 Feb 01 03:47:23 PM PST 24 15571553309 ps
T432 /workspace/coverage/default/2.keymgr_cfg_regwen.2649302226 Feb 01 03:45:52 PM PST 24 Feb 01 03:47:02 PM PST 24 949377918 ps
T1054 /workspace/coverage/default/18.keymgr_hwsw_invalid_input.767740687 Feb 01 03:47:46 PM PST 24 Feb 01 03:48:42 PM PST 24 417041863 ps
T1055 /workspace/coverage/default/26.keymgr_sideload_protect.4232412456 Feb 01 03:49:01 PM PST 24 Feb 01 03:50:14 PM PST 24 37896236 ps
T1056 /workspace/coverage/default/10.keymgr_smoke.763178475 Feb 01 03:45:52 PM PST 24 Feb 01 03:46:49 PM PST 24 20909276 ps
T1057 /workspace/coverage/default/30.keymgr_sideload_otbn.482011724 Feb 01 03:49:39 PM PST 24 Feb 01 03:50:54 PM PST 24 23941019 ps
T1058 /workspace/coverage/default/29.keymgr_custom_cm.3483517468 Feb 01 03:54:56 PM PST 24 Feb 01 03:55:11 PM PST 24 199938928 ps
T1059 /workspace/coverage/default/47.keymgr_alert_test.653983499 Feb 01 03:55:09 PM PST 24 Feb 01 03:55:17 PM PST 24 61006706 ps
T1060 /workspace/coverage/default/32.keymgr_lc_disable.3660198452 Feb 01 03:56:10 PM PST 24 Feb 01 03:56:15 PM PST 24 326934445 ps
T1061 /workspace/coverage/default/25.keymgr_cfg_regwen.4087109548 Feb 01 03:49:12 PM PST 24 Feb 01 03:50:34 PM PST 24 79283794 ps
T1062 /workspace/coverage/default/21.keymgr_sw_invalid_input.3941942961 Feb 01 03:47:55 PM PST 24 Feb 01 03:48:56 PM PST 24 209155425 ps
T1063 /workspace/coverage/default/6.keymgr_sideload.887347109 Feb 01 03:45:35 PM PST 24 Feb 01 03:46:31 PM PST 24 1072935253 ps
T1064 /workspace/coverage/default/1.keymgr_alert_test.3282094410 Feb 01 03:44:38 PM PST 24 Feb 01 03:45:08 PM PST 24 16061637 ps
T1065 /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3313525521 Feb 01 03:56:03 PM PST 24 Feb 01 03:56:09 PM PST 24 85312519 ps
T1066 /workspace/coverage/default/12.keymgr_sideload_protect.3479585650 Feb 01 03:46:53 PM PST 24 Feb 01 03:47:44 PM PST 24 212884275 ps
T1067 /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2487970869 Feb 01 03:47:46 PM PST 24 Feb 01 03:48:42 PM PST 24 512283953 ps
T1068 /workspace/coverage/default/17.keymgr_sideload.3534428555 Feb 01 03:48:29 PM PST 24 Feb 01 03:49:23 PM PST 24 907352484 ps
T1069 /workspace/coverage/default/41.keymgr_sideload.937657139 Feb 01 03:54:32 PM PST 24 Feb 01 03:54:44 PM PST 24 971414744 ps
T1070 /workspace/coverage/default/46.keymgr_lc_disable.721832062 Feb 01 03:55:15 PM PST 24 Feb 01 03:55:29 PM PST 24 83841760 ps
T1071 /workspace/coverage/default/10.keymgr_sw_invalid_input.3066003964 Feb 01 03:48:42 PM PST 24 Feb 01 03:49:35 PM PST 24 176254486 ps
T1072 /workspace/coverage/default/29.keymgr_sideload_kmac.3435799448 Feb 01 03:49:40 PM PST 24 Feb 01 03:51:00 PM PST 24 168836323 ps
T1073 /workspace/coverage/default/15.keymgr_smoke.3637942232 Feb 01 03:49:05 PM PST 24 Feb 01 03:50:23 PM PST 24 31517635 ps
T1074 /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.892085940 Feb 01 03:49:02 PM PST 24 Feb 01 03:50:23 PM PST 24 792053222 ps
T1075 /workspace/coverage/default/4.keymgr_custom_cm.3013177394 Feb 01 03:45:05 PM PST 24 Feb 01 03:45:41 PM PST 24 486189510 ps
T1076 /workspace/coverage/default/20.keymgr_direct_to_disabled.3776265855 Feb 01 03:52:47 PM PST 24 Feb 01 03:52:56 PM PST 24 219049452 ps

Test location /workspace/coverage/default/4.keymgr_stress_all.4258858714
Short name T4
Test name
Test status
Simulation time 2365496835 ps
CPU time 37.71 seconds
Started Feb 01 03:45:06 PM PST 24
Finished Feb 01 03:46:17 PM PST 24
Peak memory 216592 kb
Host smart-f4636087-d484-4f53-84ae-beaa70e6e1be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258858714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.4258858714
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3514026309
Short name T42
Test name
Test status
Simulation time 114557239128 ps
CPU time 398.79 seconds
Started Feb 01 03:49:41 PM PST 24
Finished Feb 01 03:57:35 PM PST 24
Peak memory 221760 kb
Host smart-f97015ea-a0d1-4aec-b2ff-9ce069b414b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514026309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3514026309
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2644139358
Short name T6
Test name
Test status
Simulation time 445242399 ps
CPU time 7.34 seconds
Started Feb 01 03:45:25 PM PST 24
Finished Feb 01 03:46:15 PM PST 24
Peak memory 230896 kb
Host smart-675b59a3-3faf-4854-8648-52bc0092810d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644139358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2644139358
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.4216327742
Short name T105
Test name
Test status
Simulation time 311430821 ps
CPU time 4.11 seconds
Started Feb 01 03:48:02 PM PST 24
Finished Feb 01 03:49:02 PM PST 24
Peak memory 222476 kb
Host smart-797961ef-02ed-455e-a2da-f8670b1d21a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216327742 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.4216327742
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1120549527
Short name T41
Test name
Test status
Simulation time 921105168 ps
CPU time 36.42 seconds
Started Feb 01 03:46:45 PM PST 24
Finished Feb 01 03:48:09 PM PST 24
Peak memory 220332 kb
Host smart-19245922-8809-4e21-8a98-c683142f7e66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120549527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1120549527
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3232587070
Short name T56
Test name
Test status
Simulation time 1204499462 ps
CPU time 43.64 seconds
Started Feb 01 03:53:52 PM PST 24
Finished Feb 01 03:54:42 PM PST 24
Peak memory 222192 kb
Host smart-9a715d0a-786f-4cf6-be9e-5f2798baa7f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232587070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3232587070
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2714336158
Short name T109
Test name
Test status
Simulation time 360991979 ps
CPU time 4.28 seconds
Started Feb 01 12:38:35 PM PST 24
Finished Feb 01 12:39:39 PM PST 24
Peak memory 213572 kb
Host smart-b57c9acc-e37b-44a0-9ff6-70cc49bd5759
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714336158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2714336158
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.87547923
Short name T35
Test name
Test status
Simulation time 324652376 ps
CPU time 1.99 seconds
Started Feb 01 03:45:56 PM PST 24
Finished Feb 01 03:46:55 PM PST 24
Peak memory 210040 kb
Host smart-80acb180-ab38-42da-930f-c2135f5d2be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87547923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.87547923
Directory /workspace/9.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3596268361
Short name T2
Test name
Test status
Simulation time 585010228 ps
CPU time 8.19 seconds
Started Feb 01 03:45:05 PM PST 24
Finished Feb 01 03:45:44 PM PST 24
Peak memory 214276 kb
Host smart-99bf5a61-7ae3-41b6-962c-6b4849f82a1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3596268361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3596268361
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2897601731
Short name T8
Test name
Test status
Simulation time 394973625 ps
CPU time 3.76 seconds
Started Feb 01 03:52:46 PM PST 24
Finished Feb 01 03:52:52 PM PST 24
Peak memory 215780 kb
Host smart-a1a38faf-ae4c-4364-b9e5-b4bff1471e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897601731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2897601731
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.4268099335
Short name T22
Test name
Test status
Simulation time 51823200 ps
CPU time 3.24 seconds
Started Feb 01 03:47:43 PM PST 24
Finished Feb 01 03:48:37 PM PST 24
Peak memory 222220 kb
Host smart-4f52f6f8-95fa-4a70-9627-8d4ff1e9162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268099335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.4268099335
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2227153371
Short name T49
Test name
Test status
Simulation time 1969179166 ps
CPU time 42.99 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:46 PM PST 24
Peak memory 220884 kb
Host smart-d6b2e202-6272-4158-926a-8baae969d94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227153371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2227153371
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.373360098
Short name T317
Test name
Test status
Simulation time 757080968 ps
CPU time 38.35 seconds
Started Feb 01 03:53:29 PM PST 24
Finished Feb 01 03:54:22 PM PST 24
Peak memory 214844 kb
Host smart-0ee50ef3-f312-454b-b4c1-4bca2805eeed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373360098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.373360098
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2923221566
Short name T50
Test name
Test status
Simulation time 1732923476 ps
CPU time 40.22 seconds
Started Feb 01 03:47:28 PM PST 24
Finished Feb 01 03:48:52 PM PST 24
Peak memory 221828 kb
Host smart-ce4084a9-c95c-4d56-8bc5-6fa913afb076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923221566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2923221566
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3146378442
Short name T409
Test name
Test status
Simulation time 1820607740 ps
CPU time 44.04 seconds
Started Feb 01 03:56:10 PM PST 24
Finished Feb 01 03:56:58 PM PST 24
Peak memory 213868 kb
Host smart-8b244812-dd2e-42d3-90fe-65b641350f5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146378442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3146378442
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.388577985
Short name T209
Test name
Test status
Simulation time 23265912315 ps
CPU time 661.09 seconds
Started Feb 01 03:52:07 PM PST 24
Finished Feb 01 04:03:23 PM PST 24
Peak memory 230636 kb
Host smart-1f2cff75-32b2-4697-adae-51f5946f41ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388577985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.388577985
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2589482848
Short name T59
Test name
Test status
Simulation time 911249340 ps
CPU time 34.05 seconds
Started Feb 01 03:53:49 PM PST 24
Finished Feb 01 03:54:30 PM PST 24
Peak memory 215064 kb
Host smart-adbe8efc-cfa6-470f-a76c-94581508bf1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589482848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2589482848
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1628678377
Short name T89
Test name
Test status
Simulation time 1489309396 ps
CPU time 43.8 seconds
Started Feb 01 03:46:32 PM PST 24
Finished Feb 01 03:48:07 PM PST 24
Peak memory 219560 kb
Host smart-da2d359a-03f5-47f0-a5e4-4a054dfb2a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628678377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1628678377
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.130805655
Short name T222
Test name
Test status
Simulation time 214098236 ps
CPU time 12.02 seconds
Started Feb 01 03:45:42 PM PST 24
Finished Feb 01 03:46:46 PM PST 24
Peak memory 222348 kb
Host smart-36a3afa9-6c75-4619-b417-7f230ff00bc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130805655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.130805655
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3570919894
Short name T125
Test name
Test status
Simulation time 222718359 ps
CPU time 2.93 seconds
Started Feb 01 12:38:35 PM PST 24
Finished Feb 01 12:39:37 PM PST 24
Peak memory 213412 kb
Host smart-32bf1287-48de-4f13-87c4-6d45a2fb2229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570919894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3570919894
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.739715481
Short name T248
Test name
Test status
Simulation time 456256997 ps
CPU time 12.39 seconds
Started Feb 01 03:47:06 PM PST 24
Finished Feb 01 03:47:59 PM PST 24
Peak memory 214188 kb
Host smart-9a15f418-8e71-480f-b59d-0df391f8b400
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739715481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.739715481
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3166868999
Short name T83
Test name
Test status
Simulation time 540160668 ps
CPU time 5.59 seconds
Started Feb 01 03:47:13 PM PST 24
Finished Feb 01 03:47:58 PM PST 24
Peak memory 214092 kb
Host smart-a1ff3aa9-1b3b-4038-bbd9-38e656e72495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166868999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3166868999
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3084914748
Short name T36
Test name
Test status
Simulation time 654200174 ps
CPU time 3.97 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:07 PM PST 24
Peak memory 209420 kb
Host smart-8b5aa13f-2383-42dc-aa3f-b8870ea425c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084914748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3084914748
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2649302226
Short name T432
Test name
Test status
Simulation time 949377918 ps
CPU time 13.31 seconds
Started Feb 01 03:45:52 PM PST 24
Finished Feb 01 03:47:02 PM PST 24
Peak memory 215040 kb
Host smart-0c710e81-7578-41b6-8977-f88d82ac3983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649302226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2649302226
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.553639682
Short name T206
Test name
Test status
Simulation time 1259665371 ps
CPU time 32.43 seconds
Started Feb 01 03:44:20 PM PST 24
Finished Feb 01 03:45:25 PM PST 24
Peak memory 215084 kb
Host smart-c1b382a2-6ae2-4455-a1eb-312026ebd7a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553639682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.553639682
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3116945167
Short name T29
Test name
Test status
Simulation time 166764097 ps
CPU time 1.9 seconds
Started Feb 01 03:47:44 PM PST 24
Finished Feb 01 03:48:37 PM PST 24
Peak memory 215108 kb
Host smart-63e4ad2b-289c-472e-b54d-c0e9b65b1224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116945167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3116945167
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2398907336
Short name T88
Test name
Test status
Simulation time 654463519 ps
CPU time 2.87 seconds
Started Feb 01 03:53:34 PM PST 24
Finished Feb 01 03:53:52 PM PST 24
Peak memory 214124 kb
Host smart-ea1e033c-f09b-4920-bb9f-9f2330995e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398907336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2398907336
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4054467820
Short name T119
Test name
Test status
Simulation time 216812033 ps
CPU time 8.66 seconds
Started Feb 01 12:38:37 PM PST 24
Finished Feb 01 12:39:45 PM PST 24
Peak memory 213512 kb
Host smart-449ba3ce-5d81-41d8-9de9-90fa6730ac31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054467820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4054467820
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1411570928
Short name T297
Test name
Test status
Simulation time 87466481 ps
CPU time 4.3 seconds
Started Feb 01 03:48:42 PM PST 24
Finished Feb 01 03:49:38 PM PST 24
Peak memory 213980 kb
Host smart-761a14e9-ceca-4e60-83d2-f4811daf4dac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411570928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1411570928
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1158068069
Short name T60
Test name
Test status
Simulation time 1394387579 ps
CPU time 14.05 seconds
Started Feb 01 03:55:15 PM PST 24
Finished Feb 01 03:55:39 PM PST 24
Peak memory 222360 kb
Host smart-ca743924-95e0-47f3-ae65-1567ef2a6e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158068069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1158068069
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2729934856
Short name T137
Test name
Test status
Simulation time 91046554 ps
CPU time 4.18 seconds
Started Feb 01 03:56:03 PM PST 24
Finished Feb 01 03:56:10 PM PST 24
Peak memory 216548 kb
Host smart-9154d524-0918-47a0-9490-f07f4f9f9fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729934856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2729934856
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.965720211
Short name T336
Test name
Test status
Simulation time 511923079 ps
CPU time 9.71 seconds
Started Feb 01 03:44:24 PM PST 24
Finished Feb 01 03:45:03 PM PST 24
Peak memory 222412 kb
Host smart-f6dd94fc-ef39-43e7-b4fc-762715d05145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965720211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.965720211
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2515978144
Short name T489
Test name
Test status
Simulation time 193273668 ps
CPU time 2.46 seconds
Started Feb 01 12:38:46 PM PST 24
Finished Feb 01 12:39:47 PM PST 24
Peak memory 213180 kb
Host smart-9e594508-9281-4844-9a57-f715b24706b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515978144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2515978144
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2155809515
Short name T21
Test name
Test status
Simulation time 82084292 ps
CPU time 1.94 seconds
Started Feb 01 03:47:14 PM PST 24
Finished Feb 01 03:47:55 PM PST 24
Peak memory 207716 kb
Host smart-362281af-a913-46b2-98c1-91dd7f980a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155809515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2155809515
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1618263467
Short name T452
Test name
Test status
Simulation time 723837647 ps
CPU time 9.77 seconds
Started Feb 01 12:38:16 PM PST 24
Finished Feb 01 12:39:30 PM PST 24
Peak memory 212796 kb
Host smart-0e946fba-559c-4119-8b26-5c8a8256bbba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618263467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1618263467
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2879269187
Short name T264
Test name
Test status
Simulation time 175722115 ps
CPU time 6.53 seconds
Started Feb 01 03:47:37 PM PST 24
Finished Feb 01 03:48:31 PM PST 24
Peak memory 214188 kb
Host smart-56d4d49f-b0fa-44fd-8371-8a0499a8c0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879269187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2879269187
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.857058491
Short name T1
Test name
Test status
Simulation time 2008368122 ps
CPU time 19.41 seconds
Started Feb 01 03:48:11 PM PST 24
Finished Feb 01 03:49:25 PM PST 24
Peak memory 222380 kb
Host smart-ad0207e5-7ed0-4f8a-8670-d164209b51ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857058491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.857058491
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1431288589
Short name T437
Test name
Test status
Simulation time 11853664 ps
CPU time 0.76 seconds
Started Feb 01 03:44:24 PM PST 24
Finished Feb 01 03:44:54 PM PST 24
Peak memory 205796 kb
Host smart-8524b65b-6157-4c62-90cf-eb8046ad3bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431288589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1431288589
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1489378592
Short name T253
Test name
Test status
Simulation time 188415589 ps
CPU time 5.42 seconds
Started Feb 01 03:55:03 PM PST 24
Finished Feb 01 03:55:16 PM PST 24
Peak memory 214200 kb
Host smart-d6d7c7e1-899b-4864-8ef1-1316efff5dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489378592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1489378592
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2814034844
Short name T241
Test name
Test status
Simulation time 1123070709 ps
CPU time 33.52 seconds
Started Feb 01 03:51:17 PM PST 24
Finished Feb 01 03:52:30 PM PST 24
Peak memory 219756 kb
Host smart-3382982c-2eaa-41d3-8c0d-c5f92bdb41ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814034844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2814034844
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3938947080
Short name T339
Test name
Test status
Simulation time 4536452730 ps
CPU time 105.32 seconds
Started Feb 01 03:46:03 PM PST 24
Finished Feb 01 03:48:47 PM PST 24
Peak memory 222448 kb
Host smart-3c6716f3-e74b-492b-85d9-29c5b6945384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938947080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3938947080
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1891091386
Short name T34
Test name
Test status
Simulation time 292386553 ps
CPU time 9 seconds
Started Feb 01 03:50:01 PM PST 24
Finished Feb 01 03:51:15 PM PST 24
Peak memory 209500 kb
Host smart-9626fcba-121c-4f2b-81fe-300d2369a116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891091386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1891091386
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1683062656
Short name T126
Test name
Test status
Simulation time 578603141 ps
CPU time 5.58 seconds
Started Feb 01 12:38:44 PM PST 24
Finished Feb 01 12:39:46 PM PST 24
Peak memory 208420 kb
Host smart-d852283c-5f04-40c9-99cc-5f23086bfcf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683062656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1683062656
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.837482155
Short name T150
Test name
Test status
Simulation time 250884916 ps
CPU time 9.04 seconds
Started Feb 01 12:39:03 PM PST 24
Finished Feb 01 12:40:08 PM PST 24
Peak memory 213360 kb
Host smart-ddf256de-b584-42f8-8f6e-0482327a0e25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837482155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.837482155
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2643539623
Short name T139
Test name
Test status
Simulation time 196366768 ps
CPU time 2.78 seconds
Started Feb 01 03:48:17 PM PST 24
Finished Feb 01 03:49:13 PM PST 24
Peak memory 217368 kb
Host smart-66f331f9-c708-4273-af10-3de715bb14f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643539623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2643539623
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2577538387
Short name T91
Test name
Test status
Simulation time 334299916 ps
CPU time 9.78 seconds
Started Feb 01 03:48:29 PM PST 24
Finished Feb 01 03:49:28 PM PST 24
Peak memory 222328 kb
Host smart-746df8bd-ea8f-49d0-9f8f-f794bc4453bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577538387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2577538387
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3258136523
Short name T33
Test name
Test status
Simulation time 119535801 ps
CPU time 4.91 seconds
Started Feb 01 03:54:35 PM PST 24
Finished Feb 01 03:54:44 PM PST 24
Peak memory 221632 kb
Host smart-bd10f624-1f84-4628-801c-b4f6de33d927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258136523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3258136523
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1732269894
Short name T414
Test name
Test status
Simulation time 85491665 ps
CPU time 5.32 seconds
Started Feb 01 03:54:53 PM PST 24
Finished Feb 01 03:55:01 PM PST 24
Peak memory 214612 kb
Host smart-88c28867-eb86-4455-a0d7-03f71970dc1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732269894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1732269894
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.4156328090
Short name T262
Test name
Test status
Simulation time 137970237 ps
CPU time 6.01 seconds
Started Feb 01 03:45:09 PM PST 24
Finished Feb 01 03:45:49 PM PST 24
Peak memory 222328 kb
Host smart-a17c276a-57cf-4a89-8dd0-22831c6a28c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156328090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.4156328090
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1129037416
Short name T376
Test name
Test status
Simulation time 2624289129 ps
CPU time 58.83 seconds
Started Feb 01 03:56:12 PM PST 24
Finished Feb 01 03:57:18 PM PST 24
Peak memory 221664 kb
Host smart-7a6687a9-84d3-49ef-a17a-bd4fd57e99ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129037416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1129037416
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.210512266
Short name T108
Test name
Test status
Simulation time 217711082 ps
CPU time 4.58 seconds
Started Feb 01 12:38:47 PM PST 24
Finished Feb 01 12:39:49 PM PST 24
Peak memory 208440 kb
Host smart-89c9643f-c8d7-4dfd-8187-7a7a34478bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210512266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
210512266
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2867949175
Short name T141
Test name
Test status
Simulation time 94215759 ps
CPU time 2.1 seconds
Started Feb 01 03:45:39 PM PST 24
Finished Feb 01 03:46:34 PM PST 24
Peak memory 217724 kb
Host smart-5e2014dc-341f-4e3d-bf82-503905af1120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867949175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2867949175
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1079970025
Short name T140
Test name
Test status
Simulation time 55142752 ps
CPU time 3.47 seconds
Started Feb 01 03:44:30 PM PST 24
Finished Feb 01 03:45:04 PM PST 24
Peak memory 222572 kb
Host smart-37840c0c-aa61-45f0-97b0-a1f0417a451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079970025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1079970025
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3100466828
Short name T237
Test name
Test status
Simulation time 38682407 ps
CPU time 2.66 seconds
Started Feb 01 03:44:22 PM PST 24
Finished Feb 01 03:44:56 PM PST 24
Peak memory 208532 kb
Host smart-9e816ce2-3b8c-4a99-a882-646f505d0356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100466828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3100466828
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2404171021
Short name T415
Test name
Test status
Simulation time 4401152748 ps
CPU time 52.46 seconds
Started Feb 01 03:48:39 PM PST 24
Finished Feb 01 03:50:23 PM PST 24
Peak memory 215412 kb
Host smart-ba2a144a-062d-4dfe-a14b-8648453976a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404171021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2404171021
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3551679621
Short name T216
Test name
Test status
Simulation time 4809867825 ps
CPU time 42.59 seconds
Started Feb 01 03:48:34 PM PST 24
Finished Feb 01 03:50:06 PM PST 24
Peak memory 222444 kb
Host smart-c79c0d68-2ee3-4f27-9d77-ffb5be58abf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551679621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3551679621
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2821138498
Short name T266
Test name
Test status
Simulation time 363458123 ps
CPU time 17.54 seconds
Started Feb 01 03:54:05 PM PST 24
Finished Feb 01 03:54:27 PM PST 24
Peak memory 214932 kb
Host smart-3bed7fba-1b7f-4ecf-b0ba-78ac5d01237d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821138498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2821138498
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2134947990
Short name T430
Test name
Test status
Simulation time 633603902 ps
CPU time 5.4 seconds
Started Feb 01 03:45:19 PM PST 24
Finished Feb 01 03:46:04 PM PST 24
Peak memory 215216 kb
Host smart-ab40e947-c261-4c94-a616-1f1cf28de903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134947990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2134947990
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.537430327
Short name T155
Test name
Test status
Simulation time 466834611 ps
CPU time 11.74 seconds
Started Feb 01 12:38:47 PM PST 24
Finished Feb 01 12:39:57 PM PST 24
Peak memory 213428 kb
Host smart-9bd116bb-bdf4-4a42-8d09-7f3977589b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537430327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.537430327
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3840837056
Short name T153
Test name
Test status
Simulation time 120502892 ps
CPU time 5.03 seconds
Started Feb 01 12:38:51 PM PST 24
Finished Feb 01 12:39:54 PM PST 24
Peak memory 213420 kb
Host smart-3739a256-e676-4c2d-b8db-077da68b57f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840837056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3840837056
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1201868393
Short name T215
Test name
Test status
Simulation time 1380061964 ps
CPU time 21.01 seconds
Started Feb 01 03:49:57 PM PST 24
Finished Feb 01 03:51:25 PM PST 24
Peak memory 222344 kb
Host smart-d3db9c1a-d294-464e-9c9a-93a74720ca30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201868393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1201868393
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.800313965
Short name T199
Test name
Test status
Simulation time 394205670 ps
CPU time 14.2 seconds
Started Feb 01 03:53:28 PM PST 24
Finished Feb 01 03:53:58 PM PST 24
Peak memory 220920 kb
Host smart-61fa6909-a040-4ff6-be87-79102059cd96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800313965 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.800313965
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1029139387
Short name T401
Test name
Test status
Simulation time 1986279891 ps
CPU time 13.93 seconds
Started Feb 01 03:54:19 PM PST 24
Finished Feb 01 03:54:37 PM PST 24
Peak memory 208680 kb
Host smart-558fb2b9-fd8b-48cd-8eea-40d578a30c00
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029139387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1029139387
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1662230938
Short name T310
Test name
Test status
Simulation time 42010002 ps
CPU time 2.58 seconds
Started Feb 01 03:56:12 PM PST 24
Finished Feb 01 03:56:22 PM PST 24
Peak memory 208136 kb
Host smart-9ffc63e8-1595-4282-8f34-6a811a2099a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662230938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1662230938
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4063539355
Short name T346
Test name
Test status
Simulation time 626920832 ps
CPU time 6.1 seconds
Started Feb 01 03:55:41 PM PST 24
Finished Feb 01 03:55:55 PM PST 24
Peak memory 220340 kb
Host smart-351fadb4-b571-4dae-ac88-028bbdbc08d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063539355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4063539355
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.4169178805
Short name T314
Test name
Test status
Simulation time 15571553309 ps
CPU time 56.35 seconds
Started Feb 01 03:45:35 PM PST 24
Finished Feb 01 03:47:23 PM PST 24
Peak memory 216120 kb
Host smart-2948c661-7b6a-4a02-8531-4a904147d391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169178805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.4169178805
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3336578197
Short name T51
Test name
Test status
Simulation time 185422762 ps
CPU time 4.73 seconds
Started Feb 01 03:47:46 PM PST 24
Finished Feb 01 03:48:41 PM PST 24
Peak memory 217884 kb
Host smart-7e4cebf2-af58-4225-8f62-393f9f6f6bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336578197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3336578197
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3088176603
Short name T142
Test name
Test status
Simulation time 907774095 ps
CPU time 4.55 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:09 PM PST 24
Peak memory 217768 kb
Host smart-c525652a-07a7-49d8-af3a-324c24a40ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088176603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3088176603
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.486904857
Short name T234
Test name
Test status
Simulation time 181019233 ps
CPU time 5.4 seconds
Started Feb 01 03:49:14 PM PST 24
Finished Feb 01 03:50:41 PM PST 24
Peak memory 222172 kb
Host smart-7883c0cf-6bba-43aa-aeae-f23a52949b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486904857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.486904857
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.211548692
Short name T276
Test name
Test status
Simulation time 4396643418 ps
CPU time 62.32 seconds
Started Feb 01 03:48:57 PM PST 24
Finished Feb 01 03:51:04 PM PST 24
Peak memory 214724 kb
Host smart-bac15e73-086a-4ac8-bc49-99fbc3616a99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=211548692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.211548692
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.4019027276
Short name T24
Test name
Test status
Simulation time 1761496364 ps
CPU time 48.22 seconds
Started Feb 01 03:44:49 PM PST 24
Finished Feb 01 03:46:04 PM PST 24
Peak memory 221680 kb
Host smart-0c22eb38-a06a-4c7a-99aa-8bc7277f93fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019027276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.4019027276
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1159533759
Short name T213
Test name
Test status
Simulation time 136115528 ps
CPU time 5.13 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:04 PM PST 24
Peak memory 219688 kb
Host smart-bd9d1f25-18a3-4273-a535-9e46bc73728f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159533759 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1159533759
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1152001919
Short name T46
Test name
Test status
Simulation time 95108176 ps
CPU time 2.94 seconds
Started Feb 01 03:54:03 PM PST 24
Finished Feb 01 03:54:11 PM PST 24
Peak memory 209680 kb
Host smart-dd97ae64-9023-4c48-9798-6d3a4c31ec8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152001919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1152001919
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3579927804
Short name T217
Test name
Test status
Simulation time 5666119011 ps
CPU time 24.72 seconds
Started Feb 01 03:47:48 PM PST 24
Finished Feb 01 03:49:03 PM PST 24
Peak memory 221400 kb
Host smart-07463d8f-2af4-4116-a990-53cba9b5cd54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579927804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3579927804
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2475818466
Short name T62
Test name
Test status
Simulation time 1033130158 ps
CPU time 36.69 seconds
Started Feb 01 03:45:50 PM PST 24
Finished Feb 01 03:47:22 PM PST 24
Peak memory 216024 kb
Host smart-a6ed6ce8-fabb-4fd4-b1aa-b5bdbc177036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475818466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2475818466
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3283542204
Short name T146
Test name
Test status
Simulation time 124152969 ps
CPU time 5.1 seconds
Started Feb 01 12:38:16 PM PST 24
Finished Feb 01 12:39:25 PM PST 24
Peak memory 208112 kb
Host smart-0b1e3e50-5fbd-4f8f-95a4-ddf974b60624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283542204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3283542204
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1309487011
Short name T161
Test name
Test status
Simulation time 3855336183 ps
CPU time 18.82 seconds
Started Feb 01 12:39:07 PM PST 24
Finished Feb 01 12:40:21 PM PST 24
Peak memory 213540 kb
Host smart-2425d39f-ce46-4136-b780-db54bdaee804
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309487011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1309487011
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1678360428
Short name T158
Test name
Test status
Simulation time 304445439 ps
CPU time 1.48 seconds
Started Feb 01 03:48:47 PM PST 24
Finished Feb 01 03:49:40 PM PST 24
Peak memory 209160 kb
Host smart-ab197ef6-84eb-4c1f-88da-23626032ebe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678360428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1678360428
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3816123601
Short name T54
Test name
Test status
Simulation time 77290029 ps
CPU time 3.06 seconds
Started Feb 01 03:54:24 PM PST 24
Finished Feb 01 03:54:32 PM PST 24
Peak memory 210084 kb
Host smart-1d13c3b7-bd59-40d0-8ee2-d7bc3807d13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816123601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3816123601
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3389049803
Short name T163
Test name
Test status
Simulation time 451360187 ps
CPU time 2.08 seconds
Started Feb 01 03:55:15 PM PST 24
Finished Feb 01 03:55:27 PM PST 24
Peak memory 209940 kb
Host smart-a22c0a6d-97b8-4e08-b561-62bbc49e6821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389049803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3389049803
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1267686935
Short name T138
Test name
Test status
Simulation time 291716106 ps
CPU time 8.3 seconds
Started Feb 01 03:48:04 PM PST 24
Finished Feb 01 03:49:09 PM PST 24
Peak memory 222584 kb
Host smart-7401adea-6264-4117-ad1d-ca4208fbb64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267686935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1267686935
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.267710669
Short name T143
Test name
Test status
Simulation time 310544425 ps
CPU time 3.75 seconds
Started Feb 01 03:54:05 PM PST 24
Finished Feb 01 03:54:14 PM PST 24
Peak memory 222484 kb
Host smart-fe8af06e-4104-435b-ba8a-ea22598454a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267710669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.267710669
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3560723283
Short name T285
Test name
Test status
Simulation time 74965843 ps
CPU time 4.4 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:16 PM PST 24
Peak memory 222192 kb
Host smart-40f2cb13-2d75-47b9-bebb-f0062ad717d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560723283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3560723283
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1340325246
Short name T326
Test name
Test status
Simulation time 209700548 ps
CPU time 2.87 seconds
Started Feb 01 03:45:21 PM PST 24
Finished Feb 01 03:46:06 PM PST 24
Peak memory 208404 kb
Host smart-a01b595e-3529-41c6-b635-a2e490ea5825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340325246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1340325246
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1606829223
Short name T1002
Test name
Test status
Simulation time 173608829 ps
CPU time 3.09 seconds
Started Feb 01 03:46:40 PM PST 24
Finished Feb 01 03:47:32 PM PST 24
Peak memory 208912 kb
Host smart-d66f7233-bc88-4a2e-b62c-62f09c9f373c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606829223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1606829223
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3943120511
Short name T53
Test name
Test status
Simulation time 470844659 ps
CPU time 8.68 seconds
Started Feb 01 03:47:25 PM PST 24
Finished Feb 01 03:48:14 PM PST 24
Peak memory 211056 kb
Host smart-1fb339da-335c-412e-a1d2-1354326775bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943120511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3943120511
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3155158698
Short name T373
Test name
Test status
Simulation time 670913464 ps
CPU time 9.6 seconds
Started Feb 01 03:47:23 PM PST 24
Finished Feb 01 03:48:12 PM PST 24
Peak memory 214196 kb
Host smart-e235036e-9c57-4f39-a3c7-917d94cbcee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3155158698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3155158698
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1503262004
Short name T340
Test name
Test status
Simulation time 1477751684 ps
CPU time 5.61 seconds
Started Feb 01 03:47:24 PM PST 24
Finished Feb 01 03:48:11 PM PST 24
Peak memory 219768 kb
Host smart-a7bb5b21-23b2-40df-8c65-feea3b3c41ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503262004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1503262004
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2401954487
Short name T286
Test name
Test status
Simulation time 72230074 ps
CPU time 3.69 seconds
Started Feb 01 03:48:44 PM PST 24
Finished Feb 01 03:49:37 PM PST 24
Peak memory 214520 kb
Host smart-a6455ae9-0a1d-499b-a171-c65e0e3fe874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401954487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2401954487
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.216283247
Short name T363
Test name
Test status
Simulation time 12574927915 ps
CPU time 34.59 seconds
Started Feb 01 03:48:07 PM PST 24
Finished Feb 01 03:49:36 PM PST 24
Peak memory 221408 kb
Host smart-97509472-67db-414d-b639-7d9bc83cc043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216283247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.216283247
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3210737084
Short name T369
Test name
Test status
Simulation time 158501306 ps
CPU time 2.87 seconds
Started Feb 01 03:47:45 PM PST 24
Finished Feb 01 03:48:39 PM PST 24
Peak memory 214172 kb
Host smart-73f6c97f-59a4-470d-8b45-77d50bc12804
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3210737084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3210737084
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3359603953
Short name T278
Test name
Test status
Simulation time 701992156 ps
CPU time 10.25 seconds
Started Feb 01 03:48:43 PM PST 24
Finished Feb 01 03:49:44 PM PST 24
Peak memory 214188 kb
Host smart-5f346c97-91e3-4344-8db2-f6017d8edce0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359603953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3359603953
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.804540734
Short name T235
Test name
Test status
Simulation time 1478968103 ps
CPU time 43.73 seconds
Started Feb 01 03:48:41 PM PST 24
Finished Feb 01 03:50:13 PM PST 24
Peak memory 217720 kb
Host smart-2cbf3d57-9c26-46f2-8673-d97eda88867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804540734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.804540734
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3852652994
Short name T429
Test name
Test status
Simulation time 110547287 ps
CPU time 3.82 seconds
Started Feb 01 03:55:16 PM PST 24
Finished Feb 01 03:55:30 PM PST 24
Peak memory 214892 kb
Host smart-728baf69-8609-49bd-9ce4-dad66e296fde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852652994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3852652994
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3041997807
Short name T210
Test name
Test status
Simulation time 20839183579 ps
CPU time 607.96 seconds
Started Feb 01 03:54:00 PM PST 24
Finished Feb 01 04:04:14 PM PST 24
Peak memory 222480 kb
Host smart-e3ab00fd-88ea-4ff5-8f1b-55f84c9ae07b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041997807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3041997807
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1048285514
Short name T283
Test name
Test status
Simulation time 187895052 ps
CPU time 8.54 seconds
Started Feb 01 03:53:45 PM PST 24
Finished Feb 01 03:54:02 PM PST 24
Peak memory 215340 kb
Host smart-3ea9a40a-25bc-498c-accf-cf76d2894cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1048285514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1048285514
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3536288600
Short name T218
Test name
Test status
Simulation time 162204287 ps
CPU time 5.07 seconds
Started Feb 01 03:45:52 PM PST 24
Finished Feb 01 03:46:53 PM PST 24
Peak memory 209924 kb
Host smart-43dac49c-96ac-448e-9ad8-8e58f1e3269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536288600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3536288600
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2184116507
Short name T527
Test name
Test status
Simulation time 365446774 ps
CPU time 8.35 seconds
Started Feb 01 12:38:08 PM PST 24
Finished Feb 01 12:39:22 PM PST 24
Peak memory 205140 kb
Host smart-9c1b5b89-dff7-4f64-9f82-1a8a64d72788
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184116507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
184116507
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3386364790
Short name T447
Test name
Test status
Simulation time 174607391 ps
CPU time 7.47 seconds
Started Feb 01 12:37:59 PM PST 24
Finished Feb 01 12:39:16 PM PST 24
Peak memory 205160 kb
Host smart-888ea247-811f-4659-9fcd-3af56eb0b39b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386364790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
386364790
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.740473177
Short name T472
Test name
Test status
Simulation time 74652351 ps
CPU time 1.11 seconds
Started Feb 01 12:38:28 PM PST 24
Finished Feb 01 12:39:29 PM PST 24
Peak memory 205096 kb
Host smart-fa34ec5c-8e71-4093-9bfd-36e1389314d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740473177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.740473177
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1454642890
Short name T495
Test name
Test status
Simulation time 103826368 ps
CPU time 1.21 seconds
Started Feb 01 12:37:54 PM PST 24
Finished Feb 01 12:39:06 PM PST 24
Peak memory 213504 kb
Host smart-96294bff-b896-4640-aa45-3dcc2ad97aaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454642890 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1454642890
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1045971053
Short name T563
Test name
Test status
Simulation time 16523987 ps
CPU time 0.72 seconds
Started Feb 01 12:38:10 PM PST 24
Finished Feb 01 12:39:16 PM PST 24
Peak memory 204952 kb
Host smart-41f43fdb-7f43-4eb5-8756-f75c2a726c09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045971053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1045971053
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4155124770
Short name T470
Test name
Test status
Simulation time 42324218 ps
CPU time 1.57 seconds
Started Feb 01 12:37:58 PM PST 24
Finished Feb 01 12:39:09 PM PST 24
Peak memory 205416 kb
Host smart-f5cd2f54-c611-4439-9ff7-8e4a83465cb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155124770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.4155124770
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.890797077
Short name T458
Test name
Test status
Simulation time 220981093 ps
CPU time 2.73 seconds
Started Feb 01 12:38:15 PM PST 24
Finished Feb 01 12:39:26 PM PST 24
Peak memory 218308 kb
Host smart-af9fb491-19dd-4750-b6e1-c3f4a9b3b16d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890797077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.890797077
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.112187409
Short name T182
Test name
Test status
Simulation time 105588307 ps
CPU time 3.27 seconds
Started Feb 01 12:38:25 PM PST 24
Finished Feb 01 12:39:30 PM PST 24
Peak memory 213356 kb
Host smart-efa56b30-a71a-48f4-be50-f43cd9b677fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112187409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.112187409
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4165954914
Short name T181
Test name
Test status
Simulation time 122812370 ps
CPU time 1.18 seconds
Started Feb 01 12:38:24 PM PST 24
Finished Feb 01 12:39:27 PM PST 24
Peak memory 205112 kb
Host smart-b5130971-2019-471a-ba7f-7f4b6d603d53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165954914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.4
165954914
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.289255852
Short name T168
Test name
Test status
Simulation time 27646944 ps
CPU time 1.46 seconds
Started Feb 01 12:38:30 PM PST 24
Finished Feb 01 12:39:30 PM PST 24
Peak memory 213440 kb
Host smart-4e4cc6d8-336f-4277-b5de-16705657a2c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289255852 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.289255852
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2866391244
Short name T128
Test name
Test status
Simulation time 11727499 ps
CPU time 1.01 seconds
Started Feb 01 12:38:11 PM PST 24
Finished Feb 01 12:39:17 PM PST 24
Peak memory 205104 kb
Host smart-db47f35a-6102-42c4-a502-333843d6d8e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866391244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2866391244
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1562146185
Short name T440
Test name
Test status
Simulation time 16976169 ps
CPU time 0.7 seconds
Started Feb 01 12:38:44 PM PST 24
Finished Feb 01 12:39:41 PM PST 24
Peak memory 205092 kb
Host smart-f40f2605-3432-4ad5-af92-7ef0c4e53520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562146185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1562146185
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.4224459543
Short name T129
Test name
Test status
Simulation time 70073976 ps
CPU time 2.37 seconds
Started Feb 01 12:38:00 PM PST 24
Finished Feb 01 12:39:25 PM PST 24
Peak memory 205196 kb
Host smart-258ae46d-914c-43e8-a897-a7b81cb0c6dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224459543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.4224459543
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1711202
Short name T475
Test name
Test status
Simulation time 735736629 ps
CPU time 6.9 seconds
Started Feb 01 12:38:27 PM PST 24
Finished Feb 01 12:39:34 PM PST 24
Peak memory 213688 kb
Host smart-cad69b68-dce1-473f-83c2-31daaee849a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_r
eg_errors.1711202
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.684520385
Short name T147
Test name
Test status
Simulation time 373342586 ps
CPU time 2.81 seconds
Started Feb 01 12:37:54 PM PST 24
Finished Feb 01 12:39:08 PM PST 24
Peak memory 213512 kb
Host smart-567a9b0c-4ee0-4c71-8978-ea40e8ef3a61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684520385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.684520385
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.162275292
Short name T154
Test name
Test status
Simulation time 562999924 ps
CPU time 4.64 seconds
Started Feb 01 12:37:59 PM PST 24
Finished Feb 01 12:39:13 PM PST 24
Peak memory 213416 kb
Host smart-618092b7-fa0c-41c0-9555-73cd51560e0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162275292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
162275292
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1400235033
Short name T170
Test name
Test status
Simulation time 94679015 ps
CPU time 1.25 seconds
Started Feb 01 12:38:30 PM PST 24
Finished Feb 01 12:39:30 PM PST 24
Peak memory 213312 kb
Host smart-254b929d-0087-4301-9b99-a4d854a6a95e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400235033 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1400235033
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.334655188
Short name T169
Test name
Test status
Simulation time 37003450 ps
CPU time 1.06 seconds
Started Feb 01 12:38:38 PM PST 24
Finished Feb 01 12:39:38 PM PST 24
Peak memory 205108 kb
Host smart-ba629617-936c-40fe-9387-73c0f3efe3ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334655188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.334655188
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2097929129
Short name T454
Test name
Test status
Simulation time 12555109 ps
CPU time 0.7 seconds
Started Feb 01 12:38:28 PM PST 24
Finished Feb 01 12:39:29 PM PST 24
Peak memory 205020 kb
Host smart-c7d98a86-f3da-4c8b-8e13-b8a6048794ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097929129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2097929129
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2453383686
Short name T114
Test name
Test status
Simulation time 1310934026 ps
CPU time 6.97 seconds
Started Feb 01 12:38:36 PM PST 24
Finished Feb 01 12:39:43 PM PST 24
Peak memory 213612 kb
Host smart-23521f35-897c-4f6f-84fb-b5eff7e9181b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453383686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2453383686
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.4040254692
Short name T562
Test name
Test status
Simulation time 2632677444 ps
CPU time 7.74 seconds
Started Feb 01 12:38:35 PM PST 24
Finished Feb 01 12:39:42 PM PST 24
Peak memory 221932 kb
Host smart-da12807f-a6fb-4b11-b534-b1687f73875a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040254692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.4040254692
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1130505603
Short name T501
Test name
Test status
Simulation time 34995993 ps
CPU time 1.11 seconds
Started Feb 01 12:51:45 PM PST 24
Finished Feb 01 12:51:51 PM PST 24
Peak memory 205288 kb
Host smart-802ae2ea-7c79-4c2e-ab7a-9804b58fb25c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130505603 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1130505603
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3939316846
Short name T518
Test name
Test status
Simulation time 15135079 ps
CPU time 0.85 seconds
Started Feb 01 12:38:36 PM PST 24
Finished Feb 01 12:39:36 PM PST 24
Peak memory 204952 kb
Host smart-23ce11e3-4298-4a40-9892-d96857568715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939316846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3939316846
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1414517210
Short name T171
Test name
Test status
Simulation time 7590714400 ps
CPU time 20.71 seconds
Started Feb 01 12:38:27 PM PST 24
Finished Feb 01 12:39:48 PM PST 24
Peak memory 218848 kb
Host smart-532a124f-e70a-4de9-9544-8efe7c06c0bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414517210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1414517210
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3171304332
Short name T473
Test name
Test status
Simulation time 173722514 ps
CPU time 4.27 seconds
Started Feb 01 12:38:39 PM PST 24
Finished Feb 01 12:39:42 PM PST 24
Peak memory 213800 kb
Host smart-e65c90cf-ebd9-4554-9148-e5661ab6bec5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171304332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3171304332
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1669490871
Short name T498
Test name
Test status
Simulation time 303855066 ps
CPU time 3.18 seconds
Started Feb 01 12:38:25 PM PST 24
Finished Feb 01 12:39:30 PM PST 24
Peak memory 213516 kb
Host smart-0249803e-685a-4e14-b014-46e7b38ee5e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669490871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1669490871
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.838217252
Short name T532
Test name
Test status
Simulation time 137815917 ps
CPU time 1.73 seconds
Started Feb 01 12:38:46 PM PST 24
Finished Feb 01 12:39:46 PM PST 24
Peak memory 213512 kb
Host smart-48adf092-93e7-47a7-83be-0d681a3b790d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838217252 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.838217252
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1537910998
Short name T551
Test name
Test status
Simulation time 42406017 ps
CPU time 1.33 seconds
Started Feb 01 12:38:50 PM PST 24
Finished Feb 01 12:39:49 PM PST 24
Peak memory 205192 kb
Host smart-cfb413fb-aa36-4f6b-87ae-3e5a8180ce05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537910998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1537910998
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1822550434
Short name T444
Test name
Test status
Simulation time 11314902 ps
CPU time 0.83 seconds
Started Feb 01 12:38:46 PM PST 24
Finished Feb 01 12:39:45 PM PST 24
Peak memory 204892 kb
Host smart-ec999e64-e052-4410-b262-5ab025e30232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822550434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1822550434
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3052485344
Short name T446
Test name
Test status
Simulation time 79741290 ps
CPU time 1.23 seconds
Started Feb 01 12:38:55 PM PST 24
Finished Feb 01 12:39:54 PM PST 24
Peak memory 205272 kb
Host smart-54d540ab-dd76-42a9-94e0-353011544284
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052485344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3052485344
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1072079715
Short name T504
Test name
Test status
Simulation time 85978823 ps
CPU time 2.44 seconds
Started Feb 01 12:38:38 PM PST 24
Finished Feb 01 12:39:39 PM PST 24
Peak memory 218452 kb
Host smart-05cbe33f-0a8b-4a97-8808-e3c48f95c203
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072079715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1072079715
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1873060313
Short name T131
Test name
Test status
Simulation time 653321062 ps
CPU time 6.8 seconds
Started Feb 01 12:38:34 PM PST 24
Finished Feb 01 12:39:39 PM PST 24
Peak memory 213460 kb
Host smart-8d252dbb-d314-4528-ab92-f9ec85e97cea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873060313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1873060313
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1417865176
Short name T545
Test name
Test status
Simulation time 112704036 ps
CPU time 1.99 seconds
Started Feb 01 12:38:47 PM PST 24
Finished Feb 01 12:39:47 PM PST 24
Peak memory 213448 kb
Host smart-3797f091-7354-4355-8e9b-6480dfe6bf18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417865176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1417865176
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4150611108
Short name T509
Test name
Test status
Simulation time 33046224 ps
CPU time 0.97 seconds
Started Feb 01 12:38:46 PM PST 24
Finished Feb 01 12:39:45 PM PST 24
Peak memory 204956 kb
Host smart-93a8e591-5a9d-4257-adf9-0f5dffe18257
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150611108 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4150611108
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2183056012
Short name T132
Test name
Test status
Simulation time 50509516 ps
CPU time 1.13 seconds
Started Feb 01 12:38:47 PM PST 24
Finished Feb 01 12:39:46 PM PST 24
Peak memory 205076 kb
Host smart-5cff0d16-8fa2-4ac4-be72-2808620f8169
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183056012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2183056012
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4271859387
Short name T482
Test name
Test status
Simulation time 13667686 ps
CPU time 0.91 seconds
Started Feb 01 12:38:46 PM PST 24
Finished Feb 01 12:39:45 PM PST 24
Peak memory 205008 kb
Host smart-8fd62f70-20b0-45ec-8cda-f95dfa3ede54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271859387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.4271859387
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2612779107
Short name T530
Test name
Test status
Simulation time 39298863 ps
CPU time 2.05 seconds
Started Feb 01 12:38:49 PM PST 24
Finished Feb 01 12:39:49 PM PST 24
Peak memory 205152 kb
Host smart-9b0b1572-8e39-469b-8b86-9f71f21842a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612779107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2612779107
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.790247003
Short name T565
Test name
Test status
Simulation time 278431367 ps
CPU time 2.81 seconds
Started Feb 01 12:38:44 PM PST 24
Finished Feb 01 12:39:44 PM PST 24
Peak memory 213492 kb
Host smart-b4ebf8b0-45ff-44ed-8057-9bdac6c48186
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790247003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.790247003
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3961268764
Short name T483
Test name
Test status
Simulation time 758375367 ps
CPU time 5.24 seconds
Started Feb 01 12:38:45 PM PST 24
Finished Feb 01 12:39:49 PM PST 24
Peak memory 213536 kb
Host smart-621b9c86-0cc7-49f6-bdbb-651faa554a70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961268764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3961268764
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3469847447
Short name T556
Test name
Test status
Simulation time 88035793 ps
CPU time 1.4 seconds
Started Feb 01 12:38:45 PM PST 24
Finished Feb 01 12:39:45 PM PST 24
Peak memory 221604 kb
Host smart-984df47e-148b-4bbb-ac9a-f074734f7752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469847447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3469847447
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2982420937
Short name T122
Test name
Test status
Simulation time 23650872 ps
CPU time 1.41 seconds
Started Feb 01 12:38:48 PM PST 24
Finished Feb 01 12:39:47 PM PST 24
Peak memory 213424 kb
Host smart-e1e82a8b-4d18-4474-8ddc-e3d6d9d023e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982420937 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2982420937
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.4267339399
Short name T548
Test name
Test status
Simulation time 19223538 ps
CPU time 0.88 seconds
Started Feb 01 12:38:49 PM PST 24
Finished Feb 01 12:39:48 PM PST 24
Peak memory 205036 kb
Host smart-8d266d31-f232-40cd-8abd-a310d2748915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267339399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.4267339399
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2224682392
Short name T522
Test name
Test status
Simulation time 39519780 ps
CPU time 0.7 seconds
Started Feb 01 12:38:54 PM PST 24
Finished Feb 01 12:39:53 PM PST 24
Peak memory 205032 kb
Host smart-2c8bcec2-f7f2-431e-a55c-29c5c8b5ae90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224682392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2224682392
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3254743716
Short name T552
Test name
Test status
Simulation time 134533842 ps
CPU time 2.32 seconds
Started Feb 01 12:38:52 PM PST 24
Finished Feb 01 12:39:52 PM PST 24
Peak memory 213352 kb
Host smart-b130495e-ee48-41b4-a20d-d7a546791ca7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254743716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3254743716
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.797530536
Short name T558
Test name
Test status
Simulation time 414200737 ps
CPU time 8.3 seconds
Started Feb 01 12:38:47 PM PST 24
Finished Feb 01 12:39:53 PM PST 24
Peak memory 213620 kb
Host smart-8621d348-6679-4b2a-85dc-653de16621c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797530536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.797530536
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1269396309
Short name T455
Test name
Test status
Simulation time 341041731 ps
CPU time 9.3 seconds
Started Feb 01 12:38:48 PM PST 24
Finished Feb 01 12:39:56 PM PST 24
Peak memory 213576 kb
Host smart-28569f93-9909-4f67-aedb-43f4bb573646
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269396309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1269396309
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2568816381
Short name T536
Test name
Test status
Simulation time 95501225 ps
CPU time 1.24 seconds
Started Feb 01 12:38:50 PM PST 24
Finished Feb 01 12:39:49 PM PST 24
Peak memory 213476 kb
Host smart-97577b0d-f1b9-4f66-92a7-a8669c6d9b33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568816381 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2568816381
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.4261197868
Short name T453
Test name
Test status
Simulation time 20145945 ps
CPU time 0.88 seconds
Started Feb 01 12:38:48 PM PST 24
Finished Feb 01 12:39:47 PM PST 24
Peak memory 205020 kb
Host smart-132ea0fa-062f-4129-8627-3f641c63419b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261197868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.4261197868
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2897558627
Short name T559
Test name
Test status
Simulation time 13010760 ps
CPU time 0.69 seconds
Started Feb 01 12:38:49 PM PST 24
Finished Feb 01 12:39:48 PM PST 24
Peak memory 205024 kb
Host smart-a4874183-85ad-4c98-aae4-852a8dbcdf6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897558627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2897558627
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1685721419
Short name T130
Test name
Test status
Simulation time 79007109 ps
CPU time 1.42 seconds
Started Feb 01 12:38:50 PM PST 24
Finished Feb 01 12:39:49 PM PST 24
Peak memory 205224 kb
Host smart-2e4ab457-f3b3-4816-9708-cf4d1f9b0a50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685721419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1685721419
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.383295243
Short name T553
Test name
Test status
Simulation time 170780572 ps
CPU time 4.32 seconds
Started Feb 01 12:38:47 PM PST 24
Finished Feb 01 12:39:49 PM PST 24
Peak memory 213688 kb
Host smart-43853e86-65ad-40d8-aeec-bfaade5ecb34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383295243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.383295243
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3489488648
Short name T116
Test name
Test status
Simulation time 709737614 ps
CPU time 9.9 seconds
Started Feb 01 12:38:47 PM PST 24
Finished Feb 01 12:39:55 PM PST 24
Peak memory 213644 kb
Host smart-a71495df-6826-4c5a-96bb-a46073cd8d9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489488648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3489488648
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3329034160
Short name T145
Test name
Test status
Simulation time 65117430 ps
CPU time 2.33 seconds
Started Feb 01 12:38:48 PM PST 24
Finished Feb 01 12:39:49 PM PST 24
Peak memory 216572 kb
Host smart-2b438fcb-7d3f-453a-9d80-3e2c819eb034
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329034160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3329034160
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.179905770
Short name T450
Test name
Test status
Simulation time 14453107 ps
CPU time 1.19 seconds
Started Feb 01 12:39:04 PM PST 24
Finished Feb 01 12:40:00 PM PST 24
Peak memory 205172 kb
Host smart-20a8c3c4-b8cd-4d4d-ad4f-629b8919fe36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179905770 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.179905770
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2700198432
Short name T534
Test name
Test status
Simulation time 42517275 ps
CPU time 0.87 seconds
Started Feb 01 12:39:05 PM PST 24
Finished Feb 01 12:40:00 PM PST 24
Peak memory 205056 kb
Host smart-dda6816b-f004-4cb4-9dc7-6dccda5c3853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700198432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2700198432
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3390278774
Short name T457
Test name
Test status
Simulation time 11054433 ps
CPU time 0.71 seconds
Started Feb 01 12:39:02 PM PST 24
Finished Feb 01 12:39:59 PM PST 24
Peak memory 204932 kb
Host smart-7e1f286e-5d82-4954-8c24-d5b7edfc554c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390278774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3390278774
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.611913389
Short name T484
Test name
Test status
Simulation time 21598558 ps
CPU time 1.34 seconds
Started Feb 01 12:39:03 PM PST 24
Finished Feb 01 12:40:00 PM PST 24
Peak memory 205120 kb
Host smart-38f1847a-d766-4cc6-be8a-2957f7c4c4c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611913389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.611913389
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3211174198
Short name T476
Test name
Test status
Simulation time 176615525 ps
CPU time 4.97 seconds
Started Feb 01 12:38:49 PM PST 24
Finished Feb 01 12:39:52 PM PST 24
Peak memory 213540 kb
Host smart-9c7b1e5f-4462-4c68-95ec-5a262f3907bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211174198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3211174198
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3212940621
Short name T111
Test name
Test status
Simulation time 743852119 ps
CPU time 4.55 seconds
Started Feb 01 12:39:00 PM PST 24
Finished Feb 01 12:40:02 PM PST 24
Peak memory 213676 kb
Host smart-530b0b62-3339-4050-a7db-33b2dcbe9a16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212940621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3212940621
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4273785748
Short name T541
Test name
Test status
Simulation time 79433925 ps
CPU time 2.79 seconds
Started Feb 01 12:39:02 PM PST 24
Finished Feb 01 12:40:01 PM PST 24
Peak memory 213408 kb
Host smart-290542b3-19a4-4f15-999e-dbb46efb5c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273785748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4273785748
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.16645828
Short name T107
Test name
Test status
Simulation time 220795774 ps
CPU time 8.22 seconds
Started Feb 01 12:39:02 PM PST 24
Finished Feb 01 12:40:06 PM PST 24
Peak memory 213360 kb
Host smart-d96e2f87-ef3f-4624-8564-ed105495b60c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16645828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.16645828
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2662821260
Short name T550
Test name
Test status
Simulation time 57149159 ps
CPU time 0.97 seconds
Started Feb 01 12:39:07 PM PST 24
Finished Feb 01 12:40:02 PM PST 24
Peak memory 205040 kb
Host smart-ffa67843-6f30-4230-bc60-097a1d7fe50c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662821260 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2662821260
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3406060671
Short name T526
Test name
Test status
Simulation time 37981435 ps
CPU time 0.89 seconds
Started Feb 01 12:39:05 PM PST 24
Finished Feb 01 12:40:01 PM PST 24
Peak memory 204964 kb
Host smart-d0085cc3-aeda-4e54-ba03-e2e6ac861db1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406060671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3406060671
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1966711647
Short name T516
Test name
Test status
Simulation time 42343248 ps
CPU time 0.68 seconds
Started Feb 01 12:39:05 PM PST 24
Finished Feb 01 12:40:01 PM PST 24
Peak memory 204952 kb
Host smart-112ed3c2-2f0f-473e-8ed6-036b0919a396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966711647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1966711647
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3082263603
Short name T117
Test name
Test status
Simulation time 204856977 ps
CPU time 3.86 seconds
Started Feb 01 12:39:00 PM PST 24
Finished Feb 01 12:40:02 PM PST 24
Peak memory 213576 kb
Host smart-5fabb929-59d8-4e31-a594-f37f671c44ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082263603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3082263603
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3713208556
Short name T490
Test name
Test status
Simulation time 1063282936 ps
CPU time 7.85 seconds
Started Feb 01 12:39:01 PM PST 24
Finished Feb 01 12:40:06 PM PST 24
Peak memory 221692 kb
Host smart-2fa72671-e5fc-427d-a915-57ebad067d71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713208556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3713208556
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3872100106
Short name T521
Test name
Test status
Simulation time 282854318 ps
CPU time 2.96 seconds
Started Feb 01 12:39:05 PM PST 24
Finished Feb 01 12:40:03 PM PST 24
Peak memory 215936 kb
Host smart-a2eeca99-4475-4c0d-ace1-49017c003626
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872100106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3872100106
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2905583754
Short name T442
Test name
Test status
Simulation time 39783405 ps
CPU time 1.42 seconds
Started Feb 01 12:39:09 PM PST 24
Finished Feb 01 12:40:04 PM PST 24
Peak memory 205228 kb
Host smart-1be3c003-6d7c-4f0a-b39b-7334fcfad4b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905583754 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2905583754
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3633283482
Short name T566
Test name
Test status
Simulation time 19592011 ps
CPU time 0.71 seconds
Started Feb 01 12:39:07 PM PST 24
Finished Feb 01 12:40:02 PM PST 24
Peak memory 204984 kb
Host smart-d2ae631f-3805-4794-aa99-457cf57519ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633283482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3633283482
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1588239790
Short name T464
Test name
Test status
Simulation time 109362939 ps
CPU time 2.12 seconds
Started Feb 01 12:39:09 PM PST 24
Finished Feb 01 12:40:05 PM PST 24
Peak memory 205092 kb
Host smart-37380393-d9a2-4b3c-b906-e46cab3e7805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588239790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1588239790
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.125312539
Short name T166
Test name
Test status
Simulation time 172094405 ps
CPU time 4.89 seconds
Started Feb 01 12:39:03 PM PST 24
Finished Feb 01 12:40:04 PM PST 24
Peak memory 213616 kb
Host smart-9a12b0ad-29bd-407f-aac6-e951232d59c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125312539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.125312539
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3030164367
Short name T459
Test name
Test status
Simulation time 117682132 ps
CPU time 3.92 seconds
Started Feb 01 12:39:04 PM PST 24
Finished Feb 01 12:40:03 PM PST 24
Peak memory 213596 kb
Host smart-7a3a92d7-1e4b-4b02-824e-23ee955de8a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030164367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3030164367
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.558108833
Short name T491
Test name
Test status
Simulation time 142481170 ps
CPU time 2.75 seconds
Started Feb 01 12:39:03 PM PST 24
Finished Feb 01 12:40:02 PM PST 24
Peak memory 213508 kb
Host smart-b45e6134-1623-4c73-9dba-b21137c40ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558108833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.558108833
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3695154980
Short name T525
Test name
Test status
Simulation time 107303155 ps
CPU time 2.15 seconds
Started Feb 01 12:39:11 PM PST 24
Finished Feb 01 12:40:07 PM PST 24
Peak memory 213444 kb
Host smart-a5bdb744-58f7-4f00-beb0-c868ef9db6fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695154980 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3695154980
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1875936905
Short name T524
Test name
Test status
Simulation time 109349180 ps
CPU time 1.41 seconds
Started Feb 01 12:39:08 PM PST 24
Finished Feb 01 12:40:03 PM PST 24
Peak memory 205052 kb
Host smart-0e87d792-19c0-40de-a23f-fa965251cc74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875936905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1875936905
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.69451725
Short name T486
Test name
Test status
Simulation time 11225276 ps
CPU time 0.7 seconds
Started Feb 01 12:39:07 PM PST 24
Finished Feb 01 12:40:02 PM PST 24
Peak memory 204980 kb
Host smart-4c5c7a79-f8f1-4d04-b0a5-d469c78a95e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69451725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.69451725
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.526048738
Short name T538
Test name
Test status
Simulation time 66235658 ps
CPU time 1.77 seconds
Started Feb 01 12:39:16 PM PST 24
Finished Feb 01 12:40:13 PM PST 24
Peak memory 205120 kb
Host smart-9820fb5c-1eb7-49dd-a547-895c326088db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526048738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.526048738
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.4077031856
Short name T118
Test name
Test status
Simulation time 323048567 ps
CPU time 1.9 seconds
Started Feb 01 12:39:07 PM PST 24
Finished Feb 01 12:40:04 PM PST 24
Peak memory 213720 kb
Host smart-465407f6-9c40-4ca0-a376-49bd98d0ed45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077031856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.4077031856
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2835336490
Short name T445
Test name
Test status
Simulation time 198472479 ps
CPU time 4.94 seconds
Started Feb 01 12:39:07 PM PST 24
Finished Feb 01 12:40:07 PM PST 24
Peak memory 213592 kb
Host smart-08a84ed2-9072-4af0-8c84-249cc64abd92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835336490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2835336490
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3031615527
Short name T149
Test name
Test status
Simulation time 202528730 ps
CPU time 1.6 seconds
Started Feb 01 12:39:04 PM PST 24
Finished Feb 01 12:40:01 PM PST 24
Peak memory 214416 kb
Host smart-c5a6cb5a-af31-4791-8364-da6d18bfc91d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031615527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3031615527
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.653248601
Short name T144
Test name
Test status
Simulation time 2685094014 ps
CPU time 9.52 seconds
Started Feb 01 12:37:59 PM PST 24
Finished Feb 01 12:39:17 PM PST 24
Peak memory 205300 kb
Host smart-61332b8e-160b-4683-83ee-c0c29bc51d75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653248601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.653248601
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1696628016
Short name T451
Test name
Test status
Simulation time 11808881 ps
CPU time 0.95 seconds
Started Feb 01 12:38:25 PM PST 24
Finished Feb 01 12:39:27 PM PST 24
Peak memory 205032 kb
Host smart-cd04455c-96d5-49da-bbb7-3c9d0c135833
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696628016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
696628016
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2786809057
Short name T474
Test name
Test status
Simulation time 76384708 ps
CPU time 1.39 seconds
Started Feb 01 12:38:14 PM PST 24
Finished Feb 01 12:39:19 PM PST 24
Peak memory 213504 kb
Host smart-295751d0-8998-4570-8cc1-a4e8cebc4656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786809057 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2786809057
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.4230115532
Short name T134
Test name
Test status
Simulation time 95538855 ps
CPU time 1.16 seconds
Started Feb 01 12:38:05 PM PST 24
Finished Feb 01 12:39:13 PM PST 24
Peak memory 205064 kb
Host smart-3f4c2965-2ad2-4997-a89c-f39c2c10630f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230115532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.4230115532
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1653889374
Short name T462
Test name
Test status
Simulation time 53636036 ps
CPU time 0.69 seconds
Started Feb 01 12:37:58 PM PST 24
Finished Feb 01 12:39:08 PM PST 24
Peak memory 204992 kb
Host smart-5896bc41-91db-4bb6-80ea-5a7f1506206d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653889374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1653889374
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.941282774
Short name T540
Test name
Test status
Simulation time 142076844 ps
CPU time 2.04 seconds
Started Feb 01 12:38:14 PM PST 24
Finished Feb 01 12:39:20 PM PST 24
Peak memory 205180 kb
Host smart-f9480f65-b8f1-47b9-88fb-4e3b3116bbf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941282774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.941282774
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3060497882
Short name T510
Test name
Test status
Simulation time 720594345 ps
CPU time 5.26 seconds
Started Feb 01 12:37:58 PM PST 24
Finished Feb 01 12:39:12 PM PST 24
Peak memory 213592 kb
Host smart-6eec951d-98e2-4b08-b177-bdb9af7553f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060497882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3060497882
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2374488029
Short name T460
Test name
Test status
Simulation time 755341355 ps
CPU time 4.77 seconds
Started Feb 01 12:37:58 PM PST 24
Finished Feb 01 12:39:12 PM PST 24
Peak memory 213500 kb
Host smart-ad707941-1778-4b1e-b6e0-642c96c47ede
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374488029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2374488029
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.964919339
Short name T533
Test name
Test status
Simulation time 42983145 ps
CPU time 2.89 seconds
Started Feb 01 12:38:00 PM PST 24
Finished Feb 01 12:39:15 PM PST 24
Peak memory 215552 kb
Host smart-da3286f4-7b1e-4984-aadd-0c024b2032a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964919339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.964919339
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2392440305
Short name T544
Test name
Test status
Simulation time 93850201 ps
CPU time 0.73 seconds
Started Feb 01 12:39:11 PM PST 24
Finished Feb 01 12:40:06 PM PST 24
Peak memory 204952 kb
Host smart-5785ee11-0642-4157-b5fd-d1db0ace7c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392440305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2392440305
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1504815908
Short name T466
Test name
Test status
Simulation time 22650277 ps
CPU time 0.67 seconds
Started Feb 01 12:39:17 PM PST 24
Finished Feb 01 12:40:11 PM PST 24
Peak memory 204960 kb
Host smart-13b15f4c-291a-402c-afed-f01576594ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504815908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1504815908
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.913962838
Short name T514
Test name
Test status
Simulation time 151641217 ps
CPU time 0.74 seconds
Started Feb 01 12:39:11 PM PST 24
Finished Feb 01 12:40:06 PM PST 24
Peak memory 205084 kb
Host smart-c2cdb36c-9a82-40ad-a55c-63115e1ae74f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913962838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.913962838
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2974383328
Short name T547
Test name
Test status
Simulation time 21824732 ps
CPU time 0.73 seconds
Started Feb 01 12:39:07 PM PST 24
Finished Feb 01 12:40:02 PM PST 24
Peak memory 204960 kb
Host smart-71861a2d-a3ff-4fbb-a0c5-33c61b3dde12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974383328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2974383328
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.102383818
Short name T461
Test name
Test status
Simulation time 14052211 ps
CPU time 0.65 seconds
Started Feb 01 12:39:16 PM PST 24
Finished Feb 01 12:40:10 PM PST 24
Peak memory 204968 kb
Host smart-cb722aed-b29a-4a17-bf63-2a82253a014e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102383818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.102383818
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3307573847
Short name T499
Test name
Test status
Simulation time 25321457 ps
CPU time 0.7 seconds
Started Feb 01 12:39:10 PM PST 24
Finished Feb 01 12:40:05 PM PST 24
Peak memory 205072 kb
Host smart-a98cde43-279e-496e-8eec-a68766d95a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307573847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3307573847
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1333110079
Short name T178
Test name
Test status
Simulation time 11180545 ps
CPU time 0.83 seconds
Started Feb 01 12:39:06 PM PST 24
Finished Feb 01 12:40:02 PM PST 24
Peak memory 205020 kb
Host smart-3e51bf39-703c-4496-9af4-dfd1ba5fbed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333110079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1333110079
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2936223277
Short name T449
Test name
Test status
Simulation time 19008568 ps
CPU time 0.65 seconds
Started Feb 01 12:39:17 PM PST 24
Finished Feb 01 12:40:11 PM PST 24
Peak memory 204960 kb
Host smart-606211a4-21dc-4552-8162-eb7d0bc13942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936223277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2936223277
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1041824933
Short name T467
Test name
Test status
Simulation time 11344313 ps
CPU time 0.86 seconds
Started Feb 01 12:39:11 PM PST 24
Finished Feb 01 12:40:06 PM PST 24
Peak memory 205028 kb
Host smart-d59333c3-3a44-4261-a395-6d67ea934051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041824933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1041824933
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1711665522
Short name T503
Test name
Test status
Simulation time 10944051 ps
CPU time 0.83 seconds
Started Feb 01 12:39:14 PM PST 24
Finished Feb 01 12:40:10 PM PST 24
Peak memory 204984 kb
Host smart-86ec6e25-16c2-4cf4-b394-7c78baf89ea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711665522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1711665522
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3452967884
Short name T496
Test name
Test status
Simulation time 64517325 ps
CPU time 4.21 seconds
Started Feb 01 12:38:23 PM PST 24
Finished Feb 01 12:39:31 PM PST 24
Peak memory 205096 kb
Host smart-1f533488-7a5e-4b63-8700-bdd2e95d363a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452967884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
452967884
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2448513663
Short name T520
Test name
Test status
Simulation time 532235601 ps
CPU time 7.51 seconds
Started Feb 01 12:38:18 PM PST 24
Finished Feb 01 12:39:30 PM PST 24
Peak memory 204972 kb
Host smart-5de8dcd3-bb71-44dc-a8a8-28f2511723da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448513663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
448513663
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1829886753
Short name T448
Test name
Test status
Simulation time 18788768 ps
CPU time 1.05 seconds
Started Feb 01 12:38:22 PM PST 24
Finished Feb 01 12:39:30 PM PST 24
Peak memory 205184 kb
Host smart-90759c03-aa2b-48ef-8e7d-09e2d3ec81f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829886753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
829886753
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3555135446
Short name T106
Test name
Test status
Simulation time 71206730 ps
CPU time 1.57 seconds
Started Feb 01 12:38:23 PM PST 24
Finished Feb 01 12:39:26 PM PST 24
Peak memory 213404 kb
Host smart-d7add29a-9101-44e1-a730-215a2c46aba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555135446 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3555135446
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3657048949
Short name T481
Test name
Test status
Simulation time 21407689 ps
CPU time 1.14 seconds
Started Feb 01 12:38:14 PM PST 24
Finished Feb 01 12:39:24 PM PST 24
Peak memory 205072 kb
Host smart-a8b8e390-7e34-4064-bd0b-28891a627825
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657048949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3657048949
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3260954097
Short name T560
Test name
Test status
Simulation time 27086036 ps
CPU time 0.71 seconds
Started Feb 01 12:38:22 PM PST 24
Finished Feb 01 12:39:25 PM PST 24
Peak memory 204984 kb
Host smart-bbcb58e7-5ef4-4739-8c3d-47e4249f380f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260954097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3260954097
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2432496857
Short name T512
Test name
Test status
Simulation time 87548916 ps
CPU time 2.54 seconds
Started Feb 01 12:38:23 PM PST 24
Finished Feb 01 12:39:28 PM PST 24
Peak memory 205140 kb
Host smart-85b8d4a5-b336-456f-98bc-04cd9efd5890
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432496857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2432496857
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3580255458
Short name T175
Test name
Test status
Simulation time 357183721 ps
CPU time 6.82 seconds
Started Feb 01 12:38:25 PM PST 24
Finished Feb 01 12:39:33 PM PST 24
Peak memory 213616 kb
Host smart-8c99c48c-179b-4529-bac3-692965990cc8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580255458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3580255458
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.589330299
Short name T471
Test name
Test status
Simulation time 263233570 ps
CPU time 9.96 seconds
Started Feb 01 12:38:14 PM PST 24
Finished Feb 01 12:39:28 PM PST 24
Peak memory 213628 kb
Host smart-00d7b901-4212-4596-9fa5-24a16a220087
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589330299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.589330299
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2245643761
Short name T487
Test name
Test status
Simulation time 160747978 ps
CPU time 2.9 seconds
Started Feb 01 12:38:17 PM PST 24
Finished Feb 01 12:39:23 PM PST 24
Peak memory 213424 kb
Host smart-128eba57-07d1-41ed-99a3-8fae3a8454bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245643761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2245643761
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2514419908
Short name T152
Test name
Test status
Simulation time 262703136 ps
CPU time 5.12 seconds
Started Feb 01 12:38:14 PM PST 24
Finished Feb 01 12:39:22 PM PST 24
Peak memory 213400 kb
Host smart-32cc5828-13cc-41a6-aa90-1188ef80fd6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514419908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2514419908
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2581965778
Short name T529
Test name
Test status
Simulation time 8861255 ps
CPU time 0.67 seconds
Started Feb 01 12:39:07 PM PST 24
Finished Feb 01 12:40:02 PM PST 24
Peak memory 204960 kb
Host smart-bb4d4409-c9a8-4a8e-b5b5-fefd70b9fc56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581965778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2581965778
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2229701017
Short name T535
Test name
Test status
Simulation time 13103957 ps
CPU time 0.81 seconds
Started Feb 01 12:39:15 PM PST 24
Finished Feb 01 12:40:09 PM PST 24
Peak memory 204860 kb
Host smart-59bec0f7-d2dc-4ca6-84df-27ebffdec13a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229701017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2229701017
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3932351298
Short name T561
Test name
Test status
Simulation time 36391561 ps
CPU time 0.84 seconds
Started Feb 01 12:39:15 PM PST 24
Finished Feb 01 12:40:09 PM PST 24
Peak memory 204896 kb
Host smart-3fd7d0b5-9ced-456f-8b03-05200d11c96d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932351298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3932351298
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1147727369
Short name T519
Test name
Test status
Simulation time 24535704 ps
CPU time 0.81 seconds
Started Feb 01 12:39:15 PM PST 24
Finished Feb 01 12:40:09 PM PST 24
Peak memory 204972 kb
Host smart-aaf86b51-70fa-4318-b966-6ad62a3b3794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147727369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1147727369
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3947607028
Short name T439
Test name
Test status
Simulation time 11280583 ps
CPU time 0.67 seconds
Started Feb 01 12:39:09 PM PST 24
Finished Feb 01 12:40:03 PM PST 24
Peak memory 204948 kb
Host smart-b03203d7-6921-425d-85aa-ea210b80717f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947607028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3947607028
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1602201581
Short name T513
Test name
Test status
Simulation time 11440041 ps
CPU time 0.73 seconds
Started Feb 01 12:39:15 PM PST 24
Finished Feb 01 12:40:09 PM PST 24
Peak memory 204976 kb
Host smart-f3dafbeb-8113-4be6-adf2-d48f06ec35c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602201581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1602201581
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.605484280
Short name T469
Test name
Test status
Simulation time 14471174 ps
CPU time 0.73 seconds
Started Feb 01 12:39:11 PM PST 24
Finished Feb 01 12:40:05 PM PST 24
Peak memory 205048 kb
Host smart-a185ae26-12ce-4232-8b7b-d55fe85b5573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605484280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.605484280
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2390590494
Short name T494
Test name
Test status
Simulation time 32876855 ps
CPU time 0.69 seconds
Started Feb 01 12:39:14 PM PST 24
Finished Feb 01 12:40:10 PM PST 24
Peak memory 205072 kb
Host smart-77185f13-a6b1-4923-be84-8cc0fb10fa73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390590494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2390590494
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.188044585
Short name T488
Test name
Test status
Simulation time 37166448 ps
CPU time 0.71 seconds
Started Feb 01 12:39:26 PM PST 24
Finished Feb 01 12:40:18 PM PST 24
Peak memory 205004 kb
Host smart-38e2e2bb-d545-4eb7-8dee-215dc587928f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188044585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.188044585
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1544349582
Short name T543
Test name
Test status
Simulation time 12596126 ps
CPU time 0.69 seconds
Started Feb 01 12:39:22 PM PST 24
Finished Feb 01 12:40:14 PM PST 24
Peak memory 204900 kb
Host smart-119250af-3a23-46b4-9012-2da632c347a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544349582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1544349582
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.621882871
Short name T441
Test name
Test status
Simulation time 1738924350 ps
CPU time 13.18 seconds
Started Feb 01 12:38:23 PM PST 24
Finished Feb 01 12:39:40 PM PST 24
Peak memory 205080 kb
Host smart-1d2232b1-eaee-4e42-a46a-a4f9f0cc503d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621882871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.621882871
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1660154771
Short name T502
Test name
Test status
Simulation time 40644266 ps
CPU time 1.6 seconds
Started Feb 01 12:38:19 PM PST 24
Finished Feb 01 12:39:23 PM PST 24
Peak memory 205088 kb
Host smart-56ac477f-873c-45d3-a216-154104a61ece
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660154771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
660154771
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2173121533
Short name T176
Test name
Test status
Simulation time 68467839 ps
CPU time 0.99 seconds
Started Feb 01 12:38:28 PM PST 24
Finished Feb 01 12:39:29 PM PST 24
Peak memory 205492 kb
Host smart-11888388-efa1-4100-aa36-fe4d8f99225c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173121533 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2173121533
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1839321886
Short name T506
Test name
Test status
Simulation time 27038295 ps
CPU time 0.96 seconds
Started Feb 01 12:38:18 PM PST 24
Finished Feb 01 12:39:22 PM PST 24
Peak memory 205080 kb
Host smart-3b579b63-e6ee-4dca-85f7-6b13eb409f1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839321886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1839321886
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1390083160
Short name T179
Test name
Test status
Simulation time 16541038 ps
CPU time 0.73 seconds
Started Feb 01 12:38:17 PM PST 24
Finished Feb 01 12:39:28 PM PST 24
Peak memory 205012 kb
Host smart-3c97c225-7093-481e-abfc-5a5fdf0200d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390083160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1390083160
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2269728751
Short name T528
Test name
Test status
Simulation time 88488878 ps
CPU time 2.43 seconds
Started Feb 01 12:38:28 PM PST 24
Finished Feb 01 12:39:31 PM PST 24
Peak memory 205492 kb
Host smart-7a5b9702-4c77-4c6a-9ffb-88d924b08425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269728751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2269728751
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1175184950
Short name T468
Test name
Test status
Simulation time 166357671 ps
CPU time 4.4 seconds
Started Feb 01 12:38:17 PM PST 24
Finished Feb 01 12:39:32 PM PST 24
Peak memory 220912 kb
Host smart-ca8bbd5a-bbd8-4ae4-8f83-a40977e6d081
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175184950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1175184950
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1700953704
Short name T500
Test name
Test status
Simulation time 144538473 ps
CPU time 5.46 seconds
Started Feb 01 12:38:17 PM PST 24
Finished Feb 01 12:39:33 PM PST 24
Peak memory 213652 kb
Host smart-611d2c69-03d1-4701-89b9-f247b39ee2dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700953704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1700953704
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3020190370
Short name T508
Test name
Test status
Simulation time 169515191 ps
CPU time 1.61 seconds
Started Feb 01 12:38:22 PM PST 24
Finished Feb 01 12:39:26 PM PST 24
Peak memory 213460 kb
Host smart-1dcb2b8c-5769-4856-a71a-044955bf6539
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020190370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3020190370
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.782568258
Short name T517
Test name
Test status
Simulation time 11722188 ps
CPU time 0.82 seconds
Started Feb 01 12:39:21 PM PST 24
Finished Feb 01 12:40:14 PM PST 24
Peak memory 205016 kb
Host smart-8d49c3dd-5cc6-46df-85cd-b9078e2077d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782568258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.782568258
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1977462427
Short name T515
Test name
Test status
Simulation time 41322412 ps
CPU time 0.71 seconds
Started Feb 01 12:39:20 PM PST 24
Finished Feb 01 12:40:13 PM PST 24
Peak memory 205036 kb
Host smart-febe8c00-4d3c-4da6-a6b5-fd4eb3cbd20a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977462427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1977462427
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1859209758
Short name T133
Test name
Test status
Simulation time 21914025 ps
CPU time 0.86 seconds
Started Feb 01 12:39:26 PM PST 24
Finished Feb 01 12:40:18 PM PST 24
Peak memory 205000 kb
Host smart-a114ee1b-c457-446d-b48f-0b9592dc04ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859209758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1859209758
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4134138646
Short name T478
Test name
Test status
Simulation time 13273443 ps
CPU time 0.79 seconds
Started Feb 01 12:39:18 PM PST 24
Finished Feb 01 12:40:12 PM PST 24
Peak memory 204968 kb
Host smart-e71780b1-edd8-4191-a0c0-e9465a0ca8c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134138646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4134138646
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1137949379
Short name T438
Test name
Test status
Simulation time 60216808 ps
CPU time 0.69 seconds
Started Feb 01 12:39:18 PM PST 24
Finished Feb 01 12:40:12 PM PST 24
Peak memory 204976 kb
Host smart-9665fef3-5a5c-4b41-a2eb-d2d2b673389b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137949379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1137949379
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.598299394
Short name T537
Test name
Test status
Simulation time 22738849 ps
CPU time 0.84 seconds
Started Feb 01 12:39:28 PM PST 24
Finished Feb 01 12:40:19 PM PST 24
Peak memory 204912 kb
Host smart-7bedafe5-aeba-406a-91bf-b71b9d7f6147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598299394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.598299394
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.792571396
Short name T493
Test name
Test status
Simulation time 97890585 ps
CPU time 0.77 seconds
Started Feb 01 12:39:19 PM PST 24
Finished Feb 01 12:40:13 PM PST 24
Peak memory 205032 kb
Host smart-ee5775e8-a84a-4ddb-af5f-d1412cfa6fb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792571396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.792571396
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4196044347
Short name T180
Test name
Test status
Simulation time 42414053 ps
CPU time 0.76 seconds
Started Feb 01 12:39:28 PM PST 24
Finished Feb 01 12:40:19 PM PST 24
Peak memory 204904 kb
Host smart-5238771c-05e2-41d2-860e-1d45a9c80e2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196044347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.4196044347
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1192900765
Short name T479
Test name
Test status
Simulation time 9001682 ps
CPU time 0.69 seconds
Started Feb 01 12:39:19 PM PST 24
Finished Feb 01 12:40:12 PM PST 24
Peak memory 204952 kb
Host smart-c542ecc7-7344-484f-9ef1-6b8b9fd05fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192900765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1192900765
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3062950539
Short name T557
Test name
Test status
Simulation time 28624624 ps
CPU time 0.81 seconds
Started Feb 01 12:39:20 PM PST 24
Finished Feb 01 12:40:14 PM PST 24
Peak memory 205016 kb
Host smart-b99849ea-c115-4f81-a82e-e5ec277b85a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062950539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3062950539
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.428527393
Short name T511
Test name
Test status
Simulation time 22514331 ps
CPU time 1.07 seconds
Started Feb 01 12:38:28 PM PST 24
Finished Feb 01 12:39:30 PM PST 24
Peak memory 213388 kb
Host smart-7990bfe7-a8ee-407b-8d13-6878166b1ecf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428527393 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.428527393
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.905673469
Short name T542
Test name
Test status
Simulation time 65070715 ps
CPU time 1.18 seconds
Started Feb 01 12:38:25 PM PST 24
Finished Feb 01 12:39:28 PM PST 24
Peak memory 205044 kb
Host smart-032948d4-7119-4801-9fde-312a84b47ca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905673469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.905673469
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3062114634
Short name T555
Test name
Test status
Simulation time 13314826 ps
CPU time 0.71 seconds
Started Feb 01 12:38:20 PM PST 24
Finished Feb 01 12:39:23 PM PST 24
Peak memory 204928 kb
Host smart-e87eb272-f228-49e9-a660-9928c60b04ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062114634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3062114634
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4013411726
Short name T549
Test name
Test status
Simulation time 89171502 ps
CPU time 1.57 seconds
Started Feb 01 12:38:17 PM PST 24
Finished Feb 01 12:39:22 PM PST 24
Peak memory 205160 kb
Host smart-bce24d0b-a81a-4e41-94c9-7724b44a0b3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013411726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4013411726
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1776692923
Short name T174
Test name
Test status
Simulation time 3195550683 ps
CPU time 6.48 seconds
Started Feb 01 12:38:17 PM PST 24
Finished Feb 01 12:39:40 PM PST 24
Peak memory 213716 kb
Host smart-5cd5b336-51d3-4a21-aa28-954beb8e1b09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776692923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1776692923
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2524598667
Short name T531
Test name
Test status
Simulation time 392662361 ps
CPU time 5.6 seconds
Started Feb 01 12:38:27 PM PST 24
Finished Feb 01 12:39:39 PM PST 24
Peak memory 213904 kb
Host smart-6f563530-f15a-42ee-93ef-b73451aaa1f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524598667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2524598667
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3612003073
Short name T113
Test name
Test status
Simulation time 110220910 ps
CPU time 3.84 seconds
Started Feb 01 12:38:25 PM PST 24
Finished Feb 01 12:39:30 PM PST 24
Peak memory 213424 kb
Host smart-07902b76-b5de-43cf-9b90-380f1c49f25f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612003073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3612003073
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.628223198
Short name T156
Test name
Test status
Simulation time 1087195448 ps
CPU time 8.11 seconds
Started Feb 01 12:38:22 PM PST 24
Finished Feb 01 12:39:32 PM PST 24
Peak memory 208708 kb
Host smart-2df0f5a6-33f9-4fc3-b415-7d27d58f240a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628223198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
628223198
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3054281667
Short name T172
Test name
Test status
Simulation time 65040845 ps
CPU time 1.28 seconds
Started Feb 01 12:38:33 PM PST 24
Finished Feb 01 12:39:33 PM PST 24
Peak memory 213472 kb
Host smart-594f0146-b0be-46dc-8777-321fa6f05050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054281667 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3054281667
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.741992632
Short name T492
Test name
Test status
Simulation time 194660567 ps
CPU time 1.38 seconds
Started Feb 01 12:38:24 PM PST 24
Finished Feb 01 12:39:27 PM PST 24
Peak memory 205064 kb
Host smart-41c019ee-03ff-41a8-a2ad-775b6653cee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741992632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.741992632
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1210511866
Short name T539
Test name
Test status
Simulation time 12434504 ps
CPU time 0.72 seconds
Started Feb 01 12:38:21 PM PST 24
Finished Feb 01 12:39:26 PM PST 24
Peak memory 204968 kb
Host smart-d87cc2a1-8fde-49b5-895d-c01c1bac078b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210511866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1210511866
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3359575386
Short name T485
Test name
Test status
Simulation time 39971561 ps
CPU time 1.25 seconds
Started Feb 01 12:38:31 PM PST 24
Finished Feb 01 12:39:31 PM PST 24
Peak memory 205180 kb
Host smart-19ad1f7d-828f-4193-a433-05c91e68a2e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359575386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3359575386
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1086561386
Short name T167
Test name
Test status
Simulation time 520819515 ps
CPU time 4.56 seconds
Started Feb 01 12:38:26 PM PST 24
Finished Feb 01 12:39:31 PM PST 24
Peak memory 213560 kb
Host smart-8b55aa65-dba2-47bf-ace4-4442f331eabb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086561386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1086561386
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2541606075
Short name T124
Test name
Test status
Simulation time 22490284 ps
CPU time 1.78 seconds
Started Feb 01 12:38:16 PM PST 24
Finished Feb 01 12:39:21 PM PST 24
Peak memory 213392 kb
Host smart-f9401bd8-51c2-4132-bcfa-39c15c3bc4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541606075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2541606075
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.210378299
Short name T546
Test name
Test status
Simulation time 590246661 ps
CPU time 11 seconds
Started Feb 01 12:38:21 PM PST 24
Finished Feb 01 12:39:34 PM PST 24
Peak memory 213360 kb
Host smart-13c53c68-93a3-4baa-a44e-d8d31c96ee18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210378299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
210378299
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.574543385
Short name T443
Test name
Test status
Simulation time 23201258 ps
CPU time 1.14 seconds
Started Feb 01 12:38:22 PM PST 24
Finished Feb 01 12:39:25 PM PST 24
Peak memory 213460 kb
Host smart-664c2fb7-e115-4f5b-a3c6-dde3083d5277
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574543385 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.574543385
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2318381195
Short name T497
Test name
Test status
Simulation time 10774673 ps
CPU time 0.86 seconds
Started Feb 01 12:38:28 PM PST 24
Finished Feb 01 12:39:28 PM PST 24
Peak memory 204948 kb
Host smart-8a0fbdd7-3d73-4be7-ac51-3cb554d13ee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318381195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2318381195
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3114400831
Short name T135
Test name
Test status
Simulation time 333003837 ps
CPU time 3.08 seconds
Started Feb 01 12:38:28 PM PST 24
Finished Feb 01 12:39:31 PM PST 24
Peak memory 205176 kb
Host smart-8c37144d-143e-49ab-8f08-8a46e38079bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114400831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3114400831
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2187785535
Short name T554
Test name
Test status
Simulation time 642154532 ps
CPU time 3.79 seconds
Started Feb 01 12:38:28 PM PST 24
Finished Feb 01 12:39:31 PM PST 24
Peak memory 213588 kb
Host smart-96745053-b7bf-480c-ba0d-a55d198da47b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187785535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2187785535
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2603641310
Short name T110
Test name
Test status
Simulation time 852295335 ps
CPU time 15.25 seconds
Started Feb 01 12:38:36 PM PST 24
Finished Feb 01 12:39:51 PM PST 24
Peak memory 221780 kb
Host smart-105a8987-e344-42ae-983b-6bcf2aff0f4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603641310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2603641310
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1737251239
Short name T121
Test name
Test status
Simulation time 113287167 ps
CPU time 4.2 seconds
Started Feb 01 12:38:28 PM PST 24
Finished Feb 01 12:39:32 PM PST 24
Peak memory 213364 kb
Host smart-1d3a40b7-f0d1-45f5-a348-4f17d7613aea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737251239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1737251239
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.4089833232
Short name T120
Test name
Test status
Simulation time 719205483 ps
CPU time 21.11 seconds
Started Feb 01 12:38:28 PM PST 24
Finished Feb 01 12:39:49 PM PST 24
Peak memory 213432 kb
Host smart-3cc49679-bde8-4d9e-9016-d952ac695ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089833232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.4089833232
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.583447004
Short name T505
Test name
Test status
Simulation time 123520645 ps
CPU time 1.28 seconds
Started Feb 01 12:38:35 PM PST 24
Finished Feb 01 12:39:36 PM PST 24
Peak memory 205240 kb
Host smart-19c320e5-50dc-4062-9610-89a5d90d3b6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583447004 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.583447004
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2378841673
Short name T480
Test name
Test status
Simulation time 88679698 ps
CPU time 1.39 seconds
Started Feb 01 12:38:31 PM PST 24
Finished Feb 01 12:39:31 PM PST 24
Peak memory 205152 kb
Host smart-f36e4b7b-292a-41f1-b11e-d140a03cee0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378841673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2378841673
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1639279337
Short name T456
Test name
Test status
Simulation time 16477690 ps
CPU time 0.69 seconds
Started Feb 01 12:38:37 PM PST 24
Finished Feb 01 12:39:37 PM PST 24
Peak memory 205024 kb
Host smart-f7c1659f-422e-4076-bc3a-40448ff13e46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639279337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1639279337
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2308565632
Short name T477
Test name
Test status
Simulation time 167168057 ps
CPU time 3.38 seconds
Started Feb 01 12:38:26 PM PST 24
Finished Feb 01 12:39:30 PM PST 24
Peak memory 205164 kb
Host smart-a9c529e8-2d11-4a0f-b15c-b95ea27e2668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308565632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2308565632
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2292564409
Short name T165
Test name
Test status
Simulation time 430476253 ps
CPU time 3.35 seconds
Started Feb 01 12:38:38 PM PST 24
Finished Feb 01 12:39:40 PM PST 24
Peak memory 218276 kb
Host smart-f09c9047-f8eb-4495-8273-fb8ec6395fd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292564409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2292564409
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.4221101578
Short name T507
Test name
Test status
Simulation time 41094130 ps
CPU time 1.55 seconds
Started Feb 01 12:38:59 PM PST 24
Finished Feb 01 12:39:57 PM PST 24
Peak memory 213456 kb
Host smart-b611f92c-aceb-4924-8ec1-c6d6c14aaeb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221101578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.4221101578
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1163300186
Short name T523
Test name
Test status
Simulation time 25212378 ps
CPU time 1.38 seconds
Started Feb 01 12:38:34 PM PST 24
Finished Feb 01 12:39:34 PM PST 24
Peak memory 213352 kb
Host smart-a71aa6a4-5654-4b18-8e40-5f7d782856b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163300186 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1163300186
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2766290908
Short name T463
Test name
Test status
Simulation time 46717329 ps
CPU time 0.98 seconds
Started Feb 01 12:38:36 PM PST 24
Finished Feb 01 12:39:36 PM PST 24
Peak memory 205036 kb
Host smart-6b80f1e7-20c1-4bed-9bd6-094cb6c040c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766290908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2766290908
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.503807648
Short name T465
Test name
Test status
Simulation time 54558992 ps
CPU time 0.67 seconds
Started Feb 01 12:38:31 PM PST 24
Finished Feb 01 12:39:31 PM PST 24
Peak memory 204984 kb
Host smart-a8d1f47f-082a-4794-9dee-8b94d061afbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503807648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.503807648
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3441174103
Short name T564
Test name
Test status
Simulation time 191919412 ps
CPU time 5.58 seconds
Started Feb 01 12:38:36 PM PST 24
Finished Feb 01 12:39:42 PM PST 24
Peak memory 213600 kb
Host smart-55458148-78b0-4d2e-a2c3-739ac4a65397
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441174103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3441174103
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2259604255
Short name T148
Test name
Test status
Simulation time 121053027 ps
CPU time 2.57 seconds
Started Feb 01 12:38:38 PM PST 24
Finished Feb 01 12:39:40 PM PST 24
Peak memory 215680 kb
Host smart-1f155d5e-cfbb-4cd3-88ec-6aef574d6e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259604255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2259604255
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.825229815
Short name T348
Test name
Test status
Simulation time 129590039 ps
CPU time 2.6 seconds
Started Feb 01 03:45:44 PM PST 24
Finished Feb 01 03:46:40 PM PST 24
Peak memory 214216 kb
Host smart-e3bcf500-5eac-468f-8cbd-c834ed7794bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825229815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.825229815
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.180698160
Short name T898
Test name
Test status
Simulation time 742736783 ps
CPU time 22.35 seconds
Started Feb 01 03:44:19 PM PST 24
Finished Feb 01 03:45:15 PM PST 24
Peak memory 222328 kb
Host smart-e1e63aff-16f6-4bd3-ba45-600327146f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180698160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.180698160
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2318410803
Short name T701
Test name
Test status
Simulation time 380727708 ps
CPU time 2.99 seconds
Started Feb 01 03:45:28 PM PST 24
Finished Feb 01 03:46:18 PM PST 24
Peak memory 208748 kb
Host smart-9202f583-485c-4b76-8169-9300ca994cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318410803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2318410803
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2642053854
Short name T396
Test name
Test status
Simulation time 45899711 ps
CPU time 2.67 seconds
Started Feb 01 03:44:20 PM PST 24
Finished Feb 01 03:44:56 PM PST 24
Peak memory 208432 kb
Host smart-6dca4802-54b3-4a9a-a487-9ed67a704189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642053854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2642053854
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3014556874
Short name T47
Test name
Test status
Simulation time 130952680 ps
CPU time 5.14 seconds
Started Feb 01 03:44:20 PM PST 24
Finished Feb 01 03:44:59 PM PST 24
Peak memory 214168 kb
Host smart-ab14c202-7108-469f-ab67-506876e1cb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014556874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3014556874
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.4092391760
Short name T662
Test name
Test status
Simulation time 128766161 ps
CPU time 5.11 seconds
Started Feb 01 03:44:20 PM PST 24
Finished Feb 01 03:44:58 PM PST 24
Peak memory 214188 kb
Host smart-b48a6c52-bdf4-4b25-ac93-474d728770a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092391760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.4092391760
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1813064794
Short name T11
Test name
Test status
Simulation time 1020834772 ps
CPU time 27.84 seconds
Started Feb 01 03:44:18 PM PST 24
Finished Feb 01 03:45:19 PM PST 24
Peak memory 239952 kb
Host smart-da8f1e5d-08e1-40f1-8794-6902d2dfb36c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813064794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1813064794
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1484172006
Short name T730
Test name
Test status
Simulation time 72596028 ps
CPU time 3.37 seconds
Started Feb 01 03:44:08 PM PST 24
Finished Feb 01 03:44:40 PM PST 24
Peak memory 206916 kb
Host smart-cca16864-17a9-4cd1-9833-a0a923c54294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484172006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1484172006
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1368523816
Short name T651
Test name
Test status
Simulation time 94281151 ps
CPU time 1.83 seconds
Started Feb 01 03:44:17 PM PST 24
Finished Feb 01 03:44:52 PM PST 24
Peak memory 206796 kb
Host smart-c366e9d4-3474-44df-81a8-0f20bf829a78
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368523816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1368523816
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1980535853
Short name T962
Test name
Test status
Simulation time 409022313 ps
CPU time 3.83 seconds
Started Feb 01 03:44:57 PM PST 24
Finished Feb 01 03:45:29 PM PST 24
Peak memory 208604 kb
Host smart-dce38b44-594e-4291-85ca-a06f948fabf3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980535853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1980535853
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2392571750
Short name T776
Test name
Test status
Simulation time 165403501 ps
CPU time 3.83 seconds
Started Feb 01 03:44:19 PM PST 24
Finished Feb 01 03:44:56 PM PST 24
Peak memory 208696 kb
Host smart-2088acf9-6f07-47f9-9857-7f41a482a3b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392571750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2392571750
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3796403302
Short name T420
Test name
Test status
Simulation time 57066436 ps
CPU time 2.04 seconds
Started Feb 01 03:45:31 PM PST 24
Finished Feb 01 03:46:19 PM PST 24
Peak memory 215056 kb
Host smart-b5e21299-32fd-4b5c-a035-d718c53df385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796403302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3796403302
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3392815370
Short name T929
Test name
Test status
Simulation time 42128648 ps
CPU time 1.85 seconds
Started Feb 01 03:44:07 PM PST 24
Finished Feb 01 03:44:38 PM PST 24
Peak memory 208420 kb
Host smart-e5f8f17f-58af-4a34-9fe3-cca9d4297376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392815370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3392815370
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.261022202
Short name T627
Test name
Test status
Simulation time 42036521 ps
CPU time 3.36 seconds
Started Feb 01 03:44:23 PM PST 24
Finished Feb 01 03:44:57 PM PST 24
Peak memory 217708 kb
Host smart-ba4d9748-01f5-4c68-9cc6-da0d2138abb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261022202 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.261022202
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1411474809
Short name T319
Test name
Test status
Simulation time 2233442296 ps
CPU time 17.01 seconds
Started Feb 01 03:45:41 PM PST 24
Finished Feb 01 03:46:50 PM PST 24
Peak memory 218384 kb
Host smart-68b98452-47b0-4bf6-99d5-595b7aa11dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411474809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1411474809
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3090074489
Short name T841
Test name
Test status
Simulation time 39614416 ps
CPU time 2.35 seconds
Started Feb 01 03:44:19 PM PST 24
Finished Feb 01 03:44:54 PM PST 24
Peak memory 209904 kb
Host smart-5a72b18e-f7da-424e-be9e-9050ca86d9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090074489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3090074489
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3282094410
Short name T1064
Test name
Test status
Simulation time 16061637 ps
CPU time 0.98 seconds
Started Feb 01 03:44:38 PM PST 24
Finished Feb 01 03:45:08 PM PST 24
Peak memory 205972 kb
Host smart-f1bfd41c-a6a8-463e-86b3-94394b510d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282094410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3282094410
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3294545026
Short name T10
Test name
Test status
Simulation time 197889060 ps
CPU time 3.38 seconds
Started Feb 01 03:44:38 PM PST 24
Finished Feb 01 03:45:10 PM PST 24
Peak memory 221328 kb
Host smart-6f0cfc0a-e1b3-41df-b390-6c8e367e2d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294545026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3294545026
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3636626780
Short name T257
Test name
Test status
Simulation time 617842103 ps
CPU time 7.49 seconds
Started Feb 01 03:44:24 PM PST 24
Finished Feb 01 03:45:01 PM PST 24
Peak memory 209608 kb
Host smart-055bc34f-e4a0-4434-a76f-21eef8347fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636626780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3636626780
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1230968124
Short name T315
Test name
Test status
Simulation time 391146411 ps
CPU time 4.58 seconds
Started Feb 01 03:44:35 PM PST 24
Finished Feb 01 03:45:10 PM PST 24
Peak memory 208664 kb
Host smart-28be5f6b-e779-4fac-bf2f-30a8020810c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230968124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1230968124
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2723498225
Short name T777
Test name
Test status
Simulation time 294053691 ps
CPU time 2.13 seconds
Started Feb 01 03:44:24 PM PST 24
Finished Feb 01 03:44:56 PM PST 24
Peak memory 222252 kb
Host smart-876b807e-4974-44d0-9296-e7a17b9f8caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723498225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2723498225
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.836179513
Short name T860
Test name
Test status
Simulation time 340068876 ps
CPU time 3.96 seconds
Started Feb 01 03:44:56 PM PST 24
Finished Feb 01 03:45:27 PM PST 24
Peak memory 208788 kb
Host smart-793f10f9-66c8-481a-b3d3-b3a4e1d4f942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836179513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.836179513
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4256666406
Short name T749
Test name
Test status
Simulation time 279469849 ps
CPU time 5.35 seconds
Started Feb 01 03:45:48 PM PST 24
Finished Feb 01 03:46:49 PM PST 24
Peak memory 206604 kb
Host smart-37b9901d-3d0f-456e-ae08-bd3cb4262013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256666406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4256666406
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3715455841
Short name T1051
Test name
Test status
Simulation time 86829123 ps
CPU time 1.95 seconds
Started Feb 01 03:44:23 PM PST 24
Finished Feb 01 03:44:55 PM PST 24
Peak memory 208500 kb
Host smart-9c39e455-5094-462a-96b6-771ff8ef29b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715455841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3715455841
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3752354893
Short name T868
Test name
Test status
Simulation time 248567363 ps
CPU time 9.26 seconds
Started Feb 01 03:45:49 PM PST 24
Finished Feb 01 03:46:54 PM PST 24
Peak memory 207832 kb
Host smart-7ee09340-5d14-40af-b6d3-b3a8ca6f63f7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752354893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3752354893
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3522713468
Short name T1047
Test name
Test status
Simulation time 378376729 ps
CPU time 3.56 seconds
Started Feb 01 03:46:01 PM PST 24
Finished Feb 01 03:47:03 PM PST 24
Peak memory 206720 kb
Host smart-86327da2-98c9-4b28-a06f-67a726fe41b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522713468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3522713468
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_smoke.553582153
Short name T434
Test name
Test status
Simulation time 200994974 ps
CPU time 3.95 seconds
Started Feb 01 03:44:17 PM PST 24
Finished Feb 01 03:44:53 PM PST 24
Peak memory 208288 kb
Host smart-a4cbaa92-a818-4e17-943c-6c6e5ba3d65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553582153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.553582153
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1477267311
Short name T608
Test name
Test status
Simulation time 435064549 ps
CPU time 5.14 seconds
Started Feb 01 03:45:01 PM PST 24
Finished Feb 01 03:45:37 PM PST 24
Peak memory 222428 kb
Host smart-cb08d3db-e3cd-449b-b61b-81639f7895a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477267311 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1477267311
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3619468135
Short name T267
Test name
Test status
Simulation time 82719622 ps
CPU time 3.22 seconds
Started Feb 01 03:44:22 PM PST 24
Finished Feb 01 03:44:57 PM PST 24
Peak memory 214228 kb
Host smart-77ab635c-8583-4b75-8877-8ad368cd1d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619468135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3619468135
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1432240904
Short name T606
Test name
Test status
Simulation time 236644042 ps
CPU time 1.66 seconds
Started Feb 01 03:44:35 PM PST 24
Finished Feb 01 03:45:07 PM PST 24
Peak memory 209748 kb
Host smart-3d7f72a6-230b-4e65-9af8-a2cba21c6e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432240904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1432240904
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1959483084
Short name T915
Test name
Test status
Simulation time 25196338 ps
CPU time 0.76 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:08 PM PST 24
Peak memory 205712 kb
Host smart-55d986c3-1e9e-4330-bb94-0399847827b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959483084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1959483084
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2623302029
Short name T428
Test name
Test status
Simulation time 298257784 ps
CPU time 13.95 seconds
Started Feb 01 03:46:13 PM PST 24
Finished Feb 01 03:47:24 PM PST 24
Peak memory 214120 kb
Host smart-a72e66b3-229b-46cb-b5bd-90490da90154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623302029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2623302029
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1970063142
Short name T38
Test name
Test status
Simulation time 322385445 ps
CPU time 2.99 seconds
Started Feb 01 03:48:42 PM PST 24
Finished Feb 01 03:49:36 PM PST 24
Peak memory 208932 kb
Host smart-f9dd41e6-98a2-479c-9a65-695c03b5a6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970063142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1970063142
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3740354042
Short name T948
Test name
Test status
Simulation time 402001860 ps
CPU time 3.33 seconds
Started Feb 01 03:46:15 PM PST 24
Finished Feb 01 03:47:14 PM PST 24
Peak memory 207820 kb
Host smart-7ab00f2f-e832-48ab-9ad9-364658153dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740354042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3740354042
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3615626300
Short name T903
Test name
Test status
Simulation time 1284070557 ps
CPU time 8.21 seconds
Started Feb 01 03:46:17 PM PST 24
Finished Feb 01 03:47:22 PM PST 24
Peak memory 214248 kb
Host smart-9d05c09b-9e46-40b9-b33f-ec081be6056a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615626300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3615626300
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.776685468
Short name T221
Test name
Test status
Simulation time 92023708 ps
CPU time 3.72 seconds
Started Feb 01 03:46:25 PM PST 24
Finished Feb 01 03:47:24 PM PST 24
Peak memory 220332 kb
Host smart-d4b1a358-40e8-4132-96b3-ea9b380e8347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776685468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.776685468
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1280132676
Short name T926
Test name
Test status
Simulation time 1477874987 ps
CPU time 17.53 seconds
Started Feb 01 03:54:55 PM PST 24
Finished Feb 01 03:55:18 PM PST 24
Peak memory 208128 kb
Host smart-556fa0ae-6540-4f38-acba-4cd74d818b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280132676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1280132676
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1955528496
Short name T1031
Test name
Test status
Simulation time 2658761395 ps
CPU time 41.04 seconds
Started Feb 01 03:46:10 PM PST 24
Finished Feb 01 03:47:49 PM PST 24
Peak memory 207772 kb
Host smart-0b1553b5-a14e-4d63-86bb-792d84f5e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955528496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1955528496
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1953050716
Short name T371
Test name
Test status
Simulation time 1388357297 ps
CPU time 5.72 seconds
Started Feb 01 03:46:29 PM PST 24
Finished Feb 01 03:47:26 PM PST 24
Peak memory 207820 kb
Host smart-19397b52-4274-457c-8e7a-719141d3414f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953050716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1953050716
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1197150101
Short name T715
Test name
Test status
Simulation time 4732680483 ps
CPU time 59.33 seconds
Started Feb 01 03:46:47 PM PST 24
Finished Feb 01 03:48:33 PM PST 24
Peak memory 208408 kb
Host smart-dcf545f6-13f8-43fa-a1d0-9b83034a76cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197150101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1197150101
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3434509641
Short name T842
Test name
Test status
Simulation time 178329268 ps
CPU time 5.26 seconds
Started Feb 01 03:46:26 PM PST 24
Finished Feb 01 03:47:26 PM PST 24
Peak memory 208248 kb
Host smart-1fa9377f-a617-4f94-b987-793bd7e2afc7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434509641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3434509641
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.460177886
Short name T848
Test name
Test status
Simulation time 318667695 ps
CPU time 5.03 seconds
Started Feb 01 03:48:42 PM PST 24
Finished Feb 01 03:49:35 PM PST 24
Peak memory 207284 kb
Host smart-afd97ea3-69a1-4d31-b9b2-891f489cacc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460177886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.460177886
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.763178475
Short name T1056
Test name
Test status
Simulation time 20909276 ps
CPU time 1.67 seconds
Started Feb 01 03:45:52 PM PST 24
Finished Feb 01 03:46:49 PM PST 24
Peak memory 206792 kb
Host smart-465601eb-6e12-4e30-ac05-1b49adc03aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763178475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.763178475
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3330656990
Short name T243
Test name
Test status
Simulation time 1390648156 ps
CPU time 5.18 seconds
Started Feb 01 03:48:42 PM PST 24
Finished Feb 01 03:49:35 PM PST 24
Peak memory 220824 kb
Host smart-2db38eb3-f1d5-49da-9b7f-91041bc88a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330656990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3330656990
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2617756332
Short name T702
Test name
Test status
Simulation time 658439431 ps
CPU time 13.01 seconds
Started Feb 01 03:47:06 PM PST 24
Finished Feb 01 03:48:00 PM PST 24
Peak memory 222520 kb
Host smart-368aae7d-168a-4ee2-8e53-f14fc1148c22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617756332 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2617756332
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3066003964
Short name T1071
Test name
Test status
Simulation time 176254486 ps
CPU time 4.92 seconds
Started Feb 01 03:48:42 PM PST 24
Finished Feb 01 03:49:35 PM PST 24
Peak memory 216696 kb
Host smart-333ff4fd-a72c-4239-9014-388d87022a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066003964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3066003964
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.926172722
Short name T896
Test name
Test status
Simulation time 91711823 ps
CPU time 2.12 seconds
Started Feb 01 03:48:42 PM PST 24
Finished Feb 01 03:49:36 PM PST 24
Peak memory 208976 kb
Host smart-51a0ef29-d5cc-4a25-b192-d10500e47947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926172722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.926172722
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3254902376
Short name T803
Test name
Test status
Simulation time 11867839 ps
CPU time 0.67 seconds
Started Feb 01 03:48:56 PM PST 24
Finished Feb 01 03:49:56 PM PST 24
Peak memory 205468 kb
Host smart-b7070b52-74e2-4ce3-89b6-ff1f2b0dfd55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254902376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3254902376
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.795732721
Short name T1011
Test name
Test status
Simulation time 98713406 ps
CPU time 1.55 seconds
Started Feb 01 03:47:29 PM PST 24
Finished Feb 01 03:48:14 PM PST 24
Peak memory 207920 kb
Host smart-19b4e90d-4b2f-422c-bf1b-afb4572cc279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795732721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.795732721
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2802965030
Short name T1015
Test name
Test status
Simulation time 1727618029 ps
CPU time 47.23 seconds
Started Feb 01 03:46:55 PM PST 24
Finished Feb 01 03:48:26 PM PST 24
Peak memory 221800 kb
Host smart-a14f9c35-7600-4d76-be8a-abeab805e2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802965030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2802965030
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1984349737
Short name T747
Test name
Test status
Simulation time 108481160 ps
CPU time 3.36 seconds
Started Feb 01 03:48:42 PM PST 24
Finished Feb 01 03:49:37 PM PST 24
Peak memory 221904 kb
Host smart-8a6928f7-f417-4787-a6ad-c366f5586e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984349737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1984349737
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.466956180
Short name T891
Test name
Test status
Simulation time 312264821 ps
CPU time 8.39 seconds
Started Feb 01 03:46:30 PM PST 24
Finished Feb 01 03:47:31 PM PST 24
Peak memory 214240 kb
Host smart-d976556d-afd0-480a-805d-59fcaa773993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466956180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.466956180
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2364084355
Short name T351
Test name
Test status
Simulation time 26787530 ps
CPU time 2.09 seconds
Started Feb 01 03:48:42 PM PST 24
Finished Feb 01 03:49:35 PM PST 24
Peak memory 207592 kb
Host smart-aa366e2a-54ac-4e7b-a3d3-b74dca8c4dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364084355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2364084355
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.63528624
Short name T772
Test name
Test status
Simulation time 89778272 ps
CPU time 2.45 seconds
Started Feb 01 03:46:47 PM PST 24
Finished Feb 01 03:47:36 PM PST 24
Peak memory 207156 kb
Host smart-2e3d656f-9592-44cf-a05a-42517589a973
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63528624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.63528624
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3331387745
Short name T75
Test name
Test status
Simulation time 339140478 ps
CPU time 3.64 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:11 PM PST 24
Peak memory 208508 kb
Host smart-c3efd53f-4c55-4999-97dd-29cceebeeb7c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331387745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3331387745
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2272489711
Short name T291
Test name
Test status
Simulation time 137866275 ps
CPU time 2.17 seconds
Started Feb 01 03:47:24 PM PST 24
Finished Feb 01 03:48:08 PM PST 24
Peak memory 209184 kb
Host smart-5f3cf24e-e12a-4fe3-88de-2c20b4daa10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272489711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2272489711
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.477138147
Short name T784
Test name
Test status
Simulation time 837540955 ps
CPU time 3.8 seconds
Started Feb 01 03:46:29 PM PST 24
Finished Feb 01 03:47:24 PM PST 24
Peak memory 208280 kb
Host smart-047c50d4-9396-41c9-9d92-6001ca14ad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477138147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.477138147
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3295711431
Short name T834
Test name
Test status
Simulation time 464756317 ps
CPU time 10.75 seconds
Started Feb 01 03:48:43 PM PST 24
Finished Feb 01 03:49:44 PM PST 24
Peak memory 222836 kb
Host smart-2db01eb9-d85d-47e2-9aa5-ececdfd041ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295711431 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3295711431
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.4209377294
Short name T837
Test name
Test status
Simulation time 115099052 ps
CPU time 3.7 seconds
Started Feb 01 03:46:35 PM PST 24
Finished Feb 01 03:47:29 PM PST 24
Peak memory 209644 kb
Host smart-93236f89-bef0-48af-b555-0a18c64afb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209377294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.4209377294
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.4283719516
Short name T709
Test name
Test status
Simulation time 37629323 ps
CPU time 0.73 seconds
Started Feb 01 03:47:13 PM PST 24
Finished Feb 01 03:47:53 PM PST 24
Peak memory 205780 kb
Host smart-94bf12ce-3d94-443b-92e6-23a04509a8c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283719516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.4283719516
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2456998224
Short name T31
Test name
Test status
Simulation time 1164330774 ps
CPU time 3.24 seconds
Started Feb 01 03:47:28 PM PST 24
Finished Feb 01 03:48:15 PM PST 24
Peak memory 217680 kb
Host smart-374f12bd-b469-4f2f-a3de-7c1f5319c08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456998224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2456998224
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.545054545
Short name T910
Test name
Test status
Simulation time 348926343 ps
CPU time 3.56 seconds
Started Feb 01 03:47:41 PM PST 24
Finished Feb 01 03:48:31 PM PST 24
Peak memory 209900 kb
Host smart-56283770-c8c6-4aa4-8b07-d39db0b93277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545054545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.545054545
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1553036059
Short name T86
Test name
Test status
Simulation time 357634700 ps
CPU time 12.46 seconds
Started Feb 01 03:46:28 PM PST 24
Finished Feb 01 03:47:32 PM PST 24
Peak memory 208860 kb
Host smart-2ec0a283-5e4c-49b2-84f2-1bd13c3a3ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553036059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1553036059
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1167120735
Short name T1046
Test name
Test status
Simulation time 71089683 ps
CPU time 3.26 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:11 PM PST 24
Peak memory 209512 kb
Host smart-4ba5876a-65b8-434d-bb35-f9691684cf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167120735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1167120735
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3987395183
Short name T905
Test name
Test status
Simulation time 791296096 ps
CPU time 5.92 seconds
Started Feb 01 03:47:05 PM PST 24
Finished Feb 01 03:47:52 PM PST 24
Peak memory 209624 kb
Host smart-601535cd-a74c-4dff-ab21-dcd0984c6a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987395183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3987395183
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1510165404
Short name T393
Test name
Test status
Simulation time 61100566 ps
CPU time 2.18 seconds
Started Feb 01 03:47:43 PM PST 24
Finished Feb 01 03:48:32 PM PST 24
Peak memory 206736 kb
Host smart-659c8550-73d2-42db-bdbe-763376db6896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510165404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1510165404
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3327322428
Short name T878
Test name
Test status
Simulation time 252782725 ps
CPU time 6.44 seconds
Started Feb 01 03:53:49 PM PST 24
Finished Feb 01 03:54:02 PM PST 24
Peak memory 207844 kb
Host smart-e4db8186-9aa1-412f-b9cd-bd4ffb63ab51
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327322428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3327322428
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2235132783
Short name T76
Test name
Test status
Simulation time 119310663 ps
CPU time 3.46 seconds
Started Feb 01 03:48:56 PM PST 24
Finished Feb 01 03:49:59 PM PST 24
Peak memory 206304 kb
Host smart-c7ba4e92-7384-4366-a1f7-27a87f2b0671
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235132783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2235132783
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1175312566
Short name T256
Test name
Test status
Simulation time 66891397 ps
CPU time 3.11 seconds
Started Feb 01 03:47:28 PM PST 24
Finished Feb 01 03:48:10 PM PST 24
Peak memory 207636 kb
Host smart-9aa677ea-9523-4960-b639-00686b382cd7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175312566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1175312566
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3479585650
Short name T1066
Test name
Test status
Simulation time 212884275 ps
CPU time 5.06 seconds
Started Feb 01 03:46:53 PM PST 24
Finished Feb 01 03:47:44 PM PST 24
Peak memory 215868 kb
Host smart-d6ff6643-5077-4176-b733-7865f6665d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479585650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3479585650
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3819813027
Short name T102
Test name
Test status
Simulation time 63378257 ps
CPU time 2.85 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:10 PM PST 24
Peak memory 206844 kb
Host smart-ecb9c222-72da-4a4e-96f2-9a2f48065f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819813027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3819813027
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.5524107
Short name T918
Test name
Test status
Simulation time 324111391 ps
CPU time 2.86 seconds
Started Feb 01 03:47:25 PM PST 24
Finished Feb 01 03:48:09 PM PST 24
Peak memory 218224 kb
Host smart-72c03819-3784-4c8b-8123-a7a993f396f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5524107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.5524107
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.800145826
Short name T370
Test name
Test status
Simulation time 2877021349 ps
CPU time 94.03 seconds
Started Feb 01 03:46:32 PM PST 24
Finished Feb 01 03:48:57 PM PST 24
Peak memory 209232 kb
Host smart-89954afe-169e-4b18-9591-a6bdda793126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800145826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.800145826
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1273899939
Short name T884
Test name
Test status
Simulation time 78219916 ps
CPU time 2.34 seconds
Started Feb 01 03:47:19 PM PST 24
Finished Feb 01 03:48:00 PM PST 24
Peak memory 209996 kb
Host smart-25da8d6d-d320-404b-af4b-3b05639af06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273899939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1273899939
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3856195562
Short name T761
Test name
Test status
Simulation time 65508485 ps
CPU time 0.87 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:12 PM PST 24
Peak memory 205788 kb
Host smart-419a9a83-e812-4436-9b28-fab8cbdfcc99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856195562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3856195562
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2295334374
Short name T65
Test name
Test status
Simulation time 127906127 ps
CPU time 3.01 seconds
Started Feb 01 03:47:17 PM PST 24
Finished Feb 01 03:47:59 PM PST 24
Peak memory 214512 kb
Host smart-6e5b1ffc-a50e-4f02-872a-8d613561949c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295334374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2295334374
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4001425187
Short name T45
Test name
Test status
Simulation time 45652126 ps
CPU time 2.52 seconds
Started Feb 01 03:47:08 PM PST 24
Finished Feb 01 03:47:52 PM PST 24
Peak memory 207172 kb
Host smart-61a6b6cf-e4d2-4ce2-a63a-dc26a69551ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001425187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4001425187
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.36312862
Short name T260
Test name
Test status
Simulation time 229318620 ps
CPU time 5.02 seconds
Started Feb 01 03:46:49 PM PST 24
Finished Feb 01 03:47:38 PM PST 24
Peak memory 222304 kb
Host smart-50357e9e-7b06-46fc-b930-6535ba67b99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36312862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.36312862
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1732712410
Short name T714
Test name
Test status
Simulation time 39060998 ps
CPU time 2.54 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:11 PM PST 24
Peak memory 209448 kb
Host smart-9804cbc5-449e-442f-9644-c4012729c502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732712410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1732712410
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.278392438
Short name T972
Test name
Test status
Simulation time 1338914397 ps
CPU time 4.74 seconds
Started Feb 01 03:47:25 PM PST 24
Finished Feb 01 03:48:11 PM PST 24
Peak memory 209172 kb
Host smart-1406814f-f524-4d73-bca8-0328ad31366b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278392438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.278392438
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.502490278
Short name T1038
Test name
Test status
Simulation time 121704117 ps
CPU time 3.59 seconds
Started Feb 01 03:47:25 PM PST 24
Finished Feb 01 03:48:09 PM PST 24
Peak memory 206416 kb
Host smart-43d16796-278f-4524-90a1-6f795816ca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502490278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.502490278
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1579807677
Short name T271
Test name
Test status
Simulation time 378290439 ps
CPU time 8.73 seconds
Started Feb 01 03:47:23 PM PST 24
Finished Feb 01 03:48:11 PM PST 24
Peak memory 208404 kb
Host smart-16c30d97-0777-420b-bde8-2351eb7f17d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579807677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1579807677
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1662074108
Short name T245
Test name
Test status
Simulation time 105591253 ps
CPU time 4.16 seconds
Started Feb 01 03:47:44 PM PST 24
Finished Feb 01 03:48:40 PM PST 24
Peak memory 207024 kb
Host smart-1302bd5a-36e8-47bc-87bf-5422ca3db428
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662074108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1662074108
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.4170606389
Short name T609
Test name
Test status
Simulation time 23229387 ps
CPU time 1.75 seconds
Started Feb 01 03:47:05 PM PST 24
Finished Feb 01 03:47:49 PM PST 24
Peak memory 206784 kb
Host smart-ec7ae407-e8b7-49c4-a9ae-b9a8fac1369b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170606389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4170606389
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3498972384
Short name T659
Test name
Test status
Simulation time 88215115 ps
CPU time 2.83 seconds
Started Feb 01 03:47:25 PM PST 24
Finished Feb 01 03:48:09 PM PST 24
Peak memory 207988 kb
Host smart-5919adb2-72f5-4341-b15a-3c5b7da11099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498972384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3498972384
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3217925049
Short name T849
Test name
Test status
Simulation time 200486896 ps
CPU time 6.94 seconds
Started Feb 01 03:47:15 PM PST 24
Finished Feb 01 03:48:03 PM PST 24
Peak memory 206612 kb
Host smart-9869ec80-9344-49f8-980f-86007c2f008d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217925049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3217925049
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.332574833
Short name T292
Test name
Test status
Simulation time 1177409539 ps
CPU time 10.21 seconds
Started Feb 01 03:47:43 PM PST 24
Finished Feb 01 03:48:44 PM PST 24
Peak memory 222176 kb
Host smart-3cd024c1-29e3-4536-ae67-00a5a87d9c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332574833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.332574833
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2339194070
Short name T208
Test name
Test status
Simulation time 849089143 ps
CPU time 7.65 seconds
Started Feb 01 03:49:02 PM PST 24
Finished Feb 01 03:50:25 PM PST 24
Peak memory 222384 kb
Host smart-1d725576-f51b-45f7-bbfd-ec9062507783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339194070 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2339194070
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.487023822
Short name T844
Test name
Test status
Simulation time 1571961394 ps
CPU time 8.68 seconds
Started Feb 01 03:46:59 PM PST 24
Finished Feb 01 03:47:53 PM PST 24
Peak memory 208784 kb
Host smart-29cab1dd-472b-4c51-bcff-c4a6b48571f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487023822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.487023822
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2505947762
Short name T52
Test name
Test status
Simulation time 848460614 ps
CPU time 3.19 seconds
Started Feb 01 03:47:28 PM PST 24
Finished Feb 01 03:48:15 PM PST 24
Peak memory 209596 kb
Host smart-4951ec4d-1da3-4d28-bf92-f3f6e02c6576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505947762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2505947762
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.112202940
Short name T569
Test name
Test status
Simulation time 10700961 ps
CPU time 0.72 seconds
Started Feb 01 03:47:43 PM PST 24
Finished Feb 01 03:48:35 PM PST 24
Peak memory 205804 kb
Host smart-f8f608ce-41c5-45c8-906e-f2dfc0c56dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112202940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.112202940
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2566103027
Short name T775
Test name
Test status
Simulation time 78062594 ps
CPU time 2.86 seconds
Started Feb 01 03:52:47 PM PST 24
Finished Feb 01 03:52:56 PM PST 24
Peak memory 215132 kb
Host smart-c4813393-274e-4ef0-811a-5a2ee025fdbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566103027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2566103027
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4159185868
Short name T960
Test name
Test status
Simulation time 97970680 ps
CPU time 3.92 seconds
Started Feb 01 03:47:30 PM PST 24
Finished Feb 01 03:48:19 PM PST 24
Peak memory 221332 kb
Host smart-2b8337c3-843c-49e5-b9cb-ca3d3d1c4167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159185868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4159185868
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2533609545
Short name T360
Test name
Test status
Simulation time 101700480 ps
CPU time 3.85 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:15 PM PST 24
Peak memory 210052 kb
Host smart-1194dda3-c2bc-4f51-ad23-ccef6133ef04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533609545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2533609545
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.177679587
Short name T80
Test name
Test status
Simulation time 269264774 ps
CPU time 5.93 seconds
Started Feb 01 03:47:23 PM PST 24
Finished Feb 01 03:48:09 PM PST 24
Peak memory 219340 kb
Host smart-4e4c5cb5-3b29-4984-9c42-8f97d802f18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177679587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.177679587
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1079539584
Short name T301
Test name
Test status
Simulation time 220541866 ps
CPU time 6.89 seconds
Started Feb 01 03:47:16 PM PST 24
Finished Feb 01 03:48:04 PM PST 24
Peak memory 222216 kb
Host smart-c9d02d01-effc-459c-ba00-2aec910808e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079539584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1079539584
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4051180902
Short name T63
Test name
Test status
Simulation time 1329165249 ps
CPU time 3.76 seconds
Started Feb 01 03:47:07 PM PST 24
Finished Feb 01 03:47:53 PM PST 24
Peak memory 220140 kb
Host smart-c1129316-d953-4577-ac90-e334e48408d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051180902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4051180902
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2524343926
Short name T17
Test name
Test status
Simulation time 111076787 ps
CPU time 2.26 seconds
Started Feb 01 03:49:12 PM PST 24
Finished Feb 01 03:50:34 PM PST 24
Peak memory 207500 kb
Host smart-740dde42-5db3-43cd-aa20-be3a176ebf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524343926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2524343926
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1128054025
Short name T886
Test name
Test status
Simulation time 38434464 ps
CPU time 2.26 seconds
Started Feb 01 03:47:13 PM PST 24
Finished Feb 01 03:47:55 PM PST 24
Peak memory 206732 kb
Host smart-f94176f6-39ab-4003-84f9-93b37e4ea319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128054025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1128054025
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2383618830
Short name T941
Test name
Test status
Simulation time 177651252 ps
CPU time 2.6 seconds
Started Feb 01 03:49:11 PM PST 24
Finished Feb 01 03:50:33 PM PST 24
Peak memory 207544 kb
Host smart-3eb2aef5-60d0-4f46-8e0a-486df7531669
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383618830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2383618830
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1541922594
Short name T610
Test name
Test status
Simulation time 445438033 ps
CPU time 4.19 seconds
Started Feb 01 03:47:52 PM PST 24
Finished Feb 01 03:48:50 PM PST 24
Peak memory 208464 kb
Host smart-5878fcaa-19ad-4825-83ea-f8f418697458
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541922594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1541922594
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.4122067316
Short name T342
Test name
Test status
Simulation time 258683588 ps
CPU time 3.18 seconds
Started Feb 01 03:47:43 PM PST 24
Finished Feb 01 03:48:37 PM PST 24
Peak memory 208488 kb
Host smart-d5f30e92-27fd-4df4-9c5a-f8b764970e0f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122067316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4122067316
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1069796931
Short name T741
Test name
Test status
Simulation time 105744064 ps
CPU time 2.61 seconds
Started Feb 01 03:47:18 PM PST 24
Finished Feb 01 03:47:59 PM PST 24
Peak memory 207924 kb
Host smart-05f4cb78-ed93-44c3-bcd8-74d411a8f6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069796931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1069796931
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1018581533
Short name T573
Test name
Test status
Simulation time 272342605 ps
CPU time 4.08 seconds
Started Feb 01 03:47:10 PM PST 24
Finished Feb 01 03:47:53 PM PST 24
Peak memory 207536 kb
Host smart-a1c373ab-2cb9-454d-bc6d-f2a8af047244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018581533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1018581533
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.882263895
Short name T1027
Test name
Test status
Simulation time 491978191 ps
CPU time 9.6 seconds
Started Feb 01 03:52:17 PM PST 24
Finished Feb 01 03:52:35 PM PST 24
Peak memory 222556 kb
Host smart-38d620ac-28e8-475d-a01e-bbe6f33ff3b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882263895 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.882263895
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1304902438
Short name T273
Test name
Test status
Simulation time 89897751 ps
CPU time 3.1 seconds
Started Feb 01 03:47:38 PM PST 24
Finished Feb 01 03:48:28 PM PST 24
Peak memory 209908 kb
Host smart-428ff61f-ef61-42d5-9ac1-cafe7956a90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304902438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1304902438
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1199670166
Short name T888
Test name
Test status
Simulation time 863693878 ps
CPU time 3.04 seconds
Started Feb 01 03:47:50 PM PST 24
Finished Feb 01 03:48:43 PM PST 24
Peak memory 209840 kb
Host smart-aa6d39c6-a14e-428a-8898-76c8d8dc9f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199670166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1199670166
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2733552309
Short name T603
Test name
Test status
Simulation time 44698649 ps
CPU time 0.73 seconds
Started Feb 01 03:47:05 PM PST 24
Finished Feb 01 03:47:47 PM PST 24
Peak memory 205816 kb
Host smart-e1094d7f-50f6-424e-b18d-ea456706e234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733552309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2733552309
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2772000159
Short name T230
Test name
Test status
Simulation time 560107519 ps
CPU time 10.25 seconds
Started Feb 01 03:47:41 PM PST 24
Finished Feb 01 03:48:40 PM PST 24
Peak memory 222264 kb
Host smart-b2744708-c5b6-40d7-9ed6-a625b49061fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772000159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2772000159
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1619953061
Short name T71
Test name
Test status
Simulation time 29729262 ps
CPU time 1.73 seconds
Started Feb 01 03:47:09 PM PST 24
Finished Feb 01 03:47:51 PM PST 24
Peak memory 208292 kb
Host smart-cd34dd7e-4096-4a29-a574-49ab4a3171e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619953061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1619953061
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3980149324
Short name T959
Test name
Test status
Simulation time 66917038 ps
CPU time 3.21 seconds
Started Feb 01 03:47:19 PM PST 24
Finished Feb 01 03:48:00 PM PST 24
Peak memory 207788 kb
Host smart-60b083a1-1a76-47fb-b96b-14faebb6d467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980149324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3980149324
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.283934023
Short name T911
Test name
Test status
Simulation time 82332955 ps
CPU time 2.72 seconds
Started Feb 01 03:47:34 PM PST 24
Finished Feb 01 03:48:23 PM PST 24
Peak memory 209208 kb
Host smart-3ea6d78a-45ba-461a-83e2-66160e721146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283934023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.283934023
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3546677019
Short name T344
Test name
Test status
Simulation time 196052877 ps
CPU time 5.4 seconds
Started Feb 01 03:49:01 PM PST 24
Finished Feb 01 03:50:18 PM PST 24
Peak memory 207972 kb
Host smart-7516fc20-3234-4048-b5d4-c72c09a56ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546677019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3546677019
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2075266538
Short name T851
Test name
Test status
Simulation time 506063930 ps
CPU time 4.15 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:12 PM PST 24
Peak memory 206544 kb
Host smart-5ceedfa1-3d0c-42af-ac95-fec9a0c91252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075266538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2075266538
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1671944181
Short name T74
Test name
Test status
Simulation time 529419399 ps
CPU time 10.03 seconds
Started Feb 01 03:48:02 PM PST 24
Finished Feb 01 03:49:08 PM PST 24
Peak memory 207928 kb
Host smart-fbad767d-a3ac-415e-b15c-4b40ac82cd8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671944181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1671944181
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2422091420
Short name T615
Test name
Test status
Simulation time 2287689428 ps
CPU time 7.56 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:15 PM PST 24
Peak memory 207840 kb
Host smart-c25dae4f-e089-478f-b907-b31fbbafbe2c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422091420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2422091420
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2216367244
Short name T352
Test name
Test status
Simulation time 528578101 ps
CPU time 9.75 seconds
Started Feb 01 03:47:48 PM PST 24
Finished Feb 01 03:48:50 PM PST 24
Peak memory 208420 kb
Host smart-d335b99c-8764-4463-adc7-1ef8106ab598
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216367244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2216367244
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.932204337
Short name T931
Test name
Test status
Simulation time 109228171 ps
CPU time 2.93 seconds
Started Feb 01 03:48:47 PM PST 24
Finished Feb 01 03:49:42 PM PST 24
Peak memory 215212 kb
Host smart-6f10f3e1-3c7a-41e0-a0c9-1a3deaa47082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932204337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.932204337
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3637942232
Short name T1073
Test name
Test status
Simulation time 31517635 ps
CPU time 2.12 seconds
Started Feb 01 03:49:05 PM PST 24
Finished Feb 01 03:50:23 PM PST 24
Peak memory 206460 kb
Host smart-5b646e62-5eb6-4f62-b79b-6d28f777185c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637942232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3637942232
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2713184492
Short name T318
Test name
Test status
Simulation time 261538762 ps
CPU time 6.89 seconds
Started Feb 01 03:47:24 PM PST 24
Finished Feb 01 03:48:12 PM PST 24
Peak memory 223080 kb
Host smart-feb8db40-ce51-497a-9518-f1c559f32897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713184492 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2713184492
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3161397813
Short name T361
Test name
Test status
Simulation time 262976177 ps
CPU time 3.55 seconds
Started Feb 01 03:47:32 PM PST 24
Finished Feb 01 03:48:22 PM PST 24
Peak memory 208644 kb
Host smart-f341015a-6e6b-4319-a671-f72a97420e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161397813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3161397813
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1542242553
Short name T728
Test name
Test status
Simulation time 63136267 ps
CPU time 2.71 seconds
Started Feb 01 03:47:05 PM PST 24
Finished Feb 01 03:47:50 PM PST 24
Peak memory 210084 kb
Host smart-af3dadda-6bd7-4a43-ae3c-8ecca811477a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542242553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1542242553
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.465062355
Short name T699
Test name
Test status
Simulation time 79864460 ps
CPU time 0.72 seconds
Started Feb 01 03:48:44 PM PST 24
Finished Feb 01 03:49:32 PM PST 24
Peak memory 205404 kb
Host smart-0f3cf6c0-3a8d-45d5-907c-0e0d470894d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465062355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.465062355
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.367045187
Short name T1049
Test name
Test status
Simulation time 352030796 ps
CPU time 4.45 seconds
Started Feb 01 03:47:23 PM PST 24
Finished Feb 01 03:48:07 PM PST 24
Peak memory 214576 kb
Host smart-f3947713-fbcf-4e2c-95ee-7f1c27fad6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367045187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.367045187
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2742885439
Short name T930
Test name
Test status
Simulation time 107828249 ps
CPU time 2.83 seconds
Started Feb 01 03:47:25 PM PST 24
Finished Feb 01 03:48:09 PM PST 24
Peak memory 209112 kb
Host smart-f0269634-d8cf-4e2c-847a-659e3fc78096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742885439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2742885439
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1952271181
Short name T1021
Test name
Test status
Simulation time 48379392 ps
CPU time 3.04 seconds
Started Feb 01 03:47:44 PM PST 24
Finished Feb 01 03:48:38 PM PST 24
Peak memory 208400 kb
Host smart-47214e30-0eae-4b86-a5c4-d2c7dac85315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952271181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1952271181
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.114816831
Short name T716
Test name
Test status
Simulation time 1961410540 ps
CPU time 5.06 seconds
Started Feb 01 03:47:43 PM PST 24
Finished Feb 01 03:48:39 PM PST 24
Peak memory 208244 kb
Host smart-cd181e07-fb0e-4c49-8efe-cb1f613337f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114816831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.114816831
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.344864523
Short name T592
Test name
Test status
Simulation time 138569679 ps
CPU time 4.28 seconds
Started Feb 01 03:47:16 PM PST 24
Finished Feb 01 03:47:58 PM PST 24
Peak memory 209096 kb
Host smart-532aa2bf-c1e3-49b4-b2ba-cf3385897845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344864523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.344864523
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2492216931
Short name T810
Test name
Test status
Simulation time 315429299 ps
CPU time 3.32 seconds
Started Feb 01 03:48:47 PM PST 24
Finished Feb 01 03:49:42 PM PST 24
Peak memory 208268 kb
Host smart-d4a6f2b5-eab1-4501-a7d7-4fbf034215b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492216931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2492216931
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1100592598
Short name T814
Test name
Test status
Simulation time 1369294276 ps
CPU time 29.21 seconds
Started Feb 01 03:48:45 PM PST 24
Finished Feb 01 03:50:08 PM PST 24
Peak memory 207968 kb
Host smart-034f3756-3950-4338-90b8-023179568fbb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100592598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1100592598
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.832961530
Short name T734
Test name
Test status
Simulation time 38805649 ps
CPU time 1.73 seconds
Started Feb 01 03:47:29 PM PST 24
Finished Feb 01 03:48:14 PM PST 24
Peak memory 206732 kb
Host smart-74f4de68-46d1-4b1c-acbd-6133c1f4816f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832961530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.832961530
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2033454290
Short name T123
Test name
Test status
Simulation time 21858348 ps
CPU time 1.77 seconds
Started Feb 01 03:49:55 PM PST 24
Finished Feb 01 03:51:05 PM PST 24
Peak memory 206580 kb
Host smart-123bdff2-8558-484f-bc51-71ce2c6b7559
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033454290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2033454290
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.22380654
Short name T755
Test name
Test status
Simulation time 73237038 ps
CPU time 2 seconds
Started Feb 01 03:50:07 PM PST 24
Finished Feb 01 03:51:10 PM PST 24
Peak memory 207644 kb
Host smart-0b818b7b-dd3a-4bb6-844d-baeb3e801cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22380654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.22380654
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3364413733
Short name T403
Test name
Test status
Simulation time 742707942 ps
CPU time 7.81 seconds
Started Feb 01 03:47:22 PM PST 24
Finished Feb 01 03:48:10 PM PST 24
Peak memory 206616 kb
Host smart-79062e7b-bddc-4c02-b0af-cc4800ec08c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364413733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3364413733
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3487357020
Short name T585
Test name
Test status
Simulation time 264958424 ps
CPU time 5.02 seconds
Started Feb 01 03:47:06 PM PST 24
Finished Feb 01 03:47:52 PM PST 24
Peak memory 222604 kb
Host smart-999ed9d1-9af0-43e4-877f-898bbd547a41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487357020 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3487357020
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2043277508
Short name T378
Test name
Test status
Simulation time 4212417840 ps
CPU time 32.47 seconds
Started Feb 01 03:48:29 PM PST 24
Finished Feb 01 03:49:52 PM PST 24
Peak memory 219936 kb
Host smart-29e9a489-44f7-4715-95a8-1e727d607257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043277508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2043277508
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2474021747
Short name T802
Test name
Test status
Simulation time 101395206 ps
CPU time 0.78 seconds
Started Feb 01 03:47:51 PM PST 24
Finished Feb 01 03:48:45 PM PST 24
Peak memory 205792 kb
Host smart-5d3d1287-c857-4f81-bf24-954ae492b181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474021747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2474021747
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.164391459
Short name T418
Test name
Test status
Simulation time 582565347 ps
CPU time 3.87 seconds
Started Feb 01 03:51:24 PM PST 24
Finished Feb 01 03:52:04 PM PST 24
Peak memory 214124 kb
Host smart-18dffbf9-369f-486f-a32b-da2aee2d662d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164391459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.164391459
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3616751545
Short name T679
Test name
Test status
Simulation time 206145372 ps
CPU time 3.22 seconds
Started Feb 01 03:47:43 PM PST 24
Finished Feb 01 03:48:37 PM PST 24
Peak memory 208252 kb
Host smart-2f07c4c7-dba4-4358-b38c-e5a1872c4526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616751545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3616751545
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2487970869
Short name T1067
Test name
Test status
Simulation time 512283953 ps
CPU time 5.19 seconds
Started Feb 01 03:47:46 PM PST 24
Finished Feb 01 03:48:42 PM PST 24
Peak memory 214188 kb
Host smart-edfce835-24bd-48a9-8879-18b7ca35e362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487970869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2487970869
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1559342137
Short name T391
Test name
Test status
Simulation time 4872524527 ps
CPU time 13.13 seconds
Started Feb 01 03:47:20 PM PST 24
Finished Feb 01 03:48:13 PM PST 24
Peak memory 222408 kb
Host smart-c26c4a60-5e36-41bc-90fa-49373737b3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559342137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1559342137
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.806952953
Short name T843
Test name
Test status
Simulation time 902435630 ps
CPU time 4.46 seconds
Started Feb 01 03:47:40 PM PST 24
Finished Feb 01 03:48:36 PM PST 24
Peak memory 220168 kb
Host smart-9352bb67-6841-4c8c-9a6d-c34fbfe3f994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806952953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.806952953
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.871539733
Short name T1014
Test name
Test status
Simulation time 124499534 ps
CPU time 4.54 seconds
Started Feb 01 03:47:19 PM PST 24
Finished Feb 01 03:48:01 PM PST 24
Peak memory 208436 kb
Host smart-0520e6e9-7e0a-4a14-8efa-abd0e6ad60d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871539733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.871539733
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3534428555
Short name T1068
Test name
Test status
Simulation time 907352484 ps
CPU time 3.62 seconds
Started Feb 01 03:48:29 PM PST 24
Finished Feb 01 03:49:23 PM PST 24
Peak memory 205964 kb
Host smart-244cb4f7-041b-4ab0-8c8d-802f15eb2d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534428555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3534428555
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.600576369
Short name T688
Test name
Test status
Simulation time 409925026 ps
CPU time 3.64 seconds
Started Feb 01 03:47:24 PM PST 24
Finished Feb 01 03:48:09 PM PST 24
Peak memory 206836 kb
Host smart-27969e04-cd48-4be8-bd6d-4a5d04a257dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600576369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.600576369
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.4167030994
Short name T996
Test name
Test status
Simulation time 142156240 ps
CPU time 4.16 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:08 PM PST 24
Peak memory 207696 kb
Host smart-acfc3df4-b92e-4ad8-9400-8178a9b4fa06
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167030994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.4167030994
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1374514082
Short name T690
Test name
Test status
Simulation time 72365568 ps
CPU time 2.62 seconds
Started Feb 01 03:47:26 PM PST 24
Finished Feb 01 03:48:09 PM PST 24
Peak memory 208708 kb
Host smart-d193a433-3b47-4f84-80ec-fd33708f38d1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374514082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1374514082
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1963741960
Short name T332
Test name
Test status
Simulation time 75991477 ps
CPU time 3.03 seconds
Started Feb 01 03:50:48 PM PST 24
Finished Feb 01 03:51:43 PM PST 24
Peak memory 213792 kb
Host smart-5dac31fb-dcce-4203-afc4-ad98c722a34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963741960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1963741960
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2416105792
Short name T188
Test name
Test status
Simulation time 89049447 ps
CPU time 3.75 seconds
Started Feb 01 03:47:05 PM PST 24
Finished Feb 01 03:47:51 PM PST 24
Peak memory 208456 kb
Host smart-a9168f76-95cb-497f-8acf-e275895e9b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416105792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2416105792
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2947708752
Short name T277
Test name
Test status
Simulation time 710097924 ps
CPU time 19.25 seconds
Started Feb 01 03:50:37 PM PST 24
Finished Feb 01 03:51:49 PM PST 24
Peak memory 222036 kb
Host smart-0ac078ec-27dc-4abe-98a0-d16b928ddb86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947708752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2947708752
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1198519871
Short name T938
Test name
Test status
Simulation time 918193664 ps
CPU time 13.92 seconds
Started Feb 01 03:47:49 PM PST 24
Finished Feb 01 03:48:56 PM PST 24
Peak memory 222488 kb
Host smart-70e4ac35-a615-4b5e-ad12-5cf8e82f83e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198519871 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1198519871
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.476501605
Short name T895
Test name
Test status
Simulation time 142466240 ps
CPU time 4.4 seconds
Started Feb 01 03:47:14 PM PST 24
Finished Feb 01 03:47:59 PM PST 24
Peak memory 207636 kb
Host smart-245c6592-6614-4631-bcd2-fb9b0e321dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476501605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.476501605
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.419185490
Short name T667
Test name
Test status
Simulation time 45807296 ps
CPU time 2.26 seconds
Started Feb 01 03:47:26 PM PST 24
Finished Feb 01 03:48:09 PM PST 24
Peak memory 209756 kb
Host smart-30ba6f8f-0e0c-41be-8b7f-483e279a9e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419185490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.419185490
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3375218335
Short name T583
Test name
Test status
Simulation time 13308814 ps
CPU time 0.9 seconds
Started Feb 01 03:47:49 PM PST 24
Finished Feb 01 03:48:43 PM PST 24
Peak memory 205960 kb
Host smart-3a1f7241-7282-40e1-a522-2db8692b412e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375218335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3375218335
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2782676246
Short name T295
Test name
Test status
Simulation time 704658954 ps
CPU time 8.91 seconds
Started Feb 01 03:47:45 PM PST 24
Finished Feb 01 03:48:46 PM PST 24
Peak memory 214164 kb
Host smart-bd1920c7-97d8-4867-8b72-694851127fb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782676246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2782676246
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1159391703
Short name T212
Test name
Test status
Simulation time 94027326 ps
CPU time 3.25 seconds
Started Feb 01 03:47:35 PM PST 24
Finished Feb 01 03:48:24 PM PST 24
Peak memory 209156 kb
Host smart-a1791809-e862-4a1b-a069-71e485a0beff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159391703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1159391703
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4096624641
Short name T644
Test name
Test status
Simulation time 318068074 ps
CPU time 2.56 seconds
Started Feb 01 03:49:50 PM PST 24
Finished Feb 01 03:51:04 PM PST 24
Peak memory 208536 kb
Host smart-8c10ae4d-472b-42d1-bba6-1615540beec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096624641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4096624641
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.767740687
Short name T1054
Test name
Test status
Simulation time 417041863 ps
CPU time 5.23 seconds
Started Feb 01 03:47:46 PM PST 24
Finished Feb 01 03:48:42 PM PST 24
Peak memory 214180 kb
Host smart-5056173e-a6d1-4bff-b57c-1d409d8b5ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767740687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.767740687
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.494206046
Short name T200
Test name
Test status
Simulation time 400110763 ps
CPU time 3.08 seconds
Started Feb 01 03:47:36 PM PST 24
Finished Feb 01 03:48:23 PM PST 24
Peak memory 220224 kb
Host smart-6451f725-96b7-4c7c-bf8f-172ba31e267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494206046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.494206046
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.367716678
Short name T379
Test name
Test status
Simulation time 960963935 ps
CPU time 21.88 seconds
Started Feb 01 03:47:26 PM PST 24
Finished Feb 01 03:48:28 PM PST 24
Peak memory 209696 kb
Host smart-ac40a435-1b4f-45db-8bc3-0048a37496d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367716678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.367716678
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.440383470
Short name T225
Test name
Test status
Simulation time 80358040 ps
CPU time 1.78 seconds
Started Feb 01 03:47:31 PM PST 24
Finished Feb 01 03:48:19 PM PST 24
Peak memory 207324 kb
Host smart-1fb9daa0-de1b-4420-96bb-db515b8dd7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440383470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.440383470
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1024044775
Short name T357
Test name
Test status
Simulation time 1010852670 ps
CPU time 10.09 seconds
Started Feb 01 03:53:37 PM PST 24
Finished Feb 01 03:54:00 PM PST 24
Peak memory 207728 kb
Host smart-d939f12e-a07a-434e-9e31-b162fec111de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024044775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1024044775
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2340023676
Short name T825
Test name
Test status
Simulation time 1423813978 ps
CPU time 4.46 seconds
Started Feb 01 03:47:29 PM PST 24
Finished Feb 01 03:48:17 PM PST 24
Peak memory 208464 kb
Host smart-236e0df5-acbf-4fb1-bde4-5afe36f461b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340023676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2340023676
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2424015812
Short name T600
Test name
Test status
Simulation time 94570094 ps
CPU time 2.78 seconds
Started Feb 01 03:47:38 PM PST 24
Finished Feb 01 03:48:27 PM PST 24
Peak memory 206768 kb
Host smart-a546b5aa-8585-4b03-91bb-f96d01bc47c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424015812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2424015812
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.33831123
Short name T1043
Test name
Test status
Simulation time 145116718 ps
CPU time 3.97 seconds
Started Feb 01 03:47:25 PM PST 24
Finished Feb 01 03:48:11 PM PST 24
Peak memory 209388 kb
Host smart-f8f6d154-79ae-4637-8351-278f1207131f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33831123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.33831123
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1229307457
Short name T1044
Test name
Test status
Simulation time 3325008601 ps
CPU time 10.25 seconds
Started Feb 01 03:48:29 PM PST 24
Finished Feb 01 03:49:29 PM PST 24
Peak memory 208196 kb
Host smart-b8a1895a-9fa2-4ec2-83e7-7f3c9eb0da9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229307457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1229307457
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3809567574
Short name T202
Test name
Test status
Simulation time 180869336 ps
CPU time 5.32 seconds
Started Feb 01 03:47:36 PM PST 24
Finished Feb 01 03:48:29 PM PST 24
Peak memory 221352 kb
Host smart-c0ff5da7-d7ef-4951-b439-393037c68668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809567574 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3809567574
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.417412191
Short name T821
Test name
Test status
Simulation time 1197434007 ps
CPU time 7.84 seconds
Started Feb 01 03:50:34 PM PST 24
Finished Feb 01 03:51:35 PM PST 24
Peak memory 208464 kb
Host smart-ab5638d1-96f3-41f1-abe2-3fec07153de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417412191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.417412191
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3066794137
Short name T160
Test name
Test status
Simulation time 92779167 ps
CPU time 1.93 seconds
Started Feb 01 03:47:48 PM PST 24
Finished Feb 01 03:48:42 PM PST 24
Peak memory 209936 kb
Host smart-24c1b0bb-b40e-4c8b-8707-0743b04785a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066794137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3066794137
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3906582617
Short name T818
Test name
Test status
Simulation time 36100933 ps
CPU time 0.84 seconds
Started Feb 01 03:47:42 PM PST 24
Finished Feb 01 03:48:33 PM PST 24
Peak memory 205740 kb
Host smart-b69f5e86-8b82-4fd1-8763-c02ceba58a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906582617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3906582617
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3306691462
Short name T390
Test name
Test status
Simulation time 210702961 ps
CPU time 3.84 seconds
Started Feb 01 03:47:37 PM PST 24
Finished Feb 01 03:48:28 PM PST 24
Peak memory 214288 kb
Host smart-c60c7cf4-3a35-4429-81c0-12d2502668fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306691462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3306691462
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1355324943
Short name T969
Test name
Test status
Simulation time 99552235 ps
CPU time 4.5 seconds
Started Feb 01 03:47:48 PM PST 24
Finished Feb 01 03:48:43 PM PST 24
Peak memory 208536 kb
Host smart-04d66bec-cba8-4ecf-8151-87c41c083050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355324943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1355324943
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3308369084
Short name T281
Test name
Test status
Simulation time 73124077 ps
CPU time 2.42 seconds
Started Feb 01 03:53:06 PM PST 24
Finished Feb 01 03:53:27 PM PST 24
Peak memory 207632 kb
Host smart-73cd6a88-3953-4519-9c3c-00dca198648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308369084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3308369084
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.126622207
Short name T337
Test name
Test status
Simulation time 28070866 ps
CPU time 2.09 seconds
Started Feb 01 03:48:24 PM PST 24
Finished Feb 01 03:49:17 PM PST 24
Peak memory 208312 kb
Host smart-bd758759-532b-49a6-b136-e53669ababd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126622207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.126622207
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2164603779
Short name T936
Test name
Test status
Simulation time 733914160 ps
CPU time 8.44 seconds
Started Feb 01 03:48:02 PM PST 24
Finished Feb 01 03:49:06 PM PST 24
Peak memory 222292 kb
Host smart-6dfa2374-a217-42c1-85c0-5c571732e18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164603779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2164603779
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_random.476980417
Short name T813
Test name
Test status
Simulation time 133020150 ps
CPU time 2.47 seconds
Started Feb 01 03:47:36 PM PST 24
Finished Feb 01 03:48:26 PM PST 24
Peak memory 218144 kb
Host smart-60ffe4da-b345-4f1a-ba88-7559c21a2bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476980417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.476980417
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.589356740
Short name T900
Test name
Test status
Simulation time 76560091 ps
CPU time 1.78 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:09 PM PST 24
Peak memory 206528 kb
Host smart-91c7bea7-9735-4365-b8a1-b9cabc6fc35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589356740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.589356740
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2551204847
Short name T402
Test name
Test status
Simulation time 135283829 ps
CPU time 4.73 seconds
Started Feb 01 03:49:12 PM PST 24
Finished Feb 01 03:50:37 PM PST 24
Peak memory 207940 kb
Host smart-ae8654b8-90fc-459b-be0d-d3b1d30e5256
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551204847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2551204847
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1378403605
Short name T870
Test name
Test status
Simulation time 15930947731 ps
CPU time 44.37 seconds
Started Feb 01 03:49:52 PM PST 24
Finished Feb 01 03:51:44 PM PST 24
Peak memory 207356 kb
Host smart-271da232-2a80-4ac9-b953-0a1941023565
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378403605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1378403605
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.903873475
Short name T759
Test name
Test status
Simulation time 622300333 ps
CPU time 2.65 seconds
Started Feb 01 03:47:32 PM PST 24
Finished Feb 01 03:48:21 PM PST 24
Peak memory 206728 kb
Host smart-75fce217-1463-41e7-8116-ed3883a248a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903873475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.903873475
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4220181641
Short name T877
Test name
Test status
Simulation time 1838866872 ps
CPU time 17.92 seconds
Started Feb 01 03:47:50 PM PST 24
Finished Feb 01 03:49:02 PM PST 24
Peak memory 217436 kb
Host smart-7e5d4180-0562-43d1-8eb3-40eef4a5875f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220181641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4220181641
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1667633220
Short name T626
Test name
Test status
Simulation time 4030490909 ps
CPU time 34.59 seconds
Started Feb 01 03:54:15 PM PST 24
Finished Feb 01 03:54:54 PM PST 24
Peak memory 208836 kb
Host smart-dfb29fa9-521d-46be-9764-f7c0cead8d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667633220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1667633220
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3431601038
Short name T72
Test name
Test status
Simulation time 1318366857 ps
CPU time 33.1 seconds
Started Feb 01 03:47:47 PM PST 24
Finished Feb 01 03:49:10 PM PST 24
Peak memory 222412 kb
Host smart-345575f1-b16a-4561-bc40-1a24b141732b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431601038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3431601038
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1318646362
Short name T958
Test name
Test status
Simulation time 131246160 ps
CPU time 7.87 seconds
Started Feb 01 03:47:47 PM PST 24
Finished Feb 01 03:48:46 PM PST 24
Peak memory 219688 kb
Host smart-ec6f4666-ea7c-43e3-88c4-7f549536581f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318646362 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1318646362
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4222595764
Short name T574
Test name
Test status
Simulation time 143547763 ps
CPU time 2.84 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:10 PM PST 24
Peak memory 208776 kb
Host smart-e320a598-10bd-4a5a-b6fa-8079b4db50ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222595764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4222595764
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.770801515
Short name T411
Test name
Test status
Simulation time 48535716 ps
CPU time 1.81 seconds
Started Feb 01 03:47:43 PM PST 24
Finished Feb 01 03:48:35 PM PST 24
Peak memory 209644 kb
Host smart-ab3826cc-1ed1-46cb-ba13-a34c652c998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770801515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.770801515
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.495894971
Short name T723
Test name
Test status
Simulation time 39324111 ps
CPU time 0.72 seconds
Started Feb 01 03:44:56 PM PST 24
Finished Feb 01 03:45:24 PM PST 24
Peak memory 205712 kb
Host smart-d3dd8e65-506a-4a69-a572-018a7d0800da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495894971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.495894971
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1198631736
Short name T1050
Test name
Test status
Simulation time 726198434 ps
CPU time 2.14 seconds
Started Feb 01 03:44:30 PM PST 24
Finished Feb 01 03:45:02 PM PST 24
Peak memory 214164 kb
Host smart-a9bd44cb-3bad-44c9-8c11-acf82cdee4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198631736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1198631736
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1978262434
Short name T311
Test name
Test status
Simulation time 868157123 ps
CPU time 6.08 seconds
Started Feb 01 03:45:23 PM PST 24
Finished Feb 01 03:46:10 PM PST 24
Peak memory 214156 kb
Host smart-ffe909fb-3590-4ec0-9c48-f0387c9180ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978262434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1978262434
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2048365702
Short name T261
Test name
Test status
Simulation time 1244074436 ps
CPU time 6.19 seconds
Started Feb 01 03:44:33 PM PST 24
Finished Feb 01 03:45:09 PM PST 24
Peak memory 214168 kb
Host smart-4ca5cf97-5eab-4116-8b08-23a378fe6e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048365702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2048365702
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.822899636
Short name T43
Test name
Test status
Simulation time 1287824570 ps
CPU time 3.12 seconds
Started Feb 01 03:44:31 PM PST 24
Finished Feb 01 03:45:05 PM PST 24
Peak memory 209632 kb
Host smart-5396c44a-7c79-4202-874c-d41067994573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822899636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.822899636
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3924283468
Short name T279
Test name
Test status
Simulation time 448850893 ps
CPU time 13.36 seconds
Started Feb 01 03:44:30 PM PST 24
Finished Feb 01 03:45:12 PM PST 24
Peak memory 208724 kb
Host smart-1eee1ece-4d4e-429b-966b-01c750d1b3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924283468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3924283468
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1934786989
Short name T97
Test name
Test status
Simulation time 21291645157 ps
CPU time 97.19 seconds
Started Feb 01 03:44:32 PM PST 24
Finished Feb 01 03:46:40 PM PST 24
Peak memory 260364 kb
Host smart-e0c75ae9-d682-4572-871e-4071538c5842
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934786989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1934786989
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.151458921
Short name T187
Test name
Test status
Simulation time 206199412 ps
CPU time 2.57 seconds
Started Feb 01 03:44:33 PM PST 24
Finished Feb 01 03:45:05 PM PST 24
Peak memory 206568 kb
Host smart-801b341c-c592-449f-8a9a-c9a552ec7422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151458921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.151458921
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1495639323
Short name T661
Test name
Test status
Simulation time 226654883 ps
CPU time 2.64 seconds
Started Feb 01 03:44:30 PM PST 24
Finished Feb 01 03:45:03 PM PST 24
Peak memory 206864 kb
Host smart-7f9bb8c9-a85f-421e-ab9a-5609eb1b2a42
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495639323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1495639323
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.998391868
Short name T665
Test name
Test status
Simulation time 402693003 ps
CPU time 4.02 seconds
Started Feb 01 03:44:49 PM PST 24
Finished Feb 01 03:45:20 PM PST 24
Peak memory 208356 kb
Host smart-96108f8c-e65d-4738-ac81-6bba34ace3e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998391868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.998391868
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1432747835
Short name T731
Test name
Test status
Simulation time 1404057382 ps
CPU time 28.42 seconds
Started Feb 01 03:44:32 PM PST 24
Finished Feb 01 03:45:30 PM PST 24
Peak memory 208088 kb
Host smart-6504bc41-4b9c-4ca9-99c9-169b99908378
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432747835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1432747835
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3406316909
Short name T944
Test name
Test status
Simulation time 46081691 ps
CPU time 1.88 seconds
Started Feb 01 03:44:33 PM PST 24
Finished Feb 01 03:45:05 PM PST 24
Peak memory 207672 kb
Host smart-cfe632bc-b045-49e7-80d5-839e1dcc5eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406316909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3406316909
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2617662289
Short name T582
Test name
Test status
Simulation time 283426949 ps
CPU time 3.08 seconds
Started Feb 01 03:44:32 PM PST 24
Finished Feb 01 03:45:05 PM PST 24
Peak memory 208328 kb
Host smart-6766fc2d-ce17-412c-a88b-975afcd74acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617662289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2617662289
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3041728109
Short name T823
Test name
Test status
Simulation time 189833095 ps
CPU time 4.82 seconds
Started Feb 01 03:44:38 PM PST 24
Finished Feb 01 03:45:11 PM PST 24
Peak memory 218004 kb
Host smart-5be5c5c2-4abe-403f-8e7d-6a5b5d29aba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041728109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3041728109
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1894072648
Short name T211
Test name
Test status
Simulation time 124016613 ps
CPU time 3.63 seconds
Started Feb 01 03:44:38 PM PST 24
Finished Feb 01 03:45:10 PM PST 24
Peak memory 220224 kb
Host smart-2200dfdf-2235-4e14-95b4-c1026450bffc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894072648 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1894072648
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1138874165
Short name T846
Test name
Test status
Simulation time 65517520 ps
CPU time 2.42 seconds
Started Feb 01 03:44:29 PM PST 24
Finished Feb 01 03:45:02 PM PST 24
Peak memory 207788 kb
Host smart-651cf2ed-1c7c-4d1b-bcd5-e1782885d7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138874165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1138874165
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1880317390
Short name T763
Test name
Test status
Simulation time 617004491 ps
CPU time 2.05 seconds
Started Feb 01 03:44:33 PM PST 24
Finished Feb 01 03:45:05 PM PST 24
Peak memory 209408 kb
Host smart-12316091-2d8d-4359-9a57-41a885aa7332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880317390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1880317390
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.290463056
Short name T733
Test name
Test status
Simulation time 45529195 ps
CPU time 0.71 seconds
Started Feb 01 03:48:01 PM PST 24
Finished Feb 01 03:48:59 PM PST 24
Peak memory 205816 kb
Host smart-8abd46db-617b-44af-ae0d-218f2a315618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290463056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.290463056
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.4091714765
Short name T791
Test name
Test status
Simulation time 497598349 ps
CPU time 5.18 seconds
Started Feb 01 03:47:39 PM PST 24
Finished Feb 01 03:48:34 PM PST 24
Peak memory 210520 kb
Host smart-46dd9d6b-51d6-4203-a5f2-f56b93df7445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091714765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.4091714765
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3776265855
Short name T1076
Test name
Test status
Simulation time 219049452 ps
CPU time 3.42 seconds
Started Feb 01 03:52:47 PM PST 24
Finished Feb 01 03:52:56 PM PST 24
Peak memory 209748 kb
Host smart-a7effe1d-31ca-490a-b915-bde0276574c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776265855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3776265855
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.324979654
Short name T757
Test name
Test status
Simulation time 59816572 ps
CPU time 2.28 seconds
Started Feb 01 03:47:39 PM PST 24
Finished Feb 01 03:48:31 PM PST 24
Peak memory 209744 kb
Host smart-10d27490-1469-40fd-b999-43aab12a6fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324979654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.324979654
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.4135149790
Short name T207
Test name
Test status
Simulation time 586693571 ps
CPU time 5.03 seconds
Started Feb 01 03:48:23 PM PST 24
Finished Feb 01 03:49:18 PM PST 24
Peak memory 222240 kb
Host smart-c835e222-d7de-4c96-9360-6bf7deb4fb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135149790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.4135149790
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3881056114
Short name T797
Test name
Test status
Simulation time 255752773 ps
CPU time 6.17 seconds
Started Feb 01 03:47:44 PM PST 24
Finished Feb 01 03:48:42 PM PST 24
Peak memory 207720 kb
Host smart-3921312a-59e0-48ef-8dde-4fc145382f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881056114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3881056114
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2693277892
Short name T692
Test name
Test status
Simulation time 2946542937 ps
CPU time 51.7 seconds
Started Feb 01 03:47:40 PM PST 24
Finished Feb 01 03:49:23 PM PST 24
Peak memory 207884 kb
Host smart-c595926c-17f1-440a-b623-86d48bb5b435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693277892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2693277892
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3705015737
Short name T925
Test name
Test status
Simulation time 1907636927 ps
CPU time 5.1 seconds
Started Feb 01 03:47:38 PM PST 24
Finished Feb 01 03:48:34 PM PST 24
Peak memory 206696 kb
Host smart-c3f75cf1-6c55-436f-8dd1-85865745b7af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705015737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3705015737
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2427423229
Short name T838
Test name
Test status
Simulation time 3141889049 ps
CPU time 21.74 seconds
Started Feb 01 03:47:50 PM PST 24
Finished Feb 01 03:49:04 PM PST 24
Peak memory 208556 kb
Host smart-3b0363cd-ab5a-4202-918e-06cde7b5459c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427423229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2427423229
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2746272142
Short name T928
Test name
Test status
Simulation time 58221006 ps
CPU time 2.06 seconds
Started Feb 01 03:51:57 PM PST 24
Finished Feb 01 03:52:18 PM PST 24
Peak memory 208708 kb
Host smart-484654e4-3cd2-46a2-92fe-4c34823346f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746272142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2746272142
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.679236065
Short name T127
Test name
Test status
Simulation time 34366568 ps
CPU time 1.89 seconds
Started Feb 01 03:53:20 PM PST 24
Finished Feb 01 03:53:39 PM PST 24
Peak memory 207804 kb
Host smart-08ce8170-ac46-481f-bda0-3cddaaeaf8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679236065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.679236065
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1255877651
Short name T656
Test name
Test status
Simulation time 38289780 ps
CPU time 2.3 seconds
Started Feb 01 03:47:41 PM PST 24
Finished Feb 01 03:48:34 PM PST 24
Peak memory 206540 kb
Host smart-d76a515b-d21b-4a36-ab6c-5dc9fbf5f730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255877651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1255877651
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.229836768
Short name T781
Test name
Test status
Simulation time 58840044 ps
CPU time 3.39 seconds
Started Feb 01 03:48:48 PM PST 24
Finished Feb 01 03:49:45 PM PST 24
Peak memory 208824 kb
Host smart-bdd75d18-c27e-479a-b764-653cbb3443d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229836768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.229836768
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.718975956
Short name T385
Test name
Test status
Simulation time 272780296 ps
CPU time 5.58 seconds
Started Feb 01 03:48:40 PM PST 24
Finished Feb 01 03:49:35 PM PST 24
Peak memory 222376 kb
Host smart-ab76b84e-3a17-49bf-898d-91e7d1100688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718975956 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.718975956
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2016871361
Short name T1041
Test name
Test status
Simulation time 2450134447 ps
CPU time 45.73 seconds
Started Feb 01 03:47:48 PM PST 24
Finished Feb 01 03:49:24 PM PST 24
Peak memory 214224 kb
Host smart-4fc1c07f-a8b6-4e43-bfd2-dc8885747b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016871361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2016871361
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3376086369
Short name T655
Test name
Test status
Simulation time 226937508 ps
CPU time 2.49 seconds
Started Feb 01 03:49:35 PM PST 24
Finished Feb 01 03:50:54 PM PST 24
Peak memory 209624 kb
Host smart-1cc9768c-eee6-453a-b598-5d1a54993247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376086369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3376086369
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2051217874
Short name T924
Test name
Test status
Simulation time 14307753 ps
CPU time 0.78 seconds
Started Feb 01 03:48:01 PM PST 24
Finished Feb 01 03:48:58 PM PST 24
Peak memory 205836 kb
Host smart-a8b97eb8-dadc-4ea7-8725-f9f768927fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051217874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2051217874
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2358510114
Short name T417
Test name
Test status
Simulation time 341695545 ps
CPU time 8.16 seconds
Started Feb 01 03:49:38 PM PST 24
Finished Feb 01 03:51:02 PM PST 24
Peak memory 213752 kb
Host smart-e1ae6723-6ca8-4801-9511-ca183c0e1d52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2358510114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2358510114
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1820477851
Short name T366
Test name
Test status
Simulation time 19993046 ps
CPU time 1.68 seconds
Started Feb 01 03:48:03 PM PST 24
Finished Feb 01 03:49:02 PM PST 24
Peak memory 207216 kb
Host smart-ea8b9353-65a9-436a-981d-74fe08892d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820477851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1820477851
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1182199225
Short name T987
Test name
Test status
Simulation time 113767101 ps
CPU time 3.66 seconds
Started Feb 01 03:48:01 PM PST 24
Finished Feb 01 03:49:01 PM PST 24
Peak memory 208544 kb
Host smart-33b936e3-4329-4440-ade0-46211ebc254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182199225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1182199225
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.91753995
Short name T233
Test name
Test status
Simulation time 1086689409 ps
CPU time 26.96 seconds
Started Feb 01 03:48:03 PM PST 24
Finished Feb 01 03:49:28 PM PST 24
Peak memory 214088 kb
Host smart-f7c4375b-f078-428c-848f-2e54278d6cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91753995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.91753995
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2531977374
Short name T893
Test name
Test status
Simulation time 179184892 ps
CPU time 2.89 seconds
Started Feb 01 03:47:56 PM PST 24
Finished Feb 01 03:48:54 PM PST 24
Peak memory 207664 kb
Host smart-dcdc2fc5-9f6b-4e9e-bb84-21cf86b2c452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531977374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2531977374
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2502840036
Short name T682
Test name
Test status
Simulation time 432831804 ps
CPU time 6.88 seconds
Started Feb 01 03:47:53 PM PST 24
Finished Feb 01 03:48:55 PM PST 24
Peak memory 208196 kb
Host smart-bb987c2d-25c4-4579-9ae0-d02966eced87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502840036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2502840036
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1003427428
Short name T384
Test name
Test status
Simulation time 39123102 ps
CPU time 2.38 seconds
Started Feb 01 03:50:26 PM PST 24
Finished Feb 01 03:51:24 PM PST 24
Peak memory 208260 kb
Host smart-eed0b81d-1b1f-4269-ba5d-4b1e12b049d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003427428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1003427428
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2349420782
Short name T621
Test name
Test status
Simulation time 4985231375 ps
CPU time 42.85 seconds
Started Feb 01 03:47:56 PM PST 24
Finished Feb 01 03:49:34 PM PST 24
Peak memory 208548 kb
Host smart-01ea303f-69ff-41c0-ba58-efd00dde0e1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349420782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2349420782
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.674734721
Short name T908
Test name
Test status
Simulation time 835517545 ps
CPU time 3.87 seconds
Started Feb 01 03:47:56 PM PST 24
Finished Feb 01 03:48:56 PM PST 24
Peak memory 206636 kb
Host smart-ccdae587-5968-4545-845c-6622ec6265eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674734721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.674734721
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3048185575
Short name T246
Test name
Test status
Simulation time 74834583 ps
CPU time 3.05 seconds
Started Feb 01 03:47:53 PM PST 24
Finished Feb 01 03:48:51 PM PST 24
Peak memory 208652 kb
Host smart-ad4fe250-15b5-4a90-ad07-9ff31a9ec88a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048185575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3048185575
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3747507749
Short name T290
Test name
Test status
Simulation time 188551053 ps
CPU time 3.97 seconds
Started Feb 01 03:49:29 PM PST 24
Finished Feb 01 03:50:53 PM PST 24
Peak memory 217380 kb
Host smart-3a4872c1-70b7-4167-8673-ab5f87e34098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747507749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3747507749
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.4276772528
Short name T856
Test name
Test status
Simulation time 98947807 ps
CPU time 1.75 seconds
Started Feb 01 03:50:55 PM PST 24
Finished Feb 01 03:51:47 PM PST 24
Peak memory 208224 kb
Host smart-837d849c-ade7-44d4-b896-52da48673f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276772528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.4276772528
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1783437510
Short name T232
Test name
Test status
Simulation time 477505751 ps
CPU time 16.52 seconds
Started Feb 01 03:53:26 PM PST 24
Finished Feb 01 03:53:59 PM PST 24
Peak memory 214812 kb
Host smart-7f833a49-7e8c-4940-b9ea-5618c18372a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783437510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1783437510
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2092397259
Short name T718
Test name
Test status
Simulation time 64954748 ps
CPU time 2.27 seconds
Started Feb 01 03:49:04 PM PST 24
Finished Feb 01 03:50:23 PM PST 24
Peak memory 214220 kb
Host smart-145a33f7-c9a6-4fb0-99c3-7780a8a0cae3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092397259 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2092397259
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3941942961
Short name T1062
Test name
Test status
Simulation time 209155425 ps
CPU time 4.54 seconds
Started Feb 01 03:47:55 PM PST 24
Finished Feb 01 03:48:56 PM PST 24
Peak memory 214140 kb
Host smart-e7cc71e4-54b9-4898-8891-b3accc08afb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941942961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3941942961
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1800714540
Short name T770
Test name
Test status
Simulation time 37526124 ps
CPU time 1.8 seconds
Started Feb 01 03:50:36 PM PST 24
Finished Feb 01 03:51:32 PM PST 24
Peak memory 209236 kb
Host smart-a9067a1c-9e38-4d97-81db-0f1e144b2f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800714540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1800714540
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1599410128
Short name T991
Test name
Test status
Simulation time 11737159 ps
CPU time 0.81 seconds
Started Feb 01 03:48:22 PM PST 24
Finished Feb 01 03:49:11 PM PST 24
Peak memory 205780 kb
Host smart-3aec7bd1-4130-4060-b3a0-d4498704948a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599410128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1599410128
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.872600249
Short name T303
Test name
Test status
Simulation time 157557846 ps
CPU time 2.97 seconds
Started Feb 01 03:48:15 PM PST 24
Finished Feb 01 03:49:10 PM PST 24
Peak memory 215416 kb
Host smart-8a29978c-2dd3-42fb-9787-4d0f5e08113b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872600249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.872600249
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1414881224
Short name T646
Test name
Test status
Simulation time 93587009 ps
CPU time 1.79 seconds
Started Feb 01 03:48:10 PM PST 24
Finished Feb 01 03:49:07 PM PST 24
Peak memory 214220 kb
Host smart-f9b8e16d-1b09-41d8-867f-0773a3e3b5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414881224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1414881224
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1350611273
Short name T771
Test name
Test status
Simulation time 1406526446 ps
CPU time 7.06 seconds
Started Feb 01 03:48:07 PM PST 24
Finished Feb 01 03:49:09 PM PST 24
Peak memory 218040 kb
Host smart-a5b0a1fd-cca6-450e-be9f-d7a8b9ad516a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350611273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1350611273
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.642708710
Short name T1020
Test name
Test status
Simulation time 118308804 ps
CPU time 4.14 seconds
Started Feb 01 03:48:11 PM PST 24
Finished Feb 01 03:49:10 PM PST 24
Peak memory 214184 kb
Host smart-5c4bb335-e472-4428-ac2c-0e6659dcbb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642708710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.642708710
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3289422946
Short name T240
Test name
Test status
Simulation time 743172269 ps
CPU time 8.31 seconds
Started Feb 01 03:49:12 PM PST 24
Finished Feb 01 03:50:40 PM PST 24
Peak memory 211392 kb
Host smart-cec74844-d39e-4dfe-8124-fcd5bfdcfbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289422946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3289422946
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1131469183
Short name T923
Test name
Test status
Simulation time 127274268 ps
CPU time 2.54 seconds
Started Feb 01 03:50:07 PM PST 24
Finished Feb 01 03:51:10 PM PST 24
Peak memory 218092 kb
Host smart-f444e6c4-6580-4c89-bbb5-d0b969e3367d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131469183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1131469183
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1781215578
Short name T807
Test name
Test status
Simulation time 185258395 ps
CPU time 4.45 seconds
Started Feb 01 03:48:12 PM PST 24
Finished Feb 01 03:49:11 PM PST 24
Peak memory 209592 kb
Host smart-7596ef2f-98d7-471e-8081-7e8e35433a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781215578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1781215578
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3539973889
Short name T359
Test name
Test status
Simulation time 4495166335 ps
CPU time 32.8 seconds
Started Feb 01 03:53:01 PM PST 24
Finished Feb 01 03:53:53 PM PST 24
Peak memory 208904 kb
Host smart-e4267d6b-ef2b-4907-87e9-2c7f2c6757ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539973889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3539973889
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1787018142
Short name T104
Test name
Test status
Simulation time 258007155 ps
CPU time 7.47 seconds
Started Feb 01 03:48:08 PM PST 24
Finished Feb 01 03:49:10 PM PST 24
Peak memory 208788 kb
Host smart-bebbf978-3b20-4855-b0c2-d28296d17272
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787018142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1787018142
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3649351924
Short name T857
Test name
Test status
Simulation time 461572938 ps
CPU time 3.55 seconds
Started Feb 01 03:48:15 PM PST 24
Finished Feb 01 03:49:10 PM PST 24
Peak memory 208256 kb
Host smart-41be7af5-aff7-4801-b292-788f211e572b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649351924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3649351924
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2597536211
Short name T751
Test name
Test status
Simulation time 71475200 ps
CPU time 2.6 seconds
Started Feb 01 03:48:13 PM PST 24
Finished Feb 01 03:49:10 PM PST 24
Peak memory 207272 kb
Host smart-3d98b860-47b4-42ce-a3ea-a31eb123fc0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597536211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2597536211
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.523756892
Short name T975
Test name
Test status
Simulation time 41742256 ps
CPU time 2.28 seconds
Started Feb 01 03:48:14 PM PST 24
Finished Feb 01 03:49:07 PM PST 24
Peak memory 208844 kb
Host smart-91564a6d-1c03-4f40-8cd0-cf65679c0863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523756892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.523756892
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1644850300
Short name T767
Test name
Test status
Simulation time 80406511 ps
CPU time 1.79 seconds
Started Feb 01 03:48:48 PM PST 24
Finished Feb 01 03:49:44 PM PST 24
Peak memory 206540 kb
Host smart-d55fcac1-6e35-4a79-8197-6dba93dc75ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644850300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1644850300
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2981383424
Short name T947
Test name
Test status
Simulation time 90861431 ps
CPU time 2.8 seconds
Started Feb 01 03:49:12 PM PST 24
Finished Feb 01 03:50:35 PM PST 24
Peak memory 218244 kb
Host smart-927fb2fd-773c-4538-83fe-c6696071e275
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981383424 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2981383424
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1022123924
Short name T270
Test name
Test status
Simulation time 138824167 ps
CPU time 5.3 seconds
Started Feb 01 03:48:13 PM PST 24
Finished Feb 01 03:49:13 PM PST 24
Peak memory 218100 kb
Host smart-b49e4acf-2bba-46fb-be5d-02ccb46003ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022123924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1022123924
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1201430951
Short name T720
Test name
Test status
Simulation time 175525276 ps
CPU time 2.43 seconds
Started Feb 01 03:48:13 PM PST 24
Finished Feb 01 03:49:10 PM PST 24
Peak memory 209692 kb
Host smart-61d7583f-86f9-46a4-a456-e53eae6880d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201430951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1201430951
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2558588188
Short name T742
Test name
Test status
Simulation time 14804022 ps
CPU time 0.89 seconds
Started Feb 01 03:48:39 PM PST 24
Finished Feb 01 03:49:31 PM PST 24
Peak memory 206028 kb
Host smart-ddd55896-b3e1-43ff-932f-f1816601fc8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558588188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2558588188
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2911757714
Short name T599
Test name
Test status
Simulation time 402916547 ps
CPU time 2.7 seconds
Started Feb 01 03:48:19 PM PST 24
Finished Feb 01 03:49:14 PM PST 24
Peak memory 207212 kb
Host smart-a9befbe9-358c-4a57-8a5f-03dba70f2161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911757714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2911757714
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2457676406
Short name T927
Test name
Test status
Simulation time 157203120 ps
CPU time 4.7 seconds
Started Feb 01 03:48:46 PM PST 24
Finished Feb 01 03:49:44 PM PST 24
Peak memory 214248 kb
Host smart-3abd51b5-5d81-4dbe-9f20-cf0a15f57cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457676406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2457676406
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2165645439
Short name T190
Test name
Test status
Simulation time 165683763 ps
CPU time 6.5 seconds
Started Feb 01 03:48:19 PM PST 24
Finished Feb 01 03:49:18 PM PST 24
Peak memory 222468 kb
Host smart-977fa843-42d5-49f0-8be7-245b7acfcd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165645439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2165645439
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3441196499
Short name T136
Test name
Test status
Simulation time 2295945531 ps
CPU time 9.07 seconds
Started Feb 01 03:48:18 PM PST 24
Finished Feb 01 03:49:19 PM PST 24
Peak memory 222420 kb
Host smart-dbe37a97-3d70-4c59-987a-05f4987a19a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441196499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3441196499
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1011884455
Short name T296
Test name
Test status
Simulation time 1702098267 ps
CPU time 5.5 seconds
Started Feb 01 03:48:24 PM PST 24
Finished Feb 01 03:49:19 PM PST 24
Peak memory 214152 kb
Host smart-709e588e-76e2-440f-8464-6815210ae10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011884455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1011884455
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2457139718
Short name T753
Test name
Test status
Simulation time 67048530 ps
CPU time 2.39 seconds
Started Feb 01 03:50:05 PM PST 24
Finished Feb 01 03:51:09 PM PST 24
Peak memory 205884 kb
Host smart-07b82a8d-39e3-4f18-9513-13174ed87cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457139718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2457139718
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2698560218
Short name T623
Test name
Test status
Simulation time 162739225 ps
CPU time 3.09 seconds
Started Feb 01 03:48:35 PM PST 24
Finished Feb 01 03:49:28 PM PST 24
Peak memory 206628 kb
Host smart-d266ab89-bfe8-4119-847e-dbe7c5343902
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698560218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2698560218
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3596371754
Short name T98
Test name
Test status
Simulation time 443779938 ps
CPU time 5.05 seconds
Started Feb 01 03:53:54 PM PST 24
Finished Feb 01 03:54:05 PM PST 24
Peak memory 206840 kb
Host smart-4d47d5c7-7365-4d25-98cb-1561165f3737
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596371754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3596371754
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1703380775
Short name T16
Test name
Test status
Simulation time 49954384 ps
CPU time 2.68 seconds
Started Feb 01 03:48:19 PM PST 24
Finished Feb 01 03:49:14 PM PST 24
Peak memory 207896 kb
Host smart-df1421e1-c566-4c9d-ab55-f529a095230f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703380775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1703380775
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1089671230
Short name T788
Test name
Test status
Simulation time 250520758 ps
CPU time 2.87 seconds
Started Feb 01 03:48:18 PM PST 24
Finished Feb 01 03:49:14 PM PST 24
Peak memory 209616 kb
Host smart-7799dc31-8394-486d-a425-ba17a21ac714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089671230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1089671230
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1895668363
Short name T683
Test name
Test status
Simulation time 131963085 ps
CPU time 3 seconds
Started Feb 01 03:48:13 PM PST 24
Finished Feb 01 03:49:10 PM PST 24
Peak memory 207936 kb
Host smart-d9799ad1-130e-4f5d-ad7e-89643ca40d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895668363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1895668363
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3502674058
Short name T350
Test name
Test status
Simulation time 1205682692 ps
CPU time 16.05 seconds
Started Feb 01 03:48:18 PM PST 24
Finished Feb 01 03:49:27 PM PST 24
Peak memory 222440 kb
Host smart-9abfa0bc-909a-4c4f-bdac-e69b4d5a23e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502674058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3502674058
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3518737788
Short name T653
Test name
Test status
Simulation time 742852699 ps
CPU time 4.63 seconds
Started Feb 01 03:48:36 PM PST 24
Finished Feb 01 03:49:30 PM PST 24
Peak memory 222096 kb
Host smart-d874714c-dcbf-47e1-a404-a7a5ef946849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518737788 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3518737788
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2176250347
Short name T294
Test name
Test status
Simulation time 179065742 ps
CPU time 2.88 seconds
Started Feb 01 03:48:30 PM PST 24
Finished Feb 01 03:49:22 PM PST 24
Peak memory 207208 kb
Host smart-f2749404-491d-4b65-b078-da7305ddef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176250347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2176250347
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3926016900
Short name T689
Test name
Test status
Simulation time 73824672 ps
CPU time 2.73 seconds
Started Feb 01 03:48:17 PM PST 24
Finished Feb 01 03:49:10 PM PST 24
Peak memory 210052 kb
Host smart-a69ed84a-488e-4ac4-b78e-72c7f015c434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926016900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3926016900
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3604962950
Short name T965
Test name
Test status
Simulation time 39875251 ps
CPU time 0.73 seconds
Started Feb 01 03:48:57 PM PST 24
Finished Feb 01 03:49:57 PM PST 24
Peak memory 205804 kb
Host smart-71cfd461-d2d4-4dee-adf3-0499c5460476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604962950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3604962950
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2487320762
Short name T32
Test name
Test status
Simulation time 490697157 ps
CPU time 3.44 seconds
Started Feb 01 03:48:36 PM PST 24
Finished Feb 01 03:49:29 PM PST 24
Peak memory 219284 kb
Host smart-f8835d80-e407-4adc-aab4-506a5a1b709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487320762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2487320762
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3545488088
Short name T228
Test name
Test status
Simulation time 1234240048 ps
CPU time 3.44 seconds
Started Feb 01 03:51:42 PM PST 24
Finished Feb 01 03:52:11 PM PST 24
Peak memory 208408 kb
Host smart-65af6d0b-7688-40ba-9759-083c6ad8e2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545488088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3545488088
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3865362357
Short name T920
Test name
Test status
Simulation time 58743383 ps
CPU time 2.26 seconds
Started Feb 01 03:54:40 PM PST 24
Finished Feb 01 03:54:46 PM PST 24
Peak memory 218740 kb
Host smart-79f8d2d3-ba68-464d-8d83-c59d5462ee00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865362357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3865362357
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3060512625
Short name T597
Test name
Test status
Simulation time 84801973 ps
CPU time 3.56 seconds
Started Feb 01 03:48:38 PM PST 24
Finished Feb 01 03:49:33 PM PST 24
Peak memory 214172 kb
Host smart-fb4955e2-0aa2-4a69-9bb1-a3781280d7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060512625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3060512625
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.151862264
Short name T792
Test name
Test status
Simulation time 1159911126 ps
CPU time 29.99 seconds
Started Feb 01 03:48:31 PM PST 24
Finished Feb 01 03:49:48 PM PST 24
Peak memory 208024 kb
Host smart-9c2cfb27-879c-4a40-b444-f1639de1b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151862264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.151862264
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1067196496
Short name T859
Test name
Test status
Simulation time 440051964 ps
CPU time 2.67 seconds
Started Feb 01 03:48:32 PM PST 24
Finished Feb 01 03:49:25 PM PST 24
Peak memory 206812 kb
Host smart-f924d001-8d5e-47d9-8b19-74fc64ad4f37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067196496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1067196496
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.274001728
Short name T389
Test name
Test status
Simulation time 206485332 ps
CPU time 3.19 seconds
Started Feb 01 03:48:36 PM PST 24
Finished Feb 01 03:49:29 PM PST 24
Peak memory 206788 kb
Host smart-4252f435-18b3-45fe-b127-e23f5be100d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274001728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.274001728
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3137625930
Short name T890
Test name
Test status
Simulation time 7051636787 ps
CPU time 44.23 seconds
Started Feb 01 03:48:33 PM PST 24
Finished Feb 01 03:50:06 PM PST 24
Peak memory 209016 kb
Host smart-5268f647-a7b1-410d-8319-743dcd073f36
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137625930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3137625930
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3374143668
Short name T333
Test name
Test status
Simulation time 80545977 ps
CPU time 2.75 seconds
Started Feb 01 03:48:41 PM PST 24
Finished Feb 01 03:49:32 PM PST 24
Peak memory 217784 kb
Host smart-f31c52fa-fa9a-42c5-aec2-92e731de7820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374143668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3374143668
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2331478914
Short name T827
Test name
Test status
Simulation time 2078319006 ps
CPU time 44.06 seconds
Started Feb 01 03:48:40 PM PST 24
Finished Feb 01 03:50:15 PM PST 24
Peak memory 207776 kb
Host smart-3ff60c09-0485-4eeb-813d-98dbfeb3e673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331478914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2331478914
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.77677036
Short name T425
Test name
Test status
Simulation time 75530506 ps
CPU time 3.53 seconds
Started Feb 01 03:51:40 PM PST 24
Finished Feb 01 03:52:10 PM PST 24
Peak memory 207552 kb
Host smart-5b89bc29-e3f6-4a3e-a66b-962f8d086a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77677036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.77677036
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3220779077
Short name T1048
Test name
Test status
Simulation time 46170626 ps
CPU time 2.11 seconds
Started Feb 01 03:48:42 PM PST 24
Finished Feb 01 03:49:35 PM PST 24
Peak memory 209896 kb
Host smart-6075862f-60f2-4729-8baa-5d9966b5a38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220779077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3220779077
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1589766531
Short name T913
Test name
Test status
Simulation time 14313059 ps
CPU time 0.75 seconds
Started Feb 01 03:48:57 PM PST 24
Finished Feb 01 03:49:57 PM PST 24
Peak memory 205724 kb
Host smart-054d7644-efcd-43b8-ac24-92b82fdd2e26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589766531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1589766531
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.4087109548
Short name T1061
Test name
Test status
Simulation time 79283794 ps
CPU time 1.99 seconds
Started Feb 01 03:49:12 PM PST 24
Finished Feb 01 03:50:34 PM PST 24
Peak memory 214092 kb
Host smart-a3ce8e1b-4f42-4526-99eb-56b2fde30079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087109548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.4087109548
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2624241141
Short name T963
Test name
Test status
Simulation time 117174137 ps
CPU time 5.27 seconds
Started Feb 01 03:48:58 PM PST 24
Finished Feb 01 03:50:07 PM PST 24
Peak memory 210300 kb
Host smart-7b081490-56cf-4439-bb8e-bfe2b1457706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624241141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2624241141
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3582929251
Short name T782
Test name
Test status
Simulation time 602007770 ps
CPU time 11.24 seconds
Started Feb 01 03:49:06 PM PST 24
Finished Feb 01 03:50:29 PM PST 24
Peak memory 217988 kb
Host smart-dea26df3-5508-4469-a1c7-bbf982962c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582929251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3582929251
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1137971878
Short name T284
Test name
Test status
Simulation time 470027241 ps
CPU time 7.94 seconds
Started Feb 01 03:48:56 PM PST 24
Finished Feb 01 03:50:04 PM PST 24
Peak memory 210500 kb
Host smart-8799637c-dc02-459b-85bf-78094de582bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137971878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1137971878
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1964418430
Short name T368
Test name
Test status
Simulation time 180225737 ps
CPU time 2.78 seconds
Started Feb 01 03:48:56 PM PST 24
Finished Feb 01 03:49:59 PM PST 24
Peak memory 222436 kb
Host smart-d346052a-f2a3-4e3b-8251-796ddbf01b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964418430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1964418430
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3389835898
Short name T387
Test name
Test status
Simulation time 84591168 ps
CPU time 3.9 seconds
Started Feb 01 03:48:58 PM PST 24
Finished Feb 01 03:50:07 PM PST 24
Peak memory 208884 kb
Host smart-c4025ac1-bd19-4de9-bd60-90bda3d73933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389835898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3389835898
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2092030788
Short name T670
Test name
Test status
Simulation time 278308036 ps
CPU time 7.23 seconds
Started Feb 01 03:48:54 PM PST 24
Finished Feb 01 03:50:00 PM PST 24
Peak memory 208460 kb
Host smart-b4e384df-1e5f-4c96-8631-62e34bcbf091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092030788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2092030788
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.212654369
Short name T698
Test name
Test status
Simulation time 132893840 ps
CPU time 3.21 seconds
Started Feb 01 03:48:56 PM PST 24
Finished Feb 01 03:49:56 PM PST 24
Peak memory 206880 kb
Host smart-568e50f7-1c38-4bed-8e8d-08ec44a2c79a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212654369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.212654369
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3198725706
Short name T580
Test name
Test status
Simulation time 492511399 ps
CPU time 3.55 seconds
Started Feb 01 03:48:57 PM PST 24
Finished Feb 01 03:49:59 PM PST 24
Peak memory 206524 kb
Host smart-121b3488-0f7b-438e-93a4-c31729e2fd0a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198725706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3198725706
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2547369924
Short name T282
Test name
Test status
Simulation time 56612478 ps
CPU time 2.65 seconds
Started Feb 01 03:48:52 PM PST 24
Finished Feb 01 03:49:54 PM PST 24
Peak memory 206728 kb
Host smart-dcba5672-53c9-41c5-b7d9-f96947029326
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547369924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2547369924
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3775785064
Short name T400
Test name
Test status
Simulation time 121136350 ps
CPU time 3.1 seconds
Started Feb 01 03:48:58 PM PST 24
Finished Feb 01 03:50:04 PM PST 24
Peak memory 215324 kb
Host smart-5712fb5a-ff95-458e-9580-967edd08592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775785064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3775785064
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.4026110703
Short name T575
Test name
Test status
Simulation time 115501707 ps
CPU time 2.1 seconds
Started Feb 01 03:48:53 PM PST 24
Finished Feb 01 03:49:54 PM PST 24
Peak memory 206728 kb
Host smart-f9d44bac-451c-42c4-ae0d-3580ebd88666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026110703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4026110703
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2554167048
Short name T189
Test name
Test status
Simulation time 186415737 ps
CPU time 3.83 seconds
Started Feb 01 03:48:58 PM PST 24
Finished Feb 01 03:50:05 PM PST 24
Peak memory 206792 kb
Host smart-2507efc5-c2da-4670-b53e-6c8365de429b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554167048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2554167048
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1407057829
Short name T835
Test name
Test status
Simulation time 352045651 ps
CPU time 6.46 seconds
Started Feb 01 03:49:07 PM PST 24
Finished Feb 01 03:50:32 PM PST 24
Peak memory 222372 kb
Host smart-01e27767-8a66-4fa2-9342-48aeb5e6479e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407057829 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1407057829
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1221696674
Short name T970
Test name
Test status
Simulation time 597734820 ps
CPU time 18.49 seconds
Started Feb 01 03:49:52 PM PST 24
Finished Feb 01 03:51:18 PM PST 24
Peak memory 214176 kb
Host smart-0caaf9f2-dc1c-4955-b893-07e7ce9bd23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221696674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1221696674
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2292581552
Short name T933
Test name
Test status
Simulation time 264915135 ps
CPU time 2.52 seconds
Started Feb 01 03:48:52 PM PST 24
Finished Feb 01 03:49:48 PM PST 24
Peak memory 209624 kb
Host smart-144f6b15-9fd2-45c4-901b-886196a28061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292581552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2292581552
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2021996439
Short name T881
Test name
Test status
Simulation time 26505600 ps
CPU time 0.68 seconds
Started Feb 01 03:53:45 PM PST 24
Finished Feb 01 03:53:54 PM PST 24
Peak memory 205808 kb
Host smart-c3b64956-a8af-4eb1-bb1c-282b4b51a85b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021996439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2021996439
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.906514995
Short name T26
Test name
Test status
Simulation time 194197640 ps
CPU time 2.12 seconds
Started Feb 01 03:54:13 PM PST 24
Finished Feb 01 03:54:21 PM PST 24
Peak memory 222648 kb
Host smart-3e1f64d6-9fa2-4370-a0cc-79b28c4c4c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906514995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.906514995
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3140224970
Short name T66
Test name
Test status
Simulation time 158100354 ps
CPU time 3.8 seconds
Started Feb 01 03:49:03 PM PST 24
Finished Feb 01 03:50:21 PM PST 24
Peak memory 214096 kb
Host smart-a0ea9cdb-0900-4db7-a725-d6dbff75eeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140224970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3140224970
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.126630613
Short name T330
Test name
Test status
Simulation time 3422017458 ps
CPU time 35.28 seconds
Started Feb 01 03:49:02 PM PST 24
Finished Feb 01 03:50:45 PM PST 24
Peak memory 214192 kb
Host smart-90d28bbe-e7c5-4e34-a068-724d1d52033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126630613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.126630613
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.916686888
Short name T666
Test name
Test status
Simulation time 759448181 ps
CPU time 5.65 seconds
Started Feb 01 03:49:02 PM PST 24
Finished Feb 01 03:50:16 PM PST 24
Peak memory 207580 kb
Host smart-d51e2d55-ca45-4d87-adad-cf1e7ded2112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916686888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.916686888
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3359734388
Short name T875
Test name
Test status
Simulation time 84876457 ps
CPU time 4.42 seconds
Started Feb 01 03:48:57 PM PST 24
Finished Feb 01 03:50:05 PM PST 24
Peak memory 207156 kb
Host smart-17b0b3ce-0ca0-465a-bdb9-d39f71dbd5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359734388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3359734388
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.343230681
Short name T694
Test name
Test status
Simulation time 58482927 ps
CPU time 2.99 seconds
Started Feb 01 03:48:54 PM PST 24
Finished Feb 01 03:49:55 PM PST 24
Peak memory 208656 kb
Host smart-9852bbb6-c89f-406c-9c80-676e90eb888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343230681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.343230681
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1199213501
Short name T865
Test name
Test status
Simulation time 319460697 ps
CPU time 5.02 seconds
Started Feb 01 03:49:08 PM PST 24
Finished Feb 01 03:50:31 PM PST 24
Peak memory 207760 kb
Host smart-ce460451-f761-4261-badf-915954883850
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199213501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1199213501
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.293530581
Short name T873
Test name
Test status
Simulation time 249344432 ps
CPU time 6.17 seconds
Started Feb 01 03:49:08 PM PST 24
Finished Feb 01 03:50:32 PM PST 24
Peak memory 208432 kb
Host smart-78e2ce2a-5b3a-4417-b9ae-c43162ba6cd9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293530581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.293530581
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1506170414
Short name T356
Test name
Test status
Simulation time 225899374 ps
CPU time 3.18 seconds
Started Feb 01 03:48:56 PM PST 24
Finished Feb 01 03:49:57 PM PST 24
Peak memory 206764 kb
Host smart-50b0de44-4cf5-467a-8bdd-e16cd94fb05f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506170414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1506170414
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4232412456
Short name T1055
Test name
Test status
Simulation time 37896236 ps
CPU time 1.7 seconds
Started Feb 01 03:49:01 PM PST 24
Finished Feb 01 03:50:14 PM PST 24
Peak memory 207628 kb
Host smart-a517be81-d113-48dd-81ca-aba32b0175d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232412456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4232412456
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2705590340
Short name T786
Test name
Test status
Simulation time 678614649 ps
CPU time 7.11 seconds
Started Feb 01 03:48:54 PM PST 24
Finished Feb 01 03:50:00 PM PST 24
Peak memory 208296 kb
Host smart-edfa303e-b1ef-48e7-ad71-3519305fa244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705590340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2705590340
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.892085940
Short name T1074
Test name
Test status
Simulation time 792053222 ps
CPU time 5.26 seconds
Started Feb 01 03:49:02 PM PST 24
Finished Feb 01 03:50:23 PM PST 24
Peak memory 222440 kb
Host smart-bd196288-e6de-4707-a7b0-d77e709176fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892085940 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.892085940
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1077287599
Short name T985
Test name
Test status
Simulation time 104126723 ps
CPU time 5 seconds
Started Feb 01 03:49:00 PM PST 24
Finished Feb 01 03:50:13 PM PST 24
Peak memory 210096 kb
Host smart-e652833b-c32a-4722-943b-f48898ac0e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077287599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1077287599
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2306154180
Short name T164
Test name
Test status
Simulation time 285434300 ps
CPU time 8.83 seconds
Started Feb 01 03:54:18 PM PST 24
Finished Feb 01 03:54:32 PM PST 24
Peak memory 210816 kb
Host smart-b87aacb1-45bb-4564-b9fb-fb4f66b3aec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306154180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2306154180
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.333028584
Short name T953
Test name
Test status
Simulation time 73702901 ps
CPU time 0.82 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:05 PM PST 24
Peak memory 205660 kb
Host smart-553ca2da-26b9-43eb-a056-17a531ec9647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333028584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.333028584
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1044422678
Short name T1029
Test name
Test status
Simulation time 41630231 ps
CPU time 3.16 seconds
Started Feb 01 03:53:44 PM PST 24
Finished Feb 01 03:53:56 PM PST 24
Peak memory 215196 kb
Host smart-8cd6a86c-0ac6-43e6-add4-8ca5bc87cf24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044422678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1044422678
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3377931326
Short name T103
Test name
Test status
Simulation time 41991932 ps
CPU time 2.23 seconds
Started Feb 01 03:49:01 PM PST 24
Finished Feb 01 03:50:11 PM PST 24
Peak memory 207224 kb
Host smart-dc32661d-5156-4b75-b69a-e4f626e4a50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377931326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3377931326
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2531280713
Short name T808
Test name
Test status
Simulation time 604209277 ps
CPU time 7.38 seconds
Started Feb 01 03:49:02 PM PST 24
Finished Feb 01 03:50:18 PM PST 24
Peak memory 209284 kb
Host smart-676b6f0c-79bc-4698-b046-ec92e10d9156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531280713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2531280713
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2764858979
Short name T90
Test name
Test status
Simulation time 349919305 ps
CPU time 4.79 seconds
Started Feb 01 03:53:52 PM PST 24
Finished Feb 01 03:54:03 PM PST 24
Peak memory 214064 kb
Host smart-c6c00aac-1d7f-4670-a98b-778e76585a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764858979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2764858979
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.509262065
Short name T1006
Test name
Test status
Simulation time 88806654 ps
CPU time 3.98 seconds
Started Feb 01 03:48:59 PM PST 24
Finished Feb 01 03:50:09 PM PST 24
Peak memory 222292 kb
Host smart-c4180f5f-e287-42df-a457-2310cfd63210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509262065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.509262065
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.983016070
Short name T798
Test name
Test status
Simulation time 417815700 ps
CPU time 4.83 seconds
Started Feb 01 03:49:02 PM PST 24
Finished Feb 01 03:50:22 PM PST 24
Peak memory 210036 kb
Host smart-c10410d2-fdb9-4304-bfbf-4ad3c0cb5c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983016070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.983016070
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.17078697
Short name T327
Test name
Test status
Simulation time 409824847 ps
CPU time 4.08 seconds
Started Feb 01 03:49:03 PM PST 24
Finished Feb 01 03:50:21 PM PST 24
Peak memory 208552 kb
Host smart-e990be3b-3c94-4632-8b3b-e22ba37ac7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17078697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.17078697
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.4286929063
Short name T864
Test name
Test status
Simulation time 1437101368 ps
CPU time 34.74 seconds
Started Feb 01 03:50:35 PM PST 24
Finished Feb 01 03:52:04 PM PST 24
Peak memory 208056 kb
Host smart-76324802-8541-48d7-8d87-9868371f369c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286929063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.4286929063
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.468846151
Short name T901
Test name
Test status
Simulation time 97858558 ps
CPU time 2.73 seconds
Started Feb 01 03:49:59 PM PST 24
Finished Feb 01 03:51:06 PM PST 24
Peak memory 208312 kb
Host smart-c37111c9-43eb-4f26-82e1-d4a28c8585ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468846151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.468846151
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1235764816
Short name T828
Test name
Test status
Simulation time 121962617 ps
CPU time 2.3 seconds
Started Feb 01 03:52:12 PM PST 24
Finished Feb 01 03:52:27 PM PST 24
Peak memory 206696 kb
Host smart-2f61c8b5-c612-40b5-8911-5bf03b669b13
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235764816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1235764816
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2376546076
Short name T388
Test name
Test status
Simulation time 75684852 ps
CPU time 3.43 seconds
Started Feb 01 03:49:02 PM PST 24
Finished Feb 01 03:50:14 PM PST 24
Peak memory 209172 kb
Host smart-556519da-e3a8-4972-a260-31757b74ca42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376546076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2376546076
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3805920503
Short name T815
Test name
Test status
Simulation time 100171604 ps
CPU time 3.49 seconds
Started Feb 01 03:54:10 PM PST 24
Finished Feb 01 03:54:19 PM PST 24
Peak memory 207784 kb
Host smart-af2a8200-08c7-4e0a-835a-1b776c45abc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805920503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3805920503
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1438674425
Short name T866
Test name
Test status
Simulation time 189463409 ps
CPU time 9.45 seconds
Started Feb 01 03:49:35 PM PST 24
Finished Feb 01 03:51:02 PM PST 24
Peak memory 215924 kb
Host smart-53e55620-f37f-46c4-823a-fa1593e866b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438674425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1438674425
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2481598779
Short name T1042
Test name
Test status
Simulation time 111081555 ps
CPU time 4.15 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:07 PM PST 24
Peak memory 222288 kb
Host smart-24fedec5-10a2-4938-8ec7-4b38e5b55c14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481598779 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2481598779
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3253694456
Short name T619
Test name
Test status
Simulation time 310437931 ps
CPU time 3.54 seconds
Started Feb 01 03:48:59 PM PST 24
Finished Feb 01 03:50:09 PM PST 24
Peak memory 207320 kb
Host smart-27a1777c-7aad-40c0-bc8d-314ee2d87ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253694456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3253694456
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1726819882
Short name T591
Test name
Test status
Simulation time 268473311 ps
CPU time 3.55 seconds
Started Feb 01 03:49:02 PM PST 24
Finished Feb 01 03:50:14 PM PST 24
Peak memory 210404 kb
Host smart-1fe082b6-2b6a-4135-91a6-c0745f35288f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726819882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1726819882
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1570839762
Short name T570
Test name
Test status
Simulation time 49198338 ps
CPU time 0.79 seconds
Started Feb 01 03:50:15 PM PST 24
Finished Feb 01 03:51:13 PM PST 24
Peak memory 205720 kb
Host smart-e8a8f372-7d52-4bc7-94bd-c54ea81bd1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570839762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1570839762
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.406275602
Short name T1007
Test name
Test status
Simulation time 56973381 ps
CPU time 3.64 seconds
Started Feb 01 03:54:26 PM PST 24
Finished Feb 01 03:54:34 PM PST 24
Peak memory 214164 kb
Host smart-57779db7-ff68-44d2-bdbc-aebf247be4a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=406275602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.406275602
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2906582634
Short name T1018
Test name
Test status
Simulation time 49363401 ps
CPU time 2.04 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:05 PM PST 24
Peak memory 207556 kb
Host smart-92cd3aa7-f5c1-476e-9a07-3e020c02fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906582634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2906582634
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2276402708
Short name T95
Test name
Test status
Simulation time 515874464 ps
CPU time 6.66 seconds
Started Feb 01 03:54:36 PM PST 24
Finished Feb 01 03:54:47 PM PST 24
Peak memory 214248 kb
Host smart-da0d1b02-c69b-44ef-a3f2-f541fd82811e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276402708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2276402708
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1208176301
Short name T265
Test name
Test status
Simulation time 756319402 ps
CPU time 13.91 seconds
Started Feb 01 03:51:24 PM PST 24
Finished Feb 01 03:52:14 PM PST 24
Peak memory 222244 kb
Host smart-7eeaa965-c676-4b4c-ac7d-852356033f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208176301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1208176301
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3148373270
Short name T724
Test name
Test status
Simulation time 231147105 ps
CPU time 3.33 seconds
Started Feb 01 03:49:37 PM PST 24
Finished Feb 01 03:50:56 PM PST 24
Peak memory 209464 kb
Host smart-850e94a4-23a3-486e-a594-8031a16f92c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148373270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3148373270
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2332231279
Short name T382
Test name
Test status
Simulation time 182811417 ps
CPU time 3.29 seconds
Started Feb 01 03:50:33 PM PST 24
Finished Feb 01 03:51:27 PM PST 24
Peak memory 207548 kb
Host smart-ae901582-70f1-4d31-acc5-a70e6f66f19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332231279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2332231279
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.488911358
Short name T298
Test name
Test status
Simulation time 3674706053 ps
CPU time 37.53 seconds
Started Feb 01 03:54:19 PM PST 24
Finished Feb 01 03:55:01 PM PST 24
Peak memory 209052 kb
Host smart-f71f7e41-d90d-4e32-b259-fd9e46760c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488911358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.488911358
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1165769985
Short name T636
Test name
Test status
Simulation time 331966039 ps
CPU time 7.51 seconds
Started Feb 01 03:50:32 PM PST 24
Finished Feb 01 03:51:34 PM PST 24
Peak memory 208700 kb
Host smart-27084944-2a57-4e1f-a888-628d0107f497
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165769985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1165769985
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1306607325
Short name T1052
Test name
Test status
Simulation time 2838526886 ps
CPU time 32.85 seconds
Started Feb 01 03:51:17 PM PST 24
Finished Feb 01 03:52:29 PM PST 24
Peak memory 208504 kb
Host smart-51bbd1b0-8c54-4c69-a729-60d44ea96583
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306607325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1306607325
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1252819901
Short name T1009
Test name
Test status
Simulation time 88299142 ps
CPU time 1.28 seconds
Started Feb 01 03:54:07 PM PST 24
Finished Feb 01 03:54:14 PM PST 24
Peak memory 206608 kb
Host smart-533f0ebf-9394-432e-8288-a243955c5ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252819901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1252819901
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.425786636
Short name T607
Test name
Test status
Simulation time 26762629 ps
CPU time 1.88 seconds
Started Feb 01 03:50:06 PM PST 24
Finished Feb 01 03:51:09 PM PST 24
Peak memory 206644 kb
Host smart-f6ab1f50-26ae-49f5-993d-a1835f0891b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425786636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.425786636
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2039178151
Short name T934
Test name
Test status
Simulation time 280860464 ps
CPU time 6.61 seconds
Started Feb 01 03:49:46 PM PST 24
Finished Feb 01 03:51:05 PM PST 24
Peak memory 222476 kb
Host smart-86ace909-2ce1-4e66-9b1a-f4814f558a23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039178151 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2039178151
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.938014014
Short name T1053
Test name
Test status
Simulation time 80151241 ps
CPU time 3.02 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:06 PM PST 24
Peak memory 209672 kb
Host smart-7c56913d-c82c-42d9-9bc8-877ab0614df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938014014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.938014014
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.44365559
Short name T593
Test name
Test status
Simulation time 446370327 ps
CPU time 4.59 seconds
Started Feb 01 03:51:34 PM PST 24
Finished Feb 01 03:52:08 PM PST 24
Peak memory 210624 kb
Host smart-4776bdea-b153-495e-b440-dead4d0fa691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44365559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.44365559
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2641023556
Short name T577
Test name
Test status
Simulation time 23833640 ps
CPU time 0.76 seconds
Started Feb 01 03:50:22 PM PST 24
Finished Feb 01 03:51:18 PM PST 24
Peak memory 205756 kb
Host smart-91f86305-f9f3-4b60-82b0-69201b3bc90e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641023556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2641023556
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3291717859
Short name T426
Test name
Test status
Simulation time 40984303 ps
CPU time 2.91 seconds
Started Feb 01 03:49:42 PM PST 24
Finished Feb 01 03:50:59 PM PST 24
Peak memory 222340 kb
Host smart-b597be71-1f47-43cf-9b26-bc6bb12deb47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291717859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3291717859
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3483517468
Short name T1058
Test name
Test status
Simulation time 199938928 ps
CPU time 7.73 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:11 PM PST 24
Peak memory 220172 kb
Host smart-42799009-f867-4598-80ce-77573834542d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483517468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3483517468
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3716148083
Short name T614
Test name
Test status
Simulation time 104807714 ps
CPU time 3.71 seconds
Started Feb 01 03:52:24 PM PST 24
Finished Feb 01 03:52:31 PM PST 24
Peak memory 208032 kb
Host smart-1892fb96-3a22-4eb2-8ac9-e4178b7f097e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716148083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3716148083
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.4176502976
Short name T680
Test name
Test status
Simulation time 416317221 ps
CPU time 6.48 seconds
Started Feb 01 03:49:27 PM PST 24
Finished Feb 01 03:50:53 PM PST 24
Peak memory 214216 kb
Host smart-7c802546-b87c-4290-a74b-372d099b871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176502976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.4176502976
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3901464521
Short name T760
Test name
Test status
Simulation time 3565422912 ps
CPU time 24.82 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:21 PM PST 24
Peak memory 214016 kb
Host smart-703a2ee8-a802-4596-b91c-080472d9a2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901464521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3901464521
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2789444191
Short name T299
Test name
Test status
Simulation time 93528162 ps
CPU time 3.18 seconds
Started Feb 01 03:50:36 PM PST 24
Finished Feb 01 03:51:32 PM PST 24
Peak memory 214192 kb
Host smart-4e2adefb-2ad3-428a-b982-2f3c75de1ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789444191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2789444191
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1429912963
Short name T899
Test name
Test status
Simulation time 4812749983 ps
CPU time 32.25 seconds
Started Feb 01 03:49:52 PM PST 24
Finished Feb 01 03:51:34 PM PST 24
Peak memory 219824 kb
Host smart-763bf1de-fa48-480a-b6f0-6898369672e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429912963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1429912963
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2137701104
Short name T1036
Test name
Test status
Simulation time 533823343 ps
CPU time 9.56 seconds
Started Feb 01 03:50:35 PM PST 24
Finished Feb 01 03:51:38 PM PST 24
Peak memory 208312 kb
Host smart-dcfa94f5-1b75-4fb1-909f-396e27375c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137701104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2137701104
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.4039361510
Short name T334
Test name
Test status
Simulation time 35627675 ps
CPU time 2.32 seconds
Started Feb 01 03:49:41 PM PST 24
Finished Feb 01 03:50:59 PM PST 24
Peak memory 208180 kb
Host smart-1c0f3705-5e4c-4c27-830f-534a85b44bb7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039361510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.4039361510
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3435799448
Short name T1072
Test name
Test status
Simulation time 168836323 ps
CPU time 4.29 seconds
Started Feb 01 03:49:40 PM PST 24
Finished Feb 01 03:51:00 PM PST 24
Peak memory 208540 kb
Host smart-3b79e2d0-afa1-42b6-acb7-d1749aa993bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435799448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3435799448
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2640755444
Short name T1016
Test name
Test status
Simulation time 544570977 ps
CPU time 2.21 seconds
Started Feb 01 03:53:37 PM PST 24
Finished Feb 01 03:53:52 PM PST 24
Peak memory 206732 kb
Host smart-45d3ec5b-a66b-4892-b00b-9063a6f2d112
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640755444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2640755444
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1292844160
Short name T850
Test name
Test status
Simulation time 275609806 ps
CPU time 3.02 seconds
Started Feb 01 03:50:43 PM PST 24
Finished Feb 01 03:51:37 PM PST 24
Peak memory 209748 kb
Host smart-50022ec6-4d46-422a-806e-bb7c2ebdb963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292844160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1292844160
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1013514419
Short name T685
Test name
Test status
Simulation time 1217266733 ps
CPU time 15.36 seconds
Started Feb 01 03:49:36 PM PST 24
Finished Feb 01 03:51:08 PM PST 24
Peak memory 207644 kb
Host smart-9c01712e-5780-4f96-988a-78cd6abe726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013514419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1013514419
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1492769673
Short name T94
Test name
Test status
Simulation time 68551358 ps
CPU time 2.36 seconds
Started Feb 01 03:49:54 PM PST 24
Finished Feb 01 03:51:05 PM PST 24
Peak memory 214324 kb
Host smart-064aab0f-042e-4377-8e49-72e77df526ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492769673 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1492769673
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2195670121
Short name T594
Test name
Test status
Simulation time 158657335 ps
CPU time 6.48 seconds
Started Feb 01 03:49:37 PM PST 24
Finished Feb 01 03:50:59 PM PST 24
Peak memory 208528 kb
Host smart-40923419-c279-423a-bc48-0ad12e485fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195670121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2195670121
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1679018436
Short name T604
Test name
Test status
Simulation time 52609094 ps
CPU time 2.74 seconds
Started Feb 01 03:49:42 PM PST 24
Finished Feb 01 03:50:59 PM PST 24
Peak memory 210088 kb
Host smart-c7847dfd-dc28-4810-89a1-64c2fc17ac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679018436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1679018436
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1068475773
Short name T793
Test name
Test status
Simulation time 18734806 ps
CPU time 0.96 seconds
Started Feb 01 03:44:57 PM PST 24
Finished Feb 01 03:45:28 PM PST 24
Peak memory 205924 kb
Host smart-d4fd2563-7b21-4998-b684-94a8943fd6fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068475773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1068475773
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.649388961
Short name T308
Test name
Test status
Simulation time 140186867 ps
CPU time 3.03 seconds
Started Feb 01 03:44:51 PM PST 24
Finished Feb 01 03:45:21 PM PST 24
Peak memory 215108 kb
Host smart-b5ace4ee-ccfa-4d67-a29c-ed4ef68e91c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649388961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.649388961
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.4014815730
Short name T18
Test name
Test status
Simulation time 69639752 ps
CPU time 3.08 seconds
Started Feb 01 03:45:32 PM PST 24
Finished Feb 01 03:46:25 PM PST 24
Peak memory 208756 kb
Host smart-ec254d9d-4f0e-462b-8b21-f72b1788df73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014815730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.4014815730
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2838584764
Short name T686
Test name
Test status
Simulation time 62175551 ps
CPU time 2.05 seconds
Started Feb 01 03:44:51 PM PST 24
Finished Feb 01 03:45:19 PM PST 24
Peak memory 214280 kb
Host smart-a1c91093-be98-4c3a-a5f1-c77c37c08f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838584764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2838584764
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1747919839
Short name T341
Test name
Test status
Simulation time 19907213393 ps
CPU time 62.95 seconds
Started Feb 01 03:47:59 PM PST 24
Finished Feb 01 03:49:59 PM PST 24
Peak memory 214216 kb
Host smart-c6a7ac78-648a-45b9-9494-f149d437a601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747919839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1747919839
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1558854348
Short name T251
Test name
Test status
Simulation time 435864594 ps
CPU time 4.63 seconds
Started Feb 01 03:44:54 PM PST 24
Finished Feb 01 03:45:24 PM PST 24
Peak memory 207780 kb
Host smart-802d6f34-163b-4dd7-aab9-f282949d05f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558854348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1558854348
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2359607825
Short name T421
Test name
Test status
Simulation time 186424682 ps
CPU time 4.39 seconds
Started Feb 01 03:45:23 PM PST 24
Finished Feb 01 03:46:09 PM PST 24
Peak memory 210092 kb
Host smart-264d3a0d-9d37-4350-9d6e-d23618cb5bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359607825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2359607825
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4147157253
Short name T7
Test name
Test status
Simulation time 2013677414 ps
CPU time 16.56 seconds
Started Feb 01 03:47:50 PM PST 24
Finished Feb 01 03:49:01 PM PST 24
Peak memory 239472 kb
Host smart-07aa3625-085a-4c7d-bbfe-7b05944d6654
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147157253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4147157253
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3064386433
Short name T639
Test name
Test status
Simulation time 764589186 ps
CPU time 2.57 seconds
Started Feb 01 03:44:28 PM PST 24
Finished Feb 01 03:45:02 PM PST 24
Peak memory 206608 kb
Host smart-7068ad37-6635-4519-a29f-6db814119172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064386433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3064386433
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3250928000
Short name T1037
Test name
Test status
Simulation time 151831341 ps
CPU time 3.72 seconds
Started Feb 01 03:44:54 PM PST 24
Finished Feb 01 03:45:24 PM PST 24
Peak memory 208552 kb
Host smart-82e72565-912f-445f-a1e9-49afdedcbe8d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250928000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3250928000
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3313883631
Short name T194
Test name
Test status
Simulation time 4597638914 ps
CPU time 29.79 seconds
Started Feb 01 03:47:35 PM PST 24
Finished Feb 01 03:48:50 PM PST 24
Peak memory 208500 kb
Host smart-090c450c-85e1-4d4d-872a-5359d29e5d44
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313883631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3313883631
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2029953350
Short name T836
Test name
Test status
Simulation time 27631871 ps
CPU time 1.92 seconds
Started Feb 01 03:44:50 PM PST 24
Finished Feb 01 03:45:19 PM PST 24
Peak memory 208152 kb
Host smart-e9c7c5c8-6dcc-410b-833d-c7ab78c23c07
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029953350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2029953350
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3416938719
Short name T274
Test name
Test status
Simulation time 32358147 ps
CPU time 1.45 seconds
Started Feb 01 03:47:27 PM PST 24
Finished Feb 01 03:48:13 PM PST 24
Peak memory 207556 kb
Host smart-da2e4ca6-992f-4153-9c20-885cfd478bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416938719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3416938719
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3271222765
Short name T693
Test name
Test status
Simulation time 798924974 ps
CPU time 5.37 seconds
Started Feb 01 03:44:38 PM PST 24
Finished Feb 01 03:45:12 PM PST 24
Peak memory 207680 kb
Host smart-df98424a-7fa0-4167-9194-ec8257c763af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271222765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3271222765
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3581729867
Short name T795
Test name
Test status
Simulation time 133612172 ps
CPU time 4.33 seconds
Started Feb 01 03:44:52 PM PST 24
Finished Feb 01 03:45:23 PM PST 24
Peak memory 215208 kb
Host smart-835045c8-8227-4fa7-8714-a81cd484980d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581729867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3581729867
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.539405211
Short name T766
Test name
Test status
Simulation time 495762564 ps
CPU time 4.56 seconds
Started Feb 01 03:45:56 PM PST 24
Finished Feb 01 03:46:58 PM PST 24
Peak memory 222456 kb
Host smart-6ff39ba9-bd0c-4efd-983d-81913f77e853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539405211 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.539405211
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.997862672
Short name T433
Test name
Test status
Simulation time 5202064884 ps
CPU time 19.07 seconds
Started Feb 01 03:44:50 PM PST 24
Finished Feb 01 03:45:36 PM PST 24
Peak memory 208592 kb
Host smart-4246ccfa-bb94-4ceb-ab74-236ac33a02be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997862672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.997862672
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3136677109
Short name T756
Test name
Test status
Simulation time 85411513 ps
CPU time 1.76 seconds
Started Feb 01 03:44:49 PM PST 24
Finished Feb 01 03:45:18 PM PST 24
Peak memory 210020 kb
Host smart-6fd79e28-6c89-45a0-a8b0-5a6c6ab28d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136677109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3136677109
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1824095965
Short name T601
Test name
Test status
Simulation time 106044484 ps
CPU time 0.88 seconds
Started Feb 01 03:53:12 PM PST 24
Finished Feb 01 03:53:34 PM PST 24
Peak memory 205808 kb
Host smart-4e600e64-4caf-4393-90cf-e7d43e06f1c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824095965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1824095965
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.4037736099
Short name T416
Test name
Test status
Simulation time 471973432 ps
CPU time 6.91 seconds
Started Feb 01 03:51:18 PM PST 24
Finished Feb 01 03:52:03 PM PST 24
Peak memory 214252 kb
Host smart-442c23a2-2ae4-4074-9104-afb9a4c10870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037736099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4037736099
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3578462743
Short name T28
Test name
Test status
Simulation time 489372441 ps
CPU time 4.5 seconds
Started Feb 01 03:52:08 PM PST 24
Finished Feb 01 03:52:27 PM PST 24
Peak memory 214496 kb
Host smart-bac61b9e-fbb6-49c4-8b87-688de3d1ab30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578462743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3578462743
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1190031344
Short name T231
Test name
Test status
Simulation time 406755382 ps
CPU time 3.18 seconds
Started Feb 01 03:49:53 PM PST 24
Finished Feb 01 03:51:03 PM PST 24
Peak memory 214140 kb
Host smart-b1718bd4-4ab1-4b0c-97f6-ac208cdc78ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190031344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1190031344
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.666956652
Short name T335
Test name
Test status
Simulation time 243835267 ps
CPU time 3.09 seconds
Started Feb 01 03:53:03 PM PST 24
Finished Feb 01 03:53:25 PM PST 24
Peak memory 208232 kb
Host smart-e6656586-7199-489f-98e8-95e1d6f80f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666956652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.666956652
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1135631834
Short name T263
Test name
Test status
Simulation time 2086424449 ps
CPU time 10.49 seconds
Started Feb 01 03:53:23 PM PST 24
Finished Feb 01 03:53:48 PM PST 24
Peak memory 222300 kb
Host smart-4654fd16-6ab9-404b-9a82-91f7f688a6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135631834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1135631834
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2792708852
Short name T254
Test name
Test status
Simulation time 150304560 ps
CPU time 5.34 seconds
Started Feb 01 03:51:44 PM PST 24
Finished Feb 01 03:52:14 PM PST 24
Peak memory 209176 kb
Host smart-3b932fc3-ba5c-4062-b17a-a0379d51715b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792708852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2792708852
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3026930096
Short name T624
Test name
Test status
Simulation time 177764457 ps
CPU time 5.63 seconds
Started Feb 01 03:53:03 PM PST 24
Finished Feb 01 03:53:27 PM PST 24
Peak memory 218088 kb
Host smart-412fa2d0-dfd9-49a3-977d-cbc3436a1f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026930096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3026930096
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2637049613
Short name T799
Test name
Test status
Simulation time 3119624407 ps
CPU time 18.71 seconds
Started Feb 01 03:53:44 PM PST 24
Finished Feb 01 03:54:11 PM PST 24
Peak memory 208484 kb
Host smart-e35fa416-036b-40bc-bfb1-521d86956bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637049613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2637049613
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2578633783
Short name T968
Test name
Test status
Simulation time 52544963 ps
CPU time 2.49 seconds
Started Feb 01 03:52:32 PM PST 24
Finished Feb 01 03:52:36 PM PST 24
Peak memory 208516 kb
Host smart-0a26cad2-b011-4cfd-af92-054e255c249d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578633783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2578633783
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3033322148
Short name T362
Test name
Test status
Simulation time 717645346 ps
CPU time 3.12 seconds
Started Feb 01 03:54:21 PM PST 24
Finished Feb 01 03:54:29 PM PST 24
Peak memory 208288 kb
Host smart-bc515e32-d377-491a-8122-89265e11aae4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033322148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3033322148
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.482011724
Short name T1057
Test name
Test status
Simulation time 23941019 ps
CPU time 1.8 seconds
Started Feb 01 03:49:39 PM PST 24
Finished Feb 01 03:50:54 PM PST 24
Peak memory 206604 kb
Host smart-8bcc0135-d4e0-4a16-97ac-b04b36e82165
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482011724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.482011724
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3952984316
Short name T981
Test name
Test status
Simulation time 492161002 ps
CPU time 2.88 seconds
Started Feb 01 03:49:49 PM PST 24
Finished Feb 01 03:51:04 PM PST 24
Peak memory 207736 kb
Host smart-4f38dcb8-bce4-4db0-ad37-5796f5bfb116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952984316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3952984316
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.4283478701
Short name T845
Test name
Test status
Simulation time 65967003 ps
CPU time 2.67 seconds
Started Feb 01 03:51:40 PM PST 24
Finished Feb 01 03:52:10 PM PST 24
Peak memory 208644 kb
Host smart-006a1358-f548-48f5-afc4-6c8333cc9e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283478701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4283478701
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.598760163
Short name T677
Test name
Test status
Simulation time 93157912 ps
CPU time 2.95 seconds
Started Feb 01 03:50:26 PM PST 24
Finished Feb 01 03:51:24 PM PST 24
Peak memory 222476 kb
Host smart-8e10a46d-5cfc-4a77-8c01-4031dac99586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598760163 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.598760163
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3041010898
Short name T15
Test name
Test status
Simulation time 533997823 ps
CPU time 5.64 seconds
Started Feb 01 03:52:40 PM PST 24
Finished Feb 01 03:52:48 PM PST 24
Peak memory 214184 kb
Host smart-a518c517-f4de-4865-b886-a0edaee104e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041010898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3041010898
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.916872284
Short name T939
Test name
Test status
Simulation time 332505559 ps
CPU time 4.01 seconds
Started Feb 01 03:49:48 PM PST 24
Finished Feb 01 03:51:04 PM PST 24
Peak memory 210780 kb
Host smart-4ebcf1f5-2994-44d2-91a4-5841fa5d8d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916872284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.916872284
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1209577258
Short name T620
Test name
Test status
Simulation time 35609965 ps
CPU time 0.72 seconds
Started Feb 01 03:50:04 PM PST 24
Finished Feb 01 03:51:08 PM PST 24
Peak memory 205812 kb
Host smart-7fe0a2bf-f221-42de-817d-1e59f2e2db22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209577258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1209577258
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3275989292
Short name T99
Test name
Test status
Simulation time 36182343 ps
CPU time 2.68 seconds
Started Feb 01 03:54:24 PM PST 24
Finished Feb 01 03:54:31 PM PST 24
Peak memory 214212 kb
Host smart-618c2209-df4c-4bf8-92e4-e4529b37f8a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3275989292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3275989292
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1022371790
Short name T717
Test name
Test status
Simulation time 377777579 ps
CPU time 9.74 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:13 PM PST 24
Peak memory 214176 kb
Host smart-7b2cf9d3-39e2-40b9-a644-0b721866695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022371790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1022371790
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2289599893
Short name T858
Test name
Test status
Simulation time 1116915129 ps
CPU time 16.42 seconds
Started Feb 01 03:50:09 PM PST 24
Finished Feb 01 03:51:23 PM PST 24
Peak memory 208596 kb
Host smart-356437dc-dade-42ad-bced-2a81c11c427a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289599893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2289599893
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2575372734
Short name T82
Test name
Test status
Simulation time 253239782 ps
CPU time 4.98 seconds
Started Feb 01 03:51:33 PM PST 24
Finished Feb 01 03:52:09 PM PST 24
Peak memory 208260 kb
Host smart-bc73f9ea-32e8-45af-b5d2-2054078ac928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575372734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2575372734
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2576555223
Short name T220
Test name
Test status
Simulation time 353081013 ps
CPU time 4.2 seconds
Started Feb 01 03:50:59 PM PST 24
Finished Feb 01 03:51:50 PM PST 24
Peak memory 209736 kb
Host smart-46ca529d-a215-4afa-b2ee-3213171ba469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576555223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2576555223
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.890299093
Short name T768
Test name
Test status
Simulation time 241261817 ps
CPU time 5.73 seconds
Started Feb 01 03:49:56 PM PST 24
Finished Feb 01 03:51:09 PM PST 24
Peak memory 209144 kb
Host smart-17a907be-78ce-4021-b80b-64478011272d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890299093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.890299093
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2238027358
Short name T743
Test name
Test status
Simulation time 132169020 ps
CPU time 4.28 seconds
Started Feb 01 03:53:37 PM PST 24
Finished Feb 01 03:53:54 PM PST 24
Peak memory 208224 kb
Host smart-a6677333-ce19-4758-9dbe-1c22055f717e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238027358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2238027358
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.4127210177
Short name T316
Test name
Test status
Simulation time 672179205 ps
CPU time 6.91 seconds
Started Feb 01 03:53:47 PM PST 24
Finished Feb 01 03:54:02 PM PST 24
Peak memory 207876 kb
Host smart-7b48b0e2-6a06-4c36-8eb0-eca3b9801a21
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127210177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.4127210177
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.162426321
Short name T687
Test name
Test status
Simulation time 99506211 ps
CPU time 2.68 seconds
Started Feb 01 03:49:56 PM PST 24
Finished Feb 01 03:51:06 PM PST 24
Peak memory 206828 kb
Host smart-94a119b2-99a0-4a72-bc91-aef588a306d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162426321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.162426321
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1984891577
Short name T961
Test name
Test status
Simulation time 101688640 ps
CPU time 4.28 seconds
Started Feb 01 03:49:54 PM PST 24
Finished Feb 01 03:51:07 PM PST 24
Peak memory 208412 kb
Host smart-2aba63c4-fd10-4a16-a440-0e679ae43046
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984891577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1984891577
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.155150641
Short name T754
Test name
Test status
Simulation time 43391302 ps
CPU time 2.73 seconds
Started Feb 01 03:54:40 PM PST 24
Finished Feb 01 03:54:46 PM PST 24
Peak memory 218228 kb
Host smart-6132190c-5a41-4622-867c-c059e9739e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155150641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.155150641
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1214904373
Short name T937
Test name
Test status
Simulation time 996140458 ps
CPU time 18.87 seconds
Started Feb 01 03:53:34 PM PST 24
Finished Feb 01 03:54:08 PM PST 24
Peak memory 207996 kb
Host smart-070be613-c0d7-4b84-86af-8f2ddddca1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214904373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1214904373
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.4084267152
Short name T304
Test name
Test status
Simulation time 423240100 ps
CPU time 5.55 seconds
Started Feb 01 03:53:02 PM PST 24
Finished Feb 01 03:53:27 PM PST 24
Peak memory 219440 kb
Host smart-ed8f5884-0105-487e-9589-4e1aa8025ced
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084267152 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.4084267152
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.4211122010
Short name T663
Test name
Test status
Simulation time 553152301 ps
CPU time 6.81 seconds
Started Feb 01 03:52:25 PM PST 24
Finished Feb 01 03:52:35 PM PST 24
Peak memory 219512 kb
Host smart-5123fa56-11c7-4d13-b9de-4053e97b9dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211122010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.4211122010
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.4034236981
Short name T863
Test name
Test status
Simulation time 750802362 ps
CPU time 3.56 seconds
Started Feb 01 03:54:18 PM PST 24
Finished Feb 01 03:54:26 PM PST 24
Peak memory 210028 kb
Host smart-81fbf226-4410-462b-9f7c-946db0712b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034236981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.4034236981
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1534175767
Short name T436
Test name
Test status
Simulation time 48896386 ps
CPU time 0.89 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:03 PM PST 24
Peak memory 206044 kb
Host smart-983dc7b7-0d76-4ef9-8651-42c2a0b60d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534175767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1534175767
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.784568068
Short name T419
Test name
Test status
Simulation time 121940455 ps
CPU time 2.44 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:06 PM PST 24
Peak memory 214104 kb
Host smart-08f30e3f-9d53-411b-bdcf-cb1fde382946
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=784568068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.784568068
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3911182680
Short name T992
Test name
Test status
Simulation time 229841765 ps
CPU time 7.65 seconds
Started Feb 01 03:54:19 PM PST 24
Finished Feb 01 03:54:31 PM PST 24
Peak memory 214492 kb
Host smart-16fc95d9-1f6e-4e4a-8c34-f2ca5e13ba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911182680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3911182680
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2071449457
Short name T740
Test name
Test status
Simulation time 289189005 ps
CPU time 3.37 seconds
Started Feb 01 03:56:03 PM PST 24
Finished Feb 01 03:56:09 PM PST 24
Peak memory 206400 kb
Host smart-0ba17a71-c936-4ff4-8bea-c37ed937f2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071449457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2071449457
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.287251389
Short name T904
Test name
Test status
Simulation time 243314019 ps
CPU time 4.88 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:08 PM PST 24
Peak memory 209528 kb
Host smart-9c51b986-2f2c-4b61-b67f-fc096299be7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287251389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.287251389
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1759752242
Short name T392
Test name
Test status
Simulation time 307944721 ps
CPU time 6.79 seconds
Started Feb 01 03:54:40 PM PST 24
Finished Feb 01 03:54:50 PM PST 24
Peak memory 222220 kb
Host smart-4c72cb24-4483-4250-91ed-0a21efa2e39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759752242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1759752242
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3660198452
Short name T1060
Test name
Test status
Simulation time 326934445 ps
CPU time 2.59 seconds
Started Feb 01 03:56:10 PM PST 24
Finished Feb 01 03:56:15 PM PST 24
Peak memory 208112 kb
Host smart-8381dae5-47d3-4135-b173-0891b8a0aa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660198452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3660198452
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2434977315
Short name T227
Test name
Test status
Simulation time 107140226 ps
CPU time 4.33 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:33 PM PST 24
Peak memory 209520 kb
Host smart-b4507756-6af9-4409-b56d-a9a67f8f6675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434977315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2434977315
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1368993659
Short name T729
Test name
Test status
Simulation time 3283863336 ps
CPU time 19.43 seconds
Started Feb 01 03:53:38 PM PST 24
Finished Feb 01 03:54:10 PM PST 24
Peak memory 208244 kb
Host smart-33809918-0541-4f1c-a545-023e1a060a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368993659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1368993659
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1218428376
Short name T648
Test name
Test status
Simulation time 1944588114 ps
CPU time 24.3 seconds
Started Feb 01 03:53:49 PM PST 24
Finished Feb 01 03:54:20 PM PST 24
Peak memory 207988 kb
Host smart-8e72246b-167a-4342-9775-867b4a88cf36
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218428376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1218428376
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.477752852
Short name T973
Test name
Test status
Simulation time 113063703 ps
CPU time 2.19 seconds
Started Feb 01 03:53:57 PM PST 24
Finished Feb 01 03:54:07 PM PST 24
Peak memory 206704 kb
Host smart-eb980cda-163e-4264-be3e-83f36ea496e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477752852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.477752852
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.570699625
Short name T676
Test name
Test status
Simulation time 131009648 ps
CPU time 3.1 seconds
Started Feb 01 03:50:04 PM PST 24
Finished Feb 01 03:51:11 PM PST 24
Peak memory 206760 kb
Host smart-e485fd5b-3455-45df-95da-ba58c0943af4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570699625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.570699625
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2402728729
Short name T812
Test name
Test status
Simulation time 271017614 ps
CPU time 4.13 seconds
Started Feb 01 03:50:14 PM PST 24
Finished Feb 01 03:51:14 PM PST 24
Peak memory 209828 kb
Host smart-3f2af687-4551-43f1-bf3a-49dd01eba5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402728729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2402728729
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3598485448
Short name T889
Test name
Test status
Simulation time 305004607 ps
CPU time 4.65 seconds
Started Feb 01 03:53:22 PM PST 24
Finished Feb 01 03:53:44 PM PST 24
Peak memory 208172 kb
Host smart-0875b80c-ed7d-456e-bb81-ebdf0347f320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598485448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3598485448
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1179371071
Short name T70
Test name
Test status
Simulation time 1084215032 ps
CPU time 41.21 seconds
Started Feb 01 03:54:19 PM PST 24
Finished Feb 01 03:55:05 PM PST 24
Peak memory 219872 kb
Host smart-3aa3a43f-7f63-4649-967b-7c946890f078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179371071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1179371071
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3313525521
Short name T1065
Test name
Test status
Simulation time 85312519 ps
CPU time 3.6 seconds
Started Feb 01 03:56:03 PM PST 24
Finished Feb 01 03:56:09 PM PST 24
Peak memory 221928 kb
Host smart-3607ee8f-d602-4b41-831c-a11fb2d816a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313525521 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3313525521
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2265281857
Short name T966
Test name
Test status
Simulation time 742623199 ps
CPU time 4.73 seconds
Started Feb 01 03:55:12 PM PST 24
Finished Feb 01 03:55:26 PM PST 24
Peak memory 209556 kb
Host smart-e40aae11-1ce4-472c-9914-3aeb9a19c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265281857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2265281857
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2954364022
Short name T705
Test name
Test status
Simulation time 164373498 ps
CPU time 1.95 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:06 PM PST 24
Peak memory 209712 kb
Host smart-0cc7ac94-17a3-483a-b830-5f62169d05ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954364022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2954364022
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1923108308
Short name T999
Test name
Test status
Simulation time 9434560 ps
CPU time 0.7 seconds
Started Feb 01 03:53:32 PM PST 24
Finished Feb 01 03:53:48 PM PST 24
Peak memory 205756 kb
Host smart-84ac3529-4e61-40ff-9f2a-872316ac7bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923108308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1923108308
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.4002425331
Short name T37
Test name
Test status
Simulation time 411905223 ps
CPU time 9.53 seconds
Started Feb 01 03:55:16 PM PST 24
Finished Feb 01 03:55:35 PM PST 24
Peak memory 218916 kb
Host smart-d59a58e7-6752-47f0-afca-9214b6f7a3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002425331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.4002425331
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3594817925
Short name T329
Test name
Test status
Simulation time 209560605 ps
CPU time 2.57 seconds
Started Feb 01 03:55:12 PM PST 24
Finished Feb 01 03:55:24 PM PST 24
Peak memory 214260 kb
Host smart-65f71cec-3899-433c-9b76-ff1c419ccf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594817925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3594817925
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3127380311
Short name T817
Test name
Test status
Simulation time 334781934 ps
CPU time 3.9 seconds
Started Feb 01 03:53:45 PM PST 24
Finished Feb 01 03:53:57 PM PST 24
Peak memory 214204 kb
Host smart-4d854122-a88c-43d1-8cd4-3d23361ff8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127380311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3127380311
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2764611919
Short name T399
Test name
Test status
Simulation time 94089555 ps
CPU time 4.67 seconds
Started Feb 01 03:55:15 PM PST 24
Finished Feb 01 03:55:29 PM PST 24
Peak memory 210928 kb
Host smart-f7ea5d5f-cde2-46a2-86f9-63de4fd6ced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764611919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2764611919
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1370124348
Short name T249
Test name
Test status
Simulation time 80455568 ps
CPU time 3.2 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:32 PM PST 24
Peak memory 220232 kb
Host smart-83a04791-069f-4954-a964-2696346fe17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370124348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1370124348
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2365157252
Short name T783
Test name
Test status
Simulation time 1480131281 ps
CPU time 9.95 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:07 PM PST 24
Peak memory 222364 kb
Host smart-d7be9e16-eda3-4eef-82cd-0fb1d4d94553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365157252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2365157252
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.11281813
Short name T576
Test name
Test status
Simulation time 453737441 ps
CPU time 6.45 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:12 PM PST 24
Peak memory 207896 kb
Host smart-0690176b-0b4c-476e-8f5c-90c19fdb67fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11281813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.11281813
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2660999643
Short name T967
Test name
Test status
Simulation time 101031455 ps
CPU time 2.49 seconds
Started Feb 01 03:56:20 PM PST 24
Finished Feb 01 03:56:28 PM PST 24
Peak memory 206752 kb
Host smart-4503395c-e213-4c67-8ac7-c0b55967c9fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660999643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2660999643
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2595343293
Short name T785
Test name
Test status
Simulation time 750533163 ps
CPU time 5.84 seconds
Started Feb 01 03:50:34 PM PST 24
Finished Feb 01 03:51:33 PM PST 24
Peak memory 207808 kb
Host smart-3ebbcf7c-c3c7-4e23-ad63-c9d99ad220c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595343293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2595343293
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3545530357
Short name T272
Test name
Test status
Simulation time 277388548 ps
CPU time 7.69 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:10 PM PST 24
Peak memory 208284 kb
Host smart-5928f204-1b01-49d3-9a71-ad7300f43731
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545530357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3545530357
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1638881948
Short name T631
Test name
Test status
Simulation time 104201896 ps
CPU time 2.79 seconds
Started Feb 01 03:56:20 PM PST 24
Finished Feb 01 03:56:29 PM PST 24
Peak memory 208712 kb
Host smart-0eb8ee97-09e4-4f84-8c1e-464630e07e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638881948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1638881948
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2969188911
Short name T595
Test name
Test status
Simulation time 158050043 ps
CPU time 4.57 seconds
Started Feb 01 03:54:53 PM PST 24
Finished Feb 01 03:55:01 PM PST 24
Peak memory 207836 kb
Host smart-2e5c7d0f-d7ff-4b33-80e9-35eff99a0fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969188911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2969188911
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3071922811
Short name T300
Test name
Test status
Simulation time 37226532 ps
CPU time 2.44 seconds
Started Feb 01 03:56:09 PM PST 24
Finished Feb 01 03:56:14 PM PST 24
Peak memory 206308 kb
Host smart-56c11995-bb2a-4e15-8f27-ba1b0ab9d75d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071922811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3071922811
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.322665015
Short name T201
Test name
Test status
Simulation time 76940940 ps
CPU time 2.48 seconds
Started Feb 01 03:53:43 PM PST 24
Finished Feb 01 03:53:54 PM PST 24
Peak memory 222584 kb
Host smart-11fe1644-4a7e-40c3-b7d3-ae1acd787589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322665015 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.322665015
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1593238996
Short name T652
Test name
Test status
Simulation time 442915060 ps
CPU time 10.09 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:13 PM PST 24
Peak memory 214176 kb
Host smart-9990c70e-208d-405a-92ff-65c3abb4aee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593238996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1593238996
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2732231248
Short name T669
Test name
Test status
Simulation time 375406484 ps
CPU time 3.2 seconds
Started Feb 01 03:56:09 PM PST 24
Finished Feb 01 03:56:15 PM PST 24
Peak memory 209760 kb
Host smart-6a2ee6f8-7382-40b4-9418-b0bd3c2e65e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732231248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2732231248
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2192919999
Short name T77
Test name
Test status
Simulation time 26137564 ps
CPU time 1.04 seconds
Started Feb 01 03:54:48 PM PST 24
Finished Feb 01 03:54:53 PM PST 24
Peak memory 206044 kb
Host smart-10d37f2f-ac9c-4997-b7f8-97768ad07906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192919999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2192919999
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2516178086
Short name T917
Test name
Test status
Simulation time 60399132 ps
CPU time 3.05 seconds
Started Feb 01 03:55:15 PM PST 24
Finished Feb 01 03:55:28 PM PST 24
Peak memory 216612 kb
Host smart-70e286f5-f430-47f5-9dd0-0c2ccab6cb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516178086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2516178086
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1911603204
Short name T762
Test name
Test status
Simulation time 167974570 ps
CPU time 2.4 seconds
Started Feb 01 03:53:40 PM PST 24
Finished Feb 01 03:53:53 PM PST 24
Peak memory 208204 kb
Host smart-d858b085-f9a2-4b7b-a34e-2a9e2d1fcee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911603204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1911603204
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.713712553
Short name T85
Test name
Test status
Simulation time 189789152 ps
CPU time 2.79 seconds
Started Feb 01 03:53:35 PM PST 24
Finished Feb 01 03:53:52 PM PST 24
Peak memory 207712 kb
Host smart-a0560215-4ca6-430f-8c72-a077d1fe89d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713712553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.713712553
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1265318315
Short name T914
Test name
Test status
Simulation time 204166655 ps
CPU time 5.14 seconds
Started Feb 01 03:53:53 PM PST 24
Finished Feb 01 03:54:05 PM PST 24
Peak memory 218012 kb
Host smart-454bfa4a-8814-4cb1-96a9-5d27628ddcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265318315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1265318315
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1558996477
Short name T769
Test name
Test status
Simulation time 446369457 ps
CPU time 3.57 seconds
Started Feb 01 03:56:09 PM PST 24
Finished Feb 01 03:56:15 PM PST 24
Peak memory 207428 kb
Host smart-59918920-2468-4059-8551-340c3be2cb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558996477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1558996477
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2231356135
Short name T355
Test name
Test status
Simulation time 56375678 ps
CPU time 2.57 seconds
Started Feb 01 03:56:09 PM PST 24
Finished Feb 01 03:56:14 PM PST 24
Peak memory 207856 kb
Host smart-df241e15-0df7-4791-ba35-fc29b0a22041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231356135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2231356135
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3526099347
Short name T906
Test name
Test status
Simulation time 196716776 ps
CPU time 2.85 seconds
Started Feb 01 03:56:10 PM PST 24
Finished Feb 01 03:56:15 PM PST 24
Peak memory 207988 kb
Host smart-670f2b48-7b73-4117-aca5-a27383852634
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526099347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3526099347
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1459120349
Short name T735
Test name
Test status
Simulation time 72802067 ps
CPU time 3.3 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:01 PM PST 24
Peak memory 208276 kb
Host smart-533946b7-1a84-4499-aaee-e2ba97052ab2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459120349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1459120349
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2387808141
Short name T752
Test name
Test status
Simulation time 67492271 ps
CPU time 3.16 seconds
Started Feb 01 03:56:25 PM PST 24
Finished Feb 01 03:56:34 PM PST 24
Peak memory 208644 kb
Host smart-c3ab01da-196c-462b-84e8-ba30d95fba6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387808141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2387808141
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3925740586
Short name T423
Test name
Test status
Simulation time 100138974 ps
CPU time 1.76 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:07 PM PST 24
Peak memory 215516 kb
Host smart-60d4d8d7-c7ae-467b-971b-d7f9d23bdea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925740586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3925740586
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3210012266
Short name T407
Test name
Test status
Simulation time 756010540 ps
CPU time 5.14 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:02 PM PST 24
Peak memory 208492 kb
Host smart-433a5862-dff7-4d1b-bb8b-6e8cb971ddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210012266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3210012266
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.106071590
Short name T321
Test name
Test status
Simulation time 4565100316 ps
CPU time 108.44 seconds
Started Feb 01 03:52:47 PM PST 24
Finished Feb 01 03:54:38 PM PST 24
Peak memory 216576 kb
Host smart-4e3bad86-94ae-4e17-a6eb-fcc66b299b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106071590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.106071590
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2872317955
Short name T867
Test name
Test status
Simulation time 1492778372 ps
CPU time 9.55 seconds
Started Feb 01 03:56:10 PM PST 24
Finished Feb 01 03:56:23 PM PST 24
Peak memory 222076 kb
Host smart-0ecb8828-ec3d-438c-91b7-6dc4cbf276bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872317955 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2872317955
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2824406508
Short name T79
Test name
Test status
Simulation time 102303423 ps
CPU time 3.12 seconds
Started Feb 01 03:55:15 PM PST 24
Finished Feb 01 03:55:28 PM PST 24
Peak memory 208292 kb
Host smart-57f55976-4754-4381-8988-4c2273e6c329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824406508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2824406508
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.120941854
Short name T151
Test name
Test status
Simulation time 91271857 ps
CPU time 1.71 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:26 PM PST 24
Peak memory 209524 kb
Host smart-c5eac010-cf2f-41f7-b359-5dc63329b3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120941854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.120941854
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2044463278
Short name T922
Test name
Test status
Simulation time 10872905 ps
CPU time 0.83 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:05 PM PST 24
Peak memory 205816 kb
Host smart-1c503f89-b447-4aae-a4e0-6860bf372e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044463278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2044463278
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3940470814
Short name T1024
Test name
Test status
Simulation time 71881276 ps
CPU time 2.76 seconds
Started Feb 01 03:54:19 PM PST 24
Finished Feb 01 03:54:26 PM PST 24
Peak memory 214188 kb
Host smart-b51abfe9-a963-4b8c-a3a7-4036f025c03c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940470814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3940470814
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2998089086
Short name T25
Test name
Test status
Simulation time 1962072823 ps
CPU time 11.76 seconds
Started Feb 01 03:51:23 PM PST 24
Finished Feb 01 03:52:11 PM PST 24
Peak memory 221568 kb
Host smart-046acb7a-4f0c-4efa-b464-132ead847d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998089086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2998089086
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.4168149135
Short name T737
Test name
Test status
Simulation time 38260822 ps
CPU time 2.66 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:32 PM PST 24
Peak memory 210096 kb
Host smart-42e8d959-e7d3-4821-a4c0-c578e369ceef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168149135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.4168149135
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1459122587
Short name T916
Test name
Test status
Simulation time 305103037 ps
CPU time 4.52 seconds
Started Feb 01 03:54:17 PM PST 24
Finished Feb 01 03:54:26 PM PST 24
Peak memory 214160 kb
Host smart-a468ffd5-fb5d-446c-a2b6-3176e4c5459f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459122587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1459122587
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1265390338
Short name T81
Test name
Test status
Simulation time 314096876 ps
CPU time 4.34 seconds
Started Feb 01 03:55:12 PM PST 24
Finished Feb 01 03:55:26 PM PST 24
Peak memory 222236 kb
Host smart-5190c846-8a3b-4aef-8729-523e68548b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265390338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1265390338
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3781683058
Short name T325
Test name
Test status
Simulation time 83012533 ps
CPU time 3.89 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:28 PM PST 24
Peak memory 209600 kb
Host smart-94f816a8-22d1-4d0e-af4d-77b4e0e10c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781683058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3781683058
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2039890636
Short name T773
Test name
Test status
Simulation time 2122781789 ps
CPU time 6.8 seconds
Started Feb 01 03:54:05 PM PST 24
Finished Feb 01 03:54:16 PM PST 24
Peak memory 217808 kb
Host smart-5fdb559f-b47f-401a-930e-c1d17e6c6e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039890636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2039890636
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2871156730
Short name T383
Test name
Test status
Simulation time 47060807 ps
CPU time 2.77 seconds
Started Feb 01 03:50:13 PM PST 24
Finished Feb 01 03:51:13 PM PST 24
Peak memory 206700 kb
Host smart-8f2baab7-855e-48b0-abee-aafd2e1d3338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871156730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2871156730
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3960541282
Short name T750
Test name
Test status
Simulation time 252273168 ps
CPU time 3.09 seconds
Started Feb 01 03:53:34 PM PST 24
Finished Feb 01 03:53:52 PM PST 24
Peak memory 208656 kb
Host smart-ba45c520-7782-426f-a3b2-3e300fea58c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960541282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3960541282
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.276726299
Short name T885
Test name
Test status
Simulation time 180324618 ps
CPU time 5.31 seconds
Started Feb 01 03:54:55 PM PST 24
Finished Feb 01 03:55:05 PM PST 24
Peak memory 208900 kb
Host smart-9a2a04f0-683a-4aef-bfa0-cb245e80c304
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276726299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.276726299
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3070690753
Short name T1017
Test name
Test status
Simulation time 264461442 ps
CPU time 2.97 seconds
Started Feb 01 03:54:01 PM PST 24
Finished Feb 01 03:54:09 PM PST 24
Peak memory 208528 kb
Host smart-eab89814-1555-44a3-9f6c-cabab535c329
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070690753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3070690753
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3996531007
Short name T635
Test name
Test status
Simulation time 574852360 ps
CPU time 5.93 seconds
Started Feb 01 03:54:58 PM PST 24
Finished Feb 01 03:55:12 PM PST 24
Peak memory 215880 kb
Host smart-28467aef-c5ed-4d20-97bf-f6369fccdf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996531007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3996531007
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.4134244426
Short name T854
Test name
Test status
Simulation time 25736070 ps
CPU time 1.78 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:26 PM PST 24
Peak memory 206512 kb
Host smart-c66fb542-9b8a-4247-aedf-0cff6c506f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134244426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.4134244426
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4121767202
Short name T955
Test name
Test status
Simulation time 8051973678 ps
CPU time 60.5 seconds
Started Feb 01 03:52:03 PM PST 24
Finished Feb 01 03:53:20 PM PST 24
Peak memory 222404 kb
Host smart-81a34af2-a344-418b-8dc5-de6840dcf392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121767202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4121767202
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.760603899
Short name T902
Test name
Test status
Simulation time 1623901764 ps
CPU time 16.18 seconds
Started Feb 01 03:53:43 PM PST 24
Finished Feb 01 03:54:08 PM PST 24
Peak memory 222344 kb
Host smart-169ae699-97c0-4851-9a5c-1302ca5efd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760603899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.760603899
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3400969836
Short name T157
Test name
Test status
Simulation time 277045156 ps
CPU time 1.58 seconds
Started Feb 01 03:53:43 PM PST 24
Finished Feb 01 03:53:53 PM PST 24
Peak memory 209728 kb
Host smart-af98b304-7d17-451c-8934-28e908b94705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400969836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3400969836
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3181455240
Short name T571
Test name
Test status
Simulation time 11923271 ps
CPU time 0.75 seconds
Started Feb 01 03:53:52 PM PST 24
Finished Feb 01 03:53:59 PM PST 24
Peak memory 205744 kb
Host smart-f6a2c896-752d-4cd3-8790-69936abfb282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181455240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3181455240
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.553200815
Short name T255
Test name
Test status
Simulation time 2361688197 ps
CPU time 65.78 seconds
Started Feb 01 03:50:41 PM PST 24
Finished Feb 01 03:52:39 PM PST 24
Peak memory 217240 kb
Host smart-6084f425-5a32-47b1-a08c-05fc48fa746c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=553200815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.553200815
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.625784873
Short name T30
Test name
Test status
Simulation time 657741607 ps
CPU time 2.9 seconds
Started Feb 01 03:54:59 PM PST 24
Finished Feb 01 03:55:10 PM PST 24
Peak memory 215248 kb
Host smart-d0154437-dee4-4684-8ffb-02dd6702161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625784873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.625784873
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.959922702
Short name T990
Test name
Test status
Simulation time 1406249550 ps
CPU time 13.95 seconds
Started Feb 01 03:52:26 PM PST 24
Finished Feb 01 03:52:43 PM PST 24
Peak memory 214180 kb
Host smart-0a4ee5cc-7455-4c0f-aef7-665e251efc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959922702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.959922702
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.654268777
Short name T343
Test name
Test status
Simulation time 42995220 ps
CPU time 2.84 seconds
Started Feb 01 03:53:38 PM PST 24
Finished Feb 01 03:53:53 PM PST 24
Peak memory 219628 kb
Host smart-87e42de2-eaa6-4a76-a5da-031432724ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654268777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.654268777
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3979092534
Short name T765
Test name
Test status
Simulation time 60134556 ps
CPU time 3.64 seconds
Started Feb 01 03:54:05 PM PST 24
Finished Feb 01 03:54:13 PM PST 24
Peak memory 210668 kb
Host smart-44b58049-fd68-421d-b360-8db98fc8458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979092534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3979092534
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.4027500937
Short name T422
Test name
Test status
Simulation time 271791123 ps
CPU time 3.21 seconds
Started Feb 01 03:55:00 PM PST 24
Finished Feb 01 03:55:11 PM PST 24
Peak memory 214160 kb
Host smart-c45a571b-6229-48fb-8384-b13c93199582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027500937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.4027500937
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1271598194
Short name T367
Test name
Test status
Simulation time 479579232 ps
CPU time 2.33 seconds
Started Feb 01 03:52:46 PM PST 24
Finished Feb 01 03:52:51 PM PST 24
Peak memory 207488 kb
Host smart-357ed8df-810e-4fe6-9b30-ac2f69ccfb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271598194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1271598194
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3757630801
Short name T338
Test name
Test status
Simulation time 575293644 ps
CPU time 5.94 seconds
Started Feb 01 03:53:50 PM PST 24
Finished Feb 01 03:54:02 PM PST 24
Peak memory 208576 kb
Host smart-df987a05-1901-4b49-a808-8b09f4eae00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757630801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3757630801
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1632988589
Short name T323
Test name
Test status
Simulation time 2981606383 ps
CPU time 54.11 seconds
Started Feb 01 03:55:00 PM PST 24
Finished Feb 01 03:56:02 PM PST 24
Peak memory 208756 kb
Host smart-ca0be8db-b0ba-4a99-9fc1-2a04797cd3a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632988589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1632988589
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2073197746
Short name T590
Test name
Test status
Simulation time 2084464625 ps
CPU time 55.85 seconds
Started Feb 01 03:54:29 PM PST 24
Finished Feb 01 03:55:30 PM PST 24
Peak memory 208120 kb
Host smart-86b7fcff-47f3-4ab3-983a-33e314ee0238
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073197746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2073197746
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2994040686
Short name T832
Test name
Test status
Simulation time 23679165 ps
CPU time 1.82 seconds
Started Feb 01 03:54:52 PM PST 24
Finished Feb 01 03:54:57 PM PST 24
Peak memory 214224 kb
Host smart-8a813f8c-ea0f-4e50-a6a4-1fcef22b2074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994040686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2994040686
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1036690773
Short name T1025
Test name
Test status
Simulation time 250588429 ps
CPU time 3.54 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:07 PM PST 24
Peak memory 207960 kb
Host smart-cb5a1ab6-42e9-4d3b-8e02-f67b2170530e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036690773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1036690773
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3987772530
Short name T57
Test name
Test status
Simulation time 207288422 ps
CPU time 11.24 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:15 PM PST 24
Peak memory 216732 kb
Host smart-45228b04-8aab-4e6c-b1a6-16bc41ed60bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987772530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3987772530
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2693650955
Short name T630
Test name
Test status
Simulation time 119519947 ps
CPU time 3.44 seconds
Started Feb 01 03:54:36 PM PST 24
Finished Feb 01 03:54:43 PM PST 24
Peak memory 222488 kb
Host smart-6c6c4c3f-0ddf-47cf-a264-47023d0dc7b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693650955 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2693650955
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1705475611
Short name T746
Test name
Test status
Simulation time 96579326 ps
CPU time 3.34 seconds
Started Feb 01 03:53:21 PM PST 24
Finished Feb 01 03:53:41 PM PST 24
Peak memory 207412 kb
Host smart-4ce63f8e-9c84-4fe8-9d02-aadb344c5343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705475611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1705475611
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.4154202494
Short name T794
Test name
Test status
Simulation time 72757474 ps
CPU time 2.26 seconds
Started Feb 01 03:55:10 PM PST 24
Finished Feb 01 03:55:20 PM PST 24
Peak memory 209612 kb
Host smart-d5b3a9f1-4cef-4d9a-b28b-45e2716809d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154202494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4154202494
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2667137247
Short name T1033
Test name
Test status
Simulation time 17081622 ps
CPU time 0.76 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:04 PM PST 24
Peak memory 205716 kb
Host smart-fdff6f41-0859-409d-b659-72c4575b0155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667137247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2667137247
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4127107000
Short name T242
Test name
Test status
Simulation time 240549843 ps
CPU time 3.55 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:08 PM PST 24
Peak memory 209984 kb
Host smart-d12c1458-4210-4920-8e01-4234184ad998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127107000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4127107000
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4005814915
Short name T269
Test name
Test status
Simulation time 1628836694 ps
CPU time 5.75 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:11 PM PST 24
Peak memory 218708 kb
Host smart-74330494-176e-43c3-b66d-928b4bb46180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005814915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4005814915
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2918716468
Short name T236
Test name
Test status
Simulation time 1126719480 ps
CPU time 5.26 seconds
Started Feb 01 03:54:43 PM PST 24
Finished Feb 01 03:54:53 PM PST 24
Peak memory 213960 kb
Host smart-376a5f33-212e-40b8-bc48-1657299c61f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918716468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2918716468
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1153684676
Short name T695
Test name
Test status
Simulation time 1204653619 ps
CPU time 4.15 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:07 PM PST 24
Peak memory 207508 kb
Host smart-f0d91dc4-2671-4bed-a772-28117c4c042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153684676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1153684676
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.535574083
Short name T598
Test name
Test status
Simulation time 7825640642 ps
CPU time 52.51 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:56 PM PST 24
Peak memory 208232 kb
Host smart-a6dc7e6a-3391-45c0-b6e8-8e5bf4cbb1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535574083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.535574083
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2349900218
Short name T191
Test name
Test status
Simulation time 964483586 ps
CPU time 7.24 seconds
Started Feb 01 03:54:39 PM PST 24
Finished Feb 01 03:54:49 PM PST 24
Peak memory 208124 kb
Host smart-3321db32-d70e-4c8f-bbbe-5c68fd76cf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349900218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2349900218
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1052382351
Short name T989
Test name
Test status
Simulation time 2110138534 ps
CPU time 21.08 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:18 PM PST 24
Peak memory 208096 kb
Host smart-c9c9160e-6a31-4646-8f23-be52b6f601ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052382351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1052382351
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.58353833
Short name T268
Test name
Test status
Simulation time 1029110610 ps
CPU time 5.4 seconds
Started Feb 01 03:54:07 PM PST 24
Finished Feb 01 03:54:18 PM PST 24
Peak memory 208568 kb
Host smart-0a8d1215-21e9-4642-9576-5b1fd0b8edce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58353833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.58353833
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.15679234
Short name T324
Test name
Test status
Simulation time 99710331 ps
CPU time 2.68 seconds
Started Feb 01 03:54:14 PM PST 24
Finished Feb 01 03:54:22 PM PST 24
Peak memory 206656 kb
Host smart-6f98b38f-4528-4376-a6ac-5b9fdacdf1d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15679234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.15679234
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.628785774
Short name T100
Test name
Test status
Simulation time 427161206 ps
CPU time 2.34 seconds
Started Feb 01 03:50:44 PM PST 24
Finished Feb 01 03:51:37 PM PST 24
Peak memory 207720 kb
Host smart-0053e1bb-6544-4df8-a842-3e153fe8e9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628785774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.628785774
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.4190816326
Short name T632
Test name
Test status
Simulation time 893524758 ps
CPU time 8.62 seconds
Started Feb 01 03:50:30 PM PST 24
Finished Feb 01 03:51:32 PM PST 24
Peak memory 208208 kb
Host smart-748e0176-6c52-4c01-88f2-6378ac438529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190816326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.4190816326
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2019167686
Short name T67
Test name
Test status
Simulation time 15257573985 ps
CPU time 49.22 seconds
Started Feb 01 03:53:22 PM PST 24
Finished Feb 01 03:54:29 PM PST 24
Peak memory 222496 kb
Host smart-f3225523-f78a-42dc-9a40-d98656f77ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019167686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2019167686
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1830153853
Short name T1013
Test name
Test status
Simulation time 6721932380 ps
CPU time 17.45 seconds
Started Feb 01 03:53:36 PM PST 24
Finished Feb 01 03:54:07 PM PST 24
Peak memory 222548 kb
Host smart-977ce3c7-29f7-4655-a2d8-0fceb9d099d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830153853 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1830153853
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3501879805
Short name T935
Test name
Test status
Simulation time 367938071 ps
CPU time 11.39 seconds
Started Feb 01 03:54:26 PM PST 24
Finished Feb 01 03:54:42 PM PST 24
Peak memory 217844 kb
Host smart-8697409c-6ce0-4bf1-81d6-8a4da3f7cb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501879805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3501879805
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2242883738
Short name T617
Test name
Test status
Simulation time 175833167 ps
CPU time 1.73 seconds
Started Feb 01 03:54:00 PM PST 24
Finished Feb 01 03:54:08 PM PST 24
Peak memory 210528 kb
Host smart-6616d7a8-f890-4fd9-9672-5ebff959a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242883738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2242883738
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1584783433
Short name T839
Test name
Test status
Simulation time 41414941 ps
CPU time 0.7 seconds
Started Feb 01 03:53:39 PM PST 24
Finished Feb 01 03:53:51 PM PST 24
Peak memory 205772 kb
Host smart-97cae0db-6749-488f-9b5c-5ee9cbfb07bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584783433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1584783433
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3182707879
Short name T288
Test name
Test status
Simulation time 393012796 ps
CPU time 15.77 seconds
Started Feb 01 03:53:15 PM PST 24
Finished Feb 01 03:53:51 PM PST 24
Peak memory 215596 kb
Host smart-b6dd5f4e-6854-41e8-b08a-044a20a8aef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182707879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3182707879
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2814998720
Short name T721
Test name
Test status
Simulation time 82839631 ps
CPU time 2.26 seconds
Started Feb 01 03:54:04 PM PST 24
Finished Feb 01 03:54:11 PM PST 24
Peak memory 207320 kb
Host smart-7814db33-7bb2-4c8c-a3eb-620bc66b8b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814998720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2814998720
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2580875345
Short name T640
Test name
Test status
Simulation time 129785578 ps
CPU time 3.78 seconds
Started Feb 01 03:55:15 PM PST 24
Finished Feb 01 03:55:28 PM PST 24
Peak memory 219788 kb
Host smart-bee2def9-a6d3-496f-971d-f1958b9ac6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580875345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2580875345
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3559417697
Short name T331
Test name
Test status
Simulation time 1402228358 ps
CPU time 7.34 seconds
Started Feb 01 03:54:14 PM PST 24
Finished Feb 01 03:54:27 PM PST 24
Peak memory 222336 kb
Host smart-9191807d-10cc-4938-9a8e-afb8fa87c9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559417697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3559417697
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.462477597
Short name T5
Test name
Test status
Simulation time 137361688 ps
CPU time 3.5 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:27 PM PST 24
Peak memory 216244 kb
Host smart-4ad68e8b-9304-4e40-b7ce-771ca420f9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462477597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.462477597
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.798745914
Short name T638
Test name
Test status
Simulation time 57173175 ps
CPU time 3.85 seconds
Started Feb 01 03:55:12 PM PST 24
Finished Feb 01 03:55:25 PM PST 24
Peak memory 214252 kb
Host smart-46931e19-63e1-42d9-b6c1-6804124f6c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798745914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.798745914
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2395747643
Short name T358
Test name
Test status
Simulation time 233114667 ps
CPU time 3.54 seconds
Started Feb 01 03:56:02 PM PST 24
Finished Feb 01 03:56:09 PM PST 24
Peak memory 206904 kb
Host smart-4ff2f72d-b476-485f-b594-4f77cc264277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395747643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2395747643
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1380041626
Short name T703
Test name
Test status
Simulation time 47243709 ps
CPU time 2.59 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:08 PM PST 24
Peak memory 208392 kb
Host smart-c07e141c-b42c-43c4-9ba1-b410b241445c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380041626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1380041626
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1943974059
Short name T435
Test name
Test status
Simulation time 65715859 ps
CPU time 2.26 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:00 PM PST 24
Peak memory 206820 kb
Host smart-2e749d30-9022-4ba7-ab1e-079c3db710aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943974059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1943974059
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.4160038890
Short name T840
Test name
Test status
Simulation time 26363129 ps
CPU time 1.98 seconds
Started Feb 01 03:56:02 PM PST 24
Finished Feb 01 03:56:07 PM PST 24
Peak memory 206820 kb
Host smart-c4d68934-0a26-439a-bc75-a9c1f747c219
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160038890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.4160038890
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1711173579
Short name T1039
Test name
Test status
Simulation time 32105970 ps
CPU time 1.93 seconds
Started Feb 01 03:54:58 PM PST 24
Finished Feb 01 03:55:08 PM PST 24
Peak memory 209420 kb
Host smart-7537d520-1acd-42eb-8ca4-65de6e7a3a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711173579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1711173579
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2906824021
Short name T1004
Test name
Test status
Simulation time 348172955 ps
CPU time 6.38 seconds
Started Feb 01 03:56:03 PM PST 24
Finished Feb 01 03:56:12 PM PST 24
Peak memory 206908 kb
Host smart-1ac59cbf-4787-42cb-adf5-f01f5e285ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906824021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2906824021
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1541575389
Short name T380
Test name
Test status
Simulation time 518716941 ps
CPU time 7.17 seconds
Started Feb 01 03:53:31 PM PST 24
Finished Feb 01 03:53:53 PM PST 24
Peak memory 217368 kb
Host smart-6bcf125c-1822-490a-a792-ef3146c1034a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541575389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1541575389
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1031499725
Short name T405
Test name
Test status
Simulation time 6785729730 ps
CPU time 72.7 seconds
Started Feb 01 03:54:27 PM PST 24
Finished Feb 01 03:55:44 PM PST 24
Peak memory 209252 kb
Host smart-8cd093b6-5b78-427d-af7c-56e2f80728c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031499725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1031499725
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2866716575
Short name T919
Test name
Test status
Simulation time 75618141 ps
CPU time 2.89 seconds
Started Feb 01 03:53:03 PM PST 24
Finished Feb 01 03:53:25 PM PST 24
Peak memory 210012 kb
Host smart-fbaefcde-d487-40e8-908e-442f0f4f92c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866716575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2866716575
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2694047593
Short name T650
Test name
Test status
Simulation time 100272235 ps
CPU time 0.89 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:04 PM PST 24
Peak memory 205880 kb
Host smart-9609c4f5-d682-4c90-b3a3-d2095cae5c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694047593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2694047593
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3170049552
Short name T394
Test name
Test status
Simulation time 75187607 ps
CPU time 2.84 seconds
Started Feb 01 03:54:23 PM PST 24
Finished Feb 01 03:54:31 PM PST 24
Peak memory 214164 kb
Host smart-a02ecb1f-1b98-4fec-9db3-8698236a35b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170049552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3170049552
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1864503033
Short name T787
Test name
Test status
Simulation time 1495115429 ps
CPU time 10.65 seconds
Started Feb 01 03:56:03 PM PST 24
Finished Feb 01 03:56:16 PM PST 24
Peak memory 209428 kb
Host smart-88a65078-9c8d-4bc9-8bdd-c6af51931008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864503033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1864503033
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.4115170971
Short name T625
Test name
Test status
Simulation time 46755189 ps
CPU time 2.11 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:07 PM PST 24
Peak memory 208420 kb
Host smart-1e2079fa-4941-48c4-a864-9c4c8dd66016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115170971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.4115170971
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1994726735
Short name T23
Test name
Test status
Simulation time 120718730 ps
CPU time 3.13 seconds
Started Feb 01 03:54:42 PM PST 24
Finished Feb 01 03:54:50 PM PST 24
Peak memory 208016 kb
Host smart-9df3a22f-e720-48cd-8806-5f7572f54a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994726735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1994726735
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.103927445
Short name T239
Test name
Test status
Simulation time 69648602 ps
CPU time 3.8 seconds
Started Feb 01 03:56:03 PM PST 24
Finished Feb 01 03:56:09 PM PST 24
Peak memory 221168 kb
Host smart-da557b76-521a-4180-8e63-f4b60f1ff09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103927445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.103927445
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1105043491
Short name T204
Test name
Test status
Simulation time 256212264 ps
CPU time 4.2 seconds
Started Feb 01 03:54:55 PM PST 24
Finished Feb 01 03:55:05 PM PST 24
Peak memory 220064 kb
Host smart-6cc903ec-d6f7-4b43-9680-9d99d42a5abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105043491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1105043491
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2267422799
Short name T275
Test name
Test status
Simulation time 901203022 ps
CPU time 13.22 seconds
Started Feb 01 03:54:19 PM PST 24
Finished Feb 01 03:54:37 PM PST 24
Peak memory 208856 kb
Host smart-c49a034b-ce50-4b27-b1d8-0ef5b2c15b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267422799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2267422799
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.355556000
Short name T976
Test name
Test status
Simulation time 248613966 ps
CPU time 7.27 seconds
Started Feb 01 03:56:03 PM PST 24
Finished Feb 01 03:56:13 PM PST 24
Peak memory 207072 kb
Host smart-27276f57-6a58-4615-873f-198c0b489601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355556000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.355556000
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3208453435
Short name T602
Test name
Test status
Simulation time 41163493 ps
CPU time 2.44 seconds
Started Feb 01 03:53:57 PM PST 24
Finished Feb 01 03:54:06 PM PST 24
Peak memory 206708 kb
Host smart-95136c83-85e6-4a64-a3a6-a120ee6b259f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208453435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3208453435
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2920623713
Short name T949
Test name
Test status
Simulation time 189119724 ps
CPU time 2.77 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:02 PM PST 24
Peak memory 207816 kb
Host smart-f0dcb078-96e9-42ac-a51c-1ba1d6571903
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920623713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2920623713
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1655697475
Short name T994
Test name
Test status
Simulation time 557375311 ps
CPU time 2.55 seconds
Started Feb 01 03:53:26 PM PST 24
Finished Feb 01 03:53:43 PM PST 24
Peak memory 206744 kb
Host smart-e23d6f09-0cbe-43d0-88ea-fdb04693ef01
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655697475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1655697475
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.217518291
Short name T671
Test name
Test status
Simulation time 71049072 ps
CPU time 2.02 seconds
Started Feb 01 03:55:09 PM PST 24
Finished Feb 01 03:55:18 PM PST 24
Peak memory 209276 kb
Host smart-7e575d43-78e6-48ca-bffc-f84dec533f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217518291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.217518291
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2573728089
Short name T862
Test name
Test status
Simulation time 8851253831 ps
CPU time 48.34 seconds
Started Feb 01 03:54:53 PM PST 24
Finished Feb 01 03:55:44 PM PST 24
Peak memory 208152 kb
Host smart-7b62bf2b-6d43-44b4-b28c-9bcd7ae811e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573728089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2573728089
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2123228896
Short name T977
Test name
Test status
Simulation time 552142109 ps
CPU time 3.03 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:32 PM PST 24
Peak memory 219052 kb
Host smart-6b35fc43-91fc-4a0a-9b52-51df0ddea8a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123228896 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2123228896
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2407314005
Short name T12
Test name
Test status
Simulation time 2465347743 ps
CPU time 11.22 seconds
Started Feb 01 03:56:03 PM PST 24
Finished Feb 01 03:56:16 PM PST 24
Peak memory 213460 kb
Host smart-acd422d0-7711-4b24-a2f5-5aed0cb00c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407314005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2407314005
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3978289265
Short name T39
Test name
Test status
Simulation time 264352802 ps
CPU time 2.68 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:32 PM PST 24
Peak memory 209940 kb
Host smart-a313e744-e17f-4564-b056-dd21f96d8ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978289265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3978289265
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3067350291
Short name T1030
Test name
Test status
Simulation time 17698472 ps
CPU time 0.72 seconds
Started Feb 01 03:45:10 PM PST 24
Finished Feb 01 03:45:45 PM PST 24
Peak memory 205812 kb
Host smart-0b304b86-c369-4b2e-bb59-118a049a312f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067350291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3067350291
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3013177394
Short name T1075
Test name
Test status
Simulation time 486189510 ps
CPU time 5.05 seconds
Started Feb 01 03:45:05 PM PST 24
Finished Feb 01 03:45:41 PM PST 24
Peak memory 209888 kb
Host smart-15e7aa6b-dfe5-41d9-84b6-bcd03d4e88ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013177394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3013177394
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.835986026
Short name T722
Test name
Test status
Simulation time 64758212 ps
CPU time 2.4 seconds
Started Feb 01 03:45:03 PM PST 24
Finished Feb 01 03:45:38 PM PST 24
Peak memory 207596 kb
Host smart-fbd5c7ae-3839-4285-ab36-6a6e610fb14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835986026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.835986026
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2817282150
Short name T365
Test name
Test status
Simulation time 702126795 ps
CPU time 2.83 seconds
Started Feb 01 03:45:43 PM PST 24
Finished Feb 01 03:46:39 PM PST 24
Peak memory 218888 kb
Host smart-216bff92-c346-4bb4-a844-e0b43d8123d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817282150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2817282150
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.4094519653
Short name T876
Test name
Test status
Simulation time 64470015 ps
CPU time 2.7 seconds
Started Feb 01 03:45:06 PM PST 24
Finished Feb 01 03:45:42 PM PST 24
Peak memory 208896 kb
Host smart-c6659765-3392-46a6-8332-7f64ab5ceb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094519653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.4094519653
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1243977994
Short name T778
Test name
Test status
Simulation time 46757081 ps
CPU time 2.94 seconds
Started Feb 01 03:45:14 PM PST 24
Finished Feb 01 03:45:55 PM PST 24
Peak memory 218244 kb
Host smart-113899a0-e18c-4f19-9942-aa6a5a5969e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243977994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1243977994
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3297778364
Short name T96
Test name
Test status
Simulation time 4723970905 ps
CPU time 26.12 seconds
Started Feb 01 03:45:31 PM PST 24
Finished Feb 01 03:46:44 PM PST 24
Peak memory 236008 kb
Host smart-65a93720-2017-4503-b6fb-7b5ac1703487
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297778364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3297778364
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3212371926
Short name T185
Test name
Test status
Simulation time 124404761 ps
CPU time 2.96 seconds
Started Feb 01 03:44:54 PM PST 24
Finished Feb 01 03:45:22 PM PST 24
Peak memory 206552 kb
Host smart-d7bfefe7-e566-467d-a6f3-7302f6f1c1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212371926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3212371926
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1120557724
Short name T633
Test name
Test status
Simulation time 402951736 ps
CPU time 6.74 seconds
Started Feb 01 03:44:52 PM PST 24
Finished Feb 01 03:45:25 PM PST 24
Peak memory 207844 kb
Host smart-455e6eed-db81-47b7-81af-0758a9679e88
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120557724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1120557724
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2248730418
Short name T706
Test name
Test status
Simulation time 56331504 ps
CPU time 2.79 seconds
Started Feb 01 03:45:19 PM PST 24
Finished Feb 01 03:46:01 PM PST 24
Peak memory 206692 kb
Host smart-5f263017-9e37-4b49-b569-bd5b1d6c0d9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248730418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2248730418
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2480493028
Short name T879
Test name
Test status
Simulation time 101466310 ps
CPU time 2.86 seconds
Started Feb 01 03:45:07 PM PST 24
Finished Feb 01 03:45:44 PM PST 24
Peak memory 206800 kb
Host smart-813ac64a-d5ac-4518-8d65-f16446424ca0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480493028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2480493028
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.211465695
Short name T882
Test name
Test status
Simulation time 458648482 ps
CPU time 2.3 seconds
Started Feb 01 03:46:32 PM PST 24
Finished Feb 01 03:47:25 PM PST 24
Peak memory 207696 kb
Host smart-c725ccff-9b11-4dde-8e65-66342bd8058e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211465695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.211465695
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.540586692
Short name T897
Test name
Test status
Simulation time 829209314 ps
CPU time 4.94 seconds
Started Feb 01 03:45:53 PM PST 24
Finished Feb 01 03:46:54 PM PST 24
Peak memory 208456 kb
Host smart-be6d931a-8105-4136-bc50-6278b77dd4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540586692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.540586692
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1229716395
Short name T112
Test name
Test status
Simulation time 614385775 ps
CPU time 5.51 seconds
Started Feb 01 03:45:23 PM PST 24
Finished Feb 01 03:46:10 PM PST 24
Peak memory 219848 kb
Host smart-796b9411-cbeb-47c6-9a33-75572583dc1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229716395 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1229716395
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1670994805
Short name T853
Test name
Test status
Simulation time 325841299 ps
CPU time 8.36 seconds
Started Feb 01 03:45:09 PM PST 24
Finished Feb 01 03:45:53 PM PST 24
Peak memory 217780 kb
Host smart-6ba2871c-b4e1-437d-84ac-ecbd4c448308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670994805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1670994805
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3157052107
Short name T159
Test name
Test status
Simulation time 489040466 ps
CPU time 8.27 seconds
Started Feb 01 03:47:22 PM PST 24
Finished Feb 01 03:48:10 PM PST 24
Peak memory 210344 kb
Host smart-913a26f0-644f-4eba-95d3-082e194a70c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157052107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3157052107
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2274951488
Short name T732
Test name
Test status
Simulation time 18980977 ps
CPU time 0.88 seconds
Started Feb 01 03:55:15 PM PST 24
Finished Feb 01 03:55:26 PM PST 24
Peak memory 205588 kb
Host smart-e781fc0e-4063-4128-89db-1291fdd8d628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274951488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2274951488
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3865300090
Short name T956
Test name
Test status
Simulation time 5365117733 ps
CPU time 24.14 seconds
Started Feb 01 03:53:51 PM PST 24
Finished Feb 01 03:54:21 PM PST 24
Peak memory 214252 kb
Host smart-b0db65b5-aec2-4441-adce-52d18675014d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865300090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3865300090
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3543094819
Short name T980
Test name
Test status
Simulation time 188897667 ps
CPU time 2.75 seconds
Started Feb 01 03:56:09 PM PST 24
Finished Feb 01 03:56:15 PM PST 24
Peak memory 205696 kb
Host smart-f67e90b7-2ed5-475b-8d67-44b8b6bd51d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543094819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3543094819
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2041832846
Short name T758
Test name
Test status
Simulation time 429406780 ps
CPU time 4.77 seconds
Started Feb 01 03:55:16 PM PST 24
Finished Feb 01 03:55:30 PM PST 24
Peak memory 214180 kb
Host smart-2308f86a-7934-49e9-8ac7-276e523d3eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041832846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2041832846
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1472741487
Short name T195
Test name
Test status
Simulation time 2833287165 ps
CPU time 30.22 seconds
Started Feb 01 03:53:35 PM PST 24
Finished Feb 01 03:54:20 PM PST 24
Peak memory 210312 kb
Host smart-00202426-d5de-4eaa-af56-fdaa9fbaf964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472741487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1472741487
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.562354212
Short name T945
Test name
Test status
Simulation time 578357077 ps
CPU time 6.21 seconds
Started Feb 01 03:54:55 PM PST 24
Finished Feb 01 03:55:07 PM PST 24
Peak memory 219576 kb
Host smart-8a281fba-0487-4d7f-8906-a48b4c8ad1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562354212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.562354212
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3534749995
Short name T196
Test name
Test status
Simulation time 225030820 ps
CPU time 7.01 seconds
Started Feb 01 03:55:01 PM PST 24
Finished Feb 01 03:55:17 PM PST 24
Peak memory 208096 kb
Host smart-9b91b398-3e07-43eb-b453-796007e1e54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534749995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3534749995
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.518014852
Short name T1001
Test name
Test status
Simulation time 126247544 ps
CPU time 2.36 seconds
Started Feb 01 03:55:00 PM PST 24
Finished Feb 01 03:55:11 PM PST 24
Peak memory 206664 kb
Host smart-f8244376-64ef-4ebb-a841-8bbfc0c2e763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518014852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.518014852
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.4189499533
Short name T909
Test name
Test status
Simulation time 174672713 ps
CPU time 2.45 seconds
Started Feb 01 03:54:13 PM PST 24
Finished Feb 01 03:54:22 PM PST 24
Peak memory 206764 kb
Host smart-797f0ce2-4117-4baf-a07f-54a9e4986bb7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189499533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4189499533
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2393716749
Short name T408
Test name
Test status
Simulation time 168594188 ps
CPU time 4.59 seconds
Started Feb 01 03:56:09 PM PST 24
Finished Feb 01 03:56:16 PM PST 24
Peak memory 205660 kb
Host smart-cca7e6e1-6dc6-477b-86e6-55685df8cdb7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393716749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2393716749
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2342284595
Short name T719
Test name
Test status
Simulation time 1431025755 ps
CPU time 7.46 seconds
Started Feb 01 03:53:26 PM PST 24
Finished Feb 01 03:53:50 PM PST 24
Peak memory 207812 kb
Host smart-ad150fd3-5b2d-4db6-b4d0-96dc25c74d50
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342284595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2342284595
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3720391215
Short name T347
Test name
Test status
Simulation time 285628151 ps
CPU time 2.86 seconds
Started Feb 01 03:54:50 PM PST 24
Finished Feb 01 03:54:56 PM PST 24
Peak memory 209740 kb
Host smart-2bc498c5-342e-459e-8a20-308cfa044792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720391215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3720391215
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.836333540
Short name T578
Test name
Test status
Simulation time 396009170 ps
CPU time 4.37 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:10 PM PST 24
Peak memory 205828 kb
Host smart-a1085750-160a-4ec3-a9a7-569e3ed819eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836333540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.836333540
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1226947796
Short name T177
Test name
Test status
Simulation time 410575988 ps
CPU time 13.52 seconds
Started Feb 01 03:53:45 PM PST 24
Finished Feb 01 03:54:07 PM PST 24
Peak memory 214228 kb
Host smart-a1f6fde4-f26d-4895-a07d-796ee22b34bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226947796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1226947796
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.320391352
Short name T974
Test name
Test status
Simulation time 1030765181 ps
CPU time 11.07 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:14 PM PST 24
Peak memory 222780 kb
Host smart-81314314-6cba-454c-b7ff-76ff0dfff755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320391352 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.320391352
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3816172495
Short name T822
Test name
Test status
Simulation time 1020169169 ps
CPU time 5.6 seconds
Started Feb 01 03:56:09 PM PST 24
Finished Feb 01 03:56:17 PM PST 24
Peak memory 209248 kb
Host smart-fba25743-6b0c-44d9-8da2-b011f9d6e6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816172495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3816172495
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.146331159
Short name T581
Test name
Test status
Simulation time 218165698 ps
CPU time 1.83 seconds
Started Feb 01 03:55:00 PM PST 24
Finished Feb 01 03:55:10 PM PST 24
Peak memory 209752 kb
Host smart-324d1f9f-21ba-4662-94e0-e1774e929881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146331159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.146331159
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2811167787
Short name T572
Test name
Test status
Simulation time 22925932 ps
CPU time 0.72 seconds
Started Feb 01 03:56:13 PM PST 24
Finished Feb 01 03:56:21 PM PST 24
Peak memory 204884 kb
Host smart-7b42a358-92a3-4727-9ab7-fef3485ebb19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811167787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2811167787
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2540734339
Short name T250
Test name
Test status
Simulation time 253918608 ps
CPU time 4.4 seconds
Started Feb 01 03:54:53 PM PST 24
Finished Feb 01 03:55:00 PM PST 24
Peak memory 215424 kb
Host smart-b40aea71-0002-4099-98e2-a405e9b33f33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540734339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2540734339
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3592009432
Short name T289
Test name
Test status
Simulation time 158337375 ps
CPU time 3.97 seconds
Started Feb 01 03:55:06 PM PST 24
Finished Feb 01 03:55:16 PM PST 24
Peak memory 220032 kb
Host smart-2c9bca28-6361-42f2-aba2-ea5029827969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592009432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3592009432
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2787762354
Short name T258
Test name
Test status
Simulation time 252345313 ps
CPU time 4.02 seconds
Started Feb 01 03:53:44 PM PST 24
Finished Feb 01 03:53:56 PM PST 24
Peak memory 211244 kb
Host smart-cdb3067f-e4c6-4e5a-9fd6-74cff4598db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787762354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2787762354
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.634888547
Short name T874
Test name
Test status
Simulation time 282697018 ps
CPU time 5.39 seconds
Started Feb 01 03:56:13 PM PST 24
Finished Feb 01 03:56:25 PM PST 24
Peak memory 219524 kb
Host smart-7c431000-d3da-4a33-9b23-ad4be27de39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634888547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.634888547
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3431806790
Short name T983
Test name
Test status
Simulation time 64035163 ps
CPU time 3.95 seconds
Started Feb 01 03:55:12 PM PST 24
Finished Feb 01 03:55:25 PM PST 24
Peak memory 209492 kb
Host smart-47f7fb7b-1197-4b7f-a57a-ecad1f92a7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431806790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3431806790
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.937657139
Short name T1069
Test name
Test status
Simulation time 971414744 ps
CPU time 6.72 seconds
Started Feb 01 03:54:32 PM PST 24
Finished Feb 01 03:54:44 PM PST 24
Peak memory 206604 kb
Host smart-d9620a6a-0386-4a1d-9cf8-9fa680edad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937657139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.937657139
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.100905187
Short name T406
Test name
Test status
Simulation time 60795493 ps
CPU time 3.15 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:26 PM PST 24
Peak memory 206824 kb
Host smart-67ed3e74-2e6c-493b-8a56-662db58ee9df
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100905187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.100905187
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1785755909
Short name T642
Test name
Test status
Simulation time 546582386 ps
CPU time 4.16 seconds
Started Feb 01 03:55:00 PM PST 24
Finished Feb 01 03:55:13 PM PST 24
Peak memory 208620 kb
Host smart-bf22cc8e-8e39-4146-bd6b-f2a33b830e2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785755909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1785755909
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3371279395
Short name T712
Test name
Test status
Simulation time 496105218 ps
CPU time 5.5 seconds
Started Feb 01 03:54:20 PM PST 24
Finished Feb 01 03:54:30 PM PST 24
Peak memory 208852 kb
Host smart-fc20e3ad-4b19-4e3a-bb67-0e5e01aabb08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371279395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3371279395
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2650765969
Short name T1026
Test name
Test status
Simulation time 3530714403 ps
CPU time 10.39 seconds
Started Feb 01 03:56:13 PM PST 24
Finished Feb 01 03:56:30 PM PST 24
Peak memory 216968 kb
Host smart-e703e17a-1c83-4dc4-8115-fc4be1577781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650765969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2650765969
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3045517039
Short name T847
Test name
Test status
Simulation time 40483036 ps
CPU time 1.75 seconds
Started Feb 01 03:53:38 PM PST 24
Finished Feb 01 03:53:52 PM PST 24
Peak memory 206600 kb
Host smart-50600914-3679-4e90-9b10-e16f3faf1631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045517039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3045517039
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3805660849
Short name T205
Test name
Test status
Simulation time 424895263 ps
CPU time 19.37 seconds
Started Feb 01 03:53:55 PM PST 24
Finished Feb 01 03:54:20 PM PST 24
Peak memory 222476 kb
Host smart-286131df-cbe1-439f-990e-f912ed9e0feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805660849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3805660849
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.630481271
Short name T833
Test name
Test status
Simulation time 89825696 ps
CPU time 3.25 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:28 PM PST 24
Peak memory 214120 kb
Host smart-07352355-1b50-4643-bd62-910fcc97ffb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630481271 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.630481271
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1432096429
Short name T40
Test name
Test status
Simulation time 223003149 ps
CPU time 6.76 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:06 PM PST 24
Peak memory 222324 kb
Host smart-672b332d-75da-4e2e-af64-4670040e1f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432096429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1432096429
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3237364835
Short name T1035
Test name
Test status
Simulation time 527637224 ps
CPU time 2.94 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:26 PM PST 24
Peak memory 210764 kb
Host smart-f6738a82-227c-4346-a286-b82dd4d60949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237364835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3237364835
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3654616782
Short name T907
Test name
Test status
Simulation time 13678177 ps
CPU time 0.76 seconds
Started Feb 01 03:55:00 PM PST 24
Finished Feb 01 03:55:08 PM PST 24
Peak memory 205780 kb
Host smart-15d50bdf-9b24-49c4-bfd0-f429bb2c2465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654616782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3654616782
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.950441741
Short name T307
Test name
Test status
Simulation time 364342190 ps
CPU time 10.49 seconds
Started Feb 01 03:54:53 PM PST 24
Finished Feb 01 03:55:07 PM PST 24
Peak memory 215544 kb
Host smart-908166a4-0052-4b84-acec-09cf0fbda37d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950441741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.950441741
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2800767438
Short name T287
Test name
Test status
Simulation time 549738860 ps
CPU time 6.15 seconds
Started Feb 01 03:54:55 PM PST 24
Finished Feb 01 03:55:06 PM PST 24
Peak memory 221272 kb
Host smart-f4429007-7ee0-4d08-9e13-24c785749cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800767438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2800767438
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1681948684
Short name T668
Test name
Test status
Simulation time 61397131 ps
CPU time 1.94 seconds
Started Feb 01 03:56:13 PM PST 24
Finished Feb 01 03:56:21 PM PST 24
Peak memory 207896 kb
Host smart-aed2efc9-f494-4afa-ae0f-8f9c2917e511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681948684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1681948684
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3023527527
Short name T993
Test name
Test status
Simulation time 1201136782 ps
CPU time 22.11 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:21 PM PST 24
Peak memory 214272 kb
Host smart-cd83302f-bf65-47ab-bf0e-4e6d3b01c5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023527527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3023527527
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.269945905
Short name T259
Test name
Test status
Simulation time 346376681 ps
CPU time 4.39 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:04 PM PST 24
Peak memory 214192 kb
Host smart-442b0aa8-e025-4b18-bec2-6c9bf9fc241b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269945905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.269945905
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3111124619
Short name T654
Test name
Test status
Simulation time 222964625 ps
CPU time 2.25 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:25 PM PST 24
Peak memory 220364 kb
Host smart-aa9570ac-b7a9-48a6-81da-fa26c07ffb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111124619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3111124619
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1283611768
Short name T704
Test name
Test status
Simulation time 279524561 ps
CPU time 9 seconds
Started Feb 01 03:55:01 PM PST 24
Finished Feb 01 03:55:18 PM PST 24
Peak memory 209056 kb
Host smart-31803dca-c66c-4fd5-99fd-a3b0bd77e32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283611768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1283611768
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1887175599
Short name T78
Test name
Test status
Simulation time 184883247 ps
CPU time 4.03 seconds
Started Feb 01 03:54:58 PM PST 24
Finished Feb 01 03:55:10 PM PST 24
Peak memory 206640 kb
Host smart-7c60958a-ba79-4513-80ab-8bf076a92df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887175599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1887175599
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3038896796
Short name T612
Test name
Test status
Simulation time 69101931 ps
CPU time 3.32 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:00 PM PST 24
Peak memory 207900 kb
Host smart-8a8e997e-009b-444a-956e-e522954a6a95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038896796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3038896796
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1950852026
Short name T713
Test name
Test status
Simulation time 608412556 ps
CPU time 4.82 seconds
Started Feb 01 03:54:22 PM PST 24
Finished Feb 01 03:54:31 PM PST 24
Peak memory 206724 kb
Host smart-fff6ac12-7e5e-44ce-b1c7-b96e535fc825
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950852026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1950852026
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.87571010
Short name T700
Test name
Test status
Simulation time 117551099 ps
CPU time 4.02 seconds
Started Feb 01 03:54:00 PM PST 24
Finished Feb 01 03:54:10 PM PST 24
Peak memory 206808 kb
Host smart-8b7c3f89-c8e6-4d36-90cf-6a1ec4383492
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87571010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.87571010
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.986075545
Short name T345
Test name
Test status
Simulation time 386805855 ps
CPU time 2.4 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:08 PM PST 24
Peak memory 207260 kb
Host smart-3e80533e-10a1-4082-89ab-28fb8330a0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986075545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.986075545
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1153327204
Short name T871
Test name
Test status
Simulation time 858256426 ps
CPU time 6.21 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:31 PM PST 24
Peak memory 206568 kb
Host smart-57b1c18a-1562-459b-a725-a2a449de6d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153327204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1153327204
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1484130477
Short name T819
Test name
Test status
Simulation time 51305457 ps
CPU time 3.56 seconds
Started Feb 01 03:55:10 PM PST 24
Finished Feb 01 03:55:20 PM PST 24
Peak memory 222500 kb
Host smart-7850362b-9d6b-43da-be09-86e0a910c005
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484130477 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1484130477
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1608482854
Short name T386
Test name
Test status
Simulation time 82332504 ps
CPU time 3.87 seconds
Started Feb 01 03:55:08 PM PST 24
Finished Feb 01 03:55:18 PM PST 24
Peak memory 214144 kb
Host smart-389c03fa-6df5-4bf6-8f5e-ee0d22834504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608482854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1608482854
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1256139609
Short name T921
Test name
Test status
Simulation time 10188197 ps
CPU time 0.73 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:24 PM PST 24
Peak memory 205724 kb
Host smart-16d74a33-895c-43dd-8822-fad25b0e2693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256139609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1256139609
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1183032326
Short name T280
Test name
Test status
Simulation time 120300853 ps
CPU time 4.25 seconds
Started Feb 01 03:56:12 PM PST 24
Finished Feb 01 03:56:23 PM PST 24
Peak memory 213948 kb
Host smart-92ef46de-3e2c-4a5b-b062-0740736511f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1183032326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1183032326
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.672754334
Short name T27
Test name
Test status
Simulation time 953963308 ps
CPU time 10.77 seconds
Started Feb 01 03:55:11 PM PST 24
Finished Feb 01 03:55:31 PM PST 24
Peak memory 222640 kb
Host smart-c5ae3af4-c97d-4113-9bf5-af525e8c0c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672754334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.672754334
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.361099863
Short name T69
Test name
Test status
Simulation time 426100500 ps
CPU time 9.95 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:12 PM PST 24
Peak memory 208756 kb
Host smart-e4fe6b6a-face-4130-bdf0-6f12ccb9f963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361099863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.361099863
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.856413302
Short name T302
Test name
Test status
Simulation time 136863093 ps
CPU time 4.68 seconds
Started Feb 01 03:55:12 PM PST 24
Finished Feb 01 03:55:25 PM PST 24
Peak memory 209424 kb
Host smart-ef66f582-ca2e-43d1-8f98-e17987118217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856413302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.856413302
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3195363740
Short name T244
Test name
Test status
Simulation time 124017939 ps
CPU time 2.55 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:07 PM PST 24
Peak memory 210028 kb
Host smart-1a704fb5-a559-4d23-8463-6d7d05c7eda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195363740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3195363740
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1165939820
Short name T745
Test name
Test status
Simulation time 203413146 ps
CPU time 5.48 seconds
Started Feb 01 03:56:12 PM PST 24
Finished Feb 01 03:56:24 PM PST 24
Peak memory 206804 kb
Host smart-dc046808-11ec-46c8-b5bf-0a9e3cfb14cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165939820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1165939820
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2335821460
Short name T349
Test name
Test status
Simulation time 809473970 ps
CPU time 3.29 seconds
Started Feb 01 03:56:14 PM PST 24
Finished Feb 01 03:56:23 PM PST 24
Peak memory 206160 kb
Host smart-a91ca891-07eb-4d95-a0ea-18c711fb83ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335821460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2335821460
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4116424096
Short name T192
Test name
Test status
Simulation time 1141420553 ps
CPU time 25.63 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:31 PM PST 24
Peak memory 209024 kb
Host smart-41539232-2b41-4139-bd9d-ada489e0cdb1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116424096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4116424096
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4141329898
Short name T1000
Test name
Test status
Simulation time 694835280 ps
CPU time 5.23 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:34 PM PST 24
Peak memory 208688 kb
Host smart-3e7f54f8-ed84-40cb-84bb-c0befb8b772a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141329898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4141329898
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2878828821
Short name T707
Test name
Test status
Simulation time 1129224036 ps
CPU time 34.47 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:33 PM PST 24
Peak memory 208200 kb
Host smart-79ac11c3-8895-4bc1-816a-cd2700103682
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878828821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2878828821
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1331892692
Short name T183
Test name
Test status
Simulation time 131642000 ps
CPU time 2.74 seconds
Started Feb 01 03:53:10 PM PST 24
Finished Feb 01 03:53:36 PM PST 24
Peak memory 208320 kb
Host smart-f75e1c07-95bc-40df-9b33-bdf796e7956b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331892692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1331892692
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1880749259
Short name T404
Test name
Test status
Simulation time 121988874 ps
CPU time 3.58 seconds
Started Feb 01 03:55:17 PM PST 24
Finished Feb 01 03:55:30 PM PST 24
Peak memory 206984 kb
Host smart-f5212723-e2b1-47b1-835e-7c6a46b90842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880749259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1880749259
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2990582682
Short name T584
Test name
Test status
Simulation time 459858002 ps
CPU time 3.73 seconds
Started Feb 01 03:55:00 PM PST 24
Finished Feb 01 03:55:13 PM PST 24
Peak memory 221040 kb
Host smart-57564dd6-eb6b-4058-983c-fea57011dd3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990582682 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2990582682
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3357145451
Short name T424
Test name
Test status
Simulation time 306722124 ps
CPU time 6.49 seconds
Started Feb 01 03:56:12 PM PST 24
Finished Feb 01 03:56:26 PM PST 24
Peak memory 208628 kb
Host smart-22ed4969-8e98-48a8-8b47-84d10e7a9fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357145451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3357145451
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3369977606
Short name T92
Test name
Test status
Simulation time 168898359 ps
CPU time 1.51 seconds
Started Feb 01 03:54:55 PM PST 24
Finished Feb 01 03:55:03 PM PST 24
Peak memory 209532 kb
Host smart-7a5e6139-7014-4f83-a3e4-5bdb324bca8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369977606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3369977606
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2503581197
Short name T708
Test name
Test status
Simulation time 46223240 ps
CPU time 0.79 seconds
Started Feb 01 03:54:53 PM PST 24
Finished Feb 01 03:54:57 PM PST 24
Peak memory 205800 kb
Host smart-2e575326-f24f-4a9d-963f-f9e7f82d6af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503581197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2503581197
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3824163608
Short name T115
Test name
Test status
Simulation time 1325012737 ps
CPU time 17.09 seconds
Started Feb 01 03:55:01 PM PST 24
Finished Feb 01 03:55:27 PM PST 24
Peak memory 214352 kb
Host smart-639400b6-ca59-45ef-9460-5521bbba38e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3824163608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3824163608
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3659759675
Short name T946
Test name
Test status
Simulation time 57940786 ps
CPU time 2.78 seconds
Started Feb 01 03:53:51 PM PST 24
Finished Feb 01 03:54:01 PM PST 24
Peak memory 218804 kb
Host smart-5325d8b2-76f0-452b-a1de-fe8a9fc27a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659759675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3659759675
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4071653408
Short name T375
Test name
Test status
Simulation time 10785819138 ps
CPU time 90.89 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:56:55 PM PST 24
Peak memory 218348 kb
Host smart-3dbb04a5-644b-444a-a5d5-295039f1e2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071653408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4071653408
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3868737993
Short name T618
Test name
Test status
Simulation time 1530130519 ps
CPU time 30.34 seconds
Started Feb 01 03:55:08 PM PST 24
Finished Feb 01 03:55:46 PM PST 24
Peak memory 214128 kb
Host smart-c7f0b397-a01f-44ce-b15f-a250bfd4f52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868737993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3868737993
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2595679169
Short name T1010
Test name
Test status
Simulation time 2646725043 ps
CPU time 10.21 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:34 PM PST 24
Peak memory 214204 kb
Host smart-c0b92533-e0c1-47a9-8993-47c4a1f75cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595679169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2595679169
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2642675535
Short name T883
Test name
Test status
Simulation time 526170672 ps
CPU time 4.38 seconds
Started Feb 01 03:55:10 PM PST 24
Finished Feb 01 03:55:21 PM PST 24
Peak memory 214876 kb
Host smart-4974debc-49d0-4c41-a3b1-bf9fc5724b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642675535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2642675535
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1663908874
Short name T353
Test name
Test status
Simulation time 1307473647 ps
CPU time 11.42 seconds
Started Feb 01 03:55:06 PM PST 24
Finished Feb 01 03:55:24 PM PST 24
Peak memory 209872 kb
Host smart-49652e1f-35b5-453c-9e7b-b05122e73f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663908874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1663908874
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.209270771
Short name T800
Test name
Test status
Simulation time 383028699 ps
CPU time 4.42 seconds
Started Feb 01 03:56:13 PM PST 24
Finished Feb 01 03:56:24 PM PST 24
Peak memory 205020 kb
Host smart-862820e2-7763-4417-b91d-c1f2c64aef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209270771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.209270771
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.4228170081
Short name T684
Test name
Test status
Simulation time 261128293 ps
CPU time 7.27 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:12 PM PST 24
Peak memory 208408 kb
Host smart-c944efed-e1d7-4311-a19e-747c976a2ca1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228170081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.4228170081
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.644422950
Short name T413
Test name
Test status
Simulation time 102661216 ps
CPU time 4.24 seconds
Started Feb 01 03:55:09 PM PST 24
Finished Feb 01 03:55:20 PM PST 24
Peak memory 206764 kb
Host smart-b89a939b-4ca5-4ecd-975b-188922ac6de3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644422950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.644422950
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.548512207
Short name T198
Test name
Test status
Simulation time 280831906 ps
CPU time 6.93 seconds
Started Feb 01 03:55:01 PM PST 24
Finished Feb 01 03:55:17 PM PST 24
Peak memory 208640 kb
Host smart-4d525e32-6c70-46ba-b7c7-f3ea38d708ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548512207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.548512207
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3278268462
Short name T229
Test name
Test status
Simulation time 558613637 ps
CPU time 3.37 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:27 PM PST 24
Peak memory 207820 kb
Host smart-86d99bd1-21d9-46dd-998b-5eecaaa8574b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278268462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3278268462
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3055229850
Short name T647
Test name
Test status
Simulation time 298330468 ps
CPU time 2.64 seconds
Started Feb 01 03:55:12 PM PST 24
Finished Feb 01 03:55:24 PM PST 24
Peak memory 206632 kb
Host smart-1fcdbd62-f69d-47ca-b44b-d0f1edb46c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055229850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3055229850
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.621905334
Short name T988
Test name
Test status
Simulation time 329690213 ps
CPU time 8.34 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:12 PM PST 24
Peak memory 222236 kb
Host smart-3bb49dab-edf3-45d6-9472-55810868c74f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621905334 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.621905334
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.123581690
Short name T744
Test name
Test status
Simulation time 93536101 ps
CPU time 4.33 seconds
Started Feb 01 03:55:08 PM PST 24
Finished Feb 01 03:55:20 PM PST 24
Peak memory 207360 kb
Host smart-080b5c92-44bd-4a42-acd6-b79eb2721ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123581690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.123581690
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3720579857
Short name T637
Test name
Test status
Simulation time 274454193 ps
CPU time 2.73 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:06 PM PST 24
Peak memory 209896 kb
Host smart-0a33520a-433a-40b7-bb74-9072e21a8e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720579857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3720579857
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.436408178
Short name T658
Test name
Test status
Simulation time 11750039 ps
CPU time 0.72 seconds
Started Feb 01 03:54:40 PM PST 24
Finished Feb 01 03:54:44 PM PST 24
Peak memory 205824 kb
Host smart-90a54320-fe4d-4044-ab41-cd3468758940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436408178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.436408178
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1271560759
Short name T431
Test name
Test status
Simulation time 44333460 ps
CPU time 2.86 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:25 PM PST 24
Peak memory 214792 kb
Host smart-3e62102e-4d32-440d-9a6c-1ad85d1b2809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271560759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1271560759
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3607829623
Short name T20
Test name
Test status
Simulation time 79835635 ps
CPU time 1.85 seconds
Started Feb 01 03:56:02 PM PST 24
Finished Feb 01 03:56:06 PM PST 24
Peak memory 215224 kb
Host smart-b5a73e92-8dfc-46ff-a947-a05e9be364c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607829623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3607829623
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2299515006
Short name T942
Test name
Test status
Simulation time 246836092 ps
CPU time 2.17 seconds
Started Feb 01 03:54:27 PM PST 24
Finished Feb 01 03:54:34 PM PST 24
Peak memory 207224 kb
Host smart-6e31ff05-6601-45a6-882f-9b3570beb5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299515006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2299515006
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2776723954
Short name T309
Test name
Test status
Simulation time 70616922 ps
CPU time 2.57 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:26 PM PST 24
Peak memory 218924 kb
Host smart-725bf20b-147d-4b31-a85f-de54a001b359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776723954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2776723954
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.526470942
Short name T44
Test name
Test status
Simulation time 179124789 ps
CPU time 2.78 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:31 PM PST 24
Peak memory 209668 kb
Host smart-45d0f267-c5af-43d3-a67f-07f9eb1c634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526470942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.526470942
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1813729711
Short name T587
Test name
Test status
Simulation time 7358036383 ps
CPU time 88.93 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:56:58 PM PST 24
Peak memory 222372 kb
Host smart-7ede676b-6272-4bd4-9861-c1a3aef907dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813729711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1813729711
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3258732479
Short name T940
Test name
Test status
Simulation time 1049271801 ps
CPU time 26.51 seconds
Started Feb 01 03:55:08 PM PST 24
Finished Feb 01 03:55:42 PM PST 24
Peak memory 207868 kb
Host smart-cc821d1b-b202-498c-8e9a-0d24fbd77bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258732479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3258732479
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3682580746
Short name T951
Test name
Test status
Simulation time 2911738900 ps
CPU time 20.11 seconds
Started Feb 01 03:54:55 PM PST 24
Finished Feb 01 03:55:20 PM PST 24
Peak memory 207964 kb
Host smart-bafb1f4a-61a5-4798-a0ee-792800128f4f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682580746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3682580746
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2899792677
Short name T820
Test name
Test status
Simulation time 2175572233 ps
CPU time 38.2 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:56:01 PM PST 24
Peak memory 208680 kb
Host smart-804ccd1d-9a6c-4f32-b555-1e3881358b63
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899792677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2899792677
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3282233249
Short name T672
Test name
Test status
Simulation time 537446019 ps
CPU time 4.26 seconds
Started Feb 01 03:55:15 PM PST 24
Finished Feb 01 03:55:29 PM PST 24
Peak memory 208516 kb
Host smart-42817da1-b417-4417-887d-dfb8ec9b476c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282233249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3282233249
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3544427240
Short name T727
Test name
Test status
Simulation time 84082684 ps
CPU time 1.47 seconds
Started Feb 01 03:55:09 PM PST 24
Finished Feb 01 03:55:18 PM PST 24
Peak memory 206972 kb
Host smart-a1a2fd5b-23b1-4a01-bc54-7a0dbba29a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544427240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3544427240
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.4277624629
Short name T806
Test name
Test status
Simulation time 274005792 ps
CPU time 3.84 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:27 PM PST 24
Peak memory 206412 kb
Host smart-d3af3dfe-67a6-4511-ba16-6265f329f365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277624629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.4277624629
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.716322894
Short name T412
Test name
Test status
Simulation time 584121551 ps
CPU time 5.96 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:29 PM PST 24
Peak memory 221628 kb
Host smart-ce192029-d1a0-4603-a792-d28eada598b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716322894 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.716322894
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1143509204
Short name T892
Test name
Test status
Simulation time 1487385226 ps
CPU time 11.47 seconds
Started Feb 01 03:54:15 PM PST 24
Finished Feb 01 03:54:32 PM PST 24
Peak memory 209896 kb
Host smart-d9ce3283-7619-4148-86ca-75b991183dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143509204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1143509204
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1443730422
Short name T55
Test name
Test status
Simulation time 72257715 ps
CPU time 2.28 seconds
Started Feb 01 03:55:33 PM PST 24
Finished Feb 01 03:55:44 PM PST 24
Peak memory 209656 kb
Host smart-ec840e74-21a7-4eba-8052-3731067e0d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443730422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1443730422
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4179414801
Short name T93
Test name
Test status
Simulation time 52580205 ps
CPU time 0.89 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:30 PM PST 24
Peak memory 205984 kb
Host smart-e7b51dec-fe65-468d-89b7-512a7e2bd028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179414801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4179414801
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.4244526978
Short name T381
Test name
Test status
Simulation time 424264653 ps
CPU time 22.29 seconds
Started Feb 01 03:55:10 PM PST 24
Finished Feb 01 03:55:39 PM PST 24
Peak memory 222456 kb
Host smart-2a2f4893-f3d4-42a9-a4b9-fb4c3ac1934c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244526978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.4244526978
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.198980391
Short name T64
Test name
Test status
Simulation time 241699697 ps
CPU time 7.79 seconds
Started Feb 01 03:54:53 PM PST 24
Finished Feb 01 03:55:04 PM PST 24
Peak memory 214504 kb
Host smart-3d76c2e5-b0c6-4033-8d19-7cc5e5eff0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198980391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.198980391
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.4004685796
Short name T643
Test name
Test status
Simulation time 278876710 ps
CPU time 2.67 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:26 PM PST 24
Peak memory 218324 kb
Host smart-58475c25-35cd-4cd3-850c-3f1cd323681d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004685796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.4004685796
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.4152787068
Short name T912
Test name
Test status
Simulation time 1140299575 ps
CPU time 12.78 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:17 PM PST 24
Peak memory 209356 kb
Host smart-61cf1661-f39f-40b0-a06c-233404ed797a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152787068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4152787068
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.191653289
Short name T377
Test name
Test status
Simulation time 119588827 ps
CPU time 5.73 seconds
Started Feb 01 03:54:57 PM PST 24
Finished Feb 01 03:55:11 PM PST 24
Peak memory 211796 kb
Host smart-4830fcb0-20b6-4b16-b8dd-8591d23f9d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191653289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.191653289
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.721832062
Short name T1070
Test name
Test status
Simulation time 83841760 ps
CPU time 3.94 seconds
Started Feb 01 03:55:15 PM PST 24
Finished Feb 01 03:55:29 PM PST 24
Peak memory 208312 kb
Host smart-9e3c491f-f33f-49c8-8551-42216bad6b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721832062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.721832062
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1984219633
Short name T645
Test name
Test status
Simulation time 640018526 ps
CPU time 7.35 seconds
Started Feb 01 03:55:12 PM PST 24
Finished Feb 01 03:55:29 PM PST 24
Peak memory 209040 kb
Host smart-5bb043e4-c9e3-4c44-ac97-5f613c179005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984219633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1984219633
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2345157868
Short name T622
Test name
Test status
Simulation time 68789252 ps
CPU time 3.12 seconds
Started Feb 01 03:54:11 PM PST 24
Finished Feb 01 03:54:19 PM PST 24
Peak memory 207972 kb
Host smart-5b059888-e8b2-47fa-81ba-b1d7ba882802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345157868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2345157868
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.4264764573
Short name T641
Test name
Test status
Simulation time 127896435 ps
CPU time 4.3 seconds
Started Feb 01 03:54:58 PM PST 24
Finished Feb 01 03:55:11 PM PST 24
Peak memory 208716 kb
Host smart-cf243d33-badd-4b3e-b4a3-aa167f4f5844
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264764573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.4264764573
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2781818733
Short name T678
Test name
Test status
Simulation time 26029508 ps
CPU time 2.04 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:25 PM PST 24
Peak memory 208508 kb
Host smart-f22287c7-c519-4348-9a71-a6e51cf6dd69
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781818733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2781818733
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2547927431
Short name T628
Test name
Test status
Simulation time 24087429 ps
CPU time 1.87 seconds
Started Feb 01 03:53:48 PM PST 24
Finished Feb 01 03:53:57 PM PST 24
Peak memory 207232 kb
Host smart-53f49bc6-1362-4c2d-be63-b35be841e032
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547927431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2547927431
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2815151648
Short name T293
Test name
Test status
Simulation time 188255589 ps
CPU time 3.66 seconds
Started Feb 01 03:54:54 PM PST 24
Finished Feb 01 03:55:01 PM PST 24
Peak memory 207916 kb
Host smart-96769e34-17e2-4034-b9b4-e9c6cc9a2d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815151648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2815151648
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2440329771
Short name T691
Test name
Test status
Simulation time 66936093 ps
CPU time 3.02 seconds
Started Feb 01 03:54:00 PM PST 24
Finished Feb 01 03:54:09 PM PST 24
Peak memory 206704 kb
Host smart-8d49d89b-dd0e-45b8-97ba-c32872c6970e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440329771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2440329771
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3153439744
Short name T61
Test name
Test status
Simulation time 9005462836 ps
CPU time 58.09 seconds
Started Feb 01 03:55:12 PM PST 24
Finished Feb 01 03:56:19 PM PST 24
Peak memory 222448 kb
Host smart-022100de-beb1-4647-9959-e9070c878b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153439744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3153439744
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.377455688
Short name T764
Test name
Test status
Simulation time 719978972 ps
CPU time 5.38 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:28 PM PST 24
Peak memory 222472 kb
Host smart-b8dbdf95-18e1-4b38-83b1-1468fda7f66d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377455688 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.377455688
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2757197126
Short name T611
Test name
Test status
Simulation time 207609464 ps
CPU time 3.16 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:27 PM PST 24
Peak memory 208140 kb
Host smart-a6cc3f7a-6650-4142-b0c7-78f2d4b2116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757197126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2757197126
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.653983499
Short name T1059
Test name
Test status
Simulation time 61006706 ps
CPU time 0.82 seconds
Started Feb 01 03:55:09 PM PST 24
Finished Feb 01 03:55:17 PM PST 24
Peak memory 205884 kb
Host smart-61cb3bb8-f75e-4d86-9e60-200a53619d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653983499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.653983499
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.724510106
Short name T1008
Test name
Test status
Simulation time 259110809 ps
CPU time 2.62 seconds
Started Feb 01 03:54:55 PM PST 24
Finished Feb 01 03:55:02 PM PST 24
Peak memory 214192 kb
Host smart-2ab27561-29e2-4c58-8507-87bf6f6ee774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724510106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.724510106
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3026328654
Short name T219
Test name
Test status
Simulation time 5713156812 ps
CPU time 73.93 seconds
Started Feb 01 03:53:35 PM PST 24
Finished Feb 01 03:55:03 PM PST 24
Peak memory 214396 kb
Host smart-8b53016f-42a6-49a0-9eda-b045149afc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026328654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3026328654
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.4217120911
Short name T374
Test name
Test status
Simulation time 54295508 ps
CPU time 2.06 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:31 PM PST 24
Peak memory 209328 kb
Host smart-1235ef72-36b0-432f-a8f6-d259fe6af4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217120911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.4217120911
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.4095731312
Short name T816
Test name
Test status
Simulation time 139752662 ps
CPU time 4.01 seconds
Started Feb 01 03:56:33 PM PST 24
Finished Feb 01 03:56:42 PM PST 24
Peak memory 219048 kb
Host smart-8c86cf70-d536-4972-bd9d-48f88820ccf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095731312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.4095731312
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1670092140
Short name T238
Test name
Test status
Simulation time 212387263 ps
CPU time 5.04 seconds
Started Feb 01 03:55:10 PM PST 24
Finished Feb 01 03:55:24 PM PST 24
Peak memory 210172 kb
Host smart-f29a65d5-79b5-4f2f-a11c-8a5486b11eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670092140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1670092140
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_random.933768165
Short name T605
Test name
Test status
Simulation time 120597266 ps
CPU time 4.98 seconds
Started Feb 01 03:54:52 PM PST 24
Finished Feb 01 03:55:00 PM PST 24
Peak memory 207648 kb
Host smart-0d3ab2a8-d51a-4617-8829-0b00f8aca1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933768165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.933768165
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.44509502
Short name T328
Test name
Test status
Simulation time 79970522 ps
CPU time 2.95 seconds
Started Feb 01 03:54:53 PM PST 24
Finished Feb 01 03:54:59 PM PST 24
Peak memory 208812 kb
Host smart-ebc4c92f-8cd2-4757-bc10-6c0be2d2edcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44509502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.44509502
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4084682338
Short name T3
Test name
Test status
Simulation time 185047511 ps
CPU time 4.76 seconds
Started Feb 01 03:54:55 PM PST 24
Finished Feb 01 03:55:06 PM PST 24
Peak memory 208716 kb
Host smart-aeb951aa-5daf-4fb3-834d-88cde9cc7e34
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084682338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4084682338
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2151123240
Short name T1045
Test name
Test status
Simulation time 171975899 ps
CPU time 5.15 seconds
Started Feb 01 03:54:55 PM PST 24
Finished Feb 01 03:55:06 PM PST 24
Peak memory 206600 kb
Host smart-3e04c3f6-31c8-49de-982d-fc59c2f51ea9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151123240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2151123240
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.9713276
Short name T869
Test name
Test status
Simulation time 266839418 ps
CPU time 3.48 seconds
Started Feb 01 03:55:15 PM PST 24
Finished Feb 01 03:55:28 PM PST 24
Peak memory 208160 kb
Host smart-a3264067-431b-4b75-8d9e-64bfaefb0c04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9713276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.9713276
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.4282918730
Short name T748
Test name
Test status
Simulation time 567385223 ps
CPU time 4.52 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:28 PM PST 24
Peak memory 207812 kb
Host smart-663623bf-eb1d-4502-8f75-2573a1ac32b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282918730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4282918730
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2491356914
Short name T588
Test name
Test status
Simulation time 188741377 ps
CPU time 2.91 seconds
Started Feb 01 03:54:33 PM PST 24
Finished Feb 01 03:54:40 PM PST 24
Peak memory 208276 kb
Host smart-eed230b1-d3e5-4b85-942a-c9dc32894e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491356914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2491356914
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3030950364
Short name T322
Test name
Test status
Simulation time 26756196349 ps
CPU time 103.72 seconds
Started Feb 01 03:55:34 PM PST 24
Finished Feb 01 03:57:26 PM PST 24
Peak memory 216468 kb
Host smart-5c3272c7-a07a-4752-a306-78aa0a609248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030950364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3030950364
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1103924
Short name T950
Test name
Test status
Simulation time 322669500 ps
CPU time 10.01 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:33 PM PST 24
Peak memory 220280 kb
Host smart-34b1a960-cc0d-4fda-84aa-98a4e3692f41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103924 -assert nopostpr
oc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1103924
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4065608509
Short name T372
Test name
Test status
Simulation time 160097402 ps
CPU time 3.02 seconds
Started Feb 01 03:55:15 PM PST 24
Finished Feb 01 03:55:28 PM PST 24
Peak memory 207620 kb
Host smart-680152f8-936a-4b81-98f3-a1447cc47aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065608509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4065608509
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.63183427
Short name T579
Test name
Test status
Simulation time 53821451 ps
CPU time 2.77 seconds
Started Feb 01 03:55:36 PM PST 24
Finished Feb 01 03:55:48 PM PST 24
Peak memory 210456 kb
Host smart-093ea30f-3a89-4101-856a-770d6979788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63183427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.63183427
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1496885136
Short name T1023
Test name
Test status
Simulation time 16347115 ps
CPU time 0.84 seconds
Started Feb 01 03:55:35 PM PST 24
Finished Feb 01 03:55:44 PM PST 24
Peak memory 205716 kb
Host smart-13c359c9-96ef-4af8-bd6e-c31802dee077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496885136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1496885136
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.946367380
Short name T1034
Test name
Test status
Simulation time 135163630 ps
CPU time 2.31 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:26 PM PST 24
Peak memory 207412 kb
Host smart-5db1f8fa-617d-4a4f-b785-5977b3935316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946367380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.946367380
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3519799388
Short name T87
Test name
Test status
Simulation time 414393530 ps
CPU time 5.24 seconds
Started Feb 01 03:55:35 PM PST 24
Finished Feb 01 03:55:49 PM PST 24
Peak memory 214016 kb
Host smart-2ccb1d3f-15f1-41d3-ba99-7f1c0385239c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519799388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3519799388
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2132089126
Short name T831
Test name
Test status
Simulation time 186504206 ps
CPU time 5.64 seconds
Started Feb 01 03:53:55 PM PST 24
Finished Feb 01 03:54:07 PM PST 24
Peak memory 214032 kb
Host smart-06c7395c-1e38-4eb1-a8a1-800444860d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132089126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2132089126
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2702080892
Short name T954
Test name
Test status
Simulation time 190821892 ps
CPU time 3.36 seconds
Started Feb 01 03:54:56 PM PST 24
Finished Feb 01 03:55:07 PM PST 24
Peak memory 208992 kb
Host smart-02dd2619-df2a-4ffd-8ffd-cc61855b6522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702080892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2702080892
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3664065751
Short name T673
Test name
Test status
Simulation time 135467091 ps
CPU time 5.21 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:34 PM PST 24
Peak memory 217844 kb
Host smart-54e49dea-1971-4743-bcff-3084beadf5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664065751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3664065751
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.162634967
Short name T696
Test name
Test status
Simulation time 38875368 ps
CPU time 2.57 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:32 PM PST 24
Peak memory 206760 kb
Host smart-d680d38e-5bac-477b-9b0b-210c1b9e41a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162634967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.162634967
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.75352587
Short name T664
Test name
Test status
Simulation time 47126453 ps
CPU time 2.46 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:25 PM PST 24
Peak memory 207956 kb
Host smart-fb402a3f-7646-40c9-8436-b2aa950e19f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75352587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.75352587
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2204339647
Short name T982
Test name
Test status
Simulation time 137307203 ps
CPU time 5.65 seconds
Started Feb 01 03:54:58 PM PST 24
Finished Feb 01 03:55:12 PM PST 24
Peak memory 208456 kb
Host smart-94731c75-7eeb-4108-907a-f1c912f22380
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204339647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2204339647
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3541139438
Short name T826
Test name
Test status
Simulation time 478437265 ps
CPU time 3.91 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:28 PM PST 24
Peak memory 208696 kb
Host smart-267c7d37-e1f0-458a-9d5e-b5035cc3f3dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541139438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3541139438
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.261457373
Short name T894
Test name
Test status
Simulation time 327177228 ps
CPU time 5.67 seconds
Started Feb 01 03:55:35 PM PST 24
Finished Feb 01 03:55:50 PM PST 24
Peak memory 217624 kb
Host smart-3a1531f8-34ea-4976-a7bc-15e7c69b7514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261457373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.261457373
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3649576283
Short name T978
Test name
Test status
Simulation time 279021298 ps
CPU time 3.28 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:27 PM PST 24
Peak memory 206864 kb
Host smart-0d99bf75-f3ca-4e2b-937d-380dee056dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649576283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3649576283
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2899025067
Short name T805
Test name
Test status
Simulation time 72370354493 ps
CPU time 308.17 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 04:00:37 PM PST 24
Peak memory 217428 kb
Host smart-cb8bd718-17f2-4714-88bc-1bb6ae378a59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899025067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2899025067
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2680165127
Short name T932
Test name
Test status
Simulation time 48171001 ps
CPU time 2.54 seconds
Started Feb 01 03:56:03 PM PST 24
Finished Feb 01 03:56:09 PM PST 24
Peak memory 208768 kb
Host smart-888cb1d7-210e-48ea-904c-909b692ac3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680165127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2680165127
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.531437174
Short name T162
Test name
Test status
Simulation time 125199353 ps
CPU time 3.65 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:28 PM PST 24
Peak memory 210128 kb
Host smart-626954d8-953f-4d50-9805-97ad08b993bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531437174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.531437174
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3493343478
Short name T73
Test name
Test status
Simulation time 12456091 ps
CPU time 0.74 seconds
Started Feb 01 03:55:35 PM PST 24
Finished Feb 01 03:55:44 PM PST 24
Peak memory 205716 kb
Host smart-5d9456f3-1720-414b-8eca-392b44a4bdcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493343478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3493343478
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2295324378
Short name T887
Test name
Test status
Simulation time 1408163917 ps
CPU time 4.8 seconds
Started Feb 01 03:56:10 PM PST 24
Finished Feb 01 03:56:20 PM PST 24
Peak memory 208124 kb
Host smart-68ef5b15-9d80-4fe0-9e40-14553a612e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295324378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2295324378
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3180424892
Short name T774
Test name
Test status
Simulation time 222255935 ps
CPU time 4.96 seconds
Started Feb 01 03:55:36 PM PST 24
Finished Feb 01 03:55:50 PM PST 24
Peak memory 208388 kb
Host smart-9bf9e538-b090-4e30-9869-bf2e031eb4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180424892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3180424892
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3429467831
Short name T84
Test name
Test status
Simulation time 124524374 ps
CPU time 2.71 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:27 PM PST 24
Peak memory 208396 kb
Host smart-8d5ed6dc-f6cb-4b57-abaa-fe9edbe77e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429467831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3429467831
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2255682774
Short name T986
Test name
Test status
Simulation time 72611091 ps
CPU time 4.79 seconds
Started Feb 01 03:55:14 PM PST 24
Finished Feb 01 03:55:29 PM PST 24
Peak memory 213876 kb
Host smart-db8b2be9-633e-41cb-a569-7c186900ad3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255682774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2255682774
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2150875240
Short name T984
Test name
Test status
Simulation time 362811626 ps
CPU time 4.52 seconds
Started Feb 01 03:55:18 PM PST 24
Finished Feb 01 03:55:33 PM PST 24
Peak memory 209292 kb
Host smart-7af8301a-92b9-48f9-8596-350db7ebe712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150875240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2150875240
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3312681084
Short name T427
Test name
Test status
Simulation time 749068774 ps
CPU time 8.44 seconds
Started Feb 01 03:55:28 PM PST 24
Finished Feb 01 03:55:46 PM PST 24
Peak memory 214180 kb
Host smart-ce98f722-1d04-4249-8861-7c5260f1808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312681084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3312681084
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1482125097
Short name T1032
Test name
Test status
Simulation time 128540041 ps
CPU time 4.05 seconds
Started Feb 01 03:54:15 PM PST 24
Finished Feb 01 03:54:24 PM PST 24
Peak memory 206724 kb
Host smart-f162b475-4638-4417-a81a-80b19229e2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482125097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1482125097
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1746318131
Short name T613
Test name
Test status
Simulation time 223454267 ps
CPU time 5.86 seconds
Started Feb 01 03:55:00 PM PST 24
Finished Feb 01 03:55:15 PM PST 24
Peak memory 207788 kb
Host smart-91f4dd52-a77a-475c-8c30-9ebed96395bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746318131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1746318131
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1997866140
Short name T971
Test name
Test status
Simulation time 82542271 ps
CPU time 3.8 seconds
Started Feb 01 03:55:36 PM PST 24
Finished Feb 01 03:55:49 PM PST 24
Peak memory 208508 kb
Host smart-1a9e4ba9-243a-4deb-a321-94d4ef9218b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997866140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1997866140
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.817354618
Short name T306
Test name
Test status
Simulation time 165694503 ps
CPU time 4.81 seconds
Started Feb 01 03:56:10 PM PST 24
Finished Feb 01 03:56:19 PM PST 24
Peak memory 207904 kb
Host smart-9297ed69-fd48-4bb5-b238-cb939c1456e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817354618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.817354618
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.4100615966
Short name T1019
Test name
Test status
Simulation time 192702267 ps
CPU time 2.54 seconds
Started Feb 01 03:55:13 PM PST 24
Finished Feb 01 03:55:26 PM PST 24
Peak memory 207756 kb
Host smart-3e996311-b107-4e7e-9303-cb4bbbee3ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100615966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.4100615966
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3824737474
Short name T186
Test name
Test status
Simulation time 1232591435 ps
CPU time 7.56 seconds
Started Feb 01 03:54:14 PM PST 24
Finished Feb 01 03:54:27 PM PST 24
Peak memory 208672 kb
Host smart-d7e7f1d1-fd0a-4f50-a90b-3ab0450d1b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824737474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3824737474
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1187519596
Short name T880
Test name
Test status
Simulation time 113337818539 ps
CPU time 748.71 seconds
Started Feb 01 03:55:10 PM PST 24
Finished Feb 01 04:07:47 PM PST 24
Peak memory 230752 kb
Host smart-cee62383-f353-4280-b4cd-640518479299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187519596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1187519596
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1987789484
Short name T101
Test name
Test status
Simulation time 363618809 ps
CPU time 4.28 seconds
Started Feb 01 03:55:09 PM PST 24
Finished Feb 01 03:55:20 PM PST 24
Peak memory 222596 kb
Host smart-b2ae1928-e640-4440-867c-61d29b89bc98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987789484 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1987789484
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1660744161
Short name T226
Test name
Test status
Simulation time 342557100 ps
CPU time 4.53 seconds
Started Feb 01 03:55:38 PM PST 24
Finished Feb 01 03:55:51 PM PST 24
Peak memory 208204 kb
Host smart-bc9e3aba-9cca-457e-b60c-4aef63da024e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660744161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1660744161
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2511182438
Short name T567
Test name
Test status
Simulation time 15720402 ps
CPU time 0.86 seconds
Started Feb 01 03:45:31 PM PST 24
Finished Feb 01 03:46:22 PM PST 24
Peak memory 205788 kb
Host smart-8ba9c8e3-9473-4b66-b5b5-6c288f58adff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511182438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2511182438
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3494537549
Short name T9
Test name
Test status
Simulation time 454398679 ps
CPU time 5.35 seconds
Started Feb 01 03:45:27 PM PST 24
Finished Feb 01 03:46:15 PM PST 24
Peak memory 210516 kb
Host smart-bd859138-bef1-4ee8-8460-f2fb7bc80be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494537549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3494537549
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.290755177
Short name T197
Test name
Test status
Simulation time 1913676821 ps
CPU time 4.76 seconds
Started Feb 01 03:45:18 PM PST 24
Finished Feb 01 03:46:02 PM PST 24
Peak memory 209672 kb
Host smart-e31938ac-9599-4a9a-8c28-e9f9b88f71a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290755177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.290755177
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2670279201
Short name T398
Test name
Test status
Simulation time 69510555 ps
CPU time 4 seconds
Started Feb 01 03:45:17 PM PST 24
Finished Feb 01 03:46:01 PM PST 24
Peak memory 220152 kb
Host smart-3ad47813-181f-44c1-b46e-1a7e42887c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670279201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2670279201
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.128566908
Short name T998
Test name
Test status
Simulation time 554146103 ps
CPU time 5.05 seconds
Started Feb 01 03:47:28 PM PST 24
Finished Feb 01 03:48:17 PM PST 24
Peak memory 209548 kb
Host smart-ad07d272-950f-4a63-8ad9-f9f903d1504c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128566908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.128566908
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2827871586
Short name T824
Test name
Test status
Simulation time 82984026 ps
CPU time 2.97 seconds
Started Feb 01 03:45:18 PM PST 24
Finished Feb 01 03:46:01 PM PST 24
Peak memory 214212 kb
Host smart-7432bb23-cc71-45db-87e2-94a773e0779d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827871586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2827871586
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.179335893
Short name T354
Test name
Test status
Simulation time 200179945 ps
CPU time 4.74 seconds
Started Feb 01 03:45:25 PM PST 24
Finished Feb 01 03:46:13 PM PST 24
Peak memory 207332 kb
Host smart-8ada86e5-ecbc-4df8-a53f-b5a42deef4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179335893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.179335893
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1227532279
Short name T855
Test name
Test status
Simulation time 2014420923 ps
CPU time 6.72 seconds
Started Feb 01 03:45:20 PM PST 24
Finished Feb 01 03:46:09 PM PST 24
Peak memory 207208 kb
Host smart-f0281c26-771f-4b8a-a684-50e18b50ebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227532279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1227532279
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1426166319
Short name T657
Test name
Test status
Simulation time 71965047 ps
CPU time 2.47 seconds
Started Feb 01 03:45:20 PM PST 24
Finished Feb 01 03:46:05 PM PST 24
Peak memory 206572 kb
Host smart-8c2ecc68-52ee-487e-a4fb-a119df6e30c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426166319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1426166319
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3457638510
Short name T725
Test name
Test status
Simulation time 1025594795 ps
CPU time 7.48 seconds
Started Feb 01 03:45:09 PM PST 24
Finished Feb 01 03:45:50 PM PST 24
Peak memory 208008 kb
Host smart-a0766476-186b-4e9e-bd6b-542109096e63
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457638510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3457638510
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1482438052
Short name T1012
Test name
Test status
Simulation time 243561878 ps
CPU time 3 seconds
Started Feb 01 03:45:05 PM PST 24
Finished Feb 01 03:45:40 PM PST 24
Peak memory 206704 kb
Host smart-d962e0e6-7949-4d01-9c99-4c734a04ab10
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482438052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1482438052
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3286970349
Short name T736
Test name
Test status
Simulation time 147269664 ps
CPU time 4.33 seconds
Started Feb 01 03:47:22 PM PST 24
Finished Feb 01 03:48:06 PM PST 24
Peak memory 209304 kb
Host smart-e2e833ff-530f-4a6b-8340-1ff0cb64f330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286970349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3286970349
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.4061956736
Short name T660
Test name
Test status
Simulation time 24989938 ps
CPU time 2.02 seconds
Started Feb 01 03:45:09 PM PST 24
Finished Feb 01 03:45:45 PM PST 24
Peak memory 206732 kb
Host smart-009f3ea4-4485-461f-996d-ce0347e6da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061956736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.4061956736
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2749995776
Short name T214
Test name
Test status
Simulation time 1762177343 ps
CPU time 17.16 seconds
Started Feb 01 03:45:38 PM PST 24
Finished Feb 01 03:46:48 PM PST 24
Peak memory 216216 kb
Host smart-199a8819-cf52-4aa0-bdd1-67fed0e90903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749995776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2749995776
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1695816350
Short name T14
Test name
Test status
Simulation time 99030043 ps
CPU time 4.44 seconds
Started Feb 01 03:45:28 PM PST 24
Finished Feb 01 03:46:20 PM PST 24
Peak memory 222392 kb
Host smart-348d6992-2e1f-4982-81c8-27ba20fcfbb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695816350 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1695816350
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1345956786
Short name T184
Test name
Test status
Simulation time 1055369205 ps
CPU time 6.46 seconds
Started Feb 01 03:45:22 PM PST 24
Finished Feb 01 03:46:10 PM PST 24
Peak memory 214088 kb
Host smart-8847de4b-f877-4024-a9f9-c710ce7cc967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345956786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1345956786
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2972920902
Short name T410
Test name
Test status
Simulation time 74793707 ps
CPU time 2.08 seconds
Started Feb 01 03:46:51 PM PST 24
Finished Feb 01 03:47:37 PM PST 24
Peak memory 210496 kb
Host smart-0dc213a9-0e0a-422e-9ccb-70103ef97cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972920902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2972920902
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1811567537
Short name T616
Test name
Test status
Simulation time 13333919 ps
CPU time 0.85 seconds
Started Feb 01 03:54:35 PM PST 24
Finished Feb 01 03:54:40 PM PST 24
Peak memory 205928 kb
Host smart-e54c4bb6-295f-4ff1-a613-a6bd31df59d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811567537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1811567537
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1885296501
Short name T223
Test name
Test status
Simulation time 124663619 ps
CPU time 3.64 seconds
Started Feb 01 03:47:28 PM PST 24
Finished Feb 01 03:48:15 PM PST 24
Peak memory 214148 kb
Host smart-fd1eca55-538c-48f7-aec8-3e553726e2a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885296501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1885296501
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.747802956
Short name T738
Test name
Test status
Simulation time 37222637 ps
CPU time 2.47 seconds
Started Feb 01 03:48:47 PM PST 24
Finished Feb 01 03:49:41 PM PST 24
Peak memory 213752 kb
Host smart-d5bcda98-8fed-4883-8363-6842969dc9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747802956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.747802956
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2788352450
Short name T726
Test name
Test status
Simulation time 37723347 ps
CPU time 2.37 seconds
Started Feb 01 03:54:25 PM PST 24
Finished Feb 01 03:54:32 PM PST 24
Peak memory 208112 kb
Host smart-26939d52-7fea-40b0-ad56-5e8863f816a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788352450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2788352450
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.4078670027
Short name T48
Test name
Test status
Simulation time 38253944 ps
CPU time 2.24 seconds
Started Feb 01 03:45:23 PM PST 24
Finished Feb 01 03:46:06 PM PST 24
Peak memory 214140 kb
Host smart-3d324ac6-4c85-4839-b078-fe7c0ffb6904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078670027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.4078670027
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1743601878
Short name T1040
Test name
Test status
Simulation time 432656764 ps
CPU time 10.86 seconds
Started Feb 01 03:47:28 PM PST 24
Finished Feb 01 03:48:22 PM PST 24
Peak memory 218228 kb
Host smart-841f5403-d235-4de5-ab05-974449e99136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743601878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1743601878
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.887347109
Short name T1063
Test name
Test status
Simulation time 1072935253 ps
CPU time 6.08 seconds
Started Feb 01 03:45:35 PM PST 24
Finished Feb 01 03:46:31 PM PST 24
Peak memory 208192 kb
Host smart-2774744a-125a-459d-909e-f531a9e98b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887347109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.887347109
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1275425168
Short name T809
Test name
Test status
Simulation time 303137446 ps
CPU time 7.45 seconds
Started Feb 01 03:45:25 PM PST 24
Finished Feb 01 03:46:16 PM PST 24
Peak memory 208032 kb
Host smart-f679ed71-28e0-44e0-b10b-a6dedd0f7022
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275425168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1275425168
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2939882604
Short name T649
Test name
Test status
Simulation time 67928417 ps
CPU time 2.97 seconds
Started Feb 01 03:45:07 PM PST 24
Finished Feb 01 03:45:45 PM PST 24
Peak memory 208332 kb
Host smart-3b17ca0f-5fae-40eb-b1bd-8dcaad8ba23e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939882604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2939882604
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3982637912
Short name T674
Test name
Test status
Simulation time 32126773 ps
CPU time 2.44 seconds
Started Feb 01 03:45:23 PM PST 24
Finished Feb 01 03:46:06 PM PST 24
Peak memory 206728 kb
Host smart-0960f04d-f128-4ec8-8c5b-e3c43f32e981
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982637912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3982637912
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3970611117
Short name T313
Test name
Test status
Simulation time 172785170 ps
CPU time 2.71 seconds
Started Feb 01 03:45:28 PM PST 24
Finished Feb 01 03:46:18 PM PST 24
Peak memory 209416 kb
Host smart-ed573f0d-a891-498e-95d3-0080ec227616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970611117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3970611117
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1014887307
Short name T779
Test name
Test status
Simulation time 689920847 ps
CPU time 3.87 seconds
Started Feb 01 03:45:08 PM PST 24
Finished Feb 01 03:45:47 PM PST 24
Peak memory 208240 kb
Host smart-3323d2d5-bf17-4669-82da-a3802729cfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014887307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1014887307
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3398368919
Short name T68
Test name
Test status
Simulation time 3351493975 ps
CPU time 17.57 seconds
Started Feb 01 03:50:03 PM PST 24
Finished Feb 01 03:51:25 PM PST 24
Peak memory 214436 kb
Host smart-7cfd16a5-2ea2-4daa-aede-e75be704b509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398368919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3398368919
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1391237735
Short name T629
Test name
Test status
Simulation time 90460107 ps
CPU time 2.24 seconds
Started Feb 01 03:46:50 PM PST 24
Finished Feb 01 03:47:36 PM PST 24
Peak memory 217364 kb
Host smart-c0f28a3c-b8c6-410e-ba4d-3f6a225419aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391237735 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1391237735
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2023480401
Short name T586
Test name
Test status
Simulation time 49423776 ps
CPU time 3.16 seconds
Started Feb 01 03:48:29 PM PST 24
Finished Feb 01 03:49:22 PM PST 24
Peak memory 215360 kb
Host smart-6b5c2df7-0c6f-4ee9-a489-ae08a4873b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023480401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2023480401
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1181474642
Short name T739
Test name
Test status
Simulation time 189905934 ps
CPU time 2.18 seconds
Started Feb 01 03:47:28 PM PST 24
Finished Feb 01 03:48:09 PM PST 24
Peak memory 209716 kb
Host smart-bb57d3d8-9293-4f0a-a6c7-f9850df89819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181474642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1181474642
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1850927350
Short name T710
Test name
Test status
Simulation time 24752459 ps
CPU time 0.67 seconds
Started Feb 01 03:45:58 PM PST 24
Finished Feb 01 03:46:54 PM PST 24
Peak memory 205816 kb
Host smart-7115b779-b8ea-4315-bbe1-a9ad52a85c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850927350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1850927350
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1215403383
Short name T861
Test name
Test status
Simulation time 112424884 ps
CPU time 2.78 seconds
Started Feb 01 03:47:48 PM PST 24
Finished Feb 01 03:48:41 PM PST 24
Peak memory 214168 kb
Host smart-d6062b88-aed4-49c3-955b-40245e0d5261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215403383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1215403383
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2154652663
Short name T943
Test name
Test status
Simulation time 390334629 ps
CPU time 4.7 seconds
Started Feb 01 03:45:23 PM PST 24
Finished Feb 01 03:46:08 PM PST 24
Peak memory 216148 kb
Host smart-4aa66884-6d2f-4a10-8d14-ba560c148a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154652663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2154652663
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.4167728708
Short name T829
Test name
Test status
Simulation time 2182124492 ps
CPU time 7.78 seconds
Started Feb 01 03:45:32 PM PST 24
Finished Feb 01 03:46:29 PM PST 24
Peak memory 209140 kb
Host smart-21149b10-a22e-43a2-b7b0-b9b95f1579f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167728708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.4167728708
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1267450256
Short name T395
Test name
Test status
Simulation time 896273434 ps
CPU time 5.4 seconds
Started Feb 01 03:47:03 PM PST 24
Finished Feb 01 03:47:52 PM PST 24
Peak memory 208316 kb
Host smart-de2eb90b-9500-4f7d-9fff-678dabd28bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267450256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1267450256
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.931587078
Short name T796
Test name
Test status
Simulation time 403963064 ps
CPU time 4.64 seconds
Started Feb 01 03:45:23 PM PST 24
Finished Feb 01 03:46:09 PM PST 24
Peak memory 214264 kb
Host smart-549aa6bd-5c84-4427-8695-2ffb73a7dadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931587078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.931587078
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.803477304
Short name T852
Test name
Test status
Simulation time 543757792 ps
CPU time 10.44 seconds
Started Feb 01 03:54:55 PM PST 24
Finished Feb 01 03:55:12 PM PST 24
Peak memory 209160 kb
Host smart-0f6321e4-d8f8-4b5b-b907-da97c0d97471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803477304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.803477304
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.273671865
Short name T811
Test name
Test status
Simulation time 814448787 ps
CPU time 2.79 seconds
Started Feb 01 03:49:57 PM PST 24
Finished Feb 01 03:51:06 PM PST 24
Peak memory 206132 kb
Host smart-0d90420b-7882-47fe-897f-1e4d71fbcce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273671865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.273671865
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2605187830
Short name T780
Test name
Test status
Simulation time 697043435 ps
CPU time 7.54 seconds
Started Feb 01 03:48:29 PM PST 24
Finished Feb 01 03:49:27 PM PST 24
Peak memory 205616 kb
Host smart-f4f71aa6-3668-4f99-b020-e03b0d45756c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605187830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2605187830
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1510278352
Short name T193
Test name
Test status
Simulation time 696244427 ps
CPU time 19.8 seconds
Started Feb 01 03:47:04 PM PST 24
Finished Feb 01 03:48:07 PM PST 24
Peak memory 208000 kb
Host smart-ecc56c6f-510a-45c0-9ec2-138bd9692fb7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510278352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1510278352
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.223603354
Short name T964
Test name
Test status
Simulation time 153071280 ps
CPU time 4.69 seconds
Started Feb 01 03:45:21 PM PST 24
Finished Feb 01 03:46:05 PM PST 24
Peak memory 206668 kb
Host smart-50f68576-3fa8-4a4e-87ca-c4e4e6b0bccd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223603354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.223603354
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3431491924
Short name T801
Test name
Test status
Simulation time 455299101 ps
CPU time 10.74 seconds
Started Feb 01 03:45:43 PM PST 24
Finished Feb 01 03:46:47 PM PST 24
Peak memory 214100 kb
Host smart-9da9adb2-bb1b-4093-a53d-67b20c0a321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431491924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3431491924
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.663752451
Short name T697
Test name
Test status
Simulation time 227246559 ps
CPU time 2.76 seconds
Started Feb 01 03:46:42 PM PST 24
Finished Feb 01 03:47:34 PM PST 24
Peak memory 206616 kb
Host smart-e8113ce3-e03b-4f3e-94cf-dd3f8ef22856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663752451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.663752451
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.11146128
Short name T596
Test name
Test status
Simulation time 171145958 ps
CPU time 7.56 seconds
Started Feb 01 03:47:42 PM PST 24
Finished Feb 01 03:48:41 PM PST 24
Peak memory 222484 kb
Host smart-cc18ec95-9fd6-497c-b35d-e3afb1e6bf00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11146128 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.11146128
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2017011854
Short name T173
Test name
Test status
Simulation time 224946198 ps
CPU time 7.21 seconds
Started Feb 01 03:49:55 PM PST 24
Finished Feb 01 03:51:10 PM PST 24
Peak memory 213732 kb
Host smart-5d06d1ae-8180-4e6a-b7d9-8c11c97ea2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017011854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2017011854
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.4230767148
Short name T830
Test name
Test status
Simulation time 169750688 ps
CPU time 2.71 seconds
Started Feb 01 03:47:49 PM PST 24
Finished Feb 01 03:48:42 PM PST 24
Peak memory 209972 kb
Host smart-e9de7296-ba10-4e8b-9b78-005e8d176357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230767148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.4230767148
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2329117798
Short name T1005
Test name
Test status
Simulation time 20424730 ps
CPU time 0.87 seconds
Started Feb 01 03:47:24 PM PST 24
Finished Feb 01 03:48:07 PM PST 24
Peak memory 205728 kb
Host smart-effa0105-82aa-4953-8b84-f28a4bd551ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329117798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2329117798
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2056408831
Short name T19
Test name
Test status
Simulation time 182866532 ps
CPU time 2.29 seconds
Started Feb 01 03:46:38 PM PST 24
Finished Feb 01 03:47:30 PM PST 24
Peak memory 219008 kb
Host smart-2f01d099-54f0-4c8f-b9c5-0ce60d613b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056408831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2056408831
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3811717290
Short name T58
Test name
Test status
Simulation time 469685473 ps
CPU time 4.68 seconds
Started Feb 01 03:45:36 PM PST 24
Finished Feb 01 03:46:34 PM PST 24
Peak memory 219588 kb
Host smart-7cc2f688-08ea-40ed-9dd1-3cd5d1cb122c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811717290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3811717290
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3642763225
Short name T397
Test name
Test status
Simulation time 184018318 ps
CPU time 4.83 seconds
Started Feb 01 03:47:16 PM PST 24
Finished Feb 01 03:48:01 PM PST 24
Peak memory 214228 kb
Host smart-79d8ac02-8861-43c1-ac86-ad3a7902852a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642763225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3642763225
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1016172144
Short name T789
Test name
Test status
Simulation time 165946998 ps
CPU time 6.57 seconds
Started Feb 01 03:45:51 PM PST 24
Finished Feb 01 03:46:54 PM PST 24
Peak memory 214068 kb
Host smart-b7ed8be2-1d0c-4699-a77b-78d80420ee01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016172144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1016172144
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1296947877
Short name T13
Test name
Test status
Simulation time 531729910 ps
CPU time 4.11 seconds
Started Feb 01 03:45:47 PM PST 24
Finished Feb 01 03:46:45 PM PST 24
Peak memory 214132 kb
Host smart-ea3e7556-d3bf-4d71-8941-35bcfe702948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296947877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1296947877
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1709242164
Short name T872
Test name
Test status
Simulation time 453930096 ps
CPU time 4.78 seconds
Started Feb 01 03:46:23 PM PST 24
Finished Feb 01 03:47:20 PM PST 24
Peak memory 207304 kb
Host smart-690b7a58-3f4f-43fa-b57f-947e8558cbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709242164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1709242164
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1974478262
Short name T1028
Test name
Test status
Simulation time 254763352 ps
CPU time 3.11 seconds
Started Feb 01 03:45:50 PM PST 24
Finished Feb 01 03:46:48 PM PST 24
Peak memory 206520 kb
Host smart-f29106e6-4b35-42b3-af53-54752cab449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974478262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1974478262
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4218249287
Short name T634
Test name
Test status
Simulation time 270676519 ps
CPU time 3.37 seconds
Started Feb 01 03:45:36 PM PST 24
Finished Feb 01 03:46:30 PM PST 24
Peak memory 208232 kb
Host smart-20f9b3ac-1451-4b35-8e12-42a5aa51c44d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218249287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4218249287
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2499263319
Short name T568
Test name
Test status
Simulation time 412424968 ps
CPU time 2.58 seconds
Started Feb 01 03:46:59 PM PST 24
Finished Feb 01 03:47:47 PM PST 24
Peak memory 206716 kb
Host smart-5fec0272-e11d-4236-a3d7-88ee24a1ce04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499263319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2499263319
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3598253884
Short name T1003
Test name
Test status
Simulation time 220756673 ps
CPU time 2.64 seconds
Started Feb 01 03:45:31 PM PST 24
Finished Feb 01 03:46:23 PM PST 24
Peak memory 206016 kb
Host smart-dfb65c45-997e-4357-b067-74c45e6efded
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598253884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3598253884
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4256133753
Short name T312
Test name
Test status
Simulation time 143174342 ps
CPU time 2.24 seconds
Started Feb 01 03:47:13 PM PST 24
Finished Feb 01 03:47:55 PM PST 24
Peak memory 209268 kb
Host smart-d6818b07-62d2-4d8e-a178-28fa957ce19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256133753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4256133753
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3229170213
Short name T790
Test name
Test status
Simulation time 25767842 ps
CPU time 2.03 seconds
Started Feb 01 03:45:36 PM PST 24
Finished Feb 01 03:46:31 PM PST 24
Peak memory 208384 kb
Host smart-0492d8ec-0d27-495e-be86-dfd65925eb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229170213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3229170213
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.512032045
Short name T997
Test name
Test status
Simulation time 163505606 ps
CPU time 12 seconds
Started Feb 01 03:45:35 PM PST 24
Finished Feb 01 03:46:38 PM PST 24
Peak memory 222564 kb
Host smart-00d4b9d2-3342-4d6e-96a0-8e5fddfb43d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512032045 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.512032045
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.221724472
Short name T320
Test name
Test status
Simulation time 812626661 ps
CPU time 3.83 seconds
Started Feb 01 03:45:50 PM PST 24
Finished Feb 01 03:46:48 PM PST 24
Peak memory 207480 kb
Host smart-876fbf5a-faaa-41dc-872d-3cc032326243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221724472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.221724472
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1413857938
Short name T589
Test name
Test status
Simulation time 114504890 ps
CPU time 1.88 seconds
Started Feb 01 03:45:40 PM PST 24
Finished Feb 01 03:46:34 PM PST 24
Peak memory 209728 kb
Host smart-1c93604a-76a9-47f4-954f-b388a9338198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413857938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1413857938
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.225501755
Short name T979
Test name
Test status
Simulation time 31134658 ps
CPU time 0.77 seconds
Started Feb 01 03:45:50 PM PST 24
Finished Feb 01 03:46:45 PM PST 24
Peak memory 205664 kb
Host smart-8686c4a0-c004-4981-a0a8-d4154fa7d371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225501755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.225501755
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.934985803
Short name T224
Test name
Test status
Simulation time 196728674 ps
CPU time 9.93 seconds
Started Feb 01 03:45:46 PM PST 24
Finished Feb 01 03:46:48 PM PST 24
Peak memory 215348 kb
Host smart-7fe72eb0-eeb3-40b7-ac37-2b64680f5f97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934985803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.934985803
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1616591515
Short name T957
Test name
Test status
Simulation time 87587732 ps
CPU time 3.4 seconds
Started Feb 01 03:45:48 PM PST 24
Finished Feb 01 03:46:47 PM PST 24
Peak memory 214224 kb
Host smart-84249534-32bf-46d4-8873-9fae92ddfd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616591515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1616591515
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2333644867
Short name T247
Test name
Test status
Simulation time 2283166547 ps
CPU time 59.88 seconds
Started Feb 01 03:45:45 PM PST 24
Finished Feb 01 03:47:39 PM PST 24
Peak memory 214248 kb
Host smart-abe00879-6d9e-4227-a60a-9711bf1dc5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333644867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2333644867
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3797851419
Short name T305
Test name
Test status
Simulation time 171184196 ps
CPU time 5.81 seconds
Started Feb 01 03:45:45 PM PST 24
Finished Feb 01 03:46:45 PM PST 24
Peak memory 222304 kb
Host smart-e5a2d6f0-79d1-4d3e-8382-b44d18329371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797851419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3797851419
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.566783917
Short name T364
Test name
Test status
Simulation time 2412645894 ps
CPU time 19.27 seconds
Started Feb 01 03:45:44 PM PST 24
Finished Feb 01 03:46:56 PM PST 24
Peak memory 222360 kb
Host smart-12a2d296-f482-40c6-8cec-6d15592e9f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566783917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.566783917
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1652644537
Short name T995
Test name
Test status
Simulation time 3078999642 ps
CPU time 31.86 seconds
Started Feb 01 03:45:43 PM PST 24
Finished Feb 01 03:47:08 PM PST 24
Peak memory 218168 kb
Host smart-0be7ef16-b164-424e-bd0a-6c451751a38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652644537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1652644537
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3016845623
Short name T252
Test name
Test status
Simulation time 79283274 ps
CPU time 3.02 seconds
Started Feb 01 03:45:43 PM PST 24
Finished Feb 01 03:46:39 PM PST 24
Peak memory 206784 kb
Host smart-9bc66729-af47-4be1-aacb-8cc3d784114e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016845623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3016845623
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3495604193
Short name T1022
Test name
Test status
Simulation time 6779987276 ps
CPU time 26.04 seconds
Started Feb 01 03:45:48 PM PST 24
Finished Feb 01 03:47:10 PM PST 24
Peak memory 208584 kb
Host smart-90bd1b13-5531-4e03-b558-3b7904027222
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495604193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3495604193
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3331866897
Short name T711
Test name
Test status
Simulation time 1882465813 ps
CPU time 41.68 seconds
Started Feb 01 03:49:49 PM PST 24
Finished Feb 01 03:51:42 PM PST 24
Peak memory 207188 kb
Host smart-b63abb9b-9db4-48c3-bb90-bdb9ed543839
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331866897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3331866897
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.781074431
Short name T675
Test name
Test status
Simulation time 126574493 ps
CPU time 2.35 seconds
Started Feb 01 03:47:34 PM PST 24
Finished Feb 01 03:48:22 PM PST 24
Peak memory 206512 kb
Host smart-c15210ed-d3a6-4e52-9c73-06473a94a6db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781074431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.781074431
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1672197582
Short name T681
Test name
Test status
Simulation time 63567386 ps
CPU time 3.09 seconds
Started Feb 01 03:45:51 PM PST 24
Finished Feb 01 03:46:50 PM PST 24
Peak memory 209688 kb
Host smart-20c1a51b-3f4f-41f5-b605-5ac363b77bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672197582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1672197582
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3033083037
Short name T804
Test name
Test status
Simulation time 3269410679 ps
CPU time 20.14 seconds
Started Feb 01 03:45:45 PM PST 24
Finished Feb 01 03:46:59 PM PST 24
Peak memory 207736 kb
Host smart-9f73c5bb-4163-4761-adbd-6ff1c42f594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033083037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3033083037
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2694908373
Short name T203
Test name
Test status
Simulation time 2401054851 ps
CPU time 8.43 seconds
Started Feb 01 03:45:50 PM PST 24
Finished Feb 01 03:46:52 PM PST 24
Peak memory 222620 kb
Host smart-dd539aca-a1cf-4f1b-995e-ff3267e347c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694908373 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2694908373
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.191398980
Short name T952
Test name
Test status
Simulation time 230958877 ps
CPU time 3.71 seconds
Started Feb 01 03:46:53 PM PST 24
Finished Feb 01 03:47:42 PM PST 24
Peak memory 207132 kb
Host smart-973e7fec-e1c8-4710-8779-772fba37fc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191398980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.191398980
Directory /workspace/9.keymgr_sw_invalid_input/latest
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