Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
47890 |
1 |
|
|
T1 |
29 |
|
T2 |
345 |
|
T4 |
59 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
| | | | | | | | | | | | |
auto[0] |
27470 |
1 |
|
|
T2 |
85 |
|
T4 |
59 |
|
T5 |
17 |
auto[1] |
20420 |
1 |
|
|
T1 |
29 |
|
T2 |
260 |
|
T15 |
33 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
| | | | | | | | | | | | |
auto[0] |
23892 |
1 |
|
|
T1 |
15 |
|
T2 |
217 |
|
T4 |
30 |
auto[1] |
23998 |
1 |
|
|
T1 |
14 |
|
T2 |
128 |
|
T4 |
29 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
| | | | | | | | | | | | | | |
all_values[0] |
auto[0] |
auto[0] |
13513 |
1 |
|
|
T2 |
65 |
|
T4 |
30 |
|
T5 |
9 |
all_values[0] |
auto[0] |
auto[1] |
13957 |
1 |
|
|
T2 |
20 |
|
T4 |
29 |
|
T5 |
8 |
all_values[0] |
auto[1] |
auto[0] |
10379 |
1 |
|
|
T1 |
15 |
|
T2 |
152 |
|
T15 |
17 |
all_values[0] |
auto[1] |
auto[1] |
10041 |
1 |
|
|
T1 |
14 |
|
T2 |
108 |
|
T15 |
16 |