Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
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Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
73.02 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv


Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 14 1 13 92.86
Crosses 49 16 33 67.35


Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
op_cp 5 1 4 80.00 100 1 1 0
state_cp 7 0 7 100.00 100 1 1 0
wip_cp 2 0 2 100.00 100 1 1 2


Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
state_x_wip_cross 14 1 13 92.86 100 1 1 0
state_x_op_cross 35 15 20 57.14 100 1 1 0


Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 1 4 80.00


Automatically Generated Bins for op_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[OpDisable] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[OpAdvance] 75 1 T99 2 T40 1 T110 1
auto[OpGenId] 14 1 T2 1 T99 1 T41 1
auto[OpGenSwOut] 35 1 T99 1 T58 1 T143 1
auto[OpGenHwOut] 27 1 T2 1 T99 1 T6 1


Summary for Variable state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for state_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] 1779 1 T2 2 T99 3 T44 3
auto[StInit] 140 1 T2 1 T14 1 T18 1
auto[StCreatorRootKey] 53 1 T17 1 T34 1 T195 1
auto[StOwnerIntKey] 33 1 T52 1 T51 1 T53 1
auto[StOwnerKey] 30 1 T2 1 T58 1 T56 1
auto[StDisabled] 306 1 T2 4 T44 13 T40 1
auto[StInvalid] 41 1 T25 1 T26 1 T47 1


Summary for Variable wip_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wip_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3238 1 T1 1 T2 7 T3 1
auto[1] 151 1 T2 2 T99 5 T40 1


Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 14 1 13 92.86 1


Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins
state_cpwip_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] [auto[1]] 0 1 1


Covered bins
state_cp   wip_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[0] 1762 1 T2 2 T99 3 T44 3
auto[StReset] auto[1] 17 1 T130 1 T139 1 T196 1
auto[StInit] auto[0] 57 1 T14 1 T18 1 T99 2
auto[StInit] auto[1] 83 1 T2 1 T99 5 T110 1
auto[StCreatorRootKey] auto[0] 31 1 T17 1 T34 1 T49 1
auto[StCreatorRootKey] auto[1] 22 1 T195 1 T32 1 T41 2
auto[StOwnerIntKey] auto[0] 19 1 T52 1 T53 1 T55 1
auto[StOwnerIntKey] auto[1] 14 1 T51 1 T54 1 T197 1
auto[StOwnerKey] auto[0] 22 1 T56 1 T59 1 T60 1
auto[StOwnerKey] auto[1] 8 1 T2 1 T58 1 T61 1
auto[StDisabled] auto[0] 299 1 T2 4 T44 13 T27 1
auto[StDisabled] auto[1] 7 1 T40 1 T6 1 T198 1
auto[StInvalid] auto[0] 41 1 T25 1 T26 1 T47 1


Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 35 15 20 57.14 15


Automatically Generated Cross Bins for state_x_op_cross

Element holes
state_cpop_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] * -- -- 5


Uncovered bins
state_cp   op_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[StReset]] [auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]] -- -- 4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]] [auto[OpDisable]] -- -- 4
[auto[StDisabled]] [auto[OpGenSwOut]] 0 1 1
[auto[StDisabled]] [auto[OpDisable]] 0 1 1


Covered bins
state_cp   op_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[OpAdvance] 17 1 T130 1 T139 1 T196 1
auto[StInit] auto[OpAdvance] 32 1 T99 2 T110 1 T114 2
auto[StInit] auto[OpGenId] 9 1 T2 1 T99 1 T199 1
auto[StInit] auto[OpGenSwOut] 24 1 T99 1 T143 1 T114 1
auto[StInit] auto[OpGenHwOut] 18 1 T99 1 T114 2 T7 1
auto[StCreatorRootKey] auto[OpAdvance] 11 1 T41 1 T200 1 T10 1
auto[StCreatorRootKey] auto[OpGenId] 2 1 T41 1 T50 1 - -
auto[StCreatorRootKey] auto[OpGenSwOut] 5 1 T195 1 T32 1 T29 1
auto[StCreatorRootKey] auto[OpGenHwOut] 4 1 T9 1 T201 1 T202 1
auto[StOwnerIntKey] auto[OpAdvance] 9 1 T54 1 T197 1 T203 1
auto[StOwnerIntKey] auto[OpGenId] 1 1 T204 1 - - - -
auto[StOwnerIntKey] auto[OpGenSwOut] 2 1 T51 1 T205 1 - -
auto[StOwnerIntKey] auto[OpGenHwOut] 2 1 T72 1 T206 1 - -
auto[StOwnerKey] auto[OpAdvance] 2 1 T207 1 T208 1 - -
auto[StOwnerKey] auto[OpGenId] 1 1 T61 1 - - - -
auto[StOwnerKey] auto[OpGenSwOut] 4 1 T58 1 T202 1 T209 1
auto[StOwnerKey] auto[OpGenHwOut] 1 1 T2 1 - - - -
auto[StDisabled] auto[OpAdvance] 4 1 T40 1 T30 1 T210 1
auto[StDisabled] auto[OpGenId] 1 1 T198 1 - - - -
auto[StDisabled] auto[OpGenHwOut] 2 1 T6 1 T211 1 - -