Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

9967

1

T1

6

T2

59

T4

14

auto[Attestation]

6782

1

T1

4

T2

30

T4

7

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2448	1			T1	2		T2	11		T5	1
auto[Aes]	3058	1			T1	2		T2	15		T4	21
auto[Kmac]	3002	1			T1	1		T2	16		T5	2
auto[Otbn]	2963	1			T1	2		T2	12		T14	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	6694	1			T1	3		T2	35		T4	8
auto[OpGenId]	5278	1			T1	3		T2	35		T15	3
auto[OpGenSwOut]	5061	1			T1	4		T2	28		T5	3
auto[OpGenHwOut]	6410	1			T1	3		T2	26		T4	21
auto[OpDisable]	117	1			T1	1		T2	2		T5	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

8728

1

T1

8

T2

54

T4

8

auto[OpDoneFail]

14832

1

T1

6

T2

72

T4

21

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5572	1			T1	1		T2	18		T4	14
auto[StInit]	3788	1			T1	4		T2	18		T4	2
auto[StCreatorRootKey]	2597	1			T1	2		T2	18		T4	2
auto[StOwnerIntKey]	2234	1			T1	4		T2	16		T4	2
auto[StOwnerKey]	2031	1			T2	12		T4	2		T15	2
auto[StDisabled]	6360	1			T1	3		T2	44		T4	7
auto[StInvalid]	978	1			T25	29		T26	21		T47	22

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	264	1			T2	1		T16	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	108	1			T1	1		T14	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	74	1			T38	1		T81	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	41	1			T44	1		T57	2		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	42	1			T2	1		T44	2		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	165	1			T2	1		T82	2		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	42	1			T25	1		T26	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	293	1			T2	1		T14	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	120	1			T2	3		T17	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	66	1			T44	1		T6	1		T175	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	57	1			T2	2		T82	1		T128	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	52	1			T81	1		T57	2		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	142	1			T5	1		T38	1		T44	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	33	1			T25	1		T26	1		T176	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	295	1			T2	1		T34	3		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	110	1			T23	1		T44	2		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	63	1			T83	1		T76	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	56	1			T81	1		T177	2		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	45	1			T2	1		T16	1		T178	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	182	1			T2	3		T5	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	36	1			T25	3		T26	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	296	1			T16	4		T34	1		T22	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	91	1			T22	1		T26	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	70	1			T1	1		T2	1		T120	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	56	1			T81	1		T40	1		T179	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	33	1			T24	1		T44	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	160	1			T2	2		T16	1		T82	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	20	1			T25	1		T26	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	63	1			T44	2		T110	1		T114	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T17	1		T34	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	68	1			T81	1		T52	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T180	1		T62	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T83	1		T57	2		T62	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	169	1			T16	2		T82	1		T128	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	27	1			T25	1		T26	1		T181	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	47	1			T44	1		T49	2		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	89	1			T83	1		T23	1		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	61	1			T2	1		T16	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	52	1			T2	1		T82	1		T76	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	49	1			T182	1		T57	1		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	176	1			T2	2		T5	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T26	2		T176	1		T183	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	47	1			T57	2		T49	3		T7	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	82	1			T2	1		T17	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	69	1			T2	1		T44	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	53	1			T1	1		T2	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	53	1			T2	1		T76	1		T44	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	157	1			T15	1		T24	1		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	27	1			T25	1		T47	2		T181	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	50	1			T99	1		T110	1		T49	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	95	1			T1	1		T14	2		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	62	1			T2	1		T24	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	51	1			T44	1		T185	1		T186	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	48	1			T2	1		T82	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	164	1			T2	1		T82	1		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	36	1			T25	1		T47	1		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	230	1			T2	2		T18	2		T22	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	107	1			T2	3		T22	2		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	67	1			T34	1		T120	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	49	1			T44	1		T188	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	34	1			T81	1		T79	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	153	1			T15	1		T38	1		T44	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	29	1			T181	1		T187	1		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	471	1			T4	13		T14	1		T80	7
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	132	1			T80	1		T81	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T2	1		T120	1		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	91	1			T15	1		T80	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	82	1			T4	1		T83	1		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	222	1			T1	2		T2	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	23	1			T47	1		T181	1		T191	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	401	1			T2	2		T14	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	107	1			T120	1		T23	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T24	1		T45	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T82	1		T23	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	83	1			T38	1		T82	1		T182	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	243	1			T2	3		T184	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	40	1			T25	1		T48	2		T176	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	413	1			T2	1		T14	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	140	1			T120	1		T23	1		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T120	1		T78	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	68	1			T52	1		T177	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	76	1			T2	1		T182	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	241	1			T2	3		T81	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	33	1			T26	1		T47	1		T181	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	49	1			T44	1		T77	1		T110	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	103	1			T1	1		T2	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	51	1			T52	1		T184	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	52	1			T76	1		T44	1		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	48	1			T182	1		T6	1		T193	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	151	1			T2	2		T81	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	38	1			T25	2		T47	2		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	36	1			T49	1		T41	2		T42	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	130	1			T4	1		T15	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	88	1			T4	1		T80	1		T120	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	85	1			T2	2		T4	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	77	1			T80	1		T75	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	240	1			T4	4		T80	4		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	23	1			T47	1		T181	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	34	1			T110	1		T114	1		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	120	1			T5	1		T177	1		T182	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	83	1			T120	1		T194	2		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T2	1		T177	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	76	1			T184	1		T182	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	243	1			T2	1		T81	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	30	1			T25	2		T26	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	46	1			T44	2		T110	2		T114	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	120	1			T22	1		T23	1		T177	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T81	1		T76	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T38	1		T177	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	90	1			T82	1		T83	1		T182	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	232	1			T2	1		T81	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	21	1			T47	1		T48	1		T95	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	141	1			T38	1		T81	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	595	1			T1	1		T2	3		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	158	1			T2	1		T81	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	605	1			T2	5		T5	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	152	1			T2	1		T16	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	635	1			T2	4		T5	1		T34	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	139	1			T1	1		T81	1		T120	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	587	1			T2	3		T16	5		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	181	1			T81	1		T52	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	370	1			T16	2		T17	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	151	1			T2	2		T16	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	353	1			T2	2		T5	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	159	1			T1	1		T2	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	329	1			T2	3		T15	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	153	1			T2	2		T82	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	353	1			T1	1		T2	1		T14	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	135	1			T34	1		T81	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	534	1			T2	5		T15	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	253	1			T2	1		T4	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	859	1			T1	2		T2	2		T4	13
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	254	1			T38	1		T82	2		T24	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	808	1			T2	5		T14	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	228	1			T2	1		T120	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	838	1			T2	4		T14	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	145	1			T52	1		T184	1		T182	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	347	1			T1	1		T2	3		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	235	1			T2	2		T4	2		T80	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	444	1			T4	5		T15	1		T80	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	226	1			T2	1		T120	1		T177	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	439	1			T2	1		T5	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	233	1			T38	1		T81	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	432	1			T2	1		T22	1		T81	1