Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27003

1

T1

14

T2

142

T4

34

auto[1]

262

1

T81

7

T82

3

T83

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	27008	1			T1	14		T2	142		T4	34
auto[134217728:268435455]	12	1			T82	1		T224	1		T107	1
auto[268435456:402653183]	11	1			T82	1		T83	2		T79	1
auto[402653184:536870911]	2	1			T385	1		T214	1		-	-
auto[536870912:671088639]	8	1			T107	1		T279	1		T221	1
auto[671088640:805306367]	10	1			T194	1		T212	1		T312	1
auto[805306368:939524095]	7	1			T284	1		T385	1		T214	1
auto[939524096:1073741823]	9	1			T81	1		T83	1		T194	1
auto[1073741824:1207959551]	7	1			T257	1		T312	1		T276	1
auto[1207959552:1342177279]	4	1			T276	1		T272	1		T221	1
auto[1342177280:1476395007]	9	1			T257	1		T212	1		T276	1
auto[1476395008:1610612735]	10	1			T79	1		T323	1		T259	1
auto[1610612736:1744830463]	4	1			T107	1		T323	1		T386	1
auto[1744830464:1879048191]	11	1			T81	1		T257	1		T369	1
auto[1879048192:2013265919]	6	1			T279	1		T213	1		T261	1
auto[2013265920:2147483647]	5	1			T224	1		T257	1		T221	1
auto[2147483648:2281701375]	10	1			T81	1		T194	1		T279	1
auto[2281701376:2415919103]	7	1			T83	1		T194	1		T107	1
auto[2415919104:2550136831]	11	1			T81	1		T251	1		T107	1
auto[2550136832:2684354559]	14	1			T81	1		T107	2		T323	1
auto[2684354560:2818572287]	6	1			T107	2		T348	2		T387	1
auto[2818572288:2952790015]	7	1			T81	1		T279	1		T369	1
auto[2952790016:3087007743]	13	1			T194	1		T276	1		T221	1
auto[3087007744:3221225471]	6	1			T82	1		T79	1		T276	1
auto[3221225472:3355443199]	9	1			T257	1		T107	1		T272	1
auto[3355443200:3489660927]	11	1			T83	1		T107	1		T343	2
auto[3489660928:3623878655]	7	1			T107	1		T312	1		T272	2
auto[3623878656:3758096383]	9	1			T81	1		T279	1		T272	1
auto[3758096384:3892314111]	6	1			T257	1		T279	1		T272	1
auto[3892314112:4026531839]	7	1			T257	1		T251	1		T107	1
auto[4026531840:4160749567]	12	1			T79	1		T107	1		T312	1
auto[4160749568:4294967295]	7	1			T251	1		T343	1		T388	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	27003	1			T1	14		T2	142		T4	34
auto[0:134217727]	auto[1]	5	1			T107	1		T213	1		T389	1
auto[134217728:268435455]	auto[1]	12	1			T82	1		T224	1		T107	1
auto[268435456:402653183]	auto[1]	11	1			T82	1		T83	2		T79	1
auto[402653184:536870911]	auto[1]	2	1			T385	1		T214	1		-	-
auto[536870912:671088639]	auto[1]	8	1			T107	1		T279	1		T221	1
auto[671088640:805306367]	auto[1]	10	1			T194	1		T212	1		T312	1
auto[805306368:939524095]	auto[1]	7	1			T284	1		T385	1		T214	1
auto[939524096:1073741823]	auto[1]	9	1			T81	1		T83	1		T194	1
auto[1073741824:1207959551]	auto[1]	7	1			T257	1		T312	1		T276	1
auto[1207959552:1342177279]	auto[1]	4	1			T276	1		T272	1		T221	1
auto[1342177280:1476395007]	auto[1]	9	1			T257	1		T212	1		T276	1
auto[1476395008:1610612735]	auto[1]	10	1			T79	1		T323	1		T259	1
auto[1610612736:1744830463]	auto[1]	4	1			T107	1		T323	1		T386	1
auto[1744830464:1879048191]	auto[1]	11	1			T81	1		T257	1		T369	1
auto[1879048192:2013265919]	auto[1]	6	1			T279	1		T213	1		T261	1
auto[2013265920:2147483647]	auto[1]	5	1			T224	1		T257	1		T221	1
auto[2147483648:2281701375]	auto[1]	10	1			T81	1		T194	1		T279	1
auto[2281701376:2415919103]	auto[1]	7	1			T83	1		T194	1		T107	1
auto[2415919104:2550136831]	auto[1]	11	1			T81	1		T251	1		T107	1
auto[2550136832:2684354559]	auto[1]	14	1			T81	1		T107	2		T323	1
auto[2684354560:2818572287]	auto[1]	6	1			T107	2		T348	2		T387	1
auto[2818572288:2952790015]	auto[1]	7	1			T81	1		T279	1		T369	1
auto[2952790016:3087007743]	auto[1]	13	1			T194	1		T276	1		T221	1
auto[3087007744:3221225471]	auto[1]	6	1			T82	1		T79	1		T276	1
auto[3221225472:3355443199]	auto[1]	9	1			T257	1		T107	1		T272	1
auto[3355443200:3489660927]	auto[1]	11	1			T83	1		T107	1		T343	2
auto[3489660928:3623878655]	auto[1]	7	1			T107	1		T312	1		T272	2
auto[3623878656:3758096383]	auto[1]	9	1			T81	1		T279	1		T272	1
auto[3758096384:3892314111]	auto[1]	6	1			T257	1		T279	1		T272	1
auto[3892314112:4026531839]	auto[1]	7	1			T257	1		T251	1		T107	1
auto[4026531840:4160749567]	auto[1]	12	1			T79	1		T107	1		T312	1
auto[4160749568:4294967295]	auto[1]	7	1			T251	1		T343	1		T388	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1316

1

T1

1

T2

10

T17

1

auto[1]

1535

1

T1

1

T2

16

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	76	1			T1	1		T44	1		T57	2
auto[134217728:268435455]	86	1			T5	1		T182	1		T25	1
auto[268435456:402653183]	101	1			T22	1		T81	1		T82	1
auto[402653184:536870911]	80	1			T2	2		T120	1		T23	1
auto[536870912:671088639]	98	1			T2	1		T22	1		T81	1
auto[671088640:805306367]	81	1			T2	1		T184	1		T44	1
auto[805306368:939524095]	68	1			T2	2		T184	1		T215	2
auto[939524096:1073741823]	72	1			T2	1		T81	1		T23	1
auto[1073741824:1207959551]	89	1			T2	1		T81	1		T23	1
auto[1207959552:1342177279]	84	1			T1	1		T220	1		T62	1
auto[1342177280:1476395007]	97	1			T2	1		T23	1		T184	1
auto[1476395008:1610612735]	91	1			T23	1		T76	1		T44	2
auto[1610612736:1744830463]	87	1			T22	1		T83	1		T99	1
auto[1744830464:1879048191]	96	1			T2	2		T76	1		T77	1
auto[1879048192:2013265919]	109	1			T2	1		T17	1		T22	1
auto[2013265920:2147483647]	104	1			T2	2		T17	1		T177	1
auto[2147483648:2281701375]	82	1			T2	2		T44	1		T220	1
auto[2281701376:2415919103]	101	1			T17	1		T26	1		T40	1
auto[2415919104:2550136831]	80	1			T76	1		T79	1		T57	1
auto[2550136832:2684354559]	102	1			T81	1		T23	1		T184	1
auto[2684354560:2818572287]	92	1			T2	1		T22	1		T82	1
auto[2818572288:2952790015]	88	1			T177	1		T44	1		T215	1
auto[2952790016:3087007743]	98	1			T24	1		T76	1		T142	1
auto[3087007744:3221225471]	104	1			T2	1		T22	1		T81	1
auto[3221225472:3355443199]	76	1			T2	2		T23	1		T44	1
auto[3355443200:3489660927]	73	1			T22	1		T82	2		T83	1
auto[3489660928:3623878655]	98	1			T2	3		T22	1		T83	1
auto[3623878656:3758096383]	90	1			T81	1		T45	1		T76	1
auto[3758096384:3892314111]	93	1			T22	1		T44	2		T215	2
auto[3892314112:4026531839]	80	1			T2	1		T17	1		T83	1
auto[4026531840:4160749567]	87	1			T2	1		T24	1		T46	1
auto[4160749568:4294967295]	88	1			T2	1		T44	1		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	40	1			T1	1		T44	1		T175	1
auto[0:134217727]	auto[1]	36	1			T57	2		T42	1		T212	1
auto[134217728:268435455]	auto[0]	39	1			T182	1		T25	1		T44	1
auto[134217728:268435455]	auto[1]	47	1			T5	1		T45	1		T44	1
auto[268435456:402653183]	auto[0]	50	1			T82	1		T44	1		T6	1
auto[268435456:402653183]	auto[1]	51	1			T22	1		T81	1		T76	1
auto[402653184:536870911]	auto[0]	28	1			T99	1		T51	1		T181	1
auto[402653184:536870911]	auto[1]	52	1			T2	2		T120	1		T23	1
auto[536870912:671088639]	auto[0]	46	1			T22	1		T81	1		T184	1
auto[536870912:671088639]	auto[1]	52	1			T2	1		T120	1		T82	1
auto[671088640:805306367]	auto[0]	37	1			T2	1		T184	1		T44	1
auto[671088640:805306367]	auto[1]	44	1			T110	1		T192	1		T57	1
auto[805306368:939524095]	auto[0]	32	1			T2	2		T184	1		T194	2
auto[805306368:939524095]	auto[1]	36	1			T215	2		T178	1		T193	1
auto[939524096:1073741823]	auto[0]	37	1			T81	1		T23	1		T184	1
auto[939524096:1073741823]	auto[1]	35	1			T2	1		T44	1		T26	1
auto[1073741824:1207959551]	auto[0]	41	1			T2	1		T23	1		T24	1
auto[1073741824:1207959551]	auto[1]	48	1			T81	1		T184	1		T182	1
auto[1207959552:1342177279]	auto[0]	37	1			T63	1		T238	1		T251	1
auto[1207959552:1342177279]	auto[1]	47	1			T1	1		T220	1		T62	1
auto[1342177280:1476395007]	auto[0]	47	1			T2	1		T23	1		T184	1
auto[1342177280:1476395007]	auto[1]	50	1			T76	1		T26	1		T110	1
auto[1476395008:1610612735]	auto[0]	37	1			T23	1		T44	1		T6	2
auto[1476395008:1610612735]	auto[1]	54	1			T76	1		T44	1		T58	1
auto[1610612736:1744830463]	auto[0]	39	1			T22	1		T99	1		T25	1
auto[1610612736:1744830463]	auto[1]	48	1			T83	1		T44	1		T47	1
auto[1744830464:1879048191]	auto[0]	45	1			T77	1		T8	1		T192	1
auto[1744830464:1879048191]	auto[1]	51	1			T2	2		T76	1		T178	1
auto[1879048192:2013265919]	auto[0]	56	1			T17	1		T22	1		T23	1
auto[1879048192:2013265919]	auto[1]	53	1			T2	1		T76	1		T44	2
auto[2013265920:2147483647]	auto[0]	45	1			T177	1		T99	2		T57	1
auto[2013265920:2147483647]	auto[1]	59	1			T2	2		T17	1		T128	1
auto[2147483648:2281701375]	auto[0]	33	1			T233	1		T7	1		T41	1
auto[2147483648:2281701375]	auto[1]	49	1			T2	2		T44	1		T220	1
auto[2281701376:2415919103]	auto[0]	47	1			T40	1		T57	2		T41	2
auto[2281701376:2415919103]	auto[1]	54	1			T17	1		T26	1		T56	1
auto[2415919104:2550136831]	auto[0]	43	1			T251	1		T41	1		T42	1
auto[2415919104:2550136831]	auto[1]	37	1			T76	1		T79	1		T57	1
auto[2550136832:2684354559]	auto[0]	55	1			T81	1		T23	1		T184	1
auto[2550136832:2684354559]	auto[1]	47	1			T44	1		T110	1		T57	1
auto[2684354560:2818572287]	auto[0]	46	1			T2	1		T82	1		T87	1
auto[2684354560:2818572287]	auto[1]	46	1			T22	1		T215	1		T194	1
auto[2818572288:2952790015]	auto[0]	34	1			T44	1		T215	1		T216	1
auto[2818572288:2952790015]	auto[1]	54	1			T177	1		T57	1		T225	1
auto[2952790016:3087007743]	auto[0]	44	1			T142	1		T194	1		T225	1
auto[2952790016:3087007743]	auto[1]	54	1			T24	1		T76	1		T114	1
auto[3087007744:3221225471]	auto[0]	45	1			T22	1		T81	1		T44	1
auto[3087007744:3221225471]	auto[1]	59	1			T2	1		T24	1		T26	1
auto[3221225472:3355443199]	auto[0]	34	1			T2	2		T23	1		T44	1
auto[3221225472:3355443199]	auto[1]	42	1			T6	1		T192	1		T63	1
auto[3355443200:3489660927]	auto[0]	29	1			T22	1		T83	1		T25	1
auto[3355443200:3489660927]	auto[1]	44	1			T82	2		T220	1		T195	1
auto[3489660928:3623878655]	auto[0]	48	1			T2	1		T22	1		T83	1
auto[3489660928:3623878655]	auto[1]	50	1			T2	2		T51	1		T57	1
auto[3623878656:3758096383]	auto[0]	40	1			T81	1		T45	1		T77	1
auto[3623878656:3758096383]	auto[1]	50	1			T76	1		T110	1		T224	1
auto[3758096384:3892314111]	auto[0]	45	1			T44	1		T142	1		T57	1
auto[3758096384:3892314111]	auto[1]	48	1			T22	1		T44	1		T215	2
auto[3892314112:4026531839]	auto[0]	35	1			T83	1		T175	1		T7	1
auto[3892314112:4026531839]	auto[1]	45	1			T2	1		T17	1		T182	1
auto[4026531840:4160749567]	auto[0]	39	1			T2	1		T24	1		T57	1
auto[4026531840:4160749567]	auto[1]	48	1			T46	1		T390	1		T63	1
auto[4160749568:4294967295]	auto[0]	43	1			T215	1		T57	1		T225	1
auto[4160749568:4294967295]	auto[1]	45	1			T2	1		T44	1		T6	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1371

1

T2

8

T17

1

T22

6

auto[1]

1481

1

T1

2

T2

18

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	80	1			T99	1		T79	1		T142	2
auto[134217728:268435455]	93	1			T2	2		T81	1		T44	1
auto[268435456:402653183]	69	1			T2	1		T47	1		T305	1
auto[402653184:536870911]	103	1			T81	1		T82	1		T23	1
auto[536870912:671088639]	87	1			T83	1		T23	1		T44	2
auto[671088640:805306367]	102	1			T1	1		T2	1		T22	1
auto[805306368:939524095]	107	1			T2	1		T5	1		T120	1
auto[939524096:1073741823]	94	1			T22	1		T215	1		T143	1
auto[1073741824:1207959551]	80	1			T2	1		T22	2		T83	1
auto[1207959552:1342177279]	89	1			T2	1		T177	2		T45	1
auto[1342177280:1476395007]	105	1			T2	3		T25	1		T26	1
auto[1476395008:1610612735]	89	1			T2	2		T82	1		T24	1
auto[1610612736:1744830463]	79	1			T22	1		T44	1		T110	1
auto[1744830464:1879048191]	85	1			T2	1		T83	1		T44	1
auto[1879048192:2013265919]	99	1			T1	1		T2	1		T22	3
auto[2013265920:2147483647]	84	1			T24	1		T182	1		T44	1
auto[2147483648:2281701375]	96	1			T81	1		T23	1		T99	1
auto[2281701376:2415919103]	90	1			T2	1		T22	1		T81	1
auto[2415919104:2550136831]	93	1			T2	3		T82	1		T24	1
auto[2550136832:2684354559]	81	1			T2	1		T184	1		T128	1
auto[2684354560:2818572287]	85	1			T17	1		T23	1		T44	1
auto[2818572288:2952790015]	75	1			T76	1		T44	2		T192	1
auto[2952790016:3087007743]	81	1			T2	2		T81	1		T82	1
auto[3087007744:3221225471]	96	1			T17	1		T99	1		T25	1
auto[3221225472:3355443199]	83	1			T44	1		T220	1		T215	1
auto[3355443200:3489660927]	94	1			T2	1		T23	1		T184	1
auto[3489660928:3623878655]	96	1			T82	1		T184	2		T44	1
auto[3623878656:3758096383]	85	1			T17	2		T23	2		T76	1
auto[3758096384:3892314111]	91	1			T120	1		T25	1		T76	1
auto[3892314112:4026531839]	91	1			T2	1		T44	1		T110	1
auto[4026531840:4160749567]	79	1			T2	2		T24	1		T184	1
auto[4160749568:4294967295]	91	1			T2	1		T81	1		T23	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	36	1			T79	1		T142	2		T57	1
auto[0:134217727]	auto[1]	44	1			T99	1		T181	1		T7	1
auto[134217728:268435455]	auto[0]	41	1			T81	1		T44	1		T225	3
auto[134217728:268435455]	auto[1]	52	1			T2	2		T6	1		T56	1
auto[268435456:402653183]	auto[0]	32	1			T41	1		T380	1		T391	1
auto[268435456:402653183]	auto[1]	37	1			T2	1		T47	1		T305	1
auto[402653184:536870911]	auto[0]	48	1			T81	1		T44	1		T40	1
auto[402653184:536870911]	auto[1]	55	1			T82	1		T23	1		T77	1
auto[536870912:671088639]	auto[0]	47	1			T23	1		T44	2		T175	1
auto[536870912:671088639]	auto[1]	40	1			T83	1		T110	1		T57	1
auto[671088640:805306367]	auto[0]	47	1			T81	1		T6	1		T27	1
auto[671088640:805306367]	auto[1]	55	1			T1	1		T2	1		T22	1
auto[805306368:939524095]	auto[0]	60	1			T184	1		T99	1		T192	1
auto[805306368:939524095]	auto[1]	47	1			T2	1		T5	1		T120	1
auto[939524096:1073741823]	auto[0]	49	1			T22	1		T143	1		T178	1
auto[939524096:1073741823]	auto[1]	45	1			T215	1		T193	1		T383	1
auto[1073741824:1207959551]	auto[0]	35	1			T2	1		T22	1		T83	1
auto[1073741824:1207959551]	auto[1]	45	1			T22	1		T57	2		T62	1
auto[1207959552:1342177279]	auto[0]	48	1			T2	1		T177	1		T181	1
auto[1207959552:1342177279]	auto[1]	41	1			T177	1		T45	1		T76	1
auto[1342177280:1476395007]	auto[0]	47	1			T25	1		T57	1		T41	1
auto[1342177280:1476395007]	auto[1]	58	1			T2	3		T26	1		T7	2
auto[1476395008:1610612735]	auto[0]	37	1			T2	1		T82	1		T24	1
auto[1476395008:1610612735]	auto[1]	52	1			T2	1		T57	1		T281	1
auto[1610612736:1744830463]	auto[0]	34	1			T22	1		T110	1		T225	1
auto[1610612736:1744830463]	auto[1]	45	1			T44	1		T390	1		T63	1
auto[1744830464:1879048191]	auto[0]	40	1			T44	1		T220	1		T57	1
auto[1744830464:1879048191]	auto[1]	45	1			T2	1		T83	1		T57	1
auto[1879048192:2013265919]	auto[0]	52	1			T22	2		T44	2		T57	1
auto[1879048192:2013265919]	auto[1]	47	1			T1	1		T2	1		T22	1
auto[2013265920:2147483647]	auto[0]	40	1			T24	1		T182	1		T44	1
auto[2013265920:2147483647]	auto[1]	44	1			T215	1		T63	1		T233	1
auto[2147483648:2281701375]	auto[0]	47	1			T81	1		T23	1		T99	1
auto[2147483648:2281701375]	auto[1]	49	1			T44	1		T26	2		T192	1
auto[2281701376:2415919103]	auto[0]	45	1			T22	1		T81	1		T49	1
auto[2281701376:2415919103]	auto[1]	45	1			T2	1		T99	1		T56	1
auto[2415919104:2550136831]	auto[0]	46	1			T25	1		T58	1		T57	1
auto[2415919104:2550136831]	auto[1]	47	1			T2	3		T82	1		T24	1
auto[2550136832:2684354559]	auto[0]	40	1			T2	1		T184	1		T6	1
auto[2550136832:2684354559]	auto[1]	41	1			T128	1		T238	1		T342	1
auto[2684354560:2818572287]	auto[0]	41	1			T23	1		T6	1		T8	1
auto[2684354560:2818572287]	auto[1]	44	1			T17	1		T44	1		T194	1
auto[2818572288:2952790015]	auto[0]	41	1			T44	2		T224	1		T7	1
auto[2818572288:2952790015]	auto[1]	34	1			T76	1		T192	1		T56	1
auto[2952790016:3087007743]	auto[0]	41	1			T2	1		T82	1		T83	1
auto[2952790016:3087007743]	auto[1]	40	1			T2	1		T81	1		T182	1
auto[3087007744:3221225471]	auto[0]	39	1			T25	1		T44	1		T220	1
auto[3087007744:3221225471]	auto[1]	57	1			T17	1		T99	1		T76	2
auto[3221225472:3355443199]	auto[0]	39	1			T44	1		T51	1		T233	1
auto[3221225472:3355443199]	auto[1]	44	1			T220	1		T215	1		T194	1
auto[3355443200:3489660927]	auto[0]	47	1			T23	1		T184	1		T99	1
auto[3355443200:3489660927]	auto[1]	47	1			T2	1		T7	1		T392	1
auto[3489660928:3623878655]	auto[0]	47	1			T184	2		T44	1		T215	1
auto[3489660928:3623878655]	auto[1]	49	1			T82	1		T216	2		T110	1
auto[3623878656:3758096383]	auto[0]	46	1			T17	1		T23	2		T44	1
auto[3623878656:3758096383]	auto[1]	39	1			T17	1		T76	1		T27	1
auto[3758096384:3892314111]	auto[0]	41	1			T25	1		T76	1		T6	1
auto[3758096384:3892314111]	auto[1]	50	1			T120	1		T77	1		T194	1
auto[3892314112:4026531839]	auto[0]	42	1			T2	1		T44	1		T233	1
auto[3892314112:4026531839]	auto[1]	49	1			T110	1		T224	1		T67	1
auto[4026531840:4160749567]	auto[0]	33	1			T2	1		T186	1		T49	1
auto[4026531840:4160749567]	auto[1]	46	1			T2	1		T24	1		T184	1
auto[4160749568:4294967295]	auto[0]	43	1			T2	1		T81	1		T184	1
auto[4160749568:4294967295]	auto[1]	48	1			T23	1		T76	2		T44	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1365

1

T1

1

T2

11

T5

1

auto[1]

1490

1

T1

1

T2

15

T17

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T2	4		T81	1		T24	2
auto[134217728:268435455]	83	1			T1	1		T2	3		T44	1
auto[268435456:402653183]	82	1			T2	1		T83	1		T177	1
auto[402653184:536870911]	88	1			T82	1		T24	1		T184	1
auto[536870912:671088639]	78	1			T81	1		T44	1		T26	1
auto[671088640:805306367]	92	1			T22	1		T99	1		T225	1
auto[805306368:939524095]	91	1			T76	1		T26	1		T6	1
auto[939524096:1073741823]	84	1			T2	1		T24	1		T25	1
auto[1073741824:1207959551]	95	1			T2	1		T120	1		T82	1
auto[1207959552:1342177279]	96	1			T2	1		T81	1		T23	1
auto[1342177280:1476395007]	104	1			T2	1		T22	1		T23	1
auto[1476395008:1610612735]	101	1			T2	1		T177	1		T184	1
auto[1610612736:1744830463]	91	1			T2	1		T17	1		T22	2
auto[1744830464:1879048191]	95	1			T2	1		T22	1		T82	1
auto[1879048192:2013265919]	82	1			T23	1		T182	1		T44	1
auto[2013265920:2147483647]	95	1			T2	1		T184	1		T76	1
auto[2147483648:2281701375]	88	1			T17	1		T81	1		T77	1
auto[2281701376:2415919103]	80	1			T17	1		T184	1		T76	1
auto[2415919104:2550136831]	94	1			T1	1		T120	1		T184	1
auto[2550136832:2684354559]	91	1			T2	1		T57	1		T175	1
auto[2684354560:2818572287]	88	1			T81	1		T83	2		T76	1
auto[2818572288:2952790015]	102	1			T2	1		T5	1		T17	1
auto[2952790016:3087007743]	83	1			T81	2		T23	1		T44	1
auto[3087007744:3221225471]	77	1			T2	2		T83	1		T23	1
auto[3221225472:3355443199]	99	1			T23	1		T184	1		T25	1
auto[3355443200:3489660927]	80	1			T2	1		T22	3		T220	1
auto[3489660928:3623878655]	75	1			T2	1		T27	1		T51	1
auto[3623878656:3758096383]	64	1			T2	1		T22	1		T99	1
auto[3758096384:3892314111]	101	1			T23	1		T182	1		T25	1
auto[3892314112:4026531839]	97	1			T2	1		T99	1		T45	1
auto[4026531840:4160749567]	73	1			T2	1		T82	1		T23	1
auto[4160749568:4294967295]	98	1			T2	1		T82	1		T44	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T2	1		T81	1		T24	1
auto[0:134217727]	auto[1]	61	1			T2	3		T24	1		T99	1
auto[134217728:268435455]	auto[0]	40	1			T1	1		T2	1		T44	1
auto[134217728:268435455]	auto[1]	43	1			T2	2		T49	1		T305	1
auto[268435456:402653183]	auto[0]	43	1			T83	1		T184	1		T44	1
auto[268435456:402653183]	auto[1]	39	1			T2	1		T177	1		T76	1
auto[402653184:536870911]	auto[0]	37	1			T82	1		T24	1		T390	1
auto[402653184:536870911]	auto[1]	51	1			T184	1		T76	1		T32	1
auto[536870912:671088639]	auto[0]	38	1			T81	1		T44	1		T142	1
auto[536870912:671088639]	auto[1]	40	1			T26	1		T110	1		T195	1
auto[671088640:805306367]	auto[0]	44	1			T22	1		T99	1		T181	1
auto[671088640:805306367]	auto[1]	48	1			T225	1		T63	1		T49	3
auto[805306368:939524095]	auto[0]	46	1			T6	1		T7	1		T41	2
auto[805306368:939524095]	auto[1]	45	1			T76	1		T26	1		T225	1
auto[939524096:1073741823]	auto[0]	45	1			T25	1		T57	1		T233	1
auto[939524096:1073741823]	auto[1]	39	1			T2	1		T24	1		T76	1
auto[1073741824:1207959551]	auto[0]	52	1			T45	1		T225	1		T63	1
auto[1073741824:1207959551]	auto[1]	43	1			T2	1		T120	1		T82	1
auto[1207959552:1342177279]	auto[0]	52	1			T2	1		T81	1		T184	1
auto[1207959552:1342177279]	auto[1]	44	1			T23	1		T225	1		T7	2
auto[1342177280:1476395007]	auto[0]	54	1			T2	1		T22	1		T23	1
auto[1342177280:1476395007]	auto[1]	50	1			T49	1		T7	2		T42	1
auto[1476395008:1610612735]	auto[0]	44	1			T44	2		T51	1		T57	1
auto[1476395008:1610612735]	auto[1]	57	1			T2	1		T177	1		T184	1
auto[1610612736:1744830463]	auto[0]	34	1			T22	1		T44	1		T251	1
auto[1610612736:1744830463]	auto[1]	57	1			T2	1		T17	1		T22	1
auto[1744830464:1879048191]	auto[0]	40	1			T2	1		T22	1		T99	1
auto[1744830464:1879048191]	auto[1]	55	1			T82	1		T220	1		T7	1
auto[1879048192:2013265919]	auto[0]	40	1			T23	1		T57	1		T238	1
auto[1879048192:2013265919]	auto[1]	42	1			T182	1		T44	1		T220	1
auto[2013265920:2147483647]	auto[0]	44	1			T2	1		T8	1		T220	1
auto[2013265920:2147483647]	auto[1]	51	1			T184	1		T76	1		T110	1
auto[2147483648:2281701375]	auto[0]	43	1			T81	1		T40	1		T57	1
auto[2147483648:2281701375]	auto[1]	45	1			T17	1		T77	1		T26	1
auto[2281701376:2415919103]	auto[0]	34	1			T17	1		T184	1		T87	1
auto[2281701376:2415919103]	auto[1]	46	1			T76	1		T215	1		T57	1
auto[2415919104:2550136831]	auto[0]	41	1			T184	1		T25	1		T44	2
auto[2415919104:2550136831]	auto[1]	53	1			T1	1		T120	1		T128	1
auto[2550136832:2684354559]	auto[0]	38	1			T2	1		T57	1		T175	1
auto[2550136832:2684354559]	auto[1]	53	1			T257	1		T342	1		T42	1
auto[2684354560:2818572287]	auto[0]	47	1			T81	1		T83	1		T76	1
auto[2684354560:2818572287]	auto[1]	41	1			T83	1		T224	1		T67	1
auto[2818572288:2952790015]	auto[0]	54	1			T2	1		T5	1		T44	1
auto[2818572288:2952790015]	auto[1]	48	1			T17	1		T76	1		T225	1
auto[2952790016:3087007743]	auto[0]	44	1			T81	2		T23	1		T215	1
auto[2952790016:3087007743]	auto[1]	39	1			T44	1		T194	1		T57	1
auto[3087007744:3221225471]	auto[0]	35	1			T83	1		T23	1		T44	1
auto[3087007744:3221225471]	auto[1]	42	1			T2	2		T99	1		T110	1
auto[3221225472:3355443199]	auto[0]	46	1			T184	1		T25	1		T44	1
auto[3221225472:3355443199]	auto[1]	53	1			T23	1		T44	1		T215	1
auto[3355443200:3489660927]	auto[0]	39	1			T2	1		T22	2		T192	1
auto[3355443200:3489660927]	auto[1]	41	1			T22	1		T220	1		T47	1
auto[3489660928:3623878655]	auto[0]	38	1			T2	1		T51	1		T7	1
auto[3489660928:3623878655]	auto[1]	37	1			T27	1		T57	1		T49	1
auto[3623878656:3758096383]	auto[0]	29	1			T6	1		T58	1		T192	1
auto[3623878656:3758096383]	auto[1]	35	1			T2	1		T22	1		T99	1
auto[3758096384:3892314111]	auto[0]	52	1			T23	1		T25	1		T44	1
auto[3758096384:3892314111]	auto[1]	49	1			T182	1		T44	1		T194	2
auto[3892314112:4026531839]	auto[0]	41	1			T2	1		T44	2		T142	1
auto[3892314112:4026531839]	auto[1]	56	1			T99	1		T45	1		T6	1
auto[4026531840:4160749567]	auto[0]	38	1			T23	1		T24	1		T44	1
auto[4026531840:4160749567]	auto[1]	35	1			T2	1		T82	1		T6	1
auto[4160749568:4294967295]	auto[0]	46	1			T82	1		T44	1		T51	1
auto[4160749568:4294967295]	auto[1]	52	1			T2	1		T44	1		T27	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1353

1

T1

1

T2

10

T17

1

auto[1]

1508

1

T1

1

T2

16

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	78	1			T2	1		T44	1		T110	1
auto[134217728:268435455]	93	1			T2	1		T22	1		T83	1
auto[268435456:402653183]	107	1			T2	2		T17	1		T22	1
auto[402653184:536870911]	97	1			T2	1		T22	1		T81	1
auto[536870912:671088639]	90	1			T2	1		T22	2		T23	1
auto[671088640:805306367]	92	1			T81	1		T184	1		T25	1
auto[805306368:939524095]	90	1			T2	1		T82	1		T142	1
auto[939524096:1073741823]	96	1			T81	1		T184	2		T182	1
auto[1073741824:1207959551]	83	1			T2	2		T22	1		T177	1
auto[1207959552:1342177279]	85	1			T23	1		T184	1		T110	1
auto[1342177280:1476395007]	89	1			T1	1		T82	1		T83	1
auto[1476395008:1610612735]	92	1			T2	1		T215	1		T142	1
auto[1610612736:1744830463]	104	1			T17	1		T120	1		T184	1
auto[1744830464:1879048191]	97	1			T1	1		T2	1		T184	1
auto[1879048192:2013265919]	78	1			T23	1		T45	1		T44	1
auto[2013265920:2147483647]	79	1			T2	1		T5	1		T82	1
auto[2147483648:2281701375]	103	1			T2	2		T17	1		T22	1
auto[2281701376:2415919103]	81	1			T2	2		T83	1		T23	1
auto[2415919104:2550136831]	72	1			T82	1		T25	1		T44	1
auto[2550136832:2684354559]	77	1			T2	2		T99	1		T44	3
auto[2684354560:2818572287]	76	1			T2	1		T23	1		T25	1
auto[2818572288:2952790015]	95	1			T2	3		T22	1		T24	1
auto[2952790016:3087007743]	87	1			T44	1		T58	1		T142	1
auto[3087007744:3221225471]	80	1			T24	1		T182	1		T44	1
auto[3221225472:3355443199]	92	1			T2	1		T81	1		T83	1
auto[3355443200:3489660927]	86	1			T220	1		T57	1		T47	1
auto[3489660928:3623878655]	103	1			T23	1		T24	1		T184	1
auto[3623878656:3758096383]	86	1			T23	1		T76	1		T44	1
auto[3758096384:3892314111]	94	1			T22	1		T81	2		T24	1
auto[3892314112:4026531839]	93	1			T2	2		T17	1		T120	1
auto[4026531840:4160749567]	89	1			T76	1		T44	2		T79	1
auto[4160749568:4294967295]	97	1			T2	1		T81	1		T99	1