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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3858 1 T2 42 T17 8 T22 12
auto[1] 1839 1 T1 4 T2 10 T5 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 158 1 T2 2 T22 2 T82 2
auto[134217728:268435455] 200 1 T2 2 T120 2 T24 2
auto[268435456:402653183] 162 1 T142 2 T57 2 T49 2
auto[402653184:536870911] 166 1 T83 2 T23 2 T76 2
auto[536870912:671088639] 154 1 T22 2 T81 2 T182 2
auto[671088640:805306367] 192 1 T2 2 T82 2 T184 2
auto[805306368:939524095] 166 1 T2 2 T82 2 T6 2
auto[939524096:1073741823] 180 1 T2 2 T44 2 T79 2
auto[1073741824:1207959551] 182 1 T2 2 T44 2 T77 2
auto[1207959552:1342177279] 180 1 T25 2 T44 2 T46 2
auto[1342177280:1476395007] 182 1 T2 2 T22 2 T81 2
auto[1476395008:1610612735] 186 1 T1 2 T2 2 T81 2
auto[1610612736:1744830463] 196 1 T2 6 T17 2 T81 2
auto[1744830464:1879048191] 180 1 T2 2 T81 2 T83 2
auto[1879048192:2013265919] 186 1 T2 2 T22 2 T23 2
auto[2013265920:2147483647] 166 1 T17 2 T81 2 T184 2
auto[2147483648:2281701375] 202 1 T2 8 T22 2 T24 2
auto[2281701376:2415919103] 131 1 T2 2 T24 4 T8 1
auto[2415919104:2550136831] 168 1 T17 2 T83 2 T99 2
auto[2550136832:2684354559] 160 1 T2 2 T22 2 T99 2
auto[2684354560:2818572287] 182 1 T22 2 T99 4 T25 2
auto[2818572288:2952790015] 180 1 T82 2 T184 2 T79 2
auto[2952790016:3087007743] 186 1 T2 4 T26 2 T27 2
auto[3087007744:3221225471] 196 1 T1 2 T2 2 T23 2
auto[3221225472:3355443199] 182 1 T177 2 T184 2 T76 2
auto[3355443200:3489660927] 206 1 T45 2 T44 2 T26 2
auto[3489660928:3623878655] 150 1 T82 2 T76 2 T44 2
auto[3623878656:3758096383] 196 1 T120 2 T83 2 T23 4
auto[3758096384:3892314111] 178 1 T2 4 T24 2 T44 2
auto[3892314112:4026531839] 182 1 T2 2 T17 2 T81 2
auto[4026531840:4160749567] 202 1 T2 2 T5 2 T22 4
auto[4160749568:4294967295] 160 1 T182 2 T99 4 T25 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 96 1 T2 2 T22 2 T82 2
auto[0:134217727] auto[1] 62 1 T184 2 T224 2 T178 2
auto[134217728:268435455] auto[0] 138 1 T2 2 T24 2 T184 2
auto[134217728:268435455] auto[1] 62 1 T120 2 T44 4 T187 2
auto[268435456:402653183] auto[0] 112 1 T142 2 T57 2 T7 4
auto[268435456:402653183] auto[1] 50 1 T49 2 T41 2 T367 2
auto[402653184:536870911] auto[0] 132 1 T83 2 T23 2 T76 2
auto[402653184:536870911] auto[1] 34 1 T100 2 T331 2 T401 2
auto[536870912:671088639] auto[0] 112 1 T182 2 T76 2 T44 2
auto[536870912:671088639] auto[1] 42 1 T22 2 T81 2 T44 4
auto[671088640:805306367] auto[0] 130 1 T2 2 T82 2 T44 2
auto[671088640:805306367] auto[1] 62 1 T184 2 T225 2 T87 2
auto[805306368:939524095] auto[0] 136 1 T2 2 T82 2 T6 2
auto[805306368:939524095] auto[1] 30 1 T49 2 T245 2 T197 4
auto[939524096:1073741823] auto[0] 106 1 T2 2 T44 2 T79 2
auto[939524096:1073741823] auto[1] 74 1 T57 2 T390 2 T392 2
auto[1073741824:1207959551] auto[0] 120 1 T77 2 T110 2 T186 2
auto[1073741824:1207959551] auto[1] 62 1 T2 2 T44 2 T8 2
auto[1207959552:1342177279] auto[0] 104 1 T44 2 T46 2 T7 4
auto[1207959552:1342177279] auto[1] 76 1 T25 2 T193 2 T7 2
auto[1342177280:1476395007] auto[0] 138 1 T2 2 T81 2 T23 2
auto[1342177280:1476395007] auto[1] 44 1 T22 2 T128 2 T45 2
auto[1476395008:1610612735] auto[0] 128 1 T81 2 T58 2 T56 2
auto[1476395008:1610612735] auto[1] 58 1 T1 2 T2 2 T182 2
auto[1610612736:1744830463] auto[0] 134 1 T2 6 T17 2 T81 2
auto[1610612736:1744830463] auto[1] 62 1 T49 2 T262 2 T42 4
auto[1744830464:1879048191] auto[0] 126 1 T2 2 T81 2 T83 2
auto[1744830464:1879048191] auto[1] 54 1 T44 2 T49 2 T257 2
auto[1879048192:2013265919] auto[0] 116 1 T2 2 T23 2 T25 2
auto[1879048192:2013265919] auto[1] 70 1 T22 2 T177 2 T175 2
auto[2013265920:2147483647] auto[0] 106 1 T17 2 T81 2 T44 2
auto[2013265920:2147483647] auto[1] 60 1 T184 2 T44 2 T216 2
auto[2147483648:2281701375] auto[0] 150 1 T2 6 T22 2 T24 2
auto[2147483648:2281701375] auto[1] 52 1 T2 2 T40 2 T192 2
auto[2281701376:2415919103] auto[0] 92 1 T2 2 T24 2 T192 2
auto[2281701376:2415919103] auto[1] 39 1 T24 2 T8 1 T110 2
auto[2415919104:2550136831] auto[0] 118 1 T17 2 T83 2 T99 2
auto[2415919104:2550136831] auto[1] 50 1 T40 2 T142 2 T143 2
auto[2550136832:2684354559] auto[0] 104 1 T2 2 T22 2 T76 2
auto[2550136832:2684354559] auto[1] 56 1 T99 2 T63 2 T262 2
auto[2684354560:2818572287] auto[0] 126 1 T22 2 T99 4 T25 2
auto[2684354560:2818572287] auto[1] 56 1 T195 2 T41 2 T42 2
auto[2818572288:2952790015] auto[0] 118 1 T82 2 T184 2 T79 2
auto[2818572288:2952790015] auto[1] 62 1 T220 2 T57 2 T224 2
auto[2952790016:3087007743] auto[0] 120 1 T2 4 T27 2 T233 2
auto[2952790016:3087007743] auto[1] 66 1 T26 2 T47 2 T32 2
auto[3087007744:3221225471] auto[0] 144 1 T2 2 T23 2 T44 2
auto[3087007744:3221225471] auto[1] 52 1 T1 2 T41 6 T201 2
auto[3221225472:3355443199] auto[0] 132 1 T177 2 T184 2 T76 2
auto[3221225472:3355443199] auto[1] 50 1 T192 2 T390 2 T7 4
auto[3355443200:3489660927] auto[0] 124 1 T44 2 T26 2 T225 2
auto[3355443200:3489660927] auto[1] 82 1 T45 2 T194 2 T193 2
auto[3489660928:3623878655] auto[0] 98 1 T82 2 T76 2 T44 2
auto[3489660928:3623878655] auto[1] 52 1 T110 2 T57 2 T7 2
auto[3623878656:3758096383] auto[0] 140 1 T120 2 T83 2 T23 4
auto[3623878656:3758096383] auto[1] 56 1 T44 2 T192 2 T41 2
auto[3758096384:3892314111] auto[0] 100 1 T2 2 T6 2 T220 2
auto[3758096384:3892314111] auto[1] 78 1 T2 2 T24 2 T44 2
auto[3892314112:4026531839] auto[0] 122 1 T17 2 T81 2 T184 2
auto[3892314112:4026531839] auto[1] 60 1 T2 2 T184 2 T262 2
auto[4026531840:4160749567] auto[0] 154 1 T2 2 T22 4 T44 2
auto[4026531840:4160749567] auto[1] 48 1 T5 2 T57 2 T41 2
auto[4160749568:4294967295] auto[0] 82 1 T182 2 T25 2 T175 2
auto[4160749568:4294967295] auto[1] 78 1 T99 4 T77 2 T6 2

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