dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2507 1 T1 2 T2 15 T5 1
auto[1] 250 1 T81 3 T82 5 T83 3


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 90 1 T2 1 T23 1 T44 1
auto[134217728:268435455] 81 1 T1 1 T83 1 T184 1
auto[268435456:402653183] 91 1 T184 1 T182 2 T99 2
auto[402653184:536870911] 74 1 T2 1 T81 2 T82 1
auto[536870912:671088639] 96 1 T2 1 T83 1 T184 2
auto[671088640:805306367] 83 1 T81 1 T82 1 T23 1
auto[805306368:939524095] 85 1 T184 1 T76 1 T26 1
auto[939524096:1073741823] 95 1 T82 1 T25 2 T76 1
auto[1073741824:1207959551] 68 1 T79 1 T194 1 T47 1
auto[1207959552:1342177279] 88 1 T2 2 T17 1 T83 1
auto[1342177280:1476395007] 98 1 T81 1 T83 1 T45 1
auto[1476395008:1610612735] 78 1 T2 1 T25 1 T79 1
auto[1610612736:1744830463] 95 1 T2 1 T82 1 T24 2
auto[1744830464:1879048191] 80 1 T2 2 T82 1 T44 2
auto[1879048192:2013265919] 111 1 T81 1 T120 1 T182 1
auto[2013265920:2147483647] 90 1 T81 2 T83 1 T23 1
auto[2147483648:2281701375] 82 1 T2 1 T22 2 T82 1
auto[2281701376:2415919103] 86 1 T22 1 T81 1 T194 1
auto[2415919104:2550136831] 86 1 T1 1 T22 1 T99 2
auto[2550136832:2684354559] 81 1 T82 1 T76 1 T40 1
auto[2684354560:2818572287] 85 1 T22 2 T24 1 T99 1
auto[2818572288:2952790015] 87 1 T5 1 T81 1 T23 1
auto[2952790016:3087007743] 72 1 T22 2 T82 1 T83 1
auto[3087007744:3221225471] 93 1 T99 1 T192 1 T57 2
auto[3221225472:3355443199] 83 1 T6 1 T57 2 T224 1
auto[3355443200:3489660927] 103 1 T45 1 T44 1 T40 1
auto[3489660928:3623878655] 78 1 T23 1 T177 1 T99 1
auto[3623878656:3758096383] 74 1 T2 1 T17 1 T81 1
auto[3758096384:3892314111] 76 1 T82 1 T23 1 T215 1
auto[3892314112:4026531839] 85 1 T2 1 T22 1 T23 1
auto[4026531840:4160749567] 90 1 T120 1 T82 1 T76 1
auto[4160749568:4294967295] 93 1 T2 3 T17 1 T83 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 82 1 T2 1 T23 1 T44 1
auto[0:134217727] auto[1] 8 1 T323 1 T212 1 T312 1
auto[134217728:268435455] auto[0] 72 1 T1 1 T83 1 T184 1
auto[134217728:268435455] auto[1] 9 1 T107 1 T212 1 T312 1
auto[268435456:402653183] auto[0] 85 1 T184 1 T182 2 T99 2
auto[268435456:402653183] auto[1] 6 1 T194 1 T276 1 T279 1
auto[402653184:536870911] auto[0] 69 1 T2 1 T81 1 T82 1
auto[402653184:536870911] auto[1] 5 1 T81 1 T402 2 T397 1
auto[536870912:671088639] auto[0] 90 1 T2 1 T184 2 T44 1
auto[536870912:671088639] auto[1] 6 1 T83 1 T212 1 T261 1
auto[671088640:805306367] auto[0] 77 1 T23 1 T184 1 T44 1
auto[671088640:805306367] auto[1] 6 1 T81 1 T82 1 T79 1
auto[805306368:939524095] auto[0] 76 1 T184 1 T76 1 T26 1
auto[805306368:939524095] auto[1] 9 1 T194 1 T276 1 T369 1
auto[939524096:1073741823] auto[0] 84 1 T82 1 T25 2 T76 1
auto[939524096:1073741823] auto[1] 11 1 T107 2 T386 1 T284 1
auto[1073741824:1207959551] auto[0] 57 1 T47 1 T63 1 T186 1
auto[1073741824:1207959551] auto[1] 11 1 T79 1 T194 1 T251 1
auto[1207959552:1342177279] auto[0] 80 1 T2 2 T17 1 T83 1
auto[1207959552:1342177279] auto[1] 8 1 T212 1 T312 1 T279 1
auto[1342177280:1476395007] auto[0] 88 1 T81 1 T83 1 T45 1
auto[1342177280:1476395007] auto[1] 10 1 T224 2 T107 1 T323 1
auto[1476395008:1610612735] auto[0] 74 1 T2 1 T25 1 T62 1
auto[1476395008:1610612735] auto[1] 4 1 T79 1 T251 1 T348 1
auto[1610612736:1744830463] auto[0] 81 1 T2 1 T24 2 T177 1
auto[1610612736:1744830463] auto[1] 14 1 T82 1 T194 1 T312 1
auto[1744830464:1879048191] auto[0] 74 1 T2 2 T82 1 T44 2
auto[1744830464:1879048191] auto[1] 6 1 T312 1 T279 1 T396 1
auto[1879048192:2013265919] auto[0] 104 1 T81 1 T120 1 T182 1
auto[1879048192:2013265919] auto[1] 7 1 T323 1 T212 1 T369 2
auto[2013265920:2147483647] auto[0] 83 1 T81 1 T83 1 T23 1
auto[2013265920:2147483647] auto[1] 7 1 T81 1 T289 1 T279 1
auto[2147483648:2281701375] auto[0] 75 1 T2 1 T22 2 T184 1
auto[2147483648:2281701375] auto[1] 7 1 T82 1 T107 1 T289 1
auto[2281701376:2415919103] auto[0] 82 1 T22 1 T81 1 T51 1
auto[2281701376:2415919103] auto[1] 4 1 T194 1 T323 1 T276 1
auto[2415919104:2550136831] auto[0] 77 1 T1 1 T22 1 T99 2
auto[2415919104:2550136831] auto[1] 9 1 T257 1 T276 1 T343 1
auto[2550136832:2684354559] auto[0] 71 1 T76 1 T40 1 T220 1
auto[2550136832:2684354559] auto[1] 10 1 T82 1 T224 1 T257 1
auto[2684354560:2818572287] auto[0] 82 1 T22 2 T24 1 T99 1
auto[2684354560:2818572287] auto[1] 3 1 T107 1 T399 1 T396 1
auto[2818572288:2952790015] auto[0] 76 1 T5 1 T81 1 T23 1
auto[2818572288:2952790015] auto[1] 11 1 T212 1 T289 2 T312 3
auto[2952790016:3087007743] auto[0] 61 1 T22 2 T82 1 T76 1
auto[2952790016:3087007743] auto[1] 11 1 T83 1 T194 1 T257 1
auto[3087007744:3221225471] auto[0] 87 1 T99 1 T192 1 T57 2
auto[3087007744:3221225471] auto[1] 6 1 T107 1 T259 1 T396 2
auto[3221225472:3355443199] auto[0] 76 1 T6 1 T57 2 T178 1
auto[3221225472:3355443199] auto[1] 7 1 T224 1 T257 1 T289 1
auto[3355443200:3489660927] auto[0] 92 1 T45 1 T44 1 T40 1
auto[3355443200:3489660927] auto[1] 11 1 T194 3 T212 1 T289 1
auto[3489660928:3623878655] auto[0] 72 1 T23 1 T177 1 T99 1
auto[3489660928:3623878655] auto[1] 6 1 T107 1 T272 1 T348 1
auto[3623878656:3758096383] auto[0] 70 1 T2 1 T17 1 T81 1
auto[3623878656:3758096383] auto[1] 4 1 T284 2 T389 1 T387 1
auto[3758096384:3892314111] auto[0] 69 1 T23 1 T215 1 T142 1
auto[3758096384:3892314111] auto[1] 7 1 T82 1 T194 1 T212 1
auto[3892314112:4026531839] auto[0] 77 1 T2 1 T22 1 T23 1
auto[3892314112:4026531839] auto[1] 8 1 T79 1 T388 1 T348 1
auto[4026531840:4160749567] auto[0] 79 1 T120 1 T82 1 T76 1
auto[4026531840:4160749567] auto[1] 11 1 T79 1 T107 2 T312 1
auto[4160749568:4294967295] auto[0] 85 1 T2 3 T17 1 T23 1
auto[4160749568:4294967295] auto[1] 8 1 T83 1 T194 1 T323 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%