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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5962 1 T1 4 T2 47 T5 2
auto[1] 250 1 T81 4 T82 4 T83 5


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 2472 1 T1 2 T2 15 T5 1
auto[134217728:268435455] 164 1 T2 1 T120 1 T83 1
auto[268435456:402653183] 125 1 T2 1 T184 1 T99 2
auto[402653184:536870911] 141 1 T17 1 T81 1 T23 1
auto[536870912:671088639] 137 1 T81 1 T23 1 T76 1
auto[671088640:805306367] 138 1 T1 1 T22 1 T81 1
auto[805306368:939524095] 103 1 T22 1 T82 1 T177 1
auto[939524096:1073741823] 103 1 T2 4 T82 1 T83 1
auto[1073741824:1207959551] 129 1 T2 1 T24 2 T184 1
auto[1207959552:1342177279] 117 1 T22 1 T81 1 T24 1
auto[1342177280:1476395007] 113 1 T81 1 T120 1 T23 1
auto[1476395008:1610612735] 123 1 T2 1 T22 1 T82 1
auto[1610612736:1744830463] 125 1 T81 1 T83 1 T184 1
auto[1744830464:1879048191] 100 1 T2 2 T184 1 T128 1
auto[1879048192:2013265919] 106 1 T2 1 T25 1 T194 1
auto[2013265920:2147483647] 101 1 T81 2 T23 1 T25 1
auto[2147483648:2281701375] 104 1 T2 1 T82 1 T24 1
auto[2281701376:2415919103] 114 1 T2 1 T17 1 T22 1
auto[2415919104:2550136831] 112 1 T2 2 T5 1 T81 1
auto[2550136832:2684354559] 122 1 T1 1 T2 2 T22 2
auto[2684354560:2818572287] 126 1 T2 2 T120 1 T177 1
auto[2818572288:2952790015] 130 1 T2 1 T17 1 T82 2
auto[2952790016:3087007743] 118 1 T2 1 T182 1 T99 1
auto[3087007744:3221225471] 108 1 T2 1 T22 1 T81 1
auto[3221225472:3355443199] 126 1 T2 1 T23 1 T24 2
auto[3355443200:3489660927] 147 1 T2 1 T22 2 T83 1
auto[3489660928:3623878655] 100 1 T82 1 T99 1 T215 1
auto[3623878656:3758096383] 111 1 T2 1 T17 1 T81 1
auto[3758096384:3892314111] 140 1 T2 3 T22 1 T83 2
auto[3892314112:4026531839] 116 1 T2 1 T81 1 T82 1
auto[4026531840:4160749567] 130 1 T2 3 T81 1 T23 1
auto[4160749568:4294967295] 111 1 T22 1 T24 1 T128 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 2467 1 T1 2 T2 15 T5 1
auto[0:134217727] auto[1] 5 1 T284 1 T214 2 T362 1
auto[134217728:268435455] auto[0] 151 1 T2 1 T120 1 T24 1
auto[134217728:268435455] auto[1] 13 1 T83 1 T79 1 T224 1
auto[268435456:402653183] auto[0] 121 1 T2 1 T184 1 T99 2
auto[268435456:402653183] auto[1] 4 1 T194 1 T395 1 T214 1
auto[402653184:536870911] auto[0] 132 1 T17 1 T81 1 T23 1
auto[402653184:536870911] auto[1] 9 1 T194 1 T323 1 T276 1
auto[536870912:671088639] auto[0] 130 1 T81 1 T23 1 T76 1
auto[536870912:671088639] auto[1] 7 1 T79 1 T276 1 T369 1
auto[671088640:805306367] auto[0] 129 1 T1 1 T22 1 T23 1
auto[671088640:805306367] auto[1] 9 1 T81 1 T82 1 T107 1
auto[805306368:939524095] auto[0] 98 1 T22 1 T82 1 T177 1
auto[805306368:939524095] auto[1] 5 1 T279 1 T395 1 T261 1
auto[939524096:1073741823] auto[0] 96 1 T2 4 T82 1 T23 1
auto[939524096:1073741823] auto[1] 7 1 T83 1 T194 1 T212 1
auto[1073741824:1207959551] auto[0] 119 1 T2 1 T24 2 T184 1
auto[1073741824:1207959551] auto[1] 10 1 T312 1 T276 1 T279 2
auto[1207959552:1342177279] auto[0] 109 1 T22 1 T81 1 T24 1
auto[1207959552:1342177279] auto[1] 8 1 T79 1 T272 1 T388 2
auto[1342177280:1476395007] auto[0] 107 1 T81 1 T120 1 T23 1
auto[1342177280:1476395007] auto[1] 6 1 T194 1 T107 2 T272 2
auto[1476395008:1610612735] auto[0] 120 1 T2 1 T22 1 T82 1
auto[1476395008:1610612735] auto[1] 3 1 T348 1 T396 1 T397 1
auto[1610612736:1744830463] auto[0] 121 1 T83 1 T184 1 T110 2
auto[1610612736:1744830463] auto[1] 4 1 T81 1 T272 1 T343 1
auto[1744830464:1879048191] auto[0] 89 1 T2 2 T184 1 T128 1
auto[1744830464:1879048191] auto[1] 11 1 T79 1 T323 1 T212 1
auto[1879048192:2013265919] auto[0] 97 1 T2 1 T25 1 T194 1
auto[1879048192:2013265919] auto[1] 9 1 T257 1 T212 1 T279 2
auto[2013265920:2147483647] auto[0] 99 1 T81 2 T23 1 T25 1
auto[2013265920:2147483647] auto[1] 2 1 T398 1 T387 1 - -
auto[2147483648:2281701375] auto[0] 103 1 T2 1 T82 1 T24 1
auto[2147483648:2281701375] auto[1] 1 1 T399 1 - - - -
auto[2281701376:2415919103] auto[0] 108 1 T2 1 T17 1 T22 1
auto[2281701376:2415919103] auto[1] 6 1 T79 1 T279 1 T388 1
auto[2415919104:2550136831] auto[0] 105 1 T2 2 T5 1 T177 1
auto[2415919104:2550136831] auto[1] 7 1 T81 1 T107 1 T272 1
auto[2550136832:2684354559] auto[0] 112 1 T1 1 T2 2 T22 2
auto[2550136832:2684354559] auto[1] 10 1 T83 1 T224 1 T386 1
auto[2684354560:2818572287] auto[0] 117 1 T2 2 T120 1 T177 1
auto[2684354560:2818572287] auto[1] 9 1 T79 1 T107 2 T279 1
auto[2818572288:2952790015] auto[0] 116 1 T2 1 T17 1 T44 2
auto[2818572288:2952790015] auto[1] 14 1 T82 2 T224 1 T279 1
auto[2952790016:3087007743] auto[0] 112 1 T2 1 T182 1 T99 1
auto[2952790016:3087007743] auto[1] 6 1 T272 1 T213 1 T386 1
auto[3087007744:3221225471] auto[0] 96 1 T2 1 T22 1 T24 1
auto[3087007744:3221225471] auto[1] 12 1 T81 1 T194 1 T224 1
auto[3221225472:3355443199] auto[0] 115 1 T2 1 T23 1 T24 2
auto[3221225472:3355443199] auto[1] 11 1 T194 1 T279 2 T272 1
auto[3355443200:3489660927] auto[0] 136 1 T2 1 T22 2 T25 1
auto[3355443200:3489660927] auto[1] 11 1 T83 1 T194 1 T312 1
auto[3489660928:3623878655] auto[0] 91 1 T99 1 T215 1 T51 1
auto[3489660928:3623878655] auto[1] 9 1 T82 1 T369 1 T213 1
auto[3623878656:3758096383] auto[0] 106 1 T2 1 T17 1 T81 1
auto[3623878656:3758096383] auto[1] 5 1 T194 1 T343 1 T261 1
auto[3758096384:3892314111] auto[0] 131 1 T2 3 T22 1 T83 1
auto[3758096384:3892314111] auto[1] 9 1 T83 1 T212 1 T388 2
auto[3892314112:4026531839] auto[0] 110 1 T2 1 T81 1 T82 1
auto[3892314112:4026531839] auto[1] 6 1 T212 1 T279 1 T369 1
auto[4026531840:4160749567] auto[0] 118 1 T2 3 T81 1 T23 1
auto[4026531840:4160749567] auto[1] 12 1 T257 2 T107 3 T276 2
auto[4160749568:4294967295] auto[0] 101 1 T22 1 T24 1 T128 1
auto[4160749568:4294967295] auto[1] 10 1 T194 1 T107 1 T276 1

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