Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.84	99.10	97.99	98.69	100.00	99.11	98.41	91.58

Total test records in report: 1007

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T101	/workspace/coverage/default/4.keymgr_sec_cm.2197574450			Feb 05 03:36:44 PM PST 24	Feb 05 03:37:14 PM PST 24	2940720577 ps
T1004	/workspace/coverage/default/48.keymgr_smoke.3606751468			Feb 05 03:40:20 PM PST 24	Feb 05 03:40:29 PM PST 24	241938039 ps
T308	/workspace/coverage/default/39.keymgr_kmac_rsp_err.4130429756			Feb 05 03:39:40 PM PST 24	Feb 05 03:39:51 PM PST 24	3101267676 ps
T1005	/workspace/coverage/default/11.keymgr_hwsw_invalid_input.2840772311			Feb 05 03:37:30 PM PST 24	Feb 05 03:37:36 PM PST 24	86896043 ps
T144	/workspace/coverage/default/37.keymgr_custom_cm.769514336			Feb 05 03:39:30 PM PST 24	Feb 05 03:39:36 PM PST 24	282532613 ps
T1006	/workspace/coverage/default/36.keymgr_alert_test.1753967003			Feb 05 03:39:32 PM PST 24	Feb 05 03:39:36 PM PST 24	66081865 ps
T1007	/workspace/coverage/default/41.keymgr_custom_cm.2563368133			Feb 05 03:40:01 PM PST 24	Feb 05 03:40:06 PM PST 24	588167678 ps

Test location	/workspace/coverage/default/34.keymgr_stress_all.3316253291
Short name	T2
Test name
Test status
Simulation time	12735954446 ps
CPU time	81.56 seconds
Started	Feb 05 03:39:15 PM PST 24
Finished	Feb 05 03:40:45 PM PST 24
Peak memory	216696 kb
Host	smart-d8bbb9fb-c767-4844-bf2d-ace2334840fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316253291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3316253291
Directory	/workspace/34.keymgr_stress_all/latest

Test location	/workspace/coverage/default/42.keymgr_stress_all.798344658
Short name	T44
Test name
Test status
Simulation time	2076268258 ps
CPU time	43.63 seconds
Started	Feb 05 03:39:50 PM PST 24
Finished	Feb 05 03:40:34 PM PST 24
Peak memory	222412 kb
Host	smart-14fa9428-ae68-437d-9691-4fb8fb63a45f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798344658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.798344658
Directory	/workspace/42.keymgr_stress_all/latest

Test location	/workspace/coverage/default/1.keymgr_sec_cm.1651509521
Short name	T11
Test name
Test status
Simulation time	1735513202 ps
CPU time	13.05 seconds
Started	Feb 05 03:36:18 PM PST 24
Finished	Feb 05 03:36:41 PM PST 24
Peak memory	231764 kb
Host	smart-9b34e15a-8ac4-41fa-9011-b47d8470d324
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651509521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1651509521
Directory	/workspace/1.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/28.keymgr_stress_all.2498523498
Short name	T41
Test name
Test status
Simulation time	3023946500 ps
CPU time	72.69 seconds
Started	Feb 05 03:38:58 PM PST 24
Finished	Feb 05 03:40:14 PM PST 24
Peak memory	215036 kb
Host	smart-9bdfc52f-4b4f-4f90-9868-47c5e34b0372
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498523498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2498523498
Directory	/workspace/28.keymgr_stress_all/latest

Test location	/workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.120029084
Short name	T77
Test name
Test status
Simulation time	615801667 ps
CPU time	2.67 seconds
Started	Feb 05 03:39:26 PM PST 24
Finished	Feb 05 03:39:30 PM PST 24
Peak memory	217824 kb
Host	smart-58ca7ae9-77db-49ac-b456-0287c94a1066
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120029084 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.120029084
Directory	/workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.keymgr_stress_all.3974877670
Short name	T197
Test name
Test status
Simulation time	4553665392 ps
CPU time	51.39 seconds
Started	Feb 05 03:37:37 PM PST 24
Finished	Feb 05 03:38:32 PM PST 24
Peak memory	214964 kb
Host	smart-bfecae59-851c-4bc6-b09f-2a7b678a5f69
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974877670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3974877670
Directory	/workspace/12.keymgr_stress_all/latest

Test location	/workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3551590767
Short name	T110
Test name
Test status
Simulation time	491101527 ps
CPU time	7.44 seconds
Started	Feb 05 03:37:37 PM PST 24
Finished	Feb 05 03:37:47 PM PST 24
Peak memory	222588 kb
Host	smart-e7a32273-6a8d-4c57-a978-9e5e967e7286
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551590767 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3551590767
Directory	/workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.keymgr_stress_all.1727550473
Short name	T57
Test name
Test status
Simulation time	13708425533 ps
CPU time	415.77 seconds
Started	Feb 05 03:36:46 PM PST 24
Finished	Feb 05 03:43:48 PM PST 24
Peak memory	221056 kb
Host	smart-9ba2985c-f8e1-4627-9aa2-0575133dadcf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727550473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1727550473
Directory	/workspace/4.keymgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3666431623
Short name	T111
Test name
Test status
Simulation time	342053418 ps
CPU time	5.74 seconds
Started	Feb 05 01:15:25 PM PST 24
Finished	Feb 05 01:15:39 PM PST 24
Peak memory	213692 kb
Host	smart-11ccad65-57d7-4972-b01e-fb0c829c30d7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666431623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. keymgr_shadow_reg_errors_with_csr_rw.3666431623
Directory	/workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/34.keymgr_cfg_regwen.270685987
Short name	T107
Test name
Test status
Simulation time	5975461765 ps
CPU time	78.9 seconds
Started	Feb 05 03:39:19 PM PST 24
Finished	Feb 05 03:40:45 PM PST 24
Peak memory	214848 kb
Host	smart-3d067725-3fc0-46ac-ab2a-ab2bb45f9427
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=270685987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.270685987
Directory	/workspace/34.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/17.keymgr_custom_cm.1737661277
Short name	T8
Test name
Test status
Simulation time	921950563 ps
CPU time	4.1 seconds
Started	Feb 05 03:38:01 PM PST 24
Finished	Feb 05 03:38:17 PM PST 24
Peak memory	222852 kb
Host	smart-0313a33e-4658-4f1a-aba7-1ea3553309c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1737661277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1737661277
Directory	/workspace/17.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/20.keymgr_lc_disable.2388998079
Short name	T43
Test name
Test status
Simulation time	98287864 ps
CPU time	3.19 seconds
Started	Feb 05 03:38:12 PM PST 24
Finished	Feb 05 03:38:24 PM PST 24
Peak memory	214368 kb
Host	smart-8fc803ab-e06b-4fbf-97f6-1c6ad2112379
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388998079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2388998079
Directory	/workspace/20.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/44.keymgr_kmac_rsp_err.2041131934
Short name	T25
Test name
Test status
Simulation time	8879678516 ps
CPU time	71.74 seconds
Started	Feb 05 03:39:56 PM PST 24
Finished	Feb 05 03:41:12 PM PST 24
Peak memory	231708 kb
Host	smart-bd7125d5-09b5-4302-a202-66f3bd1f7155
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041131934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2041131934
Directory	/workspace/44.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/13.keymgr_cfg_regwen.170585851
Short name	T194
Test name
Test status
Simulation time	756006983 ps
CPU time	10.69 seconds
Started	Feb 05 03:37:36 PM PST 24
Finished	Feb 05 03:37:50 PM PST 24
Peak memory	215392 kb
Host	smart-f07b572d-fcfd-457f-ace5-31aad28d10e5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=170585851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.170585851
Directory	/workspace/13.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/6.keymgr_stress_all.3760709068
Short name	T7
Test name
Test status
Simulation time	44858434101 ps
CPU time	628.94 seconds
Started	Feb 05 03:36:54 PM PST 24
Finished	Feb 05 03:47:26 PM PST 24
Peak memory	230748 kb
Host	smart-b0123552-d5bb-48b9-8195-408d2e929d62
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760709068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3760709068
Directory	/workspace/6.keymgr_stress_all/latest

Test location	/workspace/coverage/default/35.keymgr_cfg_regwen.3599727929
Short name	T388
Test name
Test status
Simulation time	5698225925 ps
CPU time	69.56 seconds
Started	Feb 05 03:39:25 PM PST 24
Finished	Feb 05 03:40:37 PM PST 24
Peak memory	214376 kb
Host	smart-b1fc3b40-2eef-4a30-946e-2df8ab55c292
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3599727929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3599727929
Directory	/workspace/35.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/6.keymgr_hwsw_invalid_input.648826983
Short name	T23
Test name
Test status
Simulation time	287660563 ps
CPU time	7.38 seconds
Started	Feb 05 03:36:52 PM PST 24
Finished	Feb 05 03:37:04 PM PST 24
Peak memory	214288 kb
Host	smart-26677e8e-b34f-4094-a58a-67e4a9a7b752
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648826983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.648826983
Directory	/workspace/6.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/18.keymgr_cfg_regwen.548264235
Short name	T362
Test name
Test status
Simulation time	195513918 ps
CPU time	11.09 seconds
Started	Feb 05 03:38:04 PM PST 24
Finished	Feb 05 03:38:25 PM PST 24
Peak memory	214356 kb
Host	smart-9b6a5eb5-2dc7-470a-8050-02c15d184c87
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=548264235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.548264235
Directory	/workspace/18.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.345122431
Short name	T129
Test name
Test status
Simulation time	123688298 ps
CPU time	6.36 seconds
Started	Feb 05 01:15:42 PM PST 24
Finished	Feb 05 01:15:50 PM PST 24
Peak memory	209064 kb
Host	smart-81f7099a-7720-43d4-bca8-fd27bb10e760
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345122431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err .345122431
Directory	/workspace/16.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/11.keymgr_stress_all.187154677
Short name	T42
Test name
Test status
Simulation time	20774063410 ps
CPU time	112.3 seconds
Started	Feb 05 03:37:41 PM PST 24
Finished	Feb 05 03:39:35 PM PST 24
Peak memory	216064 kb
Host	smart-0dd06726-572b-4dd9-b6a6-2b4247393988
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187154677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.187154677
Directory	/workspace/11.keymgr_stress_all/latest

Test location	/workspace/coverage/default/32.keymgr_cfg_regwen.4141311113
Short name	T279
Test name
Test status
Simulation time	1100587573 ps
CPU time	16.12 seconds
Started	Feb 05 03:39:14 PM PST 24
Finished	Feb 05 03:39:36 PM PST 24
Peak memory	214316 kb
Host	smart-95abd9aa-cc08-4cb7-afb4-d30d1c89a31a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4141311113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.4141311113
Directory	/workspace/32.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3276791449
Short name	T116
Test name
Test status
Simulation time	343027548 ps
CPU time	6.67 seconds
Started	Feb 05 01:15:07 PM PST 24
Finished	Feb 05 01:15:15 PM PST 24
Peak memory	221876 kb
Host	smart-7e838143-19ed-4a48-9bb6-ac8de7ed2bba
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276791449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado w_reg_errors.3276791449
Directory	/workspace/1.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/14.keymgr_cfg_regwen.4159655148
Short name	T81
Test name
Test status
Simulation time	240840464 ps
CPU time	7.48 seconds
Started	Feb 05 03:37:46 PM PST 24
Finished	Feb 05 03:38:01 PM PST 24
Peak memory	215384 kb
Host	smart-f65982d3-a09a-4c89-9d95-9bacb5e7760f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4159655148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.4159655148
Directory	/workspace/14.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/40.keymgr_custom_cm.139253238
Short name	T36
Test name
Test status
Simulation time	689259686 ps
CPU time	15.76 seconds
Started	Feb 05 03:39:36 PM PST 24
Finished	Feb 05 03:39:54 PM PST 24
Peak memory	220844 kb
Host	smart-b3c5f22c-5cfa-4fa9-b845-bf4197d1f4e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=139253238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.139253238
Directory	/workspace/40.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/24.keymgr_hwsw_invalid_input.2497506365
Short name	T94
Test name
Test status
Simulation time	124389737 ps
CPU time	2.57 seconds
Started	Feb 05 03:38:31 PM PST 24
Finished	Feb 05 03:38:39 PM PST 24
Peak memory	208316 kb
Host	smart-e38baa04-2c94-4ae4-9475-fc31eea87efd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497506365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2497506365
Directory	/workspace/24.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/2.keymgr_cfg_regwen.1059114477
Short name	T214
Test name
Test status
Simulation time	1107991621 ps
CPU time	10.12 seconds
Started	Feb 05 03:36:21 PM PST 24
Finished	Feb 05 03:36:49 PM PST 24
Peak memory	215680 kb
Host	smart-a5883608-854e-47cf-98c2-de619501a1fa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1059114477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1059114477
Directory	/workspace/2.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/38.keymgr_custom_cm.44391376
Short name	T29
Test name
Test status
Simulation time	191241595 ps
CPU time	7.85 seconds
Started	Feb 05 03:39:36 PM PST 24
Finished	Feb 05 03:39:47 PM PST 24
Peak memory	209616 kb
Host	smart-45fc4fc4-3970-42ff-a37b-263c3621c8cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44391376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.44391376
Directory	/workspace/38.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/21.keymgr_hwsw_invalid_input.683181318
Short name	T273
Test name
Test status
Simulation time	1125055221 ps
CPU time	6.17 seconds
Started	Feb 05 03:38:18 PM PST 24
Finished	Feb 05 03:38:33 PM PST 24
Peak memory	214312 kb
Host	smart-f5f5e24a-3b0f-442b-a8e9-ce12b7e8f84f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683181318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.683181318
Directory	/workspace/21.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/38.keymgr_cfg_regwen.4141745880
Short name	T224
Test name
Test status
Simulation time	54457445 ps
CPU time	3.78 seconds
Started	Feb 05 03:39:29 PM PST 24
Finished	Feb 05 03:39:35 PM PST 24
Peak memory	214544 kb
Host	smart-a41b7d97-9da6-4031-8558-7f60cfaf1fe8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4141745880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4141745880
Directory	/workspace/38.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/5.keymgr_custom_cm.3223197540
Short name	T58
Test name
Test status
Simulation time	67190999 ps
CPU time	3.67 seconds
Started	Feb 05 03:36:54 PM PST 24
Finished	Feb 05 03:37:01 PM PST 24
Peak memory	222532 kb
Host	smart-2a923950-e62d-41ee-8b25-ccd5a82f2292
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223197540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3223197540
Directory	/workspace/5.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/1.keymgr_stress_all.2187026431
Short name	T277
Test name
Test status
Simulation time	5614804227 ps
CPU time	58.51 seconds
Started	Feb 05 03:36:21 PM PST 24
Finished	Feb 05 03:37:37 PM PST 24
Peak memory	217036 kb
Host	smart-ec31fdf6-ff27-40b9-9a77-77723cdb46ac
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187026431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2187026431
Directory	/workspace/1.keymgr_stress_all/latest

Test location	/workspace/coverage/default/18.keymgr_kmac_rsp_err.661495335
Short name	T231
Test name
Test status
Simulation time	65085829 ps
CPU time	4.26 seconds
Started	Feb 05 03:38:06 PM PST 24
Finished	Feb 05 03:38:19 PM PST 24
Peak memory	210084 kb
Host	smart-ee260370-5576-4912-980d-cd0d05ba22dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=661495335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.661495335
Directory	/workspace/18.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/45.keymgr_custom_cm.3885326616
Short name	T9
Test name
Test status
Simulation time	121261219 ps
CPU time	5.2 seconds
Started	Feb 05 03:40:13 PM PST 24
Finished	Feb 05 03:40:22 PM PST 24
Peak memory	211112 kb
Host	smart-57db7823-1f85-4d61-aaa1-c853fe9210b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885326616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3885326616
Directory	/workspace/45.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/0.keymgr_cfg_regwen.520915286
Short name	T272
Test name
Test status
Simulation time	1481452655 ps
CPU time	13.37 seconds
Started	Feb 05 03:36:17 PM PST 24
Finished	Feb 05 03:36:41 PM PST 24
Peak memory	222364 kb
Host	smart-e7b76891-ff31-4072-884b-58b23e268e28
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=520915286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.520915286
Directory	/workspace/0.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/20.keymgr_stress_all.2058062790
Short name	T202
Test name
Test status
Simulation time	709311781 ps
CPU time	32.74 seconds
Started	Feb 05 03:38:18 PM PST 24
Finished	Feb 05 03:39:01 PM PST 24
Peak memory	216376 kb
Host	smart-78d1ddb2-ec9d-425d-9ac5-2fbffb3c8ce3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058062790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2058062790
Directory	/workspace/20.keymgr_stress_all/latest

Test location	/workspace/coverage/default/40.keymgr_cfg_regwen.2087082814
Short name	T82
Test name
Test status
Simulation time	240940854 ps
CPU time	4.21 seconds
Started	Feb 05 03:39:46 PM PST 24
Finished	Feb 05 03:39:51 PM PST 24
Peak memory	214248 kb
Host	smart-32235067-8dca-4086-a51d-2a1bdc8efe6a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2087082814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2087082814
Directory	/workspace/40.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/28.keymgr_kmac_rsp_err.2872926420
Short name	T248
Test name
Test status
Simulation time	40393877 ps
CPU time	2.76 seconds
Started	Feb 05 03:38:51 PM PST 24
Finished	Feb 05 03:38:55 PM PST 24
Peak memory	209092 kb
Host	smart-f4c3b657-d7fd-47eb-bc5a-c0a284b956de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872926420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2872926420
Directory	/workspace/28.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2939581253
Short name	T225
Test name
Test status
Simulation time	145995708 ps
CPU time	8.37 seconds
Started	Feb 05 03:39:55 PM PST 24
Finished	Feb 05 03:40:05 PM PST 24
Peak memory	220564 kb
Host	smart-f80e8b36-e340-4f51-9cb3-0b9a058822e3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939581253 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2939581253
Directory	/workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.keymgr_alert_test.4043450738
Short name	T551
Test name
Test status
Simulation time	34358412 ps
CPU time	0.83 seconds
Started	Feb 05 03:37:46 PM PST 24
Finished	Feb 05 03:37:55 PM PST 24
Peak memory	205788 kb
Host	smart-c81f2f07-2565-4373-a1ec-d492f13837d7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043450738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4043450738
Directory	/workspace/14.keymgr_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3228541635
Short name	T156
Test name
Test status
Simulation time	135779437 ps
CPU time	5 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:38 PM PST 24
Peak memory	208844 kb
Host	smart-dd6a8da5-cfd6-47e6-84fc-f4315c8b1f3c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228541635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err .3228541635
Directory	/workspace/5.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/31.keymgr_cfg_regwen.2081602942
Short name	T397
Test name
Test status
Simulation time	7457719253 ps
CPU time	113.6 seconds
Started	Feb 05 03:39:06 PM PST 24
Finished	Feb 05 03:41:08 PM PST 24
Peak memory	221096 kb
Host	smart-18c2c80a-7d12-4e51-90e6-26dbf9de61f8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2081602942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2081602942
Directory	/workspace/31.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/40.keymgr_kmac_rsp_err.2110280011
Short name	T218
Test name
Test status
Simulation time	103922693 ps
CPU time	5.37 seconds
Started	Feb 05 03:39:43 PM PST 24
Finished	Feb 05 03:39:49 PM PST 24
Peak memory	214172 kb
Host	smart-edab1682-d62c-4cdc-b93d-4cb5197f8293
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110280011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2110280011
Directory	/workspace/40.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/7.keymgr_stress_all.3151419630
Short name	T264
Test name
Test status
Simulation time	16324385377 ps
CPU time	306.9 seconds
Started	Feb 05 03:37:12 PM PST 24
Finished	Feb 05 03:42:27 PM PST 24
Peak memory	218804 kb
Host	smart-7b1a6441-a31b-4ce5-95c3-0cb4c800f767
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151419630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3151419630
Directory	/workspace/7.keymgr_stress_all/latest

Test location	/workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1051799787
Short name	T114
Test name
Test status
Simulation time	1094558807 ps
CPU time	8.49 seconds
Started	Feb 05 03:36:54 PM PST 24
Finished	Feb 05 03:37:06 PM PST 24
Peak memory	222640 kb
Host	smart-9514a077-71f9-4ab6-8fd4-bb2d4cd00dd1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051799787 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1051799787
Directory	/workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.keymgr_custom_cm.2803412438
Short name	T141
Test name
Test status
Simulation time	118651708 ps
CPU time	3.03 seconds
Started	Feb 05 03:39:59 PM PST 24
Finished	Feb 05 03:40:06 PM PST 24
Peak memory	222876 kb
Host	smart-6fcc08e9-7599-4522-a118-28ed73520020
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803412438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2803412438
Directory	/workspace/44.keymgr_custom_cm/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.87516911
Short name	T162
Test name
Test status
Simulation time	250563689 ps
CPU time	8.2 seconds
Started	Feb 05 01:15:30 PM PST 24
Finished	Feb 05 01:15:42 PM PST 24
Peak memory	213744 kb
Host	smart-7e5906ba-efe7-4b6e-946d-e25a55c3c5d4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87516911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.87516911
Directory	/workspace/14.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/10.keymgr_custom_cm.1522324184
Short name	T143
Test name
Test status
Simulation time	1191109210 ps
CPU time	5.53 seconds
Started	Feb 05 03:37:35 PM PST 24
Finished	Feb 05 03:37:44 PM PST 24
Peak memory	217436 kb
Host	smart-cdf264ad-8496-43ca-ab19-88182a498733
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1522324184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1522324184
Directory	/workspace/10.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/24.keymgr_custom_cm.2527457106
Short name	T140
Test name
Test status
Simulation time	80400306 ps
CPU time	3.33 seconds
Started	Feb 05 03:38:32 PM PST 24
Finished	Feb 05 03:38:40 PM PST 24
Peak memory	217828 kb
Host	smart-ef43a7b0-051c-4822-8ef7-a0eae9de6138
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527457106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2527457106
Directory	/workspace/24.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/37.keymgr_custom_cm.769514336
Short name	T144
Test name
Test status
Simulation time	282532613 ps
CPU time	2.56 seconds
Started	Feb 05 03:39:30 PM PST 24
Finished	Feb 05 03:39:36 PM PST 24
Peak memory	218188 kb
Host	smart-fbbe775a-0eb4-445d-b14d-095ca54955e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=769514336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.769514336
Directory	/workspace/37.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_aes.1682945045
Short name	T237
Test name
Test status
Simulation time	124625252 ps
CPU time	4.05 seconds
Started	Feb 05 03:37:36 PM PST 24
Finished	Feb 05 03:37:43 PM PST 24
Peak memory	208448 kb
Host	smart-2433969e-341a-4a29-900c-5be24a0e7454
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682945045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1682945045
Directory	/workspace/12.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/13.keymgr_kmac_rsp_err.1121469318
Short name	T249
Test name
Test status
Simulation time	2640871668 ps
CPU time	97.79 seconds
Started	Feb 05 03:37:44 PM PST 24
Finished	Feb 05 03:39:24 PM PST 24
Peak memory	226020 kb
Host	smart-6d6f3048-9107-401b-b299-ff08635cafdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121469318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1121469318
Directory	/workspace/13.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/49.keymgr_stress_all.515374148
Short name	T301
Test name
Test status
Simulation time	434510158 ps
CPU time	21.88 seconds
Started	Feb 05 03:40:21 PM PST 24
Finished	Feb 05 03:40:44 PM PST 24
Peak memory	215908 kb
Host	smart-3743860b-c8b2-4857-86ca-00ccc3fd6158
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515374148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.515374148
Directory	/workspace/49.keymgr_stress_all/latest

Test location	/workspace/coverage/default/7.keymgr_kmac_rsp_err.615246888
Short name	T47
Test name
Test status
Simulation time	99038864 ps
CPU time	3.34 seconds
Started	Feb 05 03:37:08 PM PST 24
Finished	Feb 05 03:37:12 PM PST 24
Peak memory	211092 kb
Host	smart-0abd4e99-a7b9-44d3-a5f7-d1d6cb67a082
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=615246888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.615246888
Directory	/workspace/7.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2874607329
Short name	T149
Test name
Test status
Simulation time	453833509 ps
CPU time	6.38 seconds
Started	Feb 05 01:15:45 PM PST 24
Finished	Feb 05 01:15:53 PM PST 24
Peak memory	213564 kb
Host	smart-abd247c2-2b12-47b7-9860-52f224d5740b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874607329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er r.2874607329
Directory	/workspace/15.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3865062316
Short name	T152
Test name
Test status
Simulation time	219629473 ps
CPU time	6.91 seconds
Started	Feb 05 01:15:33 PM PST 24
Finished	Feb 05 01:15:46 PM PST 24
Peak memory	208628 kb
Host	smart-9f5d27b3-af33-4d2e-8d03-be0766e97bbf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865062316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er r.3865062316
Directory	/workspace/17.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1639174125
Short name	T160
Test name
Test status
Simulation time	2958963581 ps
CPU time	8.77 seconds
Started	Feb 05 01:15:40 PM PST 24
Finished	Feb 05 01:15:52 PM PST 24
Peak memory	213612 kb
Host	smart-93254857-05ee-404e-89b6-2fe5b092e26e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639174125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err .1639174125
Directory	/workspace/7.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/14.keymgr_custom_cm.2865544476
Short name	T21
Test name
Test status
Simulation time	579702530 ps
CPU time	6.79 seconds
Started	Feb 05 03:37:44 PM PST 24
Finished	Feb 05 03:37:55 PM PST 24
Peak memory	222796 kb
Host	smart-7fe56bec-5296-4649-b3c2-2f2fe6ad86f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865544476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2865544476
Directory	/workspace/14.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/31.keymgr_custom_cm.3290058771
Short name	T142
Test name
Test status
Simulation time	493297681 ps
CPU time	6 seconds
Started	Feb 05 03:39:05 PM PST 24
Finished	Feb 05 03:39:20 PM PST 24
Peak memory	222776 kb
Host	smart-5a7d54f3-b433-4708-b7e3-924a0d1d1698
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3290058771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3290058771
Directory	/workspace/31.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/1.keymgr_cfg_regwen.3793046159
Short name	T79
Test name
Test status
Simulation time	2047531460 ps
CPU time	14.32 seconds
Started	Feb 05 03:36:15 PM PST 24
Finished	Feb 05 03:36:41 PM PST 24
Peak memory	214812 kb
Host	smart-39bfac22-802d-4415-aa9a-c5806f9d16d2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3793046159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3793046159
Directory	/workspace/1.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/17.keymgr_cfg_regwen.3037938026
Short name	T318
Test name
Test status
Simulation time	461250036 ps
CPU time	25.57 seconds
Started	Feb 05 03:37:59 PM PST 24
Finished	Feb 05 03:38:38 PM PST 24
Peak memory	214836 kb
Host	smart-31c6e102-2288-42fb-a7cb-9ef19e613b36
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3037938026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3037938026
Directory	/workspace/17.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/17.keymgr_stress_all.3327366775
Short name	T894
Test name
Test status
Simulation time	9801474996 ps
CPU time	95.92 seconds
Started	Feb 05 03:37:55 PM PST 24
Finished	Feb 05 03:39:34 PM PST 24
Peak memory	215904 kb
Host	smart-dee14c26-acf1-4ed2-a60a-b7a53968652e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327366775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3327366775
Directory	/workspace/17.keymgr_stress_all/latest

Test location	/workspace/coverage/default/36.keymgr_hwsw_invalid_input.293544276
Short name	T370
Test name
Test status
Simulation time	561469902 ps
CPU time	6.89 seconds
Started	Feb 05 03:39:33 PM PST 24
Finished	Feb 05 03:39:44 PM PST 24
Peak memory	219148 kb
Host	smart-444d128d-31cc-4688-8aa5-17b81130d0f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=293544276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.293544276
Directory	/workspace/36.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/47.keymgr_cfg_regwen.2814965880
Short name	T389
Test name
Test status
Simulation time	110782144 ps
CPU time	4.07 seconds
Started	Feb 05 03:40:14 PM PST 24
Finished	Feb 05 03:40:22 PM PST 24
Peak memory	214472 kb
Host	smart-d9075f9d-bae7-4642-810d-4d6793ac2bcd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2814965880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2814965880
Directory	/workspace/47.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/19.keymgr_custom_cm.3429114756
Short name	T145
Test name
Test status
Simulation time	464165332 ps
CPU time	12.72 seconds
Started	Feb 05 03:38:18 PM PST 24
Finished	Feb 05 03:38:40 PM PST 24
Peak memory	215696 kb
Host	smart-bed1a48e-5d18-4caa-9b0c-af832e3399d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429114756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3429114756
Directory	/workspace/19.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/3.keymgr_custom_cm.183111529
Short name	T146
Test name
Test status
Simulation time	1247583241 ps
CPU time	17.77 seconds
Started	Feb 05 03:36:34 PM PST 24
Finished	Feb 05 03:37:06 PM PST 24
Peak memory	218564 kb
Host	smart-aa804890-30ec-4045-a3d2-ab517466e50e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183111529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.183111529
Directory	/workspace/3.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/36.keymgr_custom_cm.2260685311
Short name	T139
Test name
Test status
Simulation time	283405663 ps
CPU time	5.45 seconds
Started	Feb 05 03:39:27 PM PST 24
Finished	Feb 05 03:39:35 PM PST 24
Peak memory	215072 kb
Host	smart-1cef17c8-a8da-4c09-b304-ef3e5b99b031
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2260685311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2260685311
Directory	/workspace/36.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/0.keymgr_sw_invalid_input.1170086171
Short name	T355
Test name
Test status
Simulation time	3635964214 ps
CPU time	6.04 seconds
Started	Feb 05 03:36:15 PM PST 24
Finished	Feb 05 03:36:32 PM PST 24
Peak memory	209440 kb
Host	smart-11962e62-30c6-41d6-89b2-38b5ba48b7d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170086171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1170086171
Directory	/workspace/0.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/1.keymgr_hwsw_invalid_input.1505429768
Short name	T292
Test name
Test status
Simulation time	981721878 ps
CPU time	7.1 seconds
Started	Feb 05 03:36:17 PM PST 24
Finished	Feb 05 03:36:35 PM PST 24
Peak memory	219444 kb
Host	smart-12a8141c-9668-4806-a0c3-0c3c56d4fdc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505429768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1505429768
Directory	/workspace/1.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/1.keymgr_sync_async_fault_cross.3850211271
Short name	T594
Test name
Test status
Simulation time	513788654 ps
CPU time	8.47 seconds
Started	Feb 05 03:36:18 PM PST 24
Finished	Feb 05 03:36:36 PM PST 24
Peak memory	211040 kb
Host	smart-13710213-542b-43df-bf4e-8f47091cc0d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3850211271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3850211271
Directory	/workspace/1.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/12.keymgr_kmac_rsp_err.833174601
Short name	T307
Test name
Test status
Simulation time	736328016 ps
CPU time	4.83 seconds
Started	Feb 05 03:37:38 PM PST 24
Finished	Feb 05 03:37:45 PM PST 24
Peak memory	210576 kb
Host	smart-20bff986-420f-4b07-b1b4-1f1a88a18800
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833174601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.833174601
Directory	/workspace/12.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/25.keymgr_random.1337763058
Short name	T305
Test name
Test status
Simulation time	118098624 ps
CPU time	4 seconds
Started	Feb 05 03:38:34 PM PST 24
Finished	Feb 05 03:38:42 PM PST 24
Peak memory	207436 kb
Host	smart-cd8ad33c-35fa-4000-aa4e-440a56fab496
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1337763058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1337763058
Directory	/workspace/25.keymgr_random/latest

Test location	/workspace/coverage/default/26.keymgr_cfg_regwen.2920339254
Short name	T312
Test name
Test status
Simulation time	289547537 ps
CPU time	9.43 seconds
Started	Feb 05 03:38:43 PM PST 24
Finished	Feb 05 03:38:54 PM PST 24
Peak memory	214872 kb
Host	smart-2462812f-df28-4f84-ae3d-f7ff3be5c518
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2920339254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2920339254
Directory	/workspace/26.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_kmac.3524493275
Short name	T567
Test name
Test status
Simulation time	98639923 ps
CPU time	2.81 seconds
Started	Feb 05 03:38:59 PM PST 24
Finished	Feb 05 03:39:04 PM PST 24
Peak memory	206884 kb
Host	smart-839455bb-d517-475f-947e-f0dc1a8c72e5
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524493275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3524493275
Directory	/workspace/29.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/3.keymgr_stress_all.4180025077
Short name	T207
Test name
Test status
Simulation time	590143757 ps
CPU time	28.81 seconds
Started	Feb 05 03:36:33 PM PST 24
Finished	Feb 05 03:37:17 PM PST 24
Peak memory	222568 kb
Host	smart-497f2285-d75e-4b7d-9975-5a53ae1be4c6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180025077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.4180025077
Directory	/workspace/3.keymgr_stress_all/latest

Test location	/workspace/coverage/default/30.keymgr_kmac_rsp_err.3573321498
Short name	T95
Test name
Test status
Simulation time	214658678 ps
CPU time	4.22 seconds
Started	Feb 05 03:39:03 PM PST 24
Finished	Feb 05 03:39:11 PM PST 24
Peak memory	214188 kb
Host	smart-7788208a-2a26-42fc-aad5-630c9fa415ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3573321498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3573321498
Directory	/workspace/30.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/31.keymgr_kmac_rsp_err.3328529566
Short name	T246
Test name
Test status
Simulation time	553516256 ps
CPU time	5.69 seconds
Started	Feb 05 03:39:09 PM PST 24
Finished	Feb 05 03:39:22 PM PST 24
Peak memory	222320 kb
Host	smart-f7510177-494d-4c3a-a7b8-ff9d4b4612ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328529566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3328529566
Directory	/workspace/31.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/44.keymgr_hwsw_invalid_input.248325795
Short name	T84
Test name
Test status
Simulation time	2144629713 ps
CPU time	17.02 seconds
Started	Feb 05 03:39:56 PM PST 24
Finished	Feb 05 03:40:17 PM PST 24
Peak memory	214236 kb
Host	smart-608b55ed-f8be-4ab6-9ed1-fbe3fa68f3a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=248325795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.248325795
Directory	/workspace/44.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/8.keymgr_stress_all.816589150
Short name	T328
Test name
Test status
Simulation time	2967166603 ps
CPU time	59.29 seconds
Started	Feb 05 03:37:13 PM PST 24
Finished	Feb 05 03:38:20 PM PST 24
Peak memory	214928 kb
Host	smart-3c657782-edeb-4083-a645-3bd61be9520f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816589150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.816589150
Directory	/workspace/8.keymgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.984413019
Short name	T151
Test name
Test status
Simulation time	229925827 ps
CPU time	9.22 seconds
Started	Feb 05 01:15:03 PM PST 24
Finished	Feb 05 01:15:14 PM PST 24
Peak memory	213668 kb
Host	smart-0fba70d6-f39a-4246-8a6e-73be8f7f8a34
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984413019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err. 984413019
Directory	/workspace/0.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2192211521
Short name	T123
Test name
Test status
Simulation time	226783947 ps
CPU time	4.88 seconds
Started	Feb 05 01:15:24 PM PST 24
Finished	Feb 05 01:15:29 PM PST 24
Peak memory	213444 kb
Host	smart-15c3dc60-49a5-4a86-8888-c9b53ce38df1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192211521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err .2192211521
Directory	/workspace/3.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2251279528
Short name	T150
Test name
Test status
Simulation time	224973055 ps
CPU time	9.21 seconds
Started	Feb 05 01:15:28 PM PST 24
Finished	Feb 05 01:15:42 PM PST 24
Peak memory	208964 kb
Host	smart-4592dfbb-f87e-4348-a187-f88c06101f4c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251279528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err .2251279528
Directory	/workspace/8.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.keymgr_sec_cm.2987378283
Short name	T12
Test name
Test status
Simulation time	35342025060 ps
CPU time	599.51 seconds
Started	Feb 05 03:36:10 PM PST 24
Finished	Feb 05 03:46:17 PM PST 24
Peak memory	379736 kb
Host	smart-296b409b-c451-4082-b34f-535fef8600ff
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987378283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2987378283
Directory	/workspace/0.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/10.keymgr_sync_async_fault_cross.3696481403
Short name	T158
Test name
Test status
Simulation time	55467505 ps
CPU time	2.81 seconds
Started	Feb 05 03:37:32 PM PST 24
Finished	Feb 05 03:37:36 PM PST 24
Peak memory	210196 kb
Host	smart-d178a831-153e-4f8f-b938-04ba246629d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696481403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3696481403
Directory	/workspace/10.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/29.keymgr_custom_cm.3107629786
Short name	T147
Test name
Test status
Simulation time	74485865 ps
CPU time	3.86 seconds
Started	Feb 05 03:38:59 PM PST 24
Finished	Feb 05 03:39:06 PM PST 24
Peak memory	218420 kb
Host	smart-bdeb1407-1833-4e30-864b-384db56cf8a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3107629786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3107629786
Directory	/workspace/29.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/10.keymgr_direct_to_disabled.3727224290
Short name	T306
Test name
Test status
Simulation time	20607488 ps
CPU time	1.35 seconds
Started	Feb 05 03:37:29 PM PST 24
Finished	Feb 05 03:37:31 PM PST 24
Peak memory	207064 kb
Host	smart-fd5ff81e-7c60-4d3d-8577-66deda0ffcc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727224290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3727224290
Directory	/workspace/10.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/11.keymgr_kmac_rsp_err.932008223
Short name	T230
Test name
Test status
Simulation time	59914136 ps
CPU time	2.44 seconds
Started	Feb 05 03:37:31 PM PST 24
Finished	Feb 05 03:37:35 PM PST 24
Peak memory	210396 kb
Host	smart-c244892e-8285-4282-8a18-c31c6be58a21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932008223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.932008223
Directory	/workspace/11.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/13.keymgr_sync_async_fault_cross.3038152139
Short name	T560
Test name
Test status
Simulation time	166741246 ps
CPU time	1.74 seconds
Started	Feb 05 03:37:49 PM PST 24
Finished	Feb 05 03:37:58 PM PST 24
Peak memory	209884 kb
Host	smart-fc80e029-dee4-434e-ba7f-b50c4e83df64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038152139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3038152139
Directory	/workspace/13.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/15.keymgr_direct_to_disabled.719365207
Short name	T797
Test name
Test status
Simulation time	69598017 ps
CPU time	2.96 seconds
Started	Feb 05 03:37:56 PM PST 24
Finished	Feb 05 03:38:05 PM PST 24
Peak memory	208744 kb
Host	smart-e16a51d8-db68-412c-a605-74f85d8b1eec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=719365207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.719365207
Directory	/workspace/15.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/15.keymgr_stress_all.1036523594
Short name	T72
Test name
Test status
Simulation time	6908599345 ps
CPU time	69.3 seconds
Started	Feb 05 03:37:57 PM PST 24
Finished	Feb 05 03:39:19 PM PST 24
Peak memory	216860 kb
Host	smart-a971293d-0eb1-43eb-816b-90c69e27d735
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036523594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1036523594
Directory	/workspace/15.keymgr_stress_all/latest

Test location	/workspace/coverage/default/16.keymgr_kmac_rsp_err.1182471941
Short name	T191
Test name
Test status
Simulation time	59497661 ps
CPU time	2.98 seconds
Started	Feb 05 03:38:01 PM PST 24
Finished	Feb 05 03:38:16 PM PST 24
Peak memory	210592 kb
Host	smart-3b4b9cda-ca0d-4d08-8fc5-937c4fe03d45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1182471941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1182471941
Directory	/workspace/16.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/18.keymgr_hwsw_invalid_input.1911514654
Short name	T274
Test name
Test status
Simulation time	1220170671 ps
CPU time	6.41 seconds
Started	Feb 05 03:38:04 PM PST 24
Finished	Feb 05 03:38:20 PM PST 24
Peak memory	214388 kb
Host	smart-9a724000-206e-4791-b358-e66e6af45cb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1911514654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1911514654
Directory	/workspace/18.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/21.keymgr_kmac_rsp_err.160083565
Short name	T365
Test name
Test status
Simulation time	1488506354 ps
CPU time	9.2 seconds
Started	Feb 05 03:38:21 PM PST 24
Finished	Feb 05 03:38:38 PM PST 24
Peak memory	222356 kb
Host	smart-891c6f45-9ab1-45b1-a452-15189d05061d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=160083565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.160083565
Directory	/workspace/21.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/27.keymgr_cfg_regwen.4094854516
Short name	T387
Test name
Test status
Simulation time	824828377 ps
CPU time	12.11 seconds
Started	Feb 05 03:38:54 PM PST 24
Finished	Feb 05 03:39:08 PM PST 24
Peak memory	215384 kb
Host	smart-2ecb2cb8-3196-4d50-8401-3b8b0eaac671
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4094854516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4094854516
Directory	/workspace/27.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/27.keymgr_kmac_rsp_err.2116138793
Short name	T266
Test name
Test status
Simulation time	423723935 ps
CPU time	3.44 seconds
Started	Feb 05 03:38:53 PM PST 24
Finished	Feb 05 03:38:58 PM PST 24
Peak memory	210936 kb
Host	smart-0d60176a-c42d-4be2-ae03-2be39a9920ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116138793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2116138793
Directory	/workspace/27.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3558793554
Short name	T198
Test name
Test status
Simulation time	129981775 ps
CPU time	8.28 seconds
Started	Feb 05 03:39:08 PM PST 24
Finished	Feb 05 03:39:25 PM PST 24
Peak memory	222552 kb
Host	smart-dca88916-00eb-47ab-9f1c-155d8945d36f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558793554 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3558793554
Directory	/workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.keymgr_hwsw_invalid_input.2967763138
Short name	T235
Test name
Test status
Simulation time	3118824344 ps
CPU time	76.4 seconds
Started	Feb 05 03:39:01 PM PST 24
Finished	Feb 05 03:40:20 PM PST 24
Peak memory	220924 kb
Host	smart-56c9c872-d700-4162-88cf-a1579ec14935
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2967763138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2967763138
Directory	/workspace/29.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/3.keymgr_kmac_rsp_err.2038394255
Short name	T91
Test name
Test status
Simulation time	89673330 ps
CPU time	2.94 seconds
Started	Feb 05 03:36:34 PM PST 24
Finished	Feb 05 03:36:52 PM PST 24
Peak memory	209100 kb
Host	smart-e5c7c787-3914-4188-b3d9-918ca8b078d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038394255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2038394255
Directory	/workspace/3.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/31.keymgr_hwsw_invalid_input.3368572465
Short name	T371
Test name
Test status
Simulation time	18526161444 ps
CPU time	58.45 seconds
Started	Feb 05 03:39:03 PM PST 24
Finished	Feb 05 03:40:05 PM PST 24
Peak memory	218312 kb
Host	smart-199c0a75-2476-4699-835a-a19c91be58ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368572465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3368572465
Directory	/workspace/31.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/32.keymgr_lc_disable.2064505287
Short name	T51
Test name
Test status
Simulation time	1989236310 ps
CPU time	11.95 seconds
Started	Feb 05 03:39:11 PM PST 24
Finished	Feb 05 03:39:29 PM PST 24
Peak memory	209676 kb
Host	smart-ab00dcdf-70cd-49c5-b44a-9a5bf8891643
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2064505287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2064505287
Directory	/workspace/32.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/38.keymgr_lc_disable.232946757
Short name	T61
Test name
Test status
Simulation time	501164051 ps
CPU time	14.59 seconds
Started	Feb 05 03:39:30 PM PST 24
Finished	Feb 05 03:39:48 PM PST 24
Peak memory	221056 kb
Host	smart-55cb4591-3789-4fef-be1a-7d8367773de3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=232946757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.232946757
Directory	/workspace/38.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/39.keymgr_hwsw_invalid_input.3363718660
Short name	T244
Test name
Test status
Simulation time	1486582869 ps
CPU time	5.58 seconds
Started	Feb 05 03:39:38 PM PST 24
Finished	Feb 05 03:39:45 PM PST 24
Peak memory	220612 kb
Host	smart-50280af8-2f42-4bac-99ec-3baa6abf644e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363718660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3363718660
Directory	/workspace/39.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/39.keymgr_lc_disable.1432100344
Short name	T6
Test name
Test status
Simulation time	73950230 ps
CPU time	4.9 seconds
Started	Feb 05 03:39:36 PM PST 24
Finished	Feb 05 03:39:44 PM PST 24
Peak memory	214328 kb
Host	smart-042c2347-875f-4e40-80f6-ccc87e7b8543
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432100344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1432100344
Directory	/workspace/39.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/40.keymgr_random.979881966
Short name	T344
Test name
Test status
Simulation time	302139305 ps
CPU time	4.68 seconds
Started	Feb 05 03:39:41 PM PST 24
Finished	Feb 05 03:39:47 PM PST 24
Peak memory	218564 kb
Host	smart-285cad13-eec9-4fd1-8a09-5d46147a36d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=979881966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.979881966
Directory	/workspace/40.keymgr_random/latest

Test location	/workspace/coverage/default/44.keymgr_lc_disable.490462042
Short name	T204
Test name
Test status
Simulation time	901703966 ps
CPU time	8.05 seconds
Started	Feb 05 03:39:57 PM PST 24
Finished	Feb 05 03:40:10 PM PST 24
Peak memory	222384 kb
Host	smart-feefe824-717e-4aa6-967a-9c95606c66d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490462042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.490462042
Directory	/workspace/44.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/45.keymgr_sw_invalid_input.1901938259
Short name	T356
Test name
Test status
Simulation time	129713192 ps
CPU time	4.79 seconds
Started	Feb 05 03:40:03 PM PST 24
Finished	Feb 05 03:40:18 PM PST 24
Peak memory	208284 kb
Host	smart-d6715fa6-89f7-4e20-87bd-1bc8e9578eb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901938259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1901938259
Directory	/workspace/45.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/46.keymgr_cfg_regwen.2687812416
Short name	T399
Test name
Test status
Simulation time	165771092 ps
CPU time	3.1 seconds
Started	Feb 05 03:40:13 PM PST 24
Finished	Feb 05 03:40:20 PM PST 24
Peak memory	215324 kb
Host	smart-65f15ddc-9d65-4941-a64d-cdc5e8359c0f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2687812416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2687812416
Directory	/workspace/46.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1092850027
Short name	T462
Test name
Test status
Simulation time	373767730 ps
CPU time	7.22 seconds
Started	Feb 05 01:15:05 PM PST 24
Finished	Feb 05 01:15:13 PM PST 24
Peak memory	205152 kb
Host	smart-ce51109c-7e7b-4733-9223-b82f7d4bd925
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092850027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1 092850027
Directory	/workspace/0.keymgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.570240881
Short name	T174
Test name
Test status
Simulation time	60215301 ps
CPU time	1.29 seconds
Started	Feb 05 01:15:05 PM PST 24
Finished	Feb 05 01:15:08 PM PST 24
Peak memory	205316 kb
Host	smart-318a6a9e-800d-438a-8ae3-374c3df854a4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570240881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.570240881
Directory	/workspace/0.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1708321884
Short name	T169
Test name
Test status
Simulation time	29103486 ps
CPU time	1.54 seconds
Started	Feb 05 01:15:11 PM PST 24
Finished	Feb 05 01:15:13 PM PST 24
Peak memory	213596 kb
Host	smart-0e1b6aee-f710-4a30-a36a-10d6373d9510
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708321884 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1708321884
Directory	/workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3603791041
Short name	T444
Test name
Test status
Simulation time	25499481 ps
CPU time	1.2 seconds
Started	Feb 05 01:15:12 PM PST 24
Finished	Feb 05 01:15:14 PM PST 24
Peak memory	205212 kb
Host	smart-9ea3daec-728a-4e11-925c-1e2c7883fb2b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603791041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3603791041
Directory	/workspace/0.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_intr_test.3933704116
Short name	T439
Test name
Test status
Simulation time	11873442 ps
CPU time	0.86 seconds
Started	Feb 05 01:15:05 PM PST 24
Finished	Feb 05 01:15:08 PM PST 24
Peak memory	205024 kb
Host	smart-d92a4c23-3844-4cca-9abe-1c22081d62f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933704116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3933704116
Directory	/workspace/0.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1830376131
Short name	T512
Test name
Test status
Simulation time	40183561 ps
CPU time	2.74 seconds
Started	Feb 05 01:15:02 PM PST 24
Finished	Feb 05 01:15:06 PM PST 24
Peak memory	213492 kb
Host	smart-016b04fb-54cf-4d7b-b21d-25713d6227fb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830376131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa me_csr_outstanding.1830376131
Directory	/workspace/0.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.4294666863
Short name	T487
Test name
Test status
Simulation time	592813312 ps
CPU time	10.55 seconds
Started	Feb 05 01:15:11 PM PST 24
Finished	Feb 05 01:15:22 PM PST 24
Peak memory	213744 kb
Host	smart-1c1f8805-4fbf-4420-b39b-3d2524fff0b1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294666863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado w_reg_errors.4294666863
Directory	/workspace/0.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.358736850
Short name	T492
Test name
Test status
Simulation time	300797504 ps
CPU time	10.55 seconds
Started	Feb 05 01:15:05 PM PST 24
Finished	Feb 05 01:15:17 PM PST 24
Peak memory	213752 kb
Host	smart-1289bc71-1db6-469d-8829-6e4a129419d1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358736850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k eymgr_shadow_reg_errors_with_csr_rw.358736850
Directory	/workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1532579042
Short name	T121
Test name
Test status
Simulation time	1059734304 ps
CPU time	3.51 seconds
Started	Feb 05 01:15:19 PM PST 24
Finished	Feb 05 01:15:25 PM PST 24
Peak memory	213560 kb
Host	smart-74379a0a-99d7-4b3f-82e1-dc7fc36cf169
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532579042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1532579042
Directory	/workspace/0.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.390241389
Short name	T517
Test name
Test status
Simulation time	209825441 ps
CPU time	4.93 seconds
Started	Feb 05 01:15:10 PM PST 24
Finished	Feb 05 01:15:16 PM PST 24
Peak memory	205152 kb
Host	smart-10b8fd86-3794-4bee-bdaf-30ece0d81700
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390241389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.390241389
Directory	/workspace/1.keymgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3675330860
Short name	T496
Test name
Test status
Simulation time	174024895 ps
CPU time	6.54 seconds
Started	Feb 05 01:15:19 PM PST 24
Finished	Feb 05 01:15:28 PM PST 24
Peak memory	205136 kb
Host	smart-f090763f-0135-45a2-b395-fa81d574eafe
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675330860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3 675330860
Directory	/workspace/1.keymgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3541933795
Short name	T408
Test name
Test status
Simulation time	80956486 ps
CPU time	1.05 seconds
Started	Feb 05 01:15:11 PM PST 24
Finished	Feb 05 01:15:13 PM PST 24
Peak memory	205224 kb
Host	smart-b119e802-95a6-40da-83ce-55d3a48f79a9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541933795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3 541933795
Directory	/workspace/1.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2295395442
Short name	T516
Test name
Test status
Simulation time	31061218 ps
CPU time	1.42 seconds
Started	Feb 05 01:15:26 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205376 kb
Host	smart-455178a8-3caf-454b-840b-e2c6d7be8d80
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295395442 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2295395442
Directory	/workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1370519889
Short name	T511
Test name
Test status
Simulation time	62309329 ps
CPU time	0.96 seconds
Started	Feb 05 01:15:11 PM PST 24
Finished	Feb 05 01:15:13 PM PST 24
Peak memory	205248 kb
Host	smart-cd201d32-2511-4156-991f-e61fc1648844
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370519889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1370519889
Directory	/workspace/1.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_intr_test.2722296594
Short name	T469
Test name
Test status
Simulation time	19675589 ps
CPU time	0.74 seconds
Started	Feb 05 01:15:24 PM PST 24
Finished	Feb 05 01:15:25 PM PST 24
Peak memory	205140 kb
Host	smart-0c68d3ee-fa93-469e-b9de-30f39c47060a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722296594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2722296594
Directory	/workspace/1.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.223609339
Short name	T442
Test name
Test status
Simulation time	66897460 ps
CPU time	1.86 seconds
Started	Feb 05 01:15:09 PM PST 24
Finished	Feb 05 01:15:12 PM PST 24
Peak memory	205400 kb
Host	smart-9f642ce5-1d8a-4502-9752-5aab39f0894f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223609339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam e_csr_outstanding.223609339
Directory	/workspace/1.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3346015413
Short name	T432
Test name
Test status
Simulation time	86353169 ps
CPU time	3.95 seconds
Started	Feb 05 01:15:03 PM PST 24
Finished	Feb 05 01:15:09 PM PST 24
Peak memory	213688 kb
Host	smart-de825523-b6c3-431c-b540-dbfe7c16d412
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346015413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. keymgr_shadow_reg_errors_with_csr_rw.3346015413
Directory	/workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_tl_errors.326856967
Short name	T427
Test name
Test status
Simulation time	72159182 ps
CPU time	2.21 seconds
Started	Feb 05 01:15:13 PM PST 24
Finished	Feb 05 01:15:16 PM PST 24
Peak memory	213628 kb
Host	smart-b84ca8e9-35b9-49af-a121-246f1632b055
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326856967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.326856967
Directory	/workspace/1.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.56563874
Short name	T452
Test name
Test status
Simulation time	57161864 ps
CPU time	1.33 seconds
Started	Feb 05 01:15:34 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	213464 kb
Host	smart-11545f0e-68d3-42a6-9412-a3f33a2e3dc5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56563874 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.56563874
Directory	/workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_csr_rw.612400621
Short name	T472
Test name
Test status
Simulation time	45463115 ps
CPU time	1.12 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	205168 kb
Host	smart-c266a194-9d6f-4357-8d68-580a68c0df5b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612400621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.612400621
Directory	/workspace/10.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_intr_test.1758422459
Short name	T481
Test name
Test status
Simulation time	8853884 ps
CPU time	0.79 seconds
Started	Feb 05 01:15:35 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	205028 kb
Host	smart-725f1a72-9347-485c-84b8-8810ad824f6f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758422459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1758422459
Directory	/workspace/10.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.53204064
Short name	T419
Test name
Test status
Simulation time	80469351 ps
CPU time	1.53 seconds
Started	Feb 05 01:15:41 PM PST 24
Finished	Feb 05 01:15:45 PM PST 24
Peak memory	205240 kb
Host	smart-42af0b51-69fb-45cc-9902-1e060b0c1e9e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53204064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sam e_csr_outstanding.53204064
Directory	/workspace/10.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3845282502
Short name	T438
Test name
Test status
Simulation time	496396225 ps
CPU time	3.94 seconds
Started	Feb 05 01:15:37 PM PST 24
Finished	Feb 05 01:15:45 PM PST 24
Peak memory	213788 kb
Host	smart-6419a070-75df-4857-a959-4844e185a214
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845282502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad ow_reg_errors.3845282502
Directory	/workspace/10.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4229055509
Short name	T124
Test name
Test status
Simulation time	263441185 ps
CPU time	1.92 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	213420 kb
Host	smart-175b109c-2ca9-40b0-8c8b-6caddcc69060
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229055509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.4229055509
Directory	/workspace/10.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.692584722
Short name	T543
Test name
Test status
Simulation time	43391446 ps
CPU time	1.67 seconds
Started	Feb 05 01:15:34 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	213600 kb
Host	smart-5409b25d-5b19-49cd-b3d0-1bae625443ff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692584722 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.692584722
Directory	/workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_intr_test.3741545464
Short name	T544
Test name
Test status
Simulation time	43577281 ps
CPU time	0.75 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:37 PM PST 24
Peak memory	205104 kb
Host	smart-bc016842-19e3-473a-a82c-f42c05a6e973
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741545464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3741545464
Directory	/workspace/11.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2094728311
Short name	T431
Test name
Test status
Simulation time	288716748 ps
CPU time	2.11 seconds
Started	Feb 05 01:15:32 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	205228 kb
Host	smart-fffb50c2-e0e2-4817-9edd-28ce054b8583
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094728311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s ame_csr_outstanding.2094728311
Directory	/workspace/11.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.277680615
Short name	T537
Test name
Test status
Simulation time	105855471 ps
CPU time	2.2 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	213808 kb
Host	smart-62a6998f-0056-49c8-84bc-59985559c2b5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277680615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado w_reg_errors.277680615
Directory	/workspace/11.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4122190585
Short name	T122
Test name
Test status
Simulation time	540615002 ps
CPU time	4.88 seconds
Started	Feb 05 01:15:26 PM PST 24
Finished	Feb 05 01:15:38 PM PST 24
Peak memory	216660 kb
Host	smart-34d68882-9d4e-4bcf-83b2-a66f683c7779
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122190585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.4122190585
Directory	/workspace/11.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.949482201
Short name	T467
Test name
Test status
Simulation time	1532896807 ps
CPU time	8.41 seconds
Started	Feb 05 01:15:30 PM PST 24
Finished	Feb 05 01:15:42 PM PST 24
Peak memory	213524 kb
Host	smart-1020268a-189a-4cba-9a08-b566222c8b1d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949482201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err .949482201
Directory	/workspace/11.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.756676960
Short name	T413
Test name
Test status
Simulation time	53019767 ps
CPU time	0.96 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205132 kb
Host	smart-7585fb51-db3b-44bb-b9e0-51f8d1eab97f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756676960 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.756676960
Directory	/workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1436586722
Short name	T418
Test name
Test status
Simulation time	36772021 ps
CPU time	1.18 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205284 kb
Host	smart-c0ebf7c0-f66c-439a-bbaa-b331cf3eb92a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436586722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1436586722
Directory	/workspace/12.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_intr_test.1278510147
Short name	T422
Test name
Test status
Simulation time	128908783 ps
CPU time	0.79 seconds
Started	Feb 05 01:15:41 PM PST 24
Finished	Feb 05 01:15:44 PM PST 24
Peak memory	205168 kb
Host	smart-375706b9-79fb-4a5c-9294-e12419299fd7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278510147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1278510147
Directory	/workspace/12.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2573874385
Short name	T504
Test name
Test status
Simulation time	197371927 ps
CPU time	3.59 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:37 PM PST 24
Peak memory	205284 kb
Host	smart-562f49ca-5251-4f61-a11f-06567818b0c2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573874385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s ame_csr_outstanding.2573874385
Directory	/workspace/12.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4181314397
Short name	T477
Test name
Test status
Simulation time	71434868 ps
CPU time	2.22 seconds
Started	Feb 05 01:15:39 PM PST 24
Finished	Feb 05 01:15:45 PM PST 24
Peak memory	213764 kb
Host	smart-a3f9f68b-cad7-4153-80d3-00153508c8f3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181314397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad ow_reg_errors.4181314397
Directory	/workspace/12.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3869777016
Short name	T445
Test name
Test status
Simulation time	370427564 ps
CPU time	5.21 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	213756 kb
Host	smart-adc7f385-05ee-487d-bf82-af3dfdcff420
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869777016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .keymgr_shadow_reg_errors_with_csr_rw.3869777016
Directory	/workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1671753641
Short name	T528
Test name
Test status
Simulation time	244253713 ps
CPU time	4.89 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:38 PM PST 24
Peak memory	213412 kb
Host	smart-10f9b768-1192-400b-a29d-caf0cbfbea01
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671753641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1671753641
Directory	/workspace/12.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3456587405
Short name	T506
Test name
Test status
Simulation time	64648022 ps
CPU time	1.65 seconds
Started	Feb 05 01:15:29 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	213644 kb
Host	smart-eca7cb99-8853-42db-bf04-0a08c6f86748
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456587405 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3456587405
Directory	/workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_csr_rw.340108128
Short name	T134
Test name
Test status
Simulation time	19227868 ps
CPU time	0.99 seconds
Started	Feb 05 01:15:32 PM PST 24
Finished	Feb 05 01:15:40 PM PST 24
Peak memory	204784 kb
Host	smart-f32e6d1d-f99f-4ed5-b352-15e1ab05b66f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340108128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.340108128
Directory	/workspace/13.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_intr_test.3959070570
Short name	T522
Test name
Test status
Simulation time	20593779 ps
CPU time	0.74 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205152 kb
Host	smart-545256e1-4235-4fef-8219-1c832bc2121e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959070570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3959070570
Directory	/workspace/13.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3454451101
Short name	T497
Test name
Test status
Simulation time	92409912 ps
CPU time	1.8 seconds
Started	Feb 05 01:15:34 PM PST 24
Finished	Feb 05 01:15:42 PM PST 24
Peak memory	205304 kb
Host	smart-b1e937a9-394d-46f5-8848-6aea796d60a4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454451101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s ame_csr_outstanding.3454451101
Directory	/workspace/13.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1537994454
Short name	T429
Test name
Test status
Simulation time	368509951 ps
CPU time	4.76 seconds
Started	Feb 05 01:15:33 PM PST 24
Finished	Feb 05 01:15:44 PM PST 24
Peak memory	218728 kb
Host	smart-7313b40b-34be-475f-a6c1-4d4c5e545fa2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537994454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad ow_reg_errors.1537994454
Directory	/workspace/13.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1203761775
Short name	T529
Test name
Test status
Simulation time	1077009391 ps
CPU time	8.06 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:45 PM PST 24
Peak memory	213764 kb
Host	smart-2b77d86a-0d5a-4837-aa91-a606feb02a35
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203761775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .keymgr_shadow_reg_errors_with_csr_rw.1203761775
Directory	/workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_tl_errors.50713934
Short name	T449
Test name
Test status
Simulation time	106004026 ps
CPU time	3.95 seconds
Started	Feb 05 01:15:32 PM PST 24
Finished	Feb 05 01:15:43 PM PST 24
Peak memory	216984 kb
Host	smart-647fe891-81f8-4d87-8746-5177af13906f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50713934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.50713934
Directory	/workspace/13.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3967152033
Short name	T157
Test name
Test status
Simulation time	1354930386 ps
CPU time	7.39 seconds
Started	Feb 05 01:15:32 PM PST 24
Finished	Feb 05 01:15:46 PM PST 24
Peak memory	209004 kb
Host	smart-1b510597-dc90-4976-a0e7-d868abf48ebb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967152033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er r.3967152033
Directory	/workspace/13.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2171120443
Short name	T507
Test name
Test status
Simulation time	65353602 ps
CPU time	1.4 seconds
Started	Feb 05 01:15:41 PM PST 24
Finished	Feb 05 01:15:45 PM PST 24
Peak memory	205388 kb
Host	smart-532ccd30-b6a2-4753-b4b6-65c1df4ff0ee
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171120443 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2171120443
Directory	/workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_intr_test.2757635621
Short name	T483
Test name
Test status
Simulation time	29585898 ps
CPU time	0.77 seconds
Started	Feb 05 01:15:35 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	205144 kb
Host	smart-ff02f8c1-f066-467d-ac81-ff257c18e59c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757635621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2757635621
Directory	/workspace/14.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2541116900
Short name	T482
Test name
Test status
Simulation time	525908072 ps
CPU time	2.43 seconds
Started	Feb 05 01:15:32 PM PST 24
Finished	Feb 05 01:15:42 PM PST 24
Peak memory	205360 kb
Host	smart-6c9a5841-7559-4f11-a388-4c0648f35d71
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541116900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s ame_csr_outstanding.2541116900
Directory	/workspace/14.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1414814062
Short name	T451
Test name
Test status
Simulation time	234606719 ps
CPU time	4.37 seconds
Started	Feb 05 01:15:30 PM PST 24
Finished	Feb 05 01:15:38 PM PST 24
Peak memory	213788 kb
Host	smart-64d0b4e3-cbb9-468a-8069-ad66bfc92f9f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414814062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad ow_reg_errors.1414814062
Directory	/workspace/14.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.567271739
Short name	T113
Test name
Test status
Simulation time	229158883 ps
CPU time	8.6 seconds
Started	Feb 05 01:15:32 PM PST 24
Finished	Feb 05 01:15:48 PM PST 24
Peak memory	220300 kb
Host	smart-4e28b3cb-ab9b-40a3-aa74-150b63f1ba82
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567271739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. keymgr_shadow_reg_errors_with_csr_rw.567271739
Directory	/workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1454538961
Short name	T478
Test name
Test status
Simulation time	59732010 ps
CPU time	2.11 seconds
Started	Feb 05 01:15:32 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	213644 kb
Host	smart-f28fee57-d568-415a-9642-fb8faadd9c72
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454538961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1454538961
Directory	/workspace/14.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.4258637180
Short name	T433
Test name
Test status
Simulation time	35644407 ps
CPU time	1.38 seconds
Started	Feb 05 01:15:49 PM PST 24
Finished	Feb 05 01:15:55 PM PST 24
Peak memory	213676 kb
Host	smart-9ecbe09b-9dd1-4111-9100-a914fb251ebb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258637180 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.4258637180
Directory	/workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1587634559
Short name	T450
Test name
Test status
Simulation time	18432474 ps
CPU time	0.94 seconds
Started	Feb 05 01:15:44 PM PST 24
Finished	Feb 05 01:15:47 PM PST 24
Peak memory	205096 kb
Host	smart-b90fd8fa-8f5c-4738-85b7-bad98c794a57
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587634559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1587634559
Directory	/workspace/15.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_intr_test.1046276402
Short name	T171
Test name
Test status
Simulation time	43625969 ps
CPU time	0.83 seconds
Started	Feb 05 01:15:39 PM PST 24
Finished	Feb 05 01:15:43 PM PST 24
Peak memory	205052 kb
Host	smart-eb8db4d9-468f-49c3-b645-4677599ee6f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046276402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1046276402
Directory	/workspace/15.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2470109978
Short name	T502
Test name
Test status
Simulation time	129153855 ps
CPU time	2.19 seconds
Started	Feb 05 01:15:38 PM PST 24
Finished	Feb 05 01:15:44 PM PST 24
Peak memory	205312 kb
Host	smart-be9d1df8-5999-419a-ad41-8fea0eaca6c1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470109978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s ame_csr_outstanding.2470109978
Directory	/workspace/15.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2441882631
Short name	T547
Test name
Test status
Simulation time	149884530 ps
CPU time	3.42 seconds
Started	Feb 05 01:15:39 PM PST 24
Finished	Feb 05 01:15:46 PM PST 24
Peak memory	213804 kb
Host	smart-d18eb708-b63d-4c3a-8434-27d643ed05bd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441882631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad ow_reg_errors.2441882631
Directory	/workspace/15.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.960350139
Short name	T475
Test name
Test status
Simulation time	246643870 ps
CPU time	8.85 seconds
Started	Feb 05 01:15:30 PM PST 24
Finished	Feb 05 01:15:42 PM PST 24
Peak memory	213756 kb
Host	smart-63cb2130-4e27-412d-89f6-c6fadece43e6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960350139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. keymgr_shadow_reg_errors_with_csr_rw.960350139
Directory	/workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4210724698
Short name	T170
Test name
Test status
Simulation time	88948867 ps
CPU time	3.2 seconds
Started	Feb 05 01:15:38 PM PST 24
Finished	Feb 05 01:15:45 PM PST 24
Peak memory	213560 kb
Host	smart-b70b11d5-2597-436d-86ae-7dda8c7ff37e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210724698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4210724698
Directory	/workspace/15.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2809902758
Short name	T165
Test name
Test status
Simulation time	15992060 ps
CPU time	1.12 seconds
Started	Feb 05 01:15:35 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	213616 kb
Host	smart-34a8f290-bc7b-46cf-8694-b65768135729
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809902758 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2809902758
Directory	/workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2442442563
Short name	T538
Test name
Test status
Simulation time	54422004 ps
CPU time	0.89 seconds
Started	Feb 05 01:15:49 PM PST 24
Finished	Feb 05 01:15:52 PM PST 24
Peak memory	205180 kb
Host	smart-10e4057a-5e57-4fa1-8142-190219d0f23f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442442563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2442442563
Directory	/workspace/16.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_intr_test.3313432077
Short name	T443
Test name
Test status
Simulation time	26225177 ps
CPU time	0.77 seconds
Started	Feb 05 01:15:41 PM PST 24
Finished	Feb 05 01:15:44 PM PST 24
Peak memory	205188 kb
Host	smart-008dfada-70a5-42f7-bc92-68490bc18d1f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313432077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3313432077
Directory	/workspace/16.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3020800500
Short name	T115
Test name
Test status
Simulation time	1042550336 ps
CPU time	5.41 seconds
Started	Feb 05 01:15:35 PM PST 24
Finished	Feb 05 01:15:46 PM PST 24
Peak memory	213700 kb
Host	smart-83a50361-7bf5-4a45-90e0-dbbc78e56c73
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020800500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad ow_reg_errors.3020800500
Directory	/workspace/16.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.823526108
Short name	T119
Test name
Test status
Simulation time	1683775653 ps
CPU time	11.34 seconds
Started	Feb 05 01:15:49 PM PST 24
Finished	Feb 05 01:16:05 PM PST 24
Peak memory	213752 kb
Host	smart-53cb3e5e-a857-449e-bc18-eb84f33e557f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823526108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. keymgr_shadow_reg_errors_with_csr_rw.823526108
Directory	/workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3015868675
Short name	T461
Test name
Test status
Simulation time	156344353 ps
CPU time	3.55 seconds
Started	Feb 05 01:15:50 PM PST 24
Finished	Feb 05 01:15:57 PM PST 24
Peak memory	213664 kb
Host	smart-e14eb0e8-6a43-4929-882f-f599b227ef1c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015868675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3015868675
Directory	/workspace/16.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3185083511
Short name	T166
Test name
Test status
Simulation time	275510488 ps
CPU time	1.17 seconds
Started	Feb 05 01:15:41 PM PST 24
Finished	Feb 05 01:15:45 PM PST 24
Peak memory	205256 kb
Host	smart-c152d1d6-5951-4836-b441-3ecb068cbcdd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185083511 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3185083511
Directory	/workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2913687944
Short name	T518
Test name
Test status
Simulation time	432252571 ps
CPU time	1.36 seconds
Started	Feb 05 01:15:39 PM PST 24
Finished	Feb 05 01:15:44 PM PST 24
Peak memory	205276 kb
Host	smart-fd58165f-4d35-40bb-954d-a0940011e206
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913687944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2913687944
Directory	/workspace/17.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_intr_test.2153181712
Short name	T474
Test name
Test status
Simulation time	12927771 ps
CPU time	0.77 seconds
Started	Feb 05 01:15:49 PM PST 24
Finished	Feb 05 01:15:54 PM PST 24
Peak memory	205100 kb
Host	smart-c60f80b8-08d4-4f75-8b09-98df1898e6e6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153181712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2153181712
Directory	/workspace/17.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3916051424
Short name	T476
Test name
Test status
Simulation time	53737062 ps
CPU time	1.62 seconds
Started	Feb 05 01:15:40 PM PST 24
Finished	Feb 05 01:15:45 PM PST 24
Peak memory	205320 kb
Host	smart-c5f48957-caec-4d05-b142-ecfd5a819cdd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916051424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s ame_csr_outstanding.3916051424
Directory	/workspace/17.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.572381663
Short name	T117
Test name
Test status
Simulation time	406070532 ps
CPU time	4.08 seconds
Started	Feb 05 01:15:49 PM PST 24
Finished	Feb 05 01:15:55 PM PST 24
Peak memory	218540 kb
Host	smart-3bba55c1-8bc5-4114-bce9-44f36283a848
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572381663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado w_reg_errors.572381663
Directory	/workspace/17.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.424304935
Short name	T526
Test name
Test status
Simulation time	481181505 ps
CPU time	12.3 seconds
Started	Feb 05 01:15:40 PM PST 24
Finished	Feb 05 01:15:55 PM PST 24
Peak memory	213784 kb
Host	smart-fed17170-c516-45d7-aea1-078956ee13bd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424304935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. keymgr_shadow_reg_errors_with_csr_rw.424304935
Directory	/workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1297946957
Short name	T459
Test name
Test status
Simulation time	270229257 ps
CPU time	1.99 seconds
Started	Feb 05 01:15:39 PM PST 24
Finished	Feb 05 01:15:44 PM PST 24
Peak memory	213604 kb
Host	smart-6cf8865f-1763-477c-848b-9a12817b5c0c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297946957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1297946957
Directory	/workspace/17.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1254836638
Short name	T428
Test name
Test status
Simulation time	64671134 ps
CPU time	1.58 seconds
Started	Feb 05 01:15:55 PM PST 24
Finished	Feb 05 01:15:58 PM PST 24
Peak memory	213560 kb
Host	smart-c525368e-12e0-43be-b7f7-4d075a56ca68
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254836638 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1254836638
Directory	/workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2468587399
Short name	T446
Test name
Test status
Simulation time	49353117 ps
CPU time	1.2 seconds
Started	Feb 05 01:15:49 PM PST 24
Finished	Feb 05 01:15:52 PM PST 24
Peak memory	205192 kb
Host	smart-9dee0850-4e7b-40ee-be2e-b3b922b25d26
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468587399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2468587399
Directory	/workspace/18.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_intr_test.4066284415
Short name	T493
Test name
Test status
Simulation time	106458246 ps
CPU time	0.88 seconds
Started	Feb 05 01:15:37 PM PST 24
Finished	Feb 05 01:15:42 PM PST 24
Peak memory	205260 kb
Host	smart-55f37f14-8e52-4257-9bef-1bf5079301eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066284415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4066284415
Directory	/workspace/18.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3948324569
Short name	T468
Test name
Test status
Simulation time	21469351 ps
CPU time	1.7 seconds
Started	Feb 05 01:15:41 PM PST 24
Finished	Feb 05 01:15:45 PM PST 24
Peak memory	204688 kb
Host	smart-a473f241-62f0-4144-a927-ff2bb9da7799
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948324569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s ame_csr_outstanding.3948324569
Directory	/workspace/18.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2610096700
Short name	T464
Test name
Test status
Simulation time	644306160 ps
CPU time	16.71 seconds
Started	Feb 05 01:15:38 PM PST 24
Finished	Feb 05 01:15:58 PM PST 24
Peak memory	214832 kb
Host	smart-7619a293-c105-4026-90a3-ed58e5f127c3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610096700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad ow_reg_errors.2610096700
Directory	/workspace/18.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3768497843
Short name	T509
Test name
Test status
Simulation time	111771672 ps
CPU time	5.53 seconds
Started	Feb 05 01:15:35 PM PST 24
Finished	Feb 05 01:15:46 PM PST 24
Peak memory	213780 kb
Host	smart-f88faa94-6229-4ef6-aeb9-8da03e881fc9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768497843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .keymgr_shadow_reg_errors_with_csr_rw.3768497843
Directory	/workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1643661945
Short name	T126
Test name
Test status
Simulation time	602411312 ps
CPU time	2.43 seconds
Started	Feb 05 01:15:41 PM PST 24
Finished	Feb 05 01:15:46 PM PST 24
Peak memory	213520 kb
Host	smart-916e8c3e-4267-4304-8213-0112645f9a64
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643661945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1643661945
Directory	/workspace/18.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3511452901
Short name	T163
Test name
Test status
Simulation time	109325304 ps
CPU time	3.44 seconds
Started	Feb 05 01:15:37 PM PST 24
Finished	Feb 05 01:15:44 PM PST 24
Peak memory	208896 kb
Host	smart-18db09e5-6c14-422d-8eb2-1ba5ff336e28
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511452901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er r.3511452901
Directory	/workspace/18.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.4264337757
Short name	T411
Test name
Test status
Simulation time	29257831 ps
CPU time	1.36 seconds
Started	Feb 05 01:15:57 PM PST 24
Finished	Feb 05 01:15:59 PM PST 24
Peak memory	213668 kb
Host	smart-d2bd362f-77b1-4ca6-862b-3a61016fd209
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264337757 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.4264337757
Directory	/workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3573230182
Short name	T421
Test name
Test status
Simulation time	92685215 ps
CPU time	1.09 seconds
Started	Feb 05 01:15:48 PM PST 24
Finished	Feb 05 01:15:49 PM PST 24
Peak memory	205156 kb
Host	smart-e4bba29b-962b-4327-8f57-5651d3aed9c5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573230182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3573230182
Directory	/workspace/19.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_intr_test.1519130183
Short name	T473
Test name
Test status
Simulation time	12718600 ps
CPU time	0.75 seconds
Started	Feb 05 01:15:50 PM PST 24
Finished	Feb 05 01:15:55 PM PST 24
Peak memory	205144 kb
Host	smart-5fb429f5-4e12-4e43-9c93-335b46955509
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519130183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1519130183
Directory	/workspace/19.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1503926342
Short name	T173
Test name
Test status
Simulation time	62873494 ps
CPU time	1.69 seconds
Started	Feb 05 01:15:56 PM PST 24
Finished	Feb 05 01:15:59 PM PST 24
Peak memory	205276 kb
Host	smart-57fcca1d-0320-4e90-80e1-d3ae71a9d04c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503926342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s ame_csr_outstanding.1503926342
Directory	/workspace/19.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3934930152
Short name	T542
Test name
Test status
Simulation time	274049240 ps
CPU time	4.67 seconds
Started	Feb 05 01:15:52 PM PST 24
Finished	Feb 05 01:16:00 PM PST 24
Peak memory	213840 kb
Host	smart-94d6305c-c999-44c6-b568-56a3a5368ead
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934930152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad ow_reg_errors.3934930152
Directory	/workspace/19.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3243809931
Short name	T515
Test name
Test status
Simulation time	173161331 ps
CPU time	2.5 seconds
Started	Feb 05 01:15:54 PM PST 24
Finished	Feb 05 01:15:59 PM PST 24
Peak memory	213484 kb
Host	smart-458317e7-70b2-4996-b976-6ef4e6d14e33
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243809931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3243809931
Directory	/workspace/19.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.550756393
Short name	T159
Test name
Test status
Simulation time	187646750 ps
CPU time	6.13 seconds
Started	Feb 05 01:15:53 PM PST 24
Finished	Feb 05 01:16:02 PM PST 24
Peak memory	213668 kb
Host	smart-3a2a7bff-7eb9-4a76-9dbe-bed74b696a51
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550756393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err .550756393
Directory	/workspace/19.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2833930744
Short name	T535
Test name
Test status
Simulation time	557417860 ps
CPU time	14.49 seconds
Started	Feb 05 01:15:26 PM PST 24
Finished	Feb 05 01:15:48 PM PST 24
Peak memory	205320 kb
Host	smart-39d00448-03b2-4e36-a6f0-ab61d2aff747
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833930744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2 833930744
Directory	/workspace/2.keymgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2028435223
Short name	T457
Test name
Test status
Simulation time	28061881 ps
CPU time	1.43 seconds
Started	Feb 05 01:15:15 PM PST 24
Finished	Feb 05 01:15:18 PM PST 24
Peak memory	205176 kb
Host	smart-ee06cee1-dcc9-4878-a4eb-832a17c3a5d5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028435223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2 028435223
Directory	/workspace/2.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1787931032
Short name	T127
Test name
Test status
Simulation time	25300515 ps
CPU time	1.47 seconds
Started	Feb 05 01:15:15 PM PST 24
Finished	Feb 05 01:15:17 PM PST 24
Peak memory	213536 kb
Host	smart-b15c0624-230c-4532-bc5e-ca46e3615659
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787931032 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1787931032
Directory	/workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1145465188
Short name	T137
Test name
Test status
Simulation time	60282367 ps
CPU time	0.96 seconds
Started	Feb 05 01:15:19 PM PST 24
Finished	Feb 05 01:15:22 PM PST 24
Peak memory	205156 kb
Host	smart-3f885198-c72e-4585-8fe1-57b13a83a3ed
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145465188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1145465188
Directory	/workspace/2.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_intr_test.2035490017
Short name	T424
Test name
Test status
Simulation time	12636046 ps
CPU time	0.84 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205132 kb
Host	smart-800fd205-5647-4fa1-b99c-a8f56750f644
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035490017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2035490017
Directory	/workspace/2.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.416154634
Short name	T133
Test name
Test status
Simulation time	272254482 ps
CPU time	2.12 seconds
Started	Feb 05 01:15:23 PM PST 24
Finished	Feb 05 01:15:26 PM PST 24
Peak memory	205372 kb
Host	smart-410faa92-066f-4a95-b875-cffc4b940dd4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416154634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam e_csr_outstanding.416154634
Directory	/workspace/2.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3137132269
Short name	T486
Test name
Test status
Simulation time	106149816 ps
CPU time	3.48 seconds
Started	Feb 05 01:15:18 PM PST 24
Finished	Feb 05 01:15:24 PM PST 24
Peak memory	213848 kb
Host	smart-3d0d7e84-6df7-4ec9-8c66-ec38899942af
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137132269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado w_reg_errors.3137132269
Directory	/workspace/2.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_tl_errors.875841703
Short name	T454
Test name
Test status
Simulation time	42556101 ps
CPU time	2.07 seconds
Started	Feb 05 01:15:18 PM PST 24
Finished	Feb 05 01:15:22 PM PST 24
Peak memory	213520 kb
Host	smart-99b786d2-f557-4f8b-8795-2ba063e2d8bc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875841703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.875841703
Directory	/workspace/2.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.keymgr_intr_test.79336105
Short name	T471
Test name
Test status
Simulation time	12044489 ps
CPU time	0.71 seconds
Started	Feb 05 01:15:55 PM PST 24
Finished	Feb 05 01:15:57 PM PST 24
Peak memory	205104 kb
Host	smart-e58fe447-a15a-4d48-92e7-97fb21962063
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79336105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.79336105
Directory	/workspace/20.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.keymgr_intr_test.3132952513
Short name	T172
Test name
Test status
Simulation time	44003609 ps
CPU time	0.87 seconds
Started	Feb 05 01:15:55 PM PST 24
Finished	Feb 05 01:15:57 PM PST 24
Peak memory	205112 kb
Host	smart-d4ab14b1-5c2e-418b-aef6-90d1eb2f6ab5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132952513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3132952513
Directory	/workspace/21.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.keymgr_intr_test.3060232324
Short name	T460
Test name
Test status
Simulation time	39609474 ps
CPU time	0.74 seconds
Started	Feb 05 01:15:52 PM PST 24
Finished	Feb 05 01:15:56 PM PST 24
Peak memory	205156 kb
Host	smart-1a16c93d-07b1-4be3-b33f-8c26100470eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060232324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3060232324
Directory	/workspace/22.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.keymgr_intr_test.556429119
Short name	T409
Test name
Test status
Simulation time	35358127 ps
CPU time	0.77 seconds
Started	Feb 05 01:15:49 PM PST 24
Finished	Feb 05 01:15:54 PM PST 24
Peak memory	205156 kb
Host	smart-3275928c-3a28-4e97-8b7b-da16fe207268
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556429119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.556429119
Directory	/workspace/23.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.keymgr_intr_test.370727340
Short name	T531
Test name
Test status
Simulation time	13682248 ps
CPU time	0.9 seconds
Started	Feb 05 01:15:49 PM PST 24
Finished	Feb 05 01:15:54 PM PST 24
Peak memory	205216 kb
Host	smart-41c91825-edf5-4ba2-8435-f5a2a20d87be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370727340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.370727340
Directory	/workspace/24.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.keymgr_intr_test.3129807878
Short name	T480
Test name
Test status
Simulation time	98756357 ps
CPU time	0.84 seconds
Started	Feb 05 01:15:50 PM PST 24
Finished	Feb 05 01:15:55 PM PST 24
Peak memory	205072 kb
Host	smart-3764273d-bb4e-4067-ad84-e4b956c0a9b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129807878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3129807878
Directory	/workspace/25.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.keymgr_intr_test.3731065377
Short name	T524
Test name
Test status
Simulation time	21953406 ps
CPU time	0.66 seconds
Started	Feb 05 01:15:51 PM PST 24
Finished	Feb 05 01:15:55 PM PST 24
Peak memory	205140 kb
Host	smart-974bc99f-592f-45c4-9f2b-e66e4ed4fb23
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731065377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3731065377
Directory	/workspace/26.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.keymgr_intr_test.3142598519
Short name	T417
Test name
Test status
Simulation time	27832900 ps
CPU time	0.79 seconds
Started	Feb 05 01:15:52 PM PST 24
Finished	Feb 05 01:15:56 PM PST 24
Peak memory	205180 kb
Host	smart-b81d3258-a2a5-4de1-b859-1e5e5ee2e10d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142598519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3142598519
Directory	/workspace/27.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.keymgr_intr_test.1557842321
Short name	T410
Test name
Test status
Simulation time	29856642 ps
CPU time	0.82 seconds
Started	Feb 05 01:15:50 PM PST 24
Finished	Feb 05 01:15:55 PM PST 24
Peak memory	205180 kb
Host	smart-ec0ed71c-f3d9-48e7-a5e2-d77e3e6fc237
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557842321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1557842321
Directory	/workspace/28.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.keymgr_intr_test.1493807010
Short name	T458
Test name
Test status
Simulation time	17347408 ps
CPU time	0.69 seconds
Started	Feb 05 01:15:52 PM PST 24
Finished	Feb 05 01:15:56 PM PST 24
Peak memory	205176 kb
Host	smart-b91fb5fb-0b80-4025-a8d3-c050df0e7542
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493807010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1493807010
Directory	/workspace/29.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2109664001
Short name	T168
Test name
Test status
Simulation time	26151546 ps
CPU time	1.21 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:36 PM PST 24
Peak memory	205236 kb
Host	smart-8f8d1358-01f2-45b8-a2a1-ae64f3cc3987
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109664001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2 109664001
Directory	/workspace/3.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1562943715
Short name	T489
Test name
Test status
Simulation time	15116430 ps
CPU time	0.93 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205312 kb
Host	smart-09a62a0d-d139-4790-8254-11933aff9ec9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562943715 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1562943715
Directory	/workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_rw.414911301
Short name	T423
Test name
Test status
Simulation time	40619885 ps
CPU time	1.05 seconds
Started	Feb 05 01:15:23 PM PST 24
Finished	Feb 05 01:15:25 PM PST 24
Peak memory	205168 kb
Host	smart-eda3483d-6795-49ab-89df-bb0bef59bddd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414911301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.414911301
Directory	/workspace/3.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_intr_test.3692346254
Short name	T527
Test name
Test status
Simulation time	178355270 ps
CPU time	0.69 seconds
Started	Feb 05 01:15:28 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205112 kb
Host	smart-29f9317b-880d-428c-992d-bf12bcad10d9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692346254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3692346254
Directory	/workspace/3.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1566771328
Short name	T491
Test name
Test status
Simulation time	251048375 ps
CPU time	2.32 seconds
Started	Feb 05 01:15:30 PM PST 24
Finished	Feb 05 01:15:36 PM PST 24
Peak memory	205172 kb
Host	smart-e79cf223-83e5-4dff-a05e-ebfc2861f44b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566771328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa me_csr_outstanding.1566771328
Directory	/workspace/3.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1456527120
Short name	T530
Test name
Test status
Simulation time	69453044 ps
CPU time	1.51 seconds
Started	Feb 05 01:15:26 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205268 kb
Host	smart-784567d4-5ffe-48f0-8e11-1a276bae55c7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456527120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado w_reg_errors.1456527120
Directory	/workspace/3.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.14707884
Short name	T112
Test name
Test status
Simulation time	791058336 ps
CPU time	7.71 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	213620 kb
Host	smart-536863f2-0891-4cd6-bac8-8c03db616a56
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14707884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_ SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.ke ymgr_shadow_reg_errors_with_csr_rw.14707884
Directory	/workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4208726797
Short name	T485
Test name
Test status
Simulation time	66563533 ps
CPU time	2.65 seconds
Started	Feb 05 01:15:10 PM PST 24
Finished	Feb 05 01:15:14 PM PST 24
Peak memory	216580 kb
Host	smart-755f7ea6-d656-46e2-ad6b-30fdb7035c0e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208726797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4208726797
Directory	/workspace/3.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.keymgr_intr_test.2438658470
Short name	T441
Test name
Test status
Simulation time	13454719 ps
CPU time	0.88 seconds
Started	Feb 05 01:15:50 PM PST 24
Finished	Feb 05 01:15:55 PM PST 24
Peak memory	205212 kb
Host	smart-3e2d95da-2fa4-4f7f-b0ae-7906cb00442d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438658470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2438658470
Directory	/workspace/30.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.keymgr_intr_test.725313298
Short name	T412
Test name
Test status
Simulation time	30322988 ps
CPU time	0.79 seconds
Started	Feb 05 01:15:53 PM PST 24
Finished	Feb 05 01:15:56 PM PST 24
Peak memory	205096 kb
Host	smart-a13793d2-2867-442b-be25-e9b956c34635
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725313298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.725313298
Directory	/workspace/31.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.keymgr_intr_test.1576582250
Short name	T414
Test name
Test status
Simulation time	11698231 ps
CPU time	0.69 seconds
Started	Feb 05 01:15:53 PM PST 24
Finished	Feb 05 01:15:56 PM PST 24
Peak memory	205176 kb
Host	smart-b60f927a-ebc1-4543-9b6f-7b7fc890b471
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576582250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1576582250
Directory	/workspace/32.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.keymgr_intr_test.4066477826
Short name	T430
Test name
Test status
Simulation time	29721734 ps
CPU time	0.79 seconds
Started	Feb 05 01:16:01 PM PST 24
Finished	Feb 05 01:16:02 PM PST 24
Peak memory	205096 kb
Host	smart-4cda4ec0-4026-42f0-a7cf-86f8076d1b19
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066477826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.4066477826
Directory	/workspace/33.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.keymgr_intr_test.2840253330
Short name	T536
Test name
Test status
Simulation time	16890931 ps
CPU time	0.82 seconds
Started	Feb 05 01:15:53 PM PST 24
Finished	Feb 05 01:15:57 PM PST 24
Peak memory	205140 kb
Host	smart-2356cebf-434c-48a4-af93-e74641d5d13f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840253330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2840253330
Directory	/workspace/34.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.keymgr_intr_test.375834271
Short name	T448
Test name
Test status
Simulation time	14155102 ps
CPU time	0.77 seconds
Started	Feb 05 01:16:01 PM PST 24
Finished	Feb 05 01:16:03 PM PST 24
Peak memory	205080 kb
Host	smart-17128cb2-4c56-4143-bb0b-5d02d8f4006a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375834271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.375834271
Directory	/workspace/35.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.keymgr_intr_test.3074675997
Short name	T465
Test name
Test status
Simulation time	19458892 ps
CPU time	0.7 seconds
Started	Feb 05 01:16:04 PM PST 24
Finished	Feb 05 01:16:05 PM PST 24
Peak memory	205068 kb
Host	smart-bb33565f-f294-477e-b08b-42778e2d64e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074675997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3074675997
Directory	/workspace/36.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.keymgr_intr_test.2684914588
Short name	T456
Test name
Test status
Simulation time	23711873 ps
CPU time	0.81 seconds
Started	Feb 05 01:15:55 PM PST 24
Finished	Feb 05 01:15:57 PM PST 24
Peak memory	205364 kb
Host	smart-940460e2-2517-433a-8ab3-9a50c9883abf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684914588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2684914588
Directory	/workspace/37.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.keymgr_intr_test.208830329
Short name	T420
Test name
Test status
Simulation time	15228530 ps
CPU time	0.76 seconds
Started	Feb 05 01:16:03 PM PST 24
Finished	Feb 05 01:16:04 PM PST 24
Peak memory	205156 kb
Host	smart-23a589cd-0893-4780-a96b-589b8a2cbad9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208830329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.208830329
Directory	/workspace/38.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.keymgr_intr_test.1539625713
Short name	T488
Test name
Test status
Simulation time	17117833 ps
CPU time	0.71 seconds
Started	Feb 05 01:16:03 PM PST 24
Finished	Feb 05 01:16:04 PM PST 24
Peak memory	205088 kb
Host	smart-0f87fe3c-e698-43c7-81b2-d9098ca5bc3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539625713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1539625713
Directory	/workspace/39.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1509759667
Short name	T514
Test name
Test status
Simulation time	1268820815 ps
CPU time	8.22 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:44 PM PST 24
Peak memory	205224 kb
Host	smart-509a4e48-9d67-448e-9546-e955e7783154
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509759667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1 509759667
Directory	/workspace/4.keymgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.812046012
Short name	T541
Test name
Test status
Simulation time	76265146 ps
CPU time	1.23 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205264 kb
Host	smart-76ab17c3-cd36-4ad5-9916-4987710521f9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812046012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.812046012
Directory	/workspace/4.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2441052798
Short name	T455
Test name
Test status
Simulation time	145640334 ps
CPU time	1.84 seconds
Started	Feb 05 01:15:25 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	213836 kb
Host	smart-5b8749d6-4df6-416a-b61c-939b0f2762fb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441052798 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2441052798
Directory	/workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2430835399
Short name	T503
Test name
Test status
Simulation time	63606894 ps
CPU time	1.03 seconds
Started	Feb 05 01:15:26 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205152 kb
Host	smart-e442f5c5-b892-4613-bb7e-d800dde96c7a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430835399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2430835399
Directory	/workspace/4.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_intr_test.3869291060
Short name	T508
Test name
Test status
Simulation time	13140068 ps
CPU time	0.91 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205084 kb
Host	smart-95dc4adc-0dbd-465f-a8fb-cef7ba90722c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869291060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3869291060
Directory	/workspace/4.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3378820653
Short name	T546
Test name
Test status
Simulation time	109171558 ps
CPU time	1.65 seconds
Started	Feb 05 01:15:26 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205264 kb
Host	smart-fa34c28d-149d-47e0-bb1a-433fc5f7f097
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378820653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa me_csr_outstanding.3378820653
Directory	/workspace/4.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.291550365
Short name	T434
Test name
Test status
Simulation time	289300084 ps
CPU time	4.8 seconds
Started	Feb 05 01:15:36 PM PST 24
Finished	Feb 05 01:15:45 PM PST 24
Peak memory	213788 kb
Host	smart-58a51c93-105d-4d88-81dd-0aa6dbe83481
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291550365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow _reg_errors.291550365
Directory	/workspace/4.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1559394118
Short name	T490
Test name
Test status
Simulation time	83422351 ps
CPU time	2.06 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:37 PM PST 24
Peak memory	214012 kb
Host	smart-969d0350-e3d0-4086-9ad9-04694678faec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559394118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1559394118
Directory	/workspace/4.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3761959694
Short name	T125
Test name
Test status
Simulation time	228688331 ps
CPU time	9.39 seconds
Started	Feb 05 01:15:29 PM PST 24
Finished	Feb 05 01:15:43 PM PST 24
Peak memory	208860 kb
Host	smart-c2c23d6b-7262-4efb-8fe0-5ce87a2c449e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761959694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err .3761959694
Directory	/workspace/4.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.keymgr_intr_test.1259138279
Short name	T440
Test name
Test status
Simulation time	13365364 ps
CPU time	0.97 seconds
Started	Feb 05 01:15:55 PM PST 24
Finished	Feb 05 01:15:58 PM PST 24
Peak memory	205200 kb
Host	smart-5130f779-b7f3-45f5-8227-0c44432f4d81
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259138279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1259138279
Directory	/workspace/40.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.keymgr_intr_test.3234718087
Short name	T453
Test name
Test status
Simulation time	35305033 ps
CPU time	0.7 seconds
Started	Feb 05 01:16:00 PM PST 24
Finished	Feb 05 01:16:02 PM PST 24
Peak memory	205184 kb
Host	smart-8aef69e1-5e1d-4d2e-96ed-712f22b2dad9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234718087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3234718087
Directory	/workspace/41.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.keymgr_intr_test.2712320926
Short name	T505
Test name
Test status
Simulation time	20368636 ps
CPU time	0.8 seconds
Started	Feb 05 01:16:03 PM PST 24
Finished	Feb 05 01:16:05 PM PST 24
Peak memory	205128 kb
Host	smart-f8385dba-b7b7-461c-8ca6-3f5b6eab65d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712320926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2712320926
Directory	/workspace/42.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.keymgr_intr_test.2494143444
Short name	T534
Test name
Test status
Simulation time	26938959 ps
CPU time	0.68 seconds
Started	Feb 05 01:16:00 PM PST 24
Finished	Feb 05 01:16:02 PM PST 24
Peak memory	205152 kb
Host	smart-d0fd3bbc-9812-4431-b210-5fce8f783810
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494143444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2494143444
Directory	/workspace/43.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.keymgr_intr_test.3752621626
Short name	T519
Test name
Test status
Simulation time	20310526 ps
CPU time	0.73 seconds
Started	Feb 05 01:16:04 PM PST 24
Finished	Feb 05 01:16:06 PM PST 24
Peak memory	205364 kb
Host	smart-68cb8edf-65a8-4553-8d8d-8e321f6cfce7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752621626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3752621626
Directory	/workspace/44.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.keymgr_intr_test.388778273
Short name	T435
Test name
Test status
Simulation time	78656129 ps
CPU time	0.73 seconds
Started	Feb 05 01:15:55 PM PST 24
Finished	Feb 05 01:15:57 PM PST 24
Peak memory	205164 kb
Host	smart-dc160fbb-0e35-4e87-bde9-f9d4ae451933
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388778273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.388778273
Directory	/workspace/45.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.keymgr_intr_test.4148546908
Short name	T523
Test name
Test status
Simulation time	13990979 ps
CPU time	0.74 seconds
Started	Feb 05 01:15:59 PM PST 24
Finished	Feb 05 01:16:01 PM PST 24
Peak memory	205040 kb
Host	smart-f09951cb-fd01-4394-b200-fa84fa1defbb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148546908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.4148546908
Directory	/workspace/46.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.keymgr_intr_test.833983015
Short name	T494
Test name
Test status
Simulation time	23187834 ps
CPU time	0.73 seconds
Started	Feb 05 01:15:54 PM PST 24
Finished	Feb 05 01:15:57 PM PST 24
Peak memory	205096 kb
Host	smart-85d8e92d-fb1f-4bf8-b73a-eacd1c1f01ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833983015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.833983015
Directory	/workspace/47.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.keymgr_intr_test.3290112052
Short name	T525
Test name
Test status
Simulation time	19252093 ps
CPU time	0.83 seconds
Started	Feb 05 01:16:02 PM PST 24
Finished	Feb 05 01:16:03 PM PST 24
Peak memory	205096 kb
Host	smart-d7ddb299-c708-4ae3-8b9d-b5b714d959e5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290112052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3290112052
Directory	/workspace/48.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.keymgr_intr_test.3576125349
Short name	T498
Test name
Test status
Simulation time	25792985 ps
CPU time	0.77 seconds
Started	Feb 05 01:16:07 PM PST 24
Finished	Feb 05 01:16:09 PM PST 24
Peak memory	205176 kb
Host	smart-11e6bfa3-24c7-402f-a3c1-7e5905552dc0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576125349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3576125349
Directory	/workspace/49.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1891305840
Short name	T510
Test name
Test status
Simulation time	220209155 ps
CPU time	1.49 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:38 PM PST 24
Peak memory	217196 kb
Host	smart-f4624bbe-8557-4320-8e4a-65718d3aa723
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891305840 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1891305840
Directory	/workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_csr_rw.592620696
Short name	T470
Test name
Test status
Simulation time	58553276 ps
CPU time	0.94 seconds
Started	Feb 05 01:15:32 PM PST 24
Finished	Feb 05 01:15:40 PM PST 24
Peak memory	205152 kb
Host	smart-9522f2c5-9d0f-410a-be78-a4179987dcc0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592620696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.592620696
Directory	/workspace/5.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_intr_test.1899025543
Short name	T426
Test name
Test status
Simulation time	23646335 ps
CPU time	0.77 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	204992 kb
Host	smart-31d609a2-dac6-457a-a98d-b05799256ec6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899025543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1899025543
Directory	/workspace/5.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3964723057
Short name	T138
Test name
Test status
Simulation time	162626301 ps
CPU time	1.64 seconds
Started	Feb 05 01:15:30 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	205208 kb
Host	smart-c82fc177-977d-4cc8-8873-46f4cdb4984c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964723057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa me_csr_outstanding.3964723057
Directory	/workspace/5.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1758113646
Short name	T479
Test name
Test status
Simulation time	424071186 ps
CPU time	2.72 seconds
Started	Feb 05 01:15:30 PM PST 24
Finished	Feb 05 01:15:36 PM PST 24
Peak memory	213764 kb
Host	smart-f5db5b75-e1ca-47a9-a38c-4bf40df5e6d5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758113646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado w_reg_errors.1758113646
Directory	/workspace/5.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3244570077
Short name	T148
Test name
Test status
Simulation time	136671407 ps
CPU time	4.6 seconds
Started	Feb 05 01:15:26 PM PST 24
Finished	Feb 05 01:15:37 PM PST 24
Peak memory	213580 kb
Host	smart-c0304962-7139-4af0-80ea-4d5d606a2a38
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244570077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3244570077
Directory	/workspace/5.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4229494970
Short name	T463
Test name
Test status
Simulation time	46573033 ps
CPU time	1.45 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	213580 kb
Host	smart-fafe2392-b0b9-44c1-b050-fde3f1846c7f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229494970 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.4229494970
Directory	/workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_csr_rw.362824248
Short name	T135
Test name
Test status
Simulation time	22111142 ps
CPU time	1.04 seconds
Started	Feb 05 01:15:25 PM PST 24
Finished	Feb 05 01:15:33 PM PST 24
Peak memory	205156 kb
Host	smart-6e0c85b6-a3d4-4901-b625-9b45d90d7695
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362824248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.362824248
Directory	/workspace/6.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_intr_test.3298066862
Short name	T499
Test name
Test status
Simulation time	32020247 ps
CPU time	0.72 seconds
Started	Feb 05 01:15:30 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205068 kb
Host	smart-ada604c6-9ef3-45f1-b71f-3ca18b88e747
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298066862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3298066862
Directory	/workspace/6.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3302442562
Short name	T437
Test name
Test status
Simulation time	452955866 ps
CPU time	3.64 seconds
Started	Feb 05 01:15:33 PM PST 24
Finished	Feb 05 01:15:43 PM PST 24
Peak memory	205152 kb
Host	smart-67fa1e85-c655-4955-9967-9b70aece8226
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302442562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa me_csr_outstanding.3302442562
Directory	/workspace/6.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2888185252
Short name	T118
Test name
Test status
Simulation time	2103968798 ps
CPU time	4.32 seconds
Started	Feb 05 01:15:28 PM PST 24
Finished	Feb 05 01:15:37 PM PST 24
Peak memory	213836 kb
Host	smart-817d65e4-2943-453d-8141-d7b237eec818
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888185252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado w_reg_errors.2888185252
Directory	/workspace/6.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2664010434
Short name	T545
Test name
Test status
Simulation time	1134463643 ps
CPU time	8.3 seconds
Started	Feb 05 01:15:30 PM PST 24
Finished	Feb 05 01:15:42 PM PST 24
Peak memory	213608 kb
Host	smart-40393c5e-b86c-4dcc-98e2-fb60f077911d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664010434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. keymgr_shadow_reg_errors_with_csr_rw.2664010434
Directory	/workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2636884858
Short name	T415
Test name
Test status
Simulation time	175009005 ps
CPU time	2.16 seconds
Started	Feb 05 01:15:28 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	213504 kb
Host	smart-43651b95-4c5f-45aa-b3c3-b9ad5c751564
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636884858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2636884858
Directory	/workspace/6.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.281577173
Short name	T164
Test name
Test status
Simulation time	1643519313 ps
CPU time	8.62 seconds
Started	Feb 05 01:15:26 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	208832 kb
Host	smart-2fcd886d-cb85-4353-9b32-ceb89c17acd3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281577173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err. 281577173
Directory	/workspace/6.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2027928741
Short name	T533
Test name
Test status
Simulation time	13357735 ps
CPU time	1.07 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	205356 kb
Host	smart-b632a39f-3a6a-47d6-a490-46979e4ba970
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027928741 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2027928741
Directory	/workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1385723725
Short name	T416
Test name
Test status
Simulation time	29341160 ps
CPU time	1.21 seconds
Started	Feb 05 01:15:26 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205216 kb
Host	smart-37169efa-ad9c-4aa6-a543-d37de85ac730
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385723725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1385723725
Directory	/workspace/7.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_intr_test.2345129730
Short name	T136
Test name
Test status
Simulation time	67248414 ps
CPU time	0.76 seconds
Started	Feb 05 01:15:28 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205152 kb
Host	smart-0e8091e9-27c2-4192-8a4c-9ac8c28125f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345129730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2345129730
Directory	/workspace/7.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1702041501
Short name	T495
Test name
Test status
Simulation time	47261589 ps
CPU time	2.23 seconds
Started	Feb 05 01:15:32 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	205376 kb
Host	smart-33ede6c6-fb64-45fd-a4e2-df0de3b3eda7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702041501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa me_csr_outstanding.1702041501
Directory	/workspace/7.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.5748567
Short name	T500
Test name
Test status
Simulation time	76845957 ps
CPU time	2.57 seconds
Started	Feb 05 01:15:25 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	213756 kb
Host	smart-68fb1bb7-678b-46e6-b34d-7d646e25181b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5748567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_r eg_errors.5748567
Directory	/workspace/7.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4048437174
Short name	T548
Test name
Test status
Simulation time	177354999 ps
CPU time	2.4 seconds
Started	Feb 05 01:15:28 PM PST 24
Finished	Feb 05 01:15:36 PM PST 24
Peak memory	215976 kb
Host	smart-b50d9ebc-6719-449e-99f1-b879c54d997c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048437174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4048437174
Directory	/workspace/7.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4287209778
Short name	T167
Test name
Test status
Simulation time	25045656 ps
CPU time	1.07 seconds
Started	Feb 05 01:15:40 PM PST 24
Finished	Feb 05 01:15:44 PM PST 24
Peak memory	213528 kb
Host	smart-6ea4d026-10d6-4b83-a2f0-c27a9cf7c0c9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287209778 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.4287209778
Directory	/workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2682856626
Short name	T521
Test name
Test status
Simulation time	59555009 ps
CPU time	0.98 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205180 kb
Host	smart-cf8473f9-639e-4798-9818-238ba1c2d77e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682856626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2682856626
Directory	/workspace/8.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_intr_test.866045420
Short name	T540
Test name
Test status
Simulation time	16004508 ps
CPU time	0.71 seconds
Started	Feb 05 01:15:31 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	205092 kb
Host	smart-38721538-509e-4ac2-b23c-8d772c33c88a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866045420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.866045420
Directory	/workspace/8.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2503891512
Short name	T132
Test name
Test status
Simulation time	87042775 ps
CPU time	1.47 seconds
Started	Feb 05 01:15:32 PM PST 24
Finished	Feb 05 01:15:40 PM PST 24
Peak memory	204960 kb
Host	smart-c1d705af-cb37-4e5d-842a-fa5d5494d650
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503891512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa me_csr_outstanding.2503891512
Directory	/workspace/8.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.328787782
Short name	T513
Test name
Test status
Simulation time	104348498 ps
CPU time	2.17 seconds
Started	Feb 05 01:15:27 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	213740 kb
Host	smart-5dae756c-1c4f-4569-998e-7fae49c3b0e7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328787782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow _reg_errors.328787782
Directory	/workspace/8.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2335571464
Short name	T520
Test name
Test status
Simulation time	1168667908 ps
CPU time	5.32 seconds
Started	Feb 05 01:15:28 PM PST 24
Finished	Feb 05 01:15:38 PM PST 24
Peak memory	213824 kb
Host	smart-1ce5d6b3-92da-4c0d-8317-a0d57e81958f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335571464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. keymgr_shadow_reg_errors_with_csr_rw.2335571464
Directory	/workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3758141967
Short name	T447
Test name
Test status
Simulation time	480026731 ps
CPU time	3.98 seconds
Started	Feb 05 01:15:28 PM PST 24
Finished	Feb 05 01:15:37 PM PST 24
Peak memory	213600 kb
Host	smart-e0beead0-1389-403e-ae0a-40b429e1e101
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758141967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3758141967
Directory	/workspace/8.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2469826064
Short name	T425
Test name
Test status
Simulation time	44022610 ps
CPU time	1.52 seconds
Started	Feb 05 01:15:39 PM PST 24
Finished	Feb 05 01:15:44 PM PST 24
Peak memory	213532 kb
Host	smart-91a20e90-1678-4424-9c2c-ec86bef2c6d1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469826064 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2469826064
Directory	/workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2829546777
Short name	T501
Test name
Test status
Simulation time	43779491 ps
CPU time	1.14 seconds
Started	Feb 05 01:15:29 PM PST 24
Finished	Feb 05 01:15:34 PM PST 24
Peak memory	205264 kb
Host	smart-4a030cc3-2c28-4c4b-b0fe-e395be7bede6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829546777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2829546777
Directory	/workspace/9.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_intr_test.1984678487
Short name	T484
Test name
Test status
Simulation time	42659818 ps
CPU time	0.84 seconds
Started	Feb 05 01:15:35 PM PST 24
Finished	Feb 05 01:15:41 PM PST 24
Peak memory	205020 kb
Host	smart-818de8bc-7102-483c-9901-fe56d89a196d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984678487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1984678487
Directory	/workspace/9.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4021730753
Short name	T466
Test name
Test status
Simulation time	70521524 ps
CPU time	2.07 seconds
Started	Feb 05 01:15:30 PM PST 24
Finished	Feb 05 01:15:35 PM PST 24
Peak memory	205280 kb
Host	smart-80b02f78-7eeb-4f13-984a-391d1a4926a5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021730753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa me_csr_outstanding.4021730753
Directory	/workspace/9.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.717621861
Short name	T532
Test name
Test status
Simulation time	648480901 ps
CPU time	12.37 seconds
Started	Feb 05 01:15:28 PM PST 24
Finished	Feb 05 01:15:46 PM PST 24
Peak memory	221416 kb
Host	smart-b959bc0a-fd06-4333-8035-58b5a5d2e562
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717621861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow _reg_errors.717621861
Directory	/workspace/9.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1423306613
Short name	T436
Test name
Test status
Simulation time	98191626 ps
CPU time	4.81 seconds
Started	Feb 05 01:15:26 PM PST 24
Finished	Feb 05 01:15:38 PM PST 24
Peak memory	213772 kb
Host	smart-8f0a4165-5532-492b-8cdc-444934126c18
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423306613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. keymgr_shadow_reg_errors_with_csr_rw.1423306613
Directory	/workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_tl_errors.404306406
Short name	T539
Test name
Test status
Simulation time	267310262 ps
CPU time	2.79 seconds
Started	Feb 05 01:15:30 PM PST 24
Finished	Feb 05 01:15:36 PM PST 24
Peak memory	213464 kb
Host	smart-63942e34-80c0-411c-9272-250058aed265
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404306406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.404306406
Directory	/workspace/9.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3570211398
Short name	T153
Test name
Test status
Simulation time	141252075 ps
CPU time	3.7 seconds
Started	Feb 05 01:15:28 PM PST 24
Finished	Feb 05 01:15:37 PM PST 24
Peak memory	213604 kb
Host	smart-efb97051-5c20-45d9-b196-56f096c98c33
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570211398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err .3570211398
Directory	/workspace/9.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.keymgr_alert_test.1553550175
Short name	T957
Test name
Test status
Simulation time	17332139 ps
CPU time	0.95 seconds
Started	Feb 05 03:36:17 PM PST 24
Finished	Feb 05 03:36:28 PM PST 24
Peak memory	206240 kb
Host	smart-0dc9c31c-6f8f-4323-a1ec-dde6fc942905
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553550175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1553550175
Directory	/workspace/0.keymgr_alert_test/latest

Test location	/workspace/coverage/default/0.keymgr_custom_cm.2593417240
Short name	T30
Test name
Test status
Simulation time	161173714 ps
CPU time	3.01 seconds
Started	Feb 05 03:36:15 PM PST 24
Finished	Feb 05 03:36:29 PM PST 24
Peak memory	208396 kb
Host	smart-dc1adbb0-abe4-4832-9f68-2b50840162b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2593417240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2593417240
Directory	/workspace/0.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/0.keymgr_direct_to_disabled.713158064
Short name	T598
Test name
Test status
Simulation time	3021724402 ps
CPU time	10 seconds
Started	Feb 05 03:36:12 PM PST 24
Finished	Feb 05 03:36:28 PM PST 24
Peak memory	218364 kb
Host	smart-78d365d1-7db8-43f6-8f7b-c3d2fb6b47bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=713158064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.713158064
Directory	/workspace/0.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/0.keymgr_hwsw_invalid_input.3664160634
Short name	T19
Test name
Test status
Simulation time	56987255 ps
CPU time	3.33 seconds
Started	Feb 05 03:36:12 PM PST 24
Finished	Feb 05 03:36:21 PM PST 24
Peak memory	222504 kb
Host	smart-91d6fc7e-330c-4890-8e51-dfcc1f3bf3ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664160634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3664160634
Directory	/workspace/0.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/0.keymgr_lc_disable.3993020857
Short name	T64
Test name
Test status
Simulation time	124713251 ps
CPU time	3.19 seconds
Started	Feb 05 03:36:17 PM PST 24
Finished	Feb 05 03:36:31 PM PST 24
Peak memory	218688 kb
Host	smart-c1ff6434-c85a-42ef-ac91-df3d6ad343ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993020857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3993020857
Directory	/workspace/0.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/0.keymgr_random.2541694301
Short name	T281
Test name
Test status
Simulation time	86741509 ps
CPU time	3.56 seconds
Started	Feb 05 03:36:09 PM PST 24
Finished	Feb 05 03:36:18 PM PST 24
Peak memory	208172 kb
Host	smart-47b19d03-134c-461f-b33f-53da70b29daf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541694301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2541694301
Directory	/workspace/0.keymgr_random/latest

Test location	/workspace/coverage/default/0.keymgr_sideload.3042105632
Short name	T311
Test name
Test status
Simulation time	1005511111 ps
CPU time	7.81 seconds
Started	Feb 05 03:36:17 PM PST 24
Finished	Feb 05 03:36:36 PM PST 24
Peak memory	208384 kb
Host	smart-f7375f9e-509e-4518-8623-77c9e12c0562
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3042105632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3042105632
Directory	/workspace/0.keymgr_sideload/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_aes.3463627657
Short name	T1003
Test name
Test status
Simulation time	2062882554 ps
CPU time	53.98 seconds
Started	Feb 05 03:36:12 PM PST 24
Finished	Feb 05 03:37:12 PM PST 24
Peak memory	207768 kb
Host	smart-16e06b19-e5a4-4358-bd87-4987294e089e
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463627657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3463627657
Directory	/workspace/0.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_kmac.3105767697
Short name	T330
Test name
Test status
Simulation time	39103606 ps
CPU time	2.39 seconds
Started	Feb 05 03:36:11 PM PST 24
Finished	Feb 05 03:36:19 PM PST 24
Peak memory	206940 kb
Host	smart-f938709d-16f4-4427-8e5e-ce88d9e55147
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105767697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3105767697
Directory	/workspace/0.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_otbn.1683574422
Short name	T553
Test name
Test status
Simulation time	50978477 ps
CPU time	2.81 seconds
Started	Feb 05 03:36:13 PM PST 24
Finished	Feb 05 03:36:26 PM PST 24
Peak memory	206884 kb
Host	smart-f3161c88-5832-4b55-a98e-45fb5ec608de
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683574422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1683574422
Directory	/workspace/0.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_protect.2139997702
Short name	T182
Test name
Test status
Simulation time	334449061 ps
CPU time	4.46 seconds
Started	Feb 05 03:36:15 PM PST 24
Finished	Feb 05 03:36:30 PM PST 24
Peak memory	215360 kb
Host	smart-98c548db-1835-4993-a3d9-238cfdd64d48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139997702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2139997702
Directory	/workspace/0.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/0.keymgr_smoke.1321466139
Short name	T780
Test name
Test status
Simulation time	159870215 ps
CPU time	3.67 seconds
Started	Feb 05 03:36:05 PM PST 24
Finished	Feb 05 03:36:15 PM PST 24
Peak memory	208544 kb
Host	smart-0254efff-1e30-4ea8-a019-131a05a79297
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321466139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1321466139
Directory	/workspace/0.keymgr_smoke/latest

Test location	/workspace/coverage/default/0.keymgr_stress_all.430523876
Short name	T73
Test name
Test status
Simulation time	3074175260 ps
CPU time	31.95 seconds
Started	Feb 05 03:36:12 PM PST 24
Finished	Feb 05 03:36:50 PM PST 24
Peak memory	222384 kb
Host	smart-07340643-19ae-4474-8c56-eb9c22252c70
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430523876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.430523876
Directory	/workspace/0.keymgr_stress_all/latest

Test location	/workspace/coverage/default/0.keymgr_sync_async_fault_cross.2808244403
Short name	T155
Test name
Test status
Simulation time	194755058 ps
CPU time	2.88 seconds
Started	Feb 05 03:36:14 PM PST 24
Finished	Feb 05 03:36:27 PM PST 24
Peak memory	210324 kb
Host	smart-c0159257-dcee-4582-8051-35706b355132
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2808244403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2808244403
Directory	/workspace/0.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/1.keymgr_alert_test.59819851
Short name	T104
Test name
Test status
Simulation time	12567473 ps
CPU time	0.72 seconds
Started	Feb 05 03:36:17 PM PST 24
Finished	Feb 05 03:36:28 PM PST 24
Peak memory	206076 kb
Host	smart-9a5ef1b8-0f5e-4a54-99bd-d80db6b4a556
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59819851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.59819851
Directory	/workspace/1.keymgr_alert_test/latest

Test location	/workspace/coverage/default/1.keymgr_direct_to_disabled.1695723054
Short name	T45
Test name
Test status
Simulation time	27238068 ps
CPU time	1.83 seconds
Started	Feb 05 03:36:19 PM PST 24
Finished	Feb 05 03:36:41 PM PST 24
Peak memory	206996 kb
Host	smart-f405351d-aea7-44af-8097-981407219efa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695723054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1695723054
Directory	/workspace/1.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/1.keymgr_kmac_rsp_err.1711432190
Short name	T980
Test name
Test status
Simulation time	100064144 ps
CPU time	4.89 seconds
Started	Feb 05 03:36:18 PM PST 24
Finished	Feb 05 03:36:43 PM PST 24
Peak memory	210288 kb
Host	smart-bd609224-7b6f-4c79-8c83-f1f4cc9e0b88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711432190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1711432190
Directory	/workspace/1.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/1.keymgr_lc_disable.2902484716
Short name	T928
Test name
Test status
Simulation time	117994225 ps
CPU time	3.93 seconds
Started	Feb 05 03:36:21 PM PST 24
Finished	Feb 05 03:36:43 PM PST 24
Peak memory	220016 kb
Host	smart-daba9a1e-6a83-4a9c-ab74-d6f4bf094703
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902484716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2902484716
Directory	/workspace/1.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/1.keymgr_random.226227992
Short name	T223
Test name
Test status
Simulation time	288709816 ps
CPU time	3.76 seconds
Started	Feb 05 03:36:11 PM PST 24
Finished	Feb 05 03:36:21 PM PST 24
Peak memory	209152 kb
Host	smart-579fc721-79e1-4551-a657-12d07fb9e017
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226227992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.226227992
Directory	/workspace/1.keymgr_random/latest

Test location	/workspace/coverage/default/1.keymgr_sideload.2908794130
Short name	T227
Test name
Test status
Simulation time	296680014 ps
CPU time	3.42 seconds
Started	Feb 05 03:36:12 PM PST 24
Finished	Feb 05 03:36:21 PM PST 24
Peak memory	208700 kb
Host	smart-0d960c83-21d2-454f-a4e9-6289b1b152cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908794130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2908794130
Directory	/workspace/1.keymgr_sideload/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_aes.1372237222
Short name	T359
Test name
Test status
Simulation time	5815741902 ps
CPU time	53.78 seconds
Started	Feb 05 03:36:17 PM PST 24
Finished	Feb 05 03:37:22 PM PST 24
Peak memory	208392 kb
Host	smart-7df59383-2f2a-47ed-a9ad-a9c3886e3044
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372237222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1372237222
Directory	/workspace/1.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_kmac.2200117232
Short name	T986
Test name
Test status
Simulation time	971285408 ps
CPU time	3.38 seconds
Started	Feb 05 03:36:10 PM PST 24
Finished	Feb 05 03:36:20 PM PST 24
Peak memory	208388 kb
Host	smart-7f020e10-a607-4205-a986-efb1b06e89c6
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200117232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2200117232
Directory	/workspace/1.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_otbn.1483699099
Short name	T834
Test name
Test status
Simulation time	98338858 ps
CPU time	2.91 seconds
Started	Feb 05 03:36:12 PM PST 24
Finished	Feb 05 03:36:21 PM PST 24
Peak memory	206732 kb
Host	smart-80014f7b-9b47-4904-b0ef-d390ac27c6c7
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483699099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1483699099
Directory	/workspace/1.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_protect.1752523333
Short name	T714
Test name
Test status
Simulation time	186311402 ps
CPU time	3.12 seconds
Started	Feb 05 03:36:19 PM PST 24
Finished	Feb 05 03:36:41 PM PST 24
Peak memory	214320 kb
Host	smart-3938a2f3-e6ac-4f22-8182-fc6de7a338e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752523333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1752523333
Directory	/workspace/1.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/1.keymgr_smoke.59136611
Short name	T936
Test name
Test status
Simulation time	106828851 ps
CPU time	2.55 seconds
Started	Feb 05 03:36:14 PM PST 24
Finished	Feb 05 03:36:28 PM PST 24
Peak memory	207092 kb
Host	smart-82d95bbf-dc2e-4fea-9eff-829d02189350
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=59136611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.59136611
Directory	/workspace/1.keymgr_smoke/latest

Test location	/workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1581695521
Short name	T828
Test name
Test status
Simulation time	74159990 ps
CPU time	2.62 seconds
Started	Feb 05 03:36:19 PM PST 24
Finished	Feb 05 03:36:41 PM PST 24
Peak memory	218844 kb
Host	smart-bc1617ff-eb03-4bea-b0f7-7de42b15d810
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581695521 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1581695521
Directory	/workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.keymgr_sw_invalid_input.4257340889
Short name	T228
Test name
Test status
Simulation time	356720197 ps
CPU time	9.85 seconds
Started	Feb 05 03:36:25 PM PST 24
Finished	Feb 05 03:36:52 PM PST 24
Peak memory	208112 kb
Host	smart-56f7d881-7f56-4cd0-9b67-632f6e98ead9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257340889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4257340889
Directory	/workspace/1.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/10.keymgr_alert_test.4004041234
Short name	T595
Test name
Test status
Simulation time	10714718 ps
CPU time	0.86 seconds
Started	Feb 05 03:37:38 PM PST 24
Finished	Feb 05 03:37:41 PM PST 24
Peak memory	205848 kb
Host	smart-3c366410-d8f6-40a0-9ad5-5c79a6571084
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004041234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4004041234
Directory	/workspace/10.keymgr_alert_test/latest

Test location	/workspace/coverage/default/10.keymgr_cfg_regwen.359095705
Short name	T403
Test name
Test status
Simulation time	135126142 ps
CPU time	3.79 seconds
Started	Feb 05 03:37:30 PM PST 24
Finished	Feb 05 03:37:35 PM PST 24
Peak memory	214624 kb
Host	smart-d681542d-9782-4da0-b792-402d08b7c3ae
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=359095705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.359095705
Directory	/workspace/10.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/10.keymgr_lc_disable.2173409761
Short name	T40
Test name
Test status
Simulation time	48763053 ps
CPU time	3.34 seconds
Started	Feb 05 03:37:30 PM PST 24
Finished	Feb 05 03:37:34 PM PST 24
Peak memory	209248 kb
Host	smart-0103b846-89ec-43f2-8e95-2e317c41cb67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173409761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2173409761
Directory	/workspace/10.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/10.keymgr_random.3977593808
Short name	T241
Test name
Test status
Simulation time	610256273 ps
CPU time	8.47 seconds
Started	Feb 05 03:37:31 PM PST 24
Finished	Feb 05 03:37:41 PM PST 24
Peak memory	214200 kb
Host	smart-f830c995-a2e7-4e90-aece-96eabdc1b8ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3977593808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3977593808
Directory	/workspace/10.keymgr_random/latest

Test location	/workspace/coverage/default/10.keymgr_sideload.4092011741
Short name	T755
Test name
Test status
Simulation time	257612707 ps
CPU time	3.51 seconds
Started	Feb 05 03:37:31 PM PST 24
Finished	Feb 05 03:37:37 PM PST 24
Peak memory	208512 kb
Host	smart-7fd6e0c8-f5ff-4baa-b619-3715078f70ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092011741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.4092011741
Directory	/workspace/10.keymgr_sideload/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_aes.1303438914
Short name	T726
Test name
Test status
Simulation time	100599154 ps
CPU time	3.98 seconds
Started	Feb 05 03:37:33 PM PST 24
Finished	Feb 05 03:37:39 PM PST 24
Peak memory	207364 kb
Host	smart-cdb1eed4-09d7-447f-a3cd-c6bd79d660b6
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303438914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1303438914
Directory	/workspace/10.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_kmac.2179495932
Short name	T707
Test name
Test status
Simulation time	247742991 ps
CPU time	4.21 seconds
Started	Feb 05 03:37:33 PM PST 24
Finished	Feb 05 03:37:39 PM PST 24
Peak memory	206872 kb
Host	smart-c6972427-dbd1-43eb-8dbc-8e7e97c6d6e3
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179495932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2179495932
Directory	/workspace/10.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_otbn.1217790991
Short name	T302
Test name
Test status
Simulation time	72799765 ps
CPU time	3.05 seconds
Started	Feb 05 03:37:31 PM PST 24
Finished	Feb 05 03:37:36 PM PST 24
Peak memory	208432 kb
Host	smart-a1fdf9f8-93fd-4536-8dc2-7cee20cfd1aa
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217790991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1217790991
Directory	/workspace/10.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_protect.2590004484
Short name	T375
Test name
Test status
Simulation time	66838452 ps
CPU time	1.98 seconds
Started	Feb 05 03:37:32 PM PST 24
Finished	Feb 05 03:37:36 PM PST 24
Peak memory	207168 kb
Host	smart-6937bef5-a771-492a-be0e-6c1a42874f3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590004484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2590004484
Directory	/workspace/10.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/10.keymgr_smoke.1718464254
Short name	T793
Test name
Test status
Simulation time	127932403 ps
CPU time	3.18 seconds
Started	Feb 05 03:37:30 PM PST 24
Finished	Feb 05 03:37:34 PM PST 24
Peak memory	206656 kb
Host	smart-fb21d519-c6ce-4548-8613-2598dee6fb3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1718464254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1718464254
Directory	/workspace/10.keymgr_smoke/latest

Test location	/workspace/coverage/default/10.keymgr_stress_all.1765111033
Short name	T300
Test name
Test status
Simulation time	21020371771 ps
CPU time	358.74 seconds
Started	Feb 05 03:37:38 PM PST 24
Finished	Feb 05 03:43:40 PM PST 24
Peak memory	219912 kb
Host	smart-64e575c8-e0c1-4a66-b0e4-c51f5508d9e0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765111033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1765111033
Directory	/workspace/10.keymgr_stress_all/latest

Test location	/workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.439320122
Short name	T976
Test name
Test status
Simulation time	432172892 ps
CPU time	3.17 seconds
Started	Feb 05 03:37:34 PM PST 24
Finished	Feb 05 03:37:40 PM PST 24
Peak memory	222664 kb
Host	smart-7462ea85-64cb-49e5-a98e-be9890c58ba1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439320122 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.439320122
Directory	/workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.keymgr_sw_invalid_input.1467776643
Short name	T659
Test name
Test status
Simulation time	118002951 ps
CPU time	5.33 seconds
Started	Feb 05 03:37:30 PM PST 24
Finished	Feb 05 03:37:37 PM PST 24
Peak memory	210012 kb
Host	smart-85516d68-bace-4c54-9799-d0ef5dc63095
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467776643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1467776643
Directory	/workspace/10.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/11.keymgr_alert_test.939936414
Short name	T970
Test name
Test status
Simulation time	13985156 ps
CPU time	0.96 seconds
Started	Feb 05 03:37:36 PM PST 24
Finished	Feb 05 03:37:40 PM PST 24
Peak memory	206068 kb
Host	smart-d0281038-0728-4e48-bb8e-7a0043d65cf0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939936414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.939936414
Directory	/workspace/11.keymgr_alert_test/latest

Test location	/workspace/coverage/default/11.keymgr_cfg_regwen.1558288509
Short name	T809
Test name
Test status
Simulation time	56887706 ps
CPU time	3.91 seconds
Started	Feb 05 03:37:31 PM PST 24
Finished	Feb 05 03:37:37 PM PST 24
Peak memory	214364 kb
Host	smart-020ced21-ab3f-448f-a626-10c955ce9c78
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1558288509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1558288509
Directory	/workspace/11.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/11.keymgr_custom_cm.646343300
Short name	T65
Test name
Test status
Simulation time	163450949 ps
CPU time	4.61 seconds
Started	Feb 05 03:37:33 PM PST 24
Finished	Feb 05 03:37:40 PM PST 24
Peak memory	209260 kb
Host	smart-144d9ff5-bfe3-49de-82bf-a920ee7303af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=646343300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.646343300
Directory	/workspace/11.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/11.keymgr_direct_to_disabled.2512276214
Short name	T1
Test name
Test status
Simulation time	269950704 ps
CPU time	3.44 seconds
Started	Feb 05 03:37:31 PM PST 24
Finished	Feb 05 03:37:36 PM PST 24
Peak memory	209092 kb
Host	smart-9af87d41-6013-4e13-8d31-9cfdb110771c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512276214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2512276214
Directory	/workspace/11.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/11.keymgr_hwsw_invalid_input.2840772311
Short name	T1005
Test name
Test status
Simulation time	86896043 ps
CPU time	4.14 seconds
Started	Feb 05 03:37:30 PM PST 24
Finished	Feb 05 03:37:36 PM PST 24
Peak memory	217872 kb
Host	smart-bf736774-1782-424c-a967-bd88f3893c30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2840772311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2840772311
Directory	/workspace/11.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/11.keymgr_lc_disable.3085000080
Short name	T405
Test name
Test status
Simulation time	1804368417 ps
CPU time	8.94 seconds
Started	Feb 05 03:37:34 PM PST 24
Finished	Feb 05 03:37:46 PM PST 24
Peak memory	219968 kb
Host	smart-776c9e13-1f57-4df5-b479-66ba0ed96c5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085000080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3085000080
Directory	/workspace/11.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/11.keymgr_random.2290227350
Short name	T653
Test name
Test status
Simulation time	81833342 ps
CPU time	4.05 seconds
Started	Feb 05 03:37:31 PM PST 24
Finished	Feb 05 03:37:37 PM PST 24
Peak memory	218120 kb
Host	smart-5533cb9f-d10f-4465-916d-724ad4d52cb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290227350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2290227350
Directory	/workspace/11.keymgr_random/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_aes.2463435570
Short name	T650
Test name
Test status
Simulation time	36575565 ps
CPU time	2.3 seconds
Started	Feb 05 03:37:30 PM PST 24
Finished	Feb 05 03:37:34 PM PST 24
Peak memory	207048 kb
Host	smart-442ee7e5-1a65-42dc-a4ba-3059bd5edec6
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463435570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2463435570
Directory	/workspace/11.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_kmac.2565559951
Short name	T985
Test name
Test status
Simulation time	301205882 ps
CPU time	5 seconds
Started	Feb 05 03:37:29 PM PST 24
Finished	Feb 05 03:37:35 PM PST 24
Peak memory	207024 kb
Host	smart-66b7e708-c366-49f6-8469-218c2db43d69
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565559951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2565559951
Directory	/workspace/11.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_otbn.3370671217
Short name	T702
Test name
Test status
Simulation time	1006996690 ps
CPU time	8.45 seconds
Started	Feb 05 03:37:31 PM PST 24
Finished	Feb 05 03:37:41 PM PST 24
Peak memory	208212 kb
Host	smart-ea4f59aa-a3df-4e76-a700-ec1a52774faa
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370671217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3370671217
Directory	/workspace/11.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_protect.3098773490
Short name	T383
Test name
Test status
Simulation time	116986189 ps
CPU time	2.95 seconds
Started	Feb 05 03:37:35 PM PST 24
Finished	Feb 05 03:37:42 PM PST 24
Peak memory	207712 kb
Host	smart-4daedf35-f16a-4e3e-94e7-def77610e4cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098773490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3098773490
Directory	/workspace/11.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/11.keymgr_smoke.639286707
Short name	T693
Test name
Test status
Simulation time	74100175 ps
CPU time	2.66 seconds
Started	Feb 05 03:37:29 PM PST 24
Finished	Feb 05 03:37:33 PM PST 24
Peak memory	206864 kb
Host	smart-c4d4a37e-4714-4a42-9646-32aa7588b354
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=639286707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.639286707
Directory	/workspace/11.keymgr_smoke/latest

Test location	/workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.221986325
Short name	T590
Test name
Test status
Simulation time	2211155314 ps
CPU time	5.75 seconds
Started	Feb 05 03:37:36 PM PST 24
Finished	Feb 05 03:37:45 PM PST 24
Peak memory	217796 kb
Host	smart-e005af12-2b07-4fae-a080-4cb32c451b2e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221986325 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.221986325
Directory	/workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.keymgr_sw_invalid_input.2559299060
Short name	T282
Test name
Test status
Simulation time	159197388 ps
CPU time	5.99 seconds
Started	Feb 05 03:37:30 PM PST 24
Finished	Feb 05 03:37:37 PM PST 24
Peak memory	207768 kb
Host	smart-23fa92d4-0b18-4451-b7ec-72752e2eab3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559299060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2559299060
Directory	/workspace/11.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/12.keymgr_alert_test.2714931509
Short name	T822
Test name
Test status
Simulation time	75562236 ps
CPU time	0.92 seconds
Started	Feb 05 03:37:34 PM PST 24
Finished	Feb 05 03:37:37 PM PST 24
Peak memory	205964 kb
Host	smart-e6c43586-d301-46ea-b33b-83f57400c1cc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714931509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2714931509
Directory	/workspace/12.keymgr_alert_test/latest

Test location	/workspace/coverage/default/12.keymgr_cfg_regwen.2572430707
Short name	T385
Test name
Test status
Simulation time	335164426 ps
CPU time	5.43 seconds
Started	Feb 05 03:37:39 PM PST 24
Finished	Feb 05 03:37:47 PM PST 24
Peak memory	215384 kb
Host	smart-c0a2f71e-f914-43c6-a1f9-4e7022bdce52
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2572430707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2572430707
Directory	/workspace/12.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/12.keymgr_custom_cm.1326793069
Short name	T28
Test name
Test status
Simulation time	759018386 ps
CPU time	20.59 seconds
Started	Feb 05 03:37:34 PM PST 24
Finished	Feb 05 03:37:57 PM PST 24
Peak memory	222788 kb
Host	smart-cec67525-dddd-4446-b58f-574c346fcc1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1326793069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1326793069
Directory	/workspace/12.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/12.keymgr_direct_to_disabled.2226870551
Short name	T673
Test name
Test status
Simulation time	143477217 ps
CPU time	2.51 seconds
Started	Feb 05 03:37:35 PM PST 24
Finished	Feb 05 03:37:41 PM PST 24
Peak memory	208812 kb
Host	smart-0fd7108f-cf5c-4e14-83ef-f134fe31a300
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2226870551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2226870551
Directory	/workspace/12.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/12.keymgr_hwsw_invalid_input.2163029843
Short name	T87
Test name
Test status
Simulation time	370011133 ps
CPU time	13.22 seconds
Started	Feb 05 03:37:39 PM PST 24
Finished	Feb 05 03:37:54 PM PST 24
Peak memory	219348 kb
Host	smart-83257906-97cf-482e-8dbe-67f061896431
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163029843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2163029843
Directory	/workspace/12.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/12.keymgr_lc_disable.3747895637
Short name	T382
Test name
Test status
Simulation time	156160556 ps
CPU time	2.65 seconds
Started	Feb 05 03:37:32 PM PST 24
Finished	Feb 05 03:37:37 PM PST 24
Peak memory	214304 kb
Host	smart-8c1ca517-1c83-4391-ae53-4250634cf050
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747895637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3747895637
Directory	/workspace/12.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/12.keymgr_random.1284662720
Short name	T971
Test name
Test status
Simulation time	2329398269 ps
CPU time	20.26 seconds
Started	Feb 05 03:37:39 PM PST 24
Finished	Feb 05 03:38:02 PM PST 24
Peak memory	208992 kb
Host	smart-d5fa6412-fc88-4290-bfb4-f10cd70785a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284662720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1284662720
Directory	/workspace/12.keymgr_random/latest

Test location	/workspace/coverage/default/12.keymgr_sideload.3781119889
Short name	T785
Test name
Test status
Simulation time	131372005 ps
CPU time	3.58 seconds
Started	Feb 05 03:37:37 PM PST 24
Finished	Feb 05 03:37:44 PM PST 24
Peak memory	207996 kb
Host	smart-acdf220b-ad7f-48f5-a796-d841d83cbe57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781119889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3781119889
Directory	/workspace/12.keymgr_sideload/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_kmac.2007210462
Short name	T720
Test name
Test status
Simulation time	1145672530 ps
CPU time	9.24 seconds
Started	Feb 05 03:37:34 PM PST 24
Finished	Feb 05 03:37:46 PM PST 24
Peak memory	208732 kb
Host	smart-916ccdda-417f-4b59-9a50-2138f5c64988
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007210462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2007210462
Directory	/workspace/12.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_otbn.4242608553
Short name	T989
Test name
Test status
Simulation time	5475822589 ps
CPU time	15.12 seconds
Started	Feb 05 03:37:38 PM PST 24
Finished	Feb 05 03:37:56 PM PST 24
Peak memory	209028 kb
Host	smart-331ae6f6-de1d-4f89-983f-82eeb7afee53
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242608553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4242608553
Directory	/workspace/12.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_protect.2785275112
Short name	T978
Test name
Test status
Simulation time	694602853 ps
CPU time	3.78 seconds
Started	Feb 05 03:37:37 PM PST 24
Finished	Feb 05 03:37:44 PM PST 24
Peak memory	209380 kb
Host	smart-cb0bad46-3f6e-4a87-9d27-ed47f4850d83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785275112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2785275112
Directory	/workspace/12.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/12.keymgr_smoke.1321061588
Short name	T16
Test name
Test status
Simulation time	56627867 ps
CPU time	2.72 seconds
Started	Feb 05 03:37:34 PM PST 24
Finished	Feb 05 03:37:39 PM PST 24
Peak memory	207024 kb
Host	smart-e5bfec1b-ea13-445b-90a8-6a26755d307a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321061588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1321061588
Directory	/workspace/12.keymgr_smoke/latest

Test location	/workspace/coverage/default/12.keymgr_sw_invalid_input.2200385850
Short name	T975
Test name
Test status
Simulation time	52214444 ps
CPU time	3.63 seconds
Started	Feb 05 03:37:37 PM PST 24
Finished	Feb 05 03:37:44 PM PST 24
Peak memory	210220 kb
Host	smart-a7f882bc-b6c0-4909-81eb-9324e00d77fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2200385850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2200385850
Directory	/workspace/12.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/12.keymgr_sync_async_fault_cross.960156259
Short name	T882
Test name
Test status
Simulation time	213964699 ps
CPU time	1.96 seconds
Started	Feb 05 03:37:40 PM PST 24
Finished	Feb 05 03:37:44 PM PST 24
Peak memory	209580 kb
Host	smart-38feb62f-c06c-4282-96b5-49b92f7e6dde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960156259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.960156259
Directory	/workspace/12.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/13.keymgr_alert_test.3107101572
Short name	T796
Test name
Test status
Simulation time	93654309 ps
CPU time	0.9 seconds
Started	Feb 05 03:37:49 PM PST 24
Finished	Feb 05 03:37:57 PM PST 24
Peak memory	205884 kb
Host	smart-45a39852-b9fd-48a0-86bd-6f8753b81948
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107101572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3107101572
Directory	/workspace/13.keymgr_alert_test/latest

Test location	/workspace/coverage/default/13.keymgr_custom_cm.2545356467
Short name	T32
Test name
Test status
Simulation time	358604249 ps
CPU time	4.15 seconds
Started	Feb 05 03:37:45 PM PST 24
Finished	Feb 05 03:37:56 PM PST 24
Peak memory	209888 kb
Host	smart-93b260fe-73a4-4476-852a-e6987208b096
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545356467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2545356467
Directory	/workspace/13.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/13.keymgr_direct_to_disabled.1791215092
Short name	T393
Test name
Test status
Simulation time	341612492 ps
CPU time	3.49 seconds
Started	Feb 05 03:37:37 PM PST 24
Finished	Feb 05 03:37:44 PM PST 24
Peak memory	207740 kb
Host	smart-e944de25-af54-4f1c-b32f-a12c7a17eef6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1791215092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1791215092
Directory	/workspace/13.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/13.keymgr_hwsw_invalid_input.3287622373
Short name	T90
Test name
Test status
Simulation time	850792874 ps
CPU time	6.49 seconds
Started	Feb 05 03:37:48 PM PST 24
Finished	Feb 05 03:38:02 PM PST 24
Peak memory	209092 kb
Host	smart-43306277-faf9-4c6a-8834-6ffd56f25112
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287622373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3287622373
Directory	/workspace/13.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/13.keymgr_lc_disable.1617742827
Short name	T681
Test name
Test status
Simulation time	36650641 ps
CPU time	2.63 seconds
Started	Feb 05 03:37:48 PM PST 24
Finished	Feb 05 03:37:59 PM PST 24
Peak memory	222428 kb
Host	smart-0f95f923-0945-49d4-8d21-38c0c44c2a32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1617742827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1617742827
Directory	/workspace/13.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/13.keymgr_random.1530519280
Short name	T961
Test name
Test status
Simulation time	146124025 ps
CPU time	2.6 seconds
Started	Feb 05 03:37:40 PM PST 24
Finished	Feb 05 03:37:45 PM PST 24
Peak memory	207784 kb
Host	smart-32694df1-7e5a-44e9-847c-6efedb52f510
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530519280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1530519280
Directory	/workspace/13.keymgr_random/latest

Test location	/workspace/coverage/default/13.keymgr_sideload.1611105664
Short name	T787
Test name
Test status
Simulation time	858447941 ps
CPU time	6.01 seconds
Started	Feb 05 03:37:36 PM PST 24
Finished	Feb 05 03:37:45 PM PST 24
Peak memory	208508 kb
Host	smart-1d5096f2-60cb-4864-85aa-539f511a7153
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611105664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1611105664
Directory	/workspace/13.keymgr_sideload/latest

Test location	/workspace/coverage/default/13.keymgr_sideload_aes.1303344277
Short name	T847
Test name
Test status
Simulation time	59903078 ps
CPU time	2.96 seconds
Started	Feb 05 03:37:39 PM PST 24
Finished	Feb 05 03:37:45 PM PST 24
Peak memory	208416 kb
Host	smart-39055d98-f09b-4660-938c-eb81da0c2733
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303344277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1303344277
Directory	/workspace/13.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/13.keymgr_sideload_kmac.740754667
Short name	T969
Test name
Test status
Simulation time	195418092 ps
CPU time	7.26 seconds
Started	Feb 05 03:37:37 PM PST 24
Finished	Feb 05 03:37:47 PM PST 24
Peak memory	208320 kb
Host	smart-f26ed42b-abe7-418c-8ace-9639c2402504
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740754667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.740754667
Directory	/workspace/13.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/13.keymgr_sideload_protect.1790020726
Short name	T995
Test name
Test status
Simulation time	168586773 ps
CPU time	3.85 seconds
Started	Feb 05 03:37:56 PM PST 24
Finished	Feb 05 03:38:10 PM PST 24
Peak memory	209668 kb
Host	smart-4359e258-ac85-425c-b0f4-fefa764b8feb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1790020726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1790020726
Directory	/workspace/13.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/13.keymgr_smoke.2971431745
Short name	T753
Test name
Test status
Simulation time	1037782575 ps
CPU time	11.87 seconds
Started	Feb 05 03:37:35 PM PST 24
Finished	Feb 05 03:37:51 PM PST 24
Peak memory	208660 kb
Host	smart-5132d5e8-f0f2-4476-a7ee-b83738b9f75e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2971431745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2971431745
Directory	/workspace/13.keymgr_smoke/latest

Test location	/workspace/coverage/default/13.keymgr_stress_all.164558152
Short name	T278
Test name
Test status
Simulation time	914026002 ps
CPU time	20 seconds
Started	Feb 05 03:37:44 PM PST 24
Finished	Feb 05 03:38:09 PM PST 24
Peak memory	215764 kb
Host	smart-39f4a17c-1b6f-4b35-836d-07c45ff2fda5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164558152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.164558152
Directory	/workspace/13.keymgr_stress_all/latest

Test location	/workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1629989204
Short name	T271
Test name
Test status
Simulation time	220273141 ps
CPU time	3.97 seconds
Started	Feb 05 03:37:47 PM PST 24
Finished	Feb 05 03:37:59 PM PST 24
Peak memory	222620 kb
Host	smart-adda2b73-5311-4736-8059-821dc5fddbb7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629989204 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1629989204
Directory	/workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.keymgr_sw_invalid_input.2239188638
Short name	T220
Test name
Test status
Simulation time	436013836 ps
CPU time	5.33 seconds
Started	Feb 05 03:37:44 PM PST 24
Finished	Feb 05 03:37:53 PM PST 24
Peak memory	218420 kb
Host	smart-5e3336c2-c7f1-496b-8d62-e8747bd20155
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239188638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2239188638
Directory	/workspace/13.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/14.keymgr_direct_to_disabled.1624187426
Short name	T654
Test name
Test status
Simulation time	103790583 ps
CPU time	3.61 seconds
Started	Feb 05 03:37:47 PM PST 24
Finished	Feb 05 03:37:59 PM PST 24
Peak memory	209320 kb
Host	smart-32a26444-e63b-4dda-aeec-cc33c5a74b8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1624187426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1624187426
Directory	/workspace/14.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/14.keymgr_hwsw_invalid_input.2111214789
Short name	T352
Test name
Test status
Simulation time	213953372 ps
CPU time	5.7 seconds
Started	Feb 05 03:37:47 PM PST 24
Finished	Feb 05 03:38:01 PM PST 24
Peak memory	218544 kb
Host	smart-0959007f-1b89-4fd8-a94e-86f515a9a3f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2111214789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2111214789
Directory	/workspace/14.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/14.keymgr_lc_disable.3706285206
Short name	T210
Test name
Test status
Simulation time	104084277 ps
CPU time	3.25 seconds
Started	Feb 05 03:37:53 PM PST 24
Finished	Feb 05 03:38:01 PM PST 24
Peak memory	207952 kb
Host	smart-3f660fd4-5d4e-46bf-a01e-8352a960d01f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3706285206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3706285206
Directory	/workspace/14.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_aes.3416886938
Short name	T105
Test name
Test status
Simulation time	249952775 ps
CPU time	3.05 seconds
Started	Feb 05 03:37:48 PM PST 24
Finished	Feb 05 03:37:59 PM PST 24
Peak memory	207864 kb
Host	smart-41177603-be29-460f-8230-fe4df9b9c540
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416886938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3416886938
Directory	/workspace/14.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_kmac.3742600857
Short name	T727
Test name
Test status
Simulation time	305339766 ps
CPU time	8.2 seconds
Started	Feb 05 03:37:47 PM PST 24
Finished	Feb 05 03:38:04 PM PST 24
Peak memory	207872 kb
Host	smart-b0c4bc46-adac-4dc1-9793-66f492f4014a
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742600857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3742600857
Directory	/workspace/14.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_otbn.3285065898
Short name	T735
Test name
Test status
Simulation time	6772257148 ps
CPU time	27.78 seconds
Started	Feb 05 03:37:45 PM PST 24
Finished	Feb 05 03:38:20 PM PST 24
Peak memory	207976 kb
Host	smart-b0354654-60b9-4fa0-9535-aa8f7c4b2c0c
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285065898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3285065898
Directory	/workspace/14.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_protect.2298987509
Short name	T616
Test name
Test status
Simulation time	56188548 ps
CPU time	3.17 seconds
Started	Feb 05 03:37:50 PM PST 24
Finished	Feb 05 03:38:00 PM PST 24
Peak memory	215528 kb
Host	smart-5c5e54ca-bd95-44ef-b436-7344739e2f0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298987509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2298987509
Directory	/workspace/14.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/14.keymgr_smoke.976957109
Short name	T180
Test name
Test status
Simulation time	111661357 ps
CPU time	2.23 seconds
Started	Feb 05 03:37:53 PM PST 24
Finished	Feb 05 03:38:00 PM PST 24
Peak memory	206104 kb
Host	smart-4187f893-443e-49c7-adad-9b6f1048a5b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=976957109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.976957109
Directory	/workspace/14.keymgr_smoke/latest

Test location	/workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3309850936
Short name	T826
Test name
Test status
Simulation time	798583123 ps
CPU time	8.35 seconds
Started	Feb 05 03:37:47 PM PST 24
Finished	Feb 05 03:38:04 PM PST 24
Peak memory	222588 kb
Host	smart-3537481e-5c73-455a-af0b-695a04a5dfba
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309850936 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3309850936
Directory	/workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.keymgr_sw_invalid_input.3598765566
Short name	T358
Test name
Test status
Simulation time	362531822 ps
CPU time	7.5 seconds
Started	Feb 05 03:37:47 PM PST 24
Finished	Feb 05 03:38:03 PM PST 24
Peak memory	218352 kb
Host	smart-a08c8fcf-600c-466a-b525-08dff1ae028b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598765566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3598765566
Directory	/workspace/14.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/14.keymgr_sync_async_fault_cross.4267635597
Short name	T703
Test name
Test status
Simulation time	123241169 ps
CPU time	2.82 seconds
Started	Feb 05 03:37:49 PM PST 24
Finished	Feb 05 03:37:59 PM PST 24
Peak memory	210360 kb
Host	smart-1e8f198e-5cd0-49ad-aafe-148c1a7bf804
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4267635597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.4267635597
Directory	/workspace/14.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/15.keymgr_alert_test.3032424548
Short name	T838
Test name
Test status
Simulation time	10770999 ps
CPU time	0.79 seconds
Started	Feb 05 03:37:56 PM PST 24
Finished	Feb 05 03:38:06 PM PST 24
Peak memory	205864 kb
Host	smart-c5076064-fe4e-4f9d-87b0-873f8a357354
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032424548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3032424548
Directory	/workspace/15.keymgr_alert_test/latest

Test location	/workspace/coverage/default/15.keymgr_cfg_regwen.2111022739
Short name	T276
Test name
Test status
Simulation time	2451894534 ps
CPU time	10.03 seconds
Started	Feb 05 03:37:52 PM PST 24
Finished	Feb 05 03:38:07 PM PST 24
Peak memory	215800 kb
Host	smart-ada99ec3-7a44-4b5f-9453-208b35dea95f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2111022739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2111022739
Directory	/workspace/15.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/15.keymgr_custom_cm.2093497587
Short name	T716
Test name
Test status
Simulation time	376162711 ps
CPU time	3.31 seconds
Started	Feb 05 03:37:57 PM PST 24
Finished	Feb 05 03:38:10 PM PST 24
Peak memory	214516 kb
Host	smart-dd4593ec-8e03-4ea8-b9a9-f9344f4601fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2093497587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2093497587
Directory	/workspace/15.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/15.keymgr_hwsw_invalid_input.3559872691
Short name	T321
Test name
Test status
Simulation time	6773315149 ps
CPU time	43.92 seconds
Started	Feb 05 03:37:57 PM PST 24
Finished	Feb 05 03:38:51 PM PST 24
Peak memory	222544 kb
Host	smart-770a6eb7-e9bd-4f59-a92d-48c7b9964eaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3559872691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3559872691
Directory	/workspace/15.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/15.keymgr_kmac_rsp_err.1738054090
Short name	T874
Test name
Test status
Simulation time	2710555377 ps
CPU time	25.48 seconds
Started	Feb 05 03:37:49 PM PST 24
Finished	Feb 05 03:38:22 PM PST 24
Peak memory	214380 kb
Host	smart-629b8932-e53f-4a60-a72d-d4e0d3a7931f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1738054090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1738054090
Directory	/workspace/15.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/15.keymgr_random.2097598973
Short name	T901
Test name
Test status
Simulation time	303578060 ps
CPU time	10.94 seconds
Started	Feb 05 03:37:47 PM PST 24
Finished	Feb 05 03:38:06 PM PST 24
Peak memory	214304 kb
Host	smart-7c29eb9b-4cab-41ef-ae7f-af10b22da72a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097598973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2097598973
Directory	/workspace/15.keymgr_random/latest

Test location	/workspace/coverage/default/15.keymgr_sideload.3742748996
Short name	T15
Test name
Test status
Simulation time	891089679 ps
CPU time	16.35 seconds
Started	Feb 05 03:37:44 PM PST 24
Finished	Feb 05 03:38:04 PM PST 24
Peak memory	207988 kb
Host	smart-8f2346ee-6420-49d4-8bca-30ef84708e21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3742748996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3742748996
Directory	/workspace/15.keymgr_sideload/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_aes.1212140780
Short name	T254
Test name
Test status
Simulation time	34635674 ps
CPU time	2.6 seconds
Started	Feb 05 03:37:59 PM PST 24
Finished	Feb 05 03:38:15 PM PST 24
Peak memory	208840 kb
Host	smart-67ec62d0-7baa-4d3c-a612-ffe4ba21ad6e
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212140780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1212140780
Directory	/workspace/15.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_kmac.2445570095
Short name	T649
Test name
Test status
Simulation time	101253687 ps
CPU time	3.66 seconds
Started	Feb 05 03:37:44 PM PST 24
Finished	Feb 05 03:37:52 PM PST 24
Peak memory	208404 kb
Host	smart-d4492ae4-e1eb-4d36-961e-703d25377bd6
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445570095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2445570095
Directory	/workspace/15.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_otbn.2087898703
Short name	T743
Test name
Test status
Simulation time	1053635945 ps
CPU time	8.32 seconds
Started	Feb 05 03:37:57 PM PST 24
Finished	Feb 05 03:38:18 PM PST 24
Peak memory	208020 kb
Host	smart-bfac7bd7-17ef-44c4-ae33-aa5da4ae331b
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087898703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2087898703
Directory	/workspace/15.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_protect.3738522926
Short name	T769
Test name
Test status
Simulation time	138527570 ps
CPU time	3.65 seconds
Started	Feb 05 03:37:55 PM PST 24
Finished	Feb 05 03:38:02 PM PST 24
Peak memory	208560 kb
Host	smart-ac6de96a-a013-4539-8ab8-cb33a1a3a023
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738522926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3738522926
Directory	/workspace/15.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/15.keymgr_smoke.2693762195
Short name	T946
Test name
Test status
Simulation time	97723538 ps
CPU time	2.79 seconds
Started	Feb 05 03:37:49 PM PST 24
Finished	Feb 05 03:37:59 PM PST 24
Peak memory	207104 kb
Host	smart-35f4f284-36bf-4ebd-bf3a-a7177f510d73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693762195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2693762195
Directory	/workspace/15.keymgr_smoke/latest

Test location	/workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.729027798
Short name	T195
Test name
Test status
Simulation time	647060355 ps
CPU time	5.65 seconds
Started	Feb 05 03:37:50 PM PST 24
Finished	Feb 05 03:38:03 PM PST 24
Peak memory	222596 kb
Host	smart-6647f140-86f8-4c73-ae01-110d5e17989a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729027798 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.729027798
Directory	/workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.keymgr_sw_invalid_input.2922450767
Short name	T262
Test name
Test status
Simulation time	371256671 ps
CPU time	5.52 seconds
Started	Feb 05 03:37:53 PM PST 24
Finished	Feb 05 03:38:03 PM PST 24
Peak memory	207760 kb
Host	smart-839abb70-275b-420b-9661-ee9093c68a60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2922450767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2922450767
Directory	/workspace/15.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/15.keymgr_sync_async_fault_cross.1526986785
Short name	T161
Test name
Test status
Simulation time	4087864036 ps
CPU time	24.3 seconds
Started	Feb 05 03:37:53 PM PST 24
Finished	Feb 05 03:38:22 PM PST 24
Peak memory	211464 kb
Host	smart-08194b48-6f96-4806-8a8a-f10569d6a06d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1526986785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1526986785
Directory	/workspace/15.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/16.keymgr_alert_test.506400114
Short name	T552
Test name
Test status
Simulation time	43073625 ps
CPU time	0.91 seconds
Started	Feb 05 03:37:57 PM PST 24
Finished	Feb 05 03:38:11 PM PST 24
Peak memory	205884 kb
Host	smart-c2f532a4-a30a-42d7-9832-b21397fb79d9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506400114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.506400114
Directory	/workspace/16.keymgr_alert_test/latest

Test location	/workspace/coverage/default/16.keymgr_cfg_regwen.1332075659
Short name	T960
Test name
Test status
Simulation time	2707651281 ps
CPU time	38.08 seconds
Started	Feb 05 03:37:58 PM PST 24
Finished	Feb 05 03:38:48 PM PST 24
Peak memory	222588 kb
Host	smart-898c8a47-9558-4b39-ba29-76ffa1929171
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1332075659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1332075659
Directory	/workspace/16.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/16.keymgr_custom_cm.1314007029
Short name	T851
Test name
Test status
Simulation time	509434966 ps
CPU time	7.66 seconds
Started	Feb 05 03:37:56 PM PST 24
Finished	Feb 05 03:38:13 PM PST 24
Peak memory	221860 kb
Host	smart-594f94ca-1a9c-4047-9d43-395d214cf5fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1314007029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1314007029
Directory	/workspace/16.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/16.keymgr_direct_to_disabled.1072074232
Short name	T706
Test name
Test status
Simulation time	857719549 ps
CPU time	6.59 seconds
Started	Feb 05 03:37:56 PM PST 24
Finished	Feb 05 03:38:11 PM PST 24
Peak memory	218276 kb
Host	smart-aaa79323-1177-4c98-82ce-1c316d75b904
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072074232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1072074232
Directory	/workspace/16.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/16.keymgr_hwsw_invalid_input.87708260
Short name	T22
Test name
Test status
Simulation time	73829073 ps
CPU time	2.83 seconds
Started	Feb 05 03:37:56 PM PST 24
Finished	Feb 05 03:38:08 PM PST 24
Peak memory	219424 kb
Host	smart-20e60fb2-0e24-4968-8874-c35ffdd62d38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87708260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.87708260
Directory	/workspace/16.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/16.keymgr_lc_disable.1482521033
Short name	T795
Test name
Test status
Simulation time	109084887 ps
CPU time	4.27 seconds
Started	Feb 05 03:37:54 PM PST 24
Finished	Feb 05 03:38:02 PM PST 24
Peak memory	214552 kb
Host	smart-9305bbd2-6954-4171-9b6c-f45cf5d0d2fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1482521033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1482521033
Directory	/workspace/16.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/16.keymgr_sideload.148002866
Short name	T185
Test name
Test status
Simulation time	1651977050 ps
CPU time	36.69 seconds
Started	Feb 05 03:37:56 PM PST 24
Finished	Feb 05 03:38:41 PM PST 24
Peak memory	207796 kb
Host	smart-f275ffe6-2ed7-4dfa-ba11-af4b512f376b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=148002866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.148002866
Directory	/workspace/16.keymgr_sideload/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_aes.2580407762
Short name	T982
Test name
Test status
Simulation time	443892036 ps
CPU time	6.8 seconds
Started	Feb 05 03:37:49 PM PST 24
Finished	Feb 05 03:38:03 PM PST 24
Peak memory	208592 kb
Host	smart-9becefd5-d3a8-47df-9fb1-47b75760e778
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580407762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2580407762
Directory	/workspace/16.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_kmac.1475972970
Short name	T360
Test name
Test status
Simulation time	438915366 ps
CPU time	13.55 seconds
Started	Feb 05 03:37:48 PM PST 24
Finished	Feb 05 03:38:09 PM PST 24
Peak memory	208796 kb
Host	smart-91f853be-f884-46d2-b328-edea7abd2759
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475972970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1475972970
Directory	/workspace/16.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_otbn.1260165860
Short name	T999
Test name
Test status
Simulation time	89730558 ps
CPU time	3.12 seconds
Started	Feb 05 03:37:59 PM PST 24
Finished	Feb 05 03:38:16 PM PST 24
Peak memory	206908 kb
Host	smart-4b473205-fc6a-4c78-b075-13be441e014e
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260165860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1260165860
Directory	/workspace/16.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_protect.771423551
Short name	T392
Test name
Test status
Simulation time	1290492841 ps
CPU time	11.77 seconds
Started	Feb 05 03:37:47 PM PST 24
Finished	Feb 05 03:38:07 PM PST 24
Peak memory	209364 kb
Host	smart-f7a1d600-0fdf-4f2e-92e5-855f9f79310d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771423551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.771423551
Directory	/workspace/16.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/16.keymgr_smoke.1323054285
Short name	T839
Test name
Test status
Simulation time	185694884 ps
CPU time	2.5 seconds
Started	Feb 05 03:37:55 PM PST 24
Finished	Feb 05 03:38:01 PM PST 24
Peak memory	208324 kb
Host	smart-43e7522a-93e8-403d-b735-5dcaa4e60fc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323054285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1323054285
Directory	/workspace/16.keymgr_smoke/latest

Test location	/workspace/coverage/default/16.keymgr_stress_all.1553464823
Short name	T886
Test name
Test status
Simulation time	181530304 ps
CPU time	4.83 seconds
Started	Feb 05 03:37:58 PM PST 24
Finished	Feb 05 03:38:15 PM PST 24
Peak memory	214416 kb
Host	smart-9c217ecf-4c39-4a8c-b1bc-128a453dd836
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553464823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1553464823
Directory	/workspace/16.keymgr_stress_all/latest

Test location	/workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.811030436
Short name	T400
Test name
Test status
Simulation time	80540370 ps
CPU time	2.78 seconds
Started	Feb 05 03:37:56 PM PST 24
Finished	Feb 05 03:38:07 PM PST 24
Peak memory	214388 kb
Host	smart-7b4933e2-2bb8-46c9-9460-640c2787218f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811030436 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.811030436
Directory	/workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.keymgr_sw_invalid_input.1847296221
Short name	T128
Test name
Test status
Simulation time	298369168 ps
CPU time	3.62 seconds
Started	Feb 05 03:37:50 PM PST 24
Finished	Feb 05 03:38:01 PM PST 24
Peak memory	207660 kb
Host	smart-b772cb40-6de2-4c15-8eb5-0da5c458bf0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1847296221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1847296221
Directory	/workspace/16.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/16.keymgr_sync_async_fault_cross.2078292138
Short name	T923
Test name
Test status
Simulation time	40337297 ps
CPU time	2.13 seconds
Started	Feb 05 03:37:51 PM PST 24
Finished	Feb 05 03:37:59 PM PST 24
Peak memory	209752 kb
Host	smart-b6977912-4dd0-48a3-a65c-03b7ef13b4d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078292138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2078292138
Directory	/workspace/16.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/17.keymgr_alert_test.3908121324
Short name	T779
Test name
Test status
Simulation time	13962215 ps
CPU time	0.94 seconds
Started	Feb 05 03:38:01 PM PST 24
Finished	Feb 05 03:38:14 PM PST 24
Peak memory	206024 kb
Host	smart-0a75d1ab-8081-45f6-ae08-7f0d690495b3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908121324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3908121324
Directory	/workspace/17.keymgr_alert_test/latest

Test location	/workspace/coverage/default/17.keymgr_direct_to_disabled.596150147
Short name	T792
Test name
Test status
Simulation time	72403541 ps
CPU time	3.04 seconds
Started	Feb 05 03:38:01 PM PST 24
Finished	Feb 05 03:38:16 PM PST 24
Peak memory	218452 kb
Host	smart-7c2aad06-a94d-49d4-bf1b-905ec3a38555
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596150147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.596150147
Directory	/workspace/17.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/17.keymgr_hwsw_invalid_input.693979465
Short name	T914
Test name
Test status
Simulation time	1439654282 ps
CPU time	13.7 seconds
Started	Feb 05 03:38:01 PM PST 24
Finished	Feb 05 03:38:26 PM PST 24
Peak memory	214380 kb
Host	smart-b8a3b010-da17-4b8c-b6ed-6418f45e079f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=693979465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.693979465
Directory	/workspace/17.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/17.keymgr_kmac_rsp_err.1754441901
Short name	T767
Test name
Test status
Simulation time	5232521443 ps
CPU time	62.5 seconds
Started	Feb 05 03:38:01 PM PST 24
Finished	Feb 05 03:39:15 PM PST 24
Peak memory	221628 kb
Host	smart-0c0690c9-0343-4d80-ba36-9eef6f1783f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754441901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1754441901
Directory	/workspace/17.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/17.keymgr_lc_disable.304815956
Short name	T997
Test name
Test status
Simulation time	167318090 ps
CPU time	3.75 seconds
Started	Feb 05 03:37:56 PM PST 24
Finished	Feb 05 03:38:09 PM PST 24
Peak memory	208268 kb
Host	smart-9a6dc9f2-e42e-4910-917d-fc3edb9d7b9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304815956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.304815956
Directory	/workspace/17.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/17.keymgr_random.514191463
Short name	T783
Test name
Test status
Simulation time	531606734 ps
CPU time	8.38 seconds
Started	Feb 05 03:38:02 PM PST 24
Finished	Feb 05 03:38:22 PM PST 24
Peak memory	208764 kb
Host	smart-27ef49b1-4d9a-42b5-9d0c-5c2f61902cc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514191463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.514191463
Directory	/workspace/17.keymgr_random/latest

Test location	/workspace/coverage/default/17.keymgr_sideload.1813763293
Short name	T38
Test name
Test status
Simulation time	33245132 ps
CPU time	2.21 seconds
Started	Feb 05 03:37:56 PM PST 24
Finished	Feb 05 03:38:07 PM PST 24
Peak memory	206712 kb
Host	smart-c2ed1843-dacb-47b6-af61-6355c1c066bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813763293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1813763293
Directory	/workspace/17.keymgr_sideload/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_aes.475166431
Short name	T364
Test name
Test status
Simulation time	9746026847 ps
CPU time	65.21 seconds
Started	Feb 05 03:37:57 PM PST 24
Finished	Feb 05 03:39:12 PM PST 24
Peak memory	208476 kb
Host	smart-a4fcca6d-ea44-4b87-b002-54f5bf7bfea7
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475166431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.475166431
Directory	/workspace/17.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_kmac.2793481084
Short name	T920
Test name
Test status
Simulation time	146818282 ps
CPU time	2.82 seconds
Started	Feb 05 03:38:03 PM PST 24
Finished	Feb 05 03:38:16 PM PST 24
Peak memory	208588 kb
Host	smart-e9995689-f0dc-47b3-ba64-e04427b9d51f
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793481084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2793481084
Directory	/workspace/17.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_otbn.1564546454
Short name	T817
Test name
Test status
Simulation time	42556090 ps
CPU time	2.44 seconds
Started	Feb 05 03:37:56 PM PST 24
Finished	Feb 05 03:38:08 PM PST 24
Peak memory	208028 kb
Host	smart-4b7270a1-5031-49d6-a851-a6b9e791e3f1
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564546454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1564546454
Directory	/workspace/17.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_protect.1455008369
Short name	T791
Test name
Test status
Simulation time	52737288 ps
CPU time	2.48 seconds
Started	Feb 05 03:37:57 PM PST 24
Finished	Feb 05 03:38:09 PM PST 24
Peak memory	210104 kb
Host	smart-fa4255c2-7476-44e3-8cb0-be576718f83f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1455008369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1455008369
Directory	/workspace/17.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/17.keymgr_smoke.2556681376
Short name	T671
Test name
Test status
Simulation time	140063751 ps
CPU time	2.69 seconds
Started	Feb 05 03:37:57 PM PST 24
Finished	Feb 05 03:38:12 PM PST 24
Peak memory	206748 kb
Host	smart-07ca2307-d54e-4917-8dbf-0a4161c8ed89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556681376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2556681376
Directory	/workspace/17.keymgr_smoke/latest

Test location	/workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.4017609042
Short name	T99
Test name
Test status
Simulation time	916700241 ps
CPU time	7.74 seconds
Started	Feb 05 03:37:54 PM PST 24
Finished	Feb 05 03:38:06 PM PST 24
Peak memory	222616 kb
Host	smart-e4572ec1-60c0-479a-b4da-49720a7f615b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017609042 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.4017609042
Directory	/workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.keymgr_sw_invalid_input.2660008498
Short name	T1001
Test name
Test status
Simulation time	212351765 ps
CPU time	3.59 seconds
Started	Feb 05 03:38:04 PM PST 24
Finished	Feb 05 03:38:18 PM PST 24
Peak memory	209800 kb
Host	smart-ae863607-ef8e-4868-a75d-04583488fd5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660008498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2660008498
Directory	/workspace/17.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/17.keymgr_sync_async_fault_cross.3244237710
Short name	T376
Test name
Test status
Simulation time	3825724194 ps
CPU time	20.16 seconds
Started	Feb 05 03:38:02 PM PST 24
Finished	Feb 05 03:38:34 PM PST 24
Peak memory	211660 kb
Host	smart-6a40fa1d-916a-4e90-9b51-19ddc759d7ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244237710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3244237710
Directory	/workspace/17.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/18.keymgr_alert_test.156252376
Short name	T555
Test name
Test status
Simulation time	20586668 ps
CPU time	0.75 seconds
Started	Feb 05 03:38:26 PM PST 24
Finished	Feb 05 03:38:34 PM PST 24
Peak memory	205880 kb
Host	smart-187023cb-6950-456f-9e51-46f02e02fb90
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156252376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.156252376
Directory	/workspace/18.keymgr_alert_test/latest

Test location	/workspace/coverage/default/18.keymgr_direct_to_disabled.135713677
Short name	T68
Test name
Test status
Simulation time	45211097 ps
CPU time	1.55 seconds
Started	Feb 05 03:38:01 PM PST 24
Finished	Feb 05 03:38:14 PM PST 24
Peak memory	208284 kb
Host	smart-c7e8531c-637b-4861-bf23-4bc23b0a1d8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=135713677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.135713677
Directory	/workspace/18.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/18.keymgr_lc_disable.3458661030
Short name	T689
Test name
Test status
Simulation time	123952535 ps
CPU time	3.87 seconds
Started	Feb 05 03:37:58 PM PST 24
Finished	Feb 05 03:38:17 PM PST 24
Peak memory	222476 kb
Host	smart-564cdcda-5b32-4677-a0a8-dc3e71a1086a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458661030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3458661030
Directory	/workspace/18.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_aes.2235527716
Short name	T600
Test name
Test status
Simulation time	69952081 ps
CPU time	3.63 seconds
Started	Feb 05 03:37:55 PM PST 24
Finished	Feb 05 03:38:02 PM PST 24
Peak memory	206880 kb
Host	smart-7d4be0c0-2618-42d6-baef-187014010829
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235527716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2235527716
Directory	/workspace/18.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_kmac.1676372842
Short name	T260
Test name
Test status
Simulation time	148780708 ps
CPU time	5.03 seconds
Started	Feb 05 03:38:03 PM PST 24
Finished	Feb 05 03:38:18 PM PST 24
Peak memory	208792 kb
Host	smart-94d3f3d7-f8eb-4c5d-84e9-2013079605db
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676372842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1676372842
Directory	/workspace/18.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_otbn.3991940589
Short name	T959
Test name
Test status
Simulation time	38419707 ps
CPU time	2.69 seconds
Started	Feb 05 03:37:59 PM PST 24
Finished	Feb 05 03:38:15 PM PST 24
Peak memory	208784 kb
Host	smart-9355e68f-89e8-4632-9247-4ea00858e304
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991940589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3991940589
Directory	/workspace/18.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_protect.378979671
Short name	T103
Test name
Test status
Simulation time	322200979 ps
CPU time	6.75 seconds
Started	Feb 05 03:37:59 PM PST 24
Finished	Feb 05 03:38:19 PM PST 24
Peak memory	210168 kb
Host	smart-e408e6a1-b687-4f8b-adc9-1d3e3c1c52ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=378979671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.378979671
Directory	/workspace/18.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/18.keymgr_smoke.1973417040
Short name	T179
Test name
Test status
Simulation time	79708829 ps
CPU time	3.75 seconds
Started	Feb 05 03:37:59 PM PST 24
Finished	Feb 05 03:38:17 PM PST 24
Peak memory	208480 kb
Host	smart-26fb54a1-3165-4065-8b64-641faf69cb9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1973417040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1973417040
Directory	/workspace/18.keymgr_smoke/latest

Test location	/workspace/coverage/default/18.keymgr_stress_all.1463639346
Short name	T610
Test name
Test status
Simulation time	18598971 ps
CPU time	0.75 seconds
Started	Feb 05 03:38:13 PM PST 24
Finished	Feb 05 03:38:23 PM PST 24
Peak memory	205784 kb
Host	smart-58a30037-aa9d-4d9a-91bd-1cfacf05cffc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463639346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1463639346
Directory	/workspace/18.keymgr_stress_all/latest

Test location	/workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.4053411506
Short name	T836
Test name
Test status
Simulation time	342719992 ps
CPU time	7.7 seconds
Started	Feb 05 03:38:20 PM PST 24
Finished	Feb 05 03:38:36 PM PST 24
Peak memory	222600 kb
Host	smart-c24d7f43-9605-40f2-83d2-6f99d9fc32c9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053411506 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.4053411506
Directory	/workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.keymgr_sw_invalid_input.2446096581
Short name	T108
Test name
Test status
Simulation time	388443539 ps
CPU time	5.45 seconds
Started	Feb 05 03:38:10 PM PST 24
Finished	Feb 05 03:38:26 PM PST 24
Peak memory	209864 kb
Host	smart-44f3da2f-417a-4ae8-8b44-1b613d51c7b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446096581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2446096581
Directory	/workspace/18.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/19.keymgr_alert_test.3866922152
Short name	T887
Test name
Test status
Simulation time	61770201 ps
CPU time	0.83 seconds
Started	Feb 05 03:38:05 PM PST 24
Finished	Feb 05 03:38:15 PM PST 24
Peak memory	205816 kb
Host	smart-2481bd6d-6109-4422-a737-f25d5a92a42d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866922152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3866922152
Directory	/workspace/19.keymgr_alert_test/latest

Test location	/workspace/coverage/default/19.keymgr_cfg_regwen.401518841
Short name	T251
Test name
Test status
Simulation time	87891195 ps
CPU time	3.22 seconds
Started	Feb 05 03:38:15 PM PST 24
Finished	Feb 05 03:38:27 PM PST 24
Peak memory	214672 kb
Host	smart-6424627c-93cc-4d68-932a-5d2704907ffc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=401518841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.401518841
Directory	/workspace/19.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/19.keymgr_direct_to_disabled.1253153850
Short name	T736
Test name
Test status
Simulation time	123000325 ps
CPU time	3.16 seconds
Started	Feb 05 03:38:17 PM PST 24
Finished	Feb 05 03:38:28 PM PST 24
Peak memory	207584 kb
Host	smart-c2130dfd-b2ea-4c6d-9ba2-49769c667188
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253153850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1253153850
Directory	/workspace/19.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/19.keymgr_hwsw_invalid_input.3214172739
Short name	T253
Test name
Test status
Simulation time	759421220 ps
CPU time	6.05 seconds
Started	Feb 05 03:38:15 PM PST 24
Finished	Feb 05 03:38:29 PM PST 24
Peak memory	214312 kb
Host	smart-075e66db-9926-4b57-aec5-94a22fe5a7de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3214172739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3214172739
Directory	/workspace/19.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/19.keymgr_kmac_rsp_err.3412426198
Short name	T268
Test name
Test status
Simulation time	2161798394 ps
CPU time	81.14 seconds
Started	Feb 05 03:38:15 PM PST 24
Finished	Feb 05 03:39:44 PM PST 24
Peak memory	231764 kb
Host	smart-95c16ae9-348f-408c-8d7e-69c47658be66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412426198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3412426198
Directory	/workspace/19.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/19.keymgr_lc_disable.1598988591
Short name	T56
Test name
Test status
Simulation time	380389795 ps
CPU time	4.37 seconds
Started	Feb 05 03:38:08 PM PST 24
Finished	Feb 05 03:38:22 PM PST 24
Peak memory	215860 kb
Host	smart-9bb5990d-179f-40be-9bc9-e04e5f35df06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598988591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1598988591
Directory	/workspace/19.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/19.keymgr_random.1104384570
Short name	T911
Test name
Test status
Simulation time	1930205796 ps
CPU time	12.92 seconds
Started	Feb 05 03:38:08 PM PST 24
Finished	Feb 05 03:38:30 PM PST 24
Peak memory	207952 kb
Host	smart-8b8ba7db-1128-4019-90e5-e22cb29c916a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104384570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1104384570
Directory	/workspace/19.keymgr_random/latest

Test location	/workspace/coverage/default/19.keymgr_sideload.892652430
Short name	T287
Test name
Test status
Simulation time	50057381 ps
CPU time	2.94 seconds
Started	Feb 05 03:38:12 PM PST 24
Finished	Feb 05 03:38:24 PM PST 24
Peak memory	206832 kb
Host	smart-851761ed-291f-4586-bd39-cd3778222567
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=892652430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.892652430
Directory	/workspace/19.keymgr_sideload/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_aes.1350570774
Short name	T296
Test name
Test status
Simulation time	782335865 ps
CPU time	4.25 seconds
Started	Feb 05 03:38:19 PM PST 24
Finished	Feb 05 03:38:33 PM PST 24
Peak memory	206864 kb
Host	smart-6b819e80-e57d-4b5c-ad26-d14dbb4b9c6c
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350570774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1350570774
Directory	/workspace/19.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_kmac.3271167999
Short name	T384
Test name
Test status
Simulation time	46959629 ps
CPU time	1.9 seconds
Started	Feb 05 03:38:09 PM PST 24
Finished	Feb 05 03:38:19 PM PST 24
Peak memory	206864 kb
Host	smart-d674bb78-92ba-4b9e-b618-0d7c6da01387
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271167999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3271167999
Directory	/workspace/19.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_otbn.3573549778
Short name	T850
Test name
Test status
Simulation time	756958712 ps
CPU time	7.14 seconds
Started	Feb 05 03:38:19 PM PST 24
Finished	Feb 05 03:38:35 PM PST 24
Peak memory	208680 kb
Host	smart-963ce131-6b30-4a10-b33a-b90978e77004
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573549778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3573549778
Directory	/workspace/19.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_protect.4154814615
Short name	T175
Test name
Test status
Simulation time	90354600 ps
CPU time	1.89 seconds
Started	Feb 05 03:38:22 PM PST 24
Finished	Feb 05 03:38:32 PM PST 24
Peak memory	218424 kb
Host	smart-f67e282a-7c1f-4cdf-b571-d088165c4652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154814615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4154814615
Directory	/workspace/19.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/19.keymgr_smoke.3073806118
Short name	T374
Test name
Test status
Simulation time	96148345 ps
CPU time	3.11 seconds
Started	Feb 05 03:38:15 PM PST 24
Finished	Feb 05 03:38:26 PM PST 24
Peak memory	206720 kb
Host	smart-06f0a05f-1a60-4109-be0c-566caf0362a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073806118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3073806118
Directory	/workspace/19.keymgr_smoke/latest

Test location	/workspace/coverage/default/19.keymgr_stress_all.3670683148
Short name	T664
Test name
Test status
Simulation time	210341520 ps
CPU time	6.19 seconds
Started	Feb 05 03:38:16 PM PST 24
Finished	Feb 05 03:38:30 PM PST 24
Peak memory	208224 kb
Host	smart-73194193-b0d1-4d5e-a8f7-f202a8ab4312
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670683148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3670683148
Directory	/workspace/19.keymgr_stress_all/latest

Test location	/workspace/coverage/default/19.keymgr_sync_async_fault_cross.3537487143
Short name	T582
Test name
Test status
Simulation time	96783633 ps
CPU time	1.6 seconds
Started	Feb 05 03:38:09 PM PST 24
Finished	Feb 05 03:38:19 PM PST 24
Peak memory	209696 kb
Host	smart-848867b1-ea5f-4f2a-8334-9d20209a8070
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3537487143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3537487143
Directory	/workspace/19.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/2.keymgr_alert_test.1281961278
Short name	T930
Test name
Test status
Simulation time	9180971 ps
CPU time	0.79 seconds
Started	Feb 05 03:36:34 PM PST 24
Finished	Feb 05 03:36:50 PM PST 24
Peak memory	205664 kb
Host	smart-4c7742f4-1adb-42b1-9314-be41a4cf32c0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281961278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1281961278
Directory	/workspace/2.keymgr_alert_test/latest

Test location	/workspace/coverage/default/2.keymgr_direct_to_disabled.3956758184
Short name	T71
Test name
Test status
Simulation time	37952513 ps
CPU time	2.12 seconds
Started	Feb 05 03:36:21 PM PST 24
Finished	Feb 05 03:36:41 PM PST 24
Peak memory	209268 kb
Host	smart-6378b69d-0d53-4276-b149-db8e6813cde3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956758184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3956758184
Directory	/workspace/2.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/2.keymgr_hwsw_invalid_input.403538285
Short name	T695
Test name
Test status
Simulation time	211397471 ps
CPU time	5.34 seconds
Started	Feb 05 03:36:27 PM PST 24
Finished	Feb 05 03:36:52 PM PST 24
Peak memory	220104 kb
Host	smart-aa2f95ac-66b5-4e87-b562-8fb41a354da6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=403538285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.403538285
Directory	/workspace/2.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/2.keymgr_kmac_rsp_err.4189013437
Short name	T350
Test name
Test status
Simulation time	168736597 ps
CPU time	3.48 seconds
Started	Feb 05 03:36:27 PM PST 24
Finished	Feb 05 03:36:49 PM PST 24
Peak memory	222420 kb
Host	smart-b636eef1-1768-4b3e-9565-a4bd68ea61d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4189013437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.4189013437
Directory	/workspace/2.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/2.keymgr_lc_disable.3078841526
Short name	T929
Test name
Test status
Simulation time	106263942 ps
CPU time	2.25 seconds
Started	Feb 05 03:36:19 PM PST 24
Finished	Feb 05 03:36:40 PM PST 24
Peak memory	208952 kb
Host	smart-d5c60dc6-115e-49fa-9a73-01ac5e29e7f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3078841526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3078841526
Directory	/workspace/2.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/2.keymgr_random.3967468777
Short name	T973
Test name
Test status
Simulation time	54458509 ps
CPU time	2.2 seconds
Started	Feb 05 03:36:17 PM PST 24
Finished	Feb 05 03:36:30 PM PST 24
Peak memory	207816 kb
Host	smart-7e413437-2e9a-4c3a-93fe-930dad207d0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967468777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3967468777
Directory	/workspace/2.keymgr_random/latest

Test location	/workspace/coverage/default/2.keymgr_sec_cm.93509613
Short name	T39
Test name
Test status
Simulation time	8313496935 ps
CPU time	40.67 seconds
Started	Feb 05 03:36:25 PM PST 24
Finished	Feb 05 03:37:23 PM PST 24
Peak memory	243964 kb
Host	smart-9e9c2727-6967-490d-b265-b47d4ade867f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93509613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.93509613
Directory	/workspace/2.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_aes.1865445977
Short name	T80
Test name
Test status
Simulation time	622017502 ps
CPU time	6.16 seconds
Started	Feb 05 03:36:26 PM PST 24
Finished	Feb 05 03:36:48 PM PST 24
Peak memory	208716 kb
Host	smart-54b12584-ce2e-4b8d-95d1-bbc93e381f32
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865445977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1865445977
Directory	/workspace/2.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_kmac.1478074992
Short name	T634
Test name
Test status
Simulation time	39569281 ps
CPU time	2.54 seconds
Started	Feb 05 03:36:26 PM PST 24
Finished	Feb 05 03:36:45 PM PST 24
Peak memory	208688 kb
Host	smart-d269f430-4d2f-4598-a65e-417070478574
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478074992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1478074992
Directory	/workspace/2.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_otbn.1181544440
Short name	T592
Test name
Test status
Simulation time	4043827440 ps
CPU time	29.28 seconds
Started	Feb 05 03:36:21 PM PST 24
Finished	Feb 05 03:37:08 PM PST 24
Peak memory	207792 kb
Host	smart-a2823a73-fe93-4826-850f-b12998dc41ab
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181544440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1181544440
Directory	/workspace/2.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_protect.3716463233
Short name	T725
Test name
Test status
Simulation time	132530204 ps
CPU time	2.14 seconds
Started	Feb 05 03:36:27 PM PST 24
Finished	Feb 05 03:36:47 PM PST 24
Peak memory	218456 kb
Host	smart-28976a0f-1fd2-4580-a741-46212fd67c4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716463233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3716463233
Directory	/workspace/2.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/2.keymgr_smoke.4287513108
Short name	T571
Test name
Test status
Simulation time	820861177 ps
CPU time	6.14 seconds
Started	Feb 05 03:36:25 PM PST 24
Finished	Feb 05 03:36:48 PM PST 24
Peak memory	207840 kb
Host	smart-2e46c314-100f-4af7-90d6-4ad7b54484d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287513108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.4287513108
Directory	/workspace/2.keymgr_smoke/latest

Test location	/workspace/coverage/default/2.keymgr_stress_all.2985732188
Short name	T848
Test name
Test status
Simulation time	1170757000 ps
CPU time	25.92 seconds
Started	Feb 05 03:36:34 PM PST 24
Finished	Feb 05 03:37:15 PM PST 24
Peak memory	220464 kb
Host	smart-240e2005-422c-4e8c-89b8-08beef9231bf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985732188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2985732188
Directory	/workspace/2.keymgr_stress_all/latest

Test location	/workspace/coverage/default/2.keymgr_sw_invalid_input.1660568356
Short name	T963
Test name
Test status
Simulation time	202750439 ps
CPU time	6.69 seconds
Started	Feb 05 03:36:24 PM PST 24
Finished	Feb 05 03:36:48 PM PST 24
Peak memory	208868 kb
Host	smart-33d11cb3-0762-4e06-90b9-5574faeedcdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660568356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1660568356
Directory	/workspace/2.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/2.keymgr_sync_async_fault_cross.913484765
Short name	T626
Test name
Test status
Simulation time	70073111 ps
CPU time	1.87 seconds
Started	Feb 05 03:36:26 PM PST 24
Finished	Feb 05 03:36:44 PM PST 24
Peak memory	210072 kb
Host	smart-6c4f1eb5-6eca-45b0-9fe7-34b8f0f6f183
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=913484765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.913484765
Directory	/workspace/2.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/20.keymgr_alert_test.1865958471
Short name	T876
Test name
Test status
Simulation time	30655914 ps
CPU time	0.95 seconds
Started	Feb 05 03:38:18 PM PST 24
Finished	Feb 05 03:38:29 PM PST 24
Peak memory	206008 kb
Host	smart-6f79d999-7925-4f20-9726-a7923cf8100e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865958471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1865958471
Directory	/workspace/20.keymgr_alert_test/latest

Test location	/workspace/coverage/default/20.keymgr_cfg_regwen.300404032
Short name	T323
Test name
Test status
Simulation time	52469083 ps
CPU time	3.71 seconds
Started	Feb 05 03:38:14 PM PST 24
Finished	Feb 05 03:38:26 PM PST 24
Peak memory	214316 kb
Host	smart-27126f17-21d6-4505-86b3-90fe7004d27b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=300404032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.300404032
Directory	/workspace/20.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/20.keymgr_direct_to_disabled.1360623974
Short name	T977
Test name
Test status
Simulation time	124919729 ps
CPU time	2.18 seconds
Started	Feb 05 03:38:14 PM PST 24
Finished	Feb 05 03:38:24 PM PST 24
Peak memory	207172 kb
Host	smart-c40d545c-fcaa-433b-965b-ad432be599bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1360623974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1360623974
Directory	/workspace/20.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/20.keymgr_hwsw_invalid_input.273496051
Short name	T100
Test name
Test status
Simulation time	85163894 ps
CPU time	4.08 seconds
Started	Feb 05 03:38:22 PM PST 24
Finished	Feb 05 03:38:34 PM PST 24
Peak memory	209568 kb
Host	smart-329f514e-1a96-4d1d-8e40-9f5eef3bdabb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273496051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.273496051
Directory	/workspace/20.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/20.keymgr_kmac_rsp_err.3951144381
Short name	T922
Test name
Test status
Simulation time	227144818 ps
CPU time	3.13 seconds
Started	Feb 05 03:38:18 PM PST 24
Finished	Feb 05 03:38:30 PM PST 24
Peak memory	222372 kb
Host	smart-223eced8-c0e9-48d5-a416-4c3d09dd2441
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951144381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3951144381
Directory	/workspace/20.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/20.keymgr_random.181387530
Short name	T708
Test name
Test status
Simulation time	2882421670 ps
CPU time	19.65 seconds
Started	Feb 05 03:38:13 PM PST 24
Finished	Feb 05 03:38:41 PM PST 24
Peak memory	208004 kb
Host	smart-eca67a04-72fd-4f13-b008-2fec0872b6ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=181387530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.181387530
Directory	/workspace/20.keymgr_random/latest

Test location	/workspace/coverage/default/20.keymgr_sideload.3077892194
Short name	T106
Test name
Test status
Simulation time	456488539 ps
CPU time	3.68 seconds
Started	Feb 05 03:38:16 PM PST 24
Finished	Feb 05 03:38:28 PM PST 24
Peak memory	208464 kb
Host	smart-2f45137f-08d7-464d-8089-aa11f09896e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077892194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3077892194
Directory	/workspace/20.keymgr_sideload/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_aes.1378304264
Short name	T697
Test name
Test status
Simulation time	271003921 ps
CPU time	3.14 seconds
Started	Feb 05 03:38:22 PM PST 24
Finished	Feb 05 03:38:33 PM PST 24
Peak memory	207124 kb
Host	smart-61a93002-4878-4ba4-abf7-5483fd9a191c
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378304264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1378304264
Directory	/workspace/20.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_kmac.4098545039
Short name	T593
Test name
Test status
Simulation time	273503482 ps
CPU time	4.64 seconds
Started	Feb 05 03:38:19 PM PST 24
Finished	Feb 05 03:38:33 PM PST 24
Peak memory	208036 kb
Host	smart-0e859d78-706e-4798-bbfe-0a9964fdeebf
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098545039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4098545039
Directory	/workspace/20.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_otbn.823799712
Short name	T786
Test name
Test status
Simulation time	3087942637 ps
CPU time	8.43 seconds
Started	Feb 05 03:38:13 PM PST 24
Finished	Feb 05 03:38:30 PM PST 24
Peak memory	208208 kb
Host	smart-e25eb93b-e034-4f1b-8474-0f6f175a57df
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823799712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.823799712
Directory	/workspace/20.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_protect.1670991039
Short name	T863
Test name
Test status
Simulation time	505485400 ps
CPU time	3.21 seconds
Started	Feb 05 03:38:21 PM PST 24
Finished	Feb 05 03:38:32 PM PST 24
Peak memory	215448 kb
Host	smart-a6139b8c-eeb5-483c-85da-165f159abd3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1670991039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1670991039
Directory	/workspace/20.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/20.keymgr_smoke.1415805191
Short name	T843
Test name
Test status
Simulation time	286740947 ps
CPU time	3.23 seconds
Started	Feb 05 03:38:26 PM PST 24
Finished	Feb 05 03:38:37 PM PST 24
Peak memory	206604 kb
Host	smart-92642ae8-3d8a-402f-a11f-76b9c69b1595
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415805191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1415805191
Directory	/workspace/20.keymgr_smoke/latest

Test location	/workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.175048029
Short name	T660
Test name
Test status
Simulation time	123685580 ps
CPU time	7.23 seconds
Started	Feb 05 03:38:25 PM PST 24
Finished	Feb 05 03:38:40 PM PST 24
Peak memory	222692 kb
Host	smart-548324ff-dd81-4945-8a6f-bb7962fff2ed
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175048029 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.175048029
Directory	/workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.keymgr_sw_invalid_input.3567753330
Short name	T859
Test name
Test status
Simulation time	840392608 ps
CPU time	7.43 seconds
Started	Feb 05 03:38:25 PM PST 24
Finished	Feb 05 03:38:40 PM PST 24
Peak memory	214312 kb
Host	smart-dc700105-766a-4ab6-a9f4-04b599f2c6e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567753330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3567753330
Directory	/workspace/20.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/20.keymgr_sync_async_fault_cross.4161539905
Short name	T746
Test name
Test status
Simulation time	48077340 ps
CPU time	2.02 seconds
Started	Feb 05 03:38:18 PM PST 24
Finished	Feb 05 03:38:29 PM PST 24
Peak memory	210092 kb
Host	smart-5c44a260-f23e-49b1-81f7-4edcc929f2d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161539905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.4161539905
Directory	/workspace/20.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/21.keymgr_alert_test.4093552814
Short name	T987
Test name
Test status
Simulation time	52155251 ps
CPU time	0.78 seconds
Started	Feb 05 03:38:22 PM PST 24
Finished	Feb 05 03:38:30 PM PST 24
Peak memory	205836 kb
Host	smart-5072886e-6af5-431f-8d1c-1d7239ba36da
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093552814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.4093552814
Directory	/workspace/21.keymgr_alert_test/latest

Test location	/workspace/coverage/default/21.keymgr_custom_cm.3499800676
Short name	T958
Test name
Test status
Simulation time	116932422 ps
CPU time	1.95 seconds
Started	Feb 05 03:38:22 PM PST 24
Finished	Feb 05 03:38:32 PM PST 24
Peak memory	209312 kb
Host	smart-7aef8d7e-7898-478f-afa9-0d3396b33a8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3499800676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3499800676
Directory	/workspace/21.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/21.keymgr_direct_to_disabled.1930616329
Short name	T67
Test name
Test status
Simulation time	188082267 ps
CPU time	2.1 seconds
Started	Feb 05 03:38:24 PM PST 24
Finished	Feb 05 03:38:33 PM PST 24
Peak memory	207324 kb
Host	smart-31bd3b18-0211-4bfb-92d6-21137f905ebc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930616329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1930616329
Directory	/workspace/21.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/21.keymgr_lc_disable.1703654033
Short name	T1000
Test name
Test status
Simulation time	441689101 ps
CPU time	4.85 seconds
Started	Feb 05 03:38:21 PM PST 24
Finished	Feb 05 03:38:34 PM PST 24
Peak memory	209800 kb
Host	smart-00772103-1b45-4d1d-875e-ed37bc252f8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1703654033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1703654033
Directory	/workspace/21.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/21.keymgr_random.3889432304
Short name	T186
Test name
Test status
Simulation time	118312953 ps
CPU time	2.35 seconds
Started	Feb 05 03:38:21 PM PST 24
Finished	Feb 05 03:38:32 PM PST 24
Peak memory	207180 kb
Host	smart-8486d8f2-a69b-4d55-9ceb-9161cc19536f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3889432304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3889432304
Directory	/workspace/21.keymgr_random/latest

Test location	/workspace/coverage/default/21.keymgr_sideload.62647078
Short name	T609
Test name
Test status
Simulation time	67111630 ps
CPU time	2.46 seconds
Started	Feb 05 03:38:19 PM PST 24
Finished	Feb 05 03:38:31 PM PST 24
Peak memory	206580 kb
Host	smart-76870802-5c4a-4a55-a934-d70b45b36e93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62647078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.62647078
Directory	/workspace/21.keymgr_sideload/latest

Test location	/workspace/coverage/default/21.keymgr_sideload_aes.4027795516
Short name	T814
Test name
Test status
Simulation time	329298081 ps
CPU time	9.48 seconds
Started	Feb 05 03:38:20 PM PST 24
Finished	Feb 05 03:38:38 PM PST 24
Peak memory	208124 kb
Host	smart-c820bf8b-877c-4614-87e1-92b31e0c2f99
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027795516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4027795516
Directory	/workspace/21.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/21.keymgr_sideload_otbn.63479207
Short name	T581
Test name
Test status
Simulation time	103609747 ps
CPU time	2.82 seconds
Started	Feb 05 03:38:22 PM PST 24
Finished	Feb 05 03:38:32 PM PST 24
Peak memory	206896 kb
Host	smart-72cb7f37-aed8-4e46-8d3e-d3842cafcf07
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63479207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.63479207
Directory	/workspace/21.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/21.keymgr_sideload_protect.3383293015
Short name	T361
Test name
Test status
Simulation time	290682414 ps
CPU time	2.96 seconds
Started	Feb 05 03:38:16 PM PST 24
Finished	Feb 05 03:38:27 PM PST 24
Peak memory	209808 kb
Host	smart-4728d72d-62d9-4de9-b6cc-1f9668b1f62c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383293015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3383293015
Directory	/workspace/21.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/21.keymgr_smoke.2659045891
Short name	T921
Test name
Test status
Simulation time	697312459 ps
CPU time	5.73 seconds
Started	Feb 05 03:38:14 PM PST 24
Finished	Feb 05 03:38:28 PM PST 24
Peak memory	208712 kb
Host	smart-e9c841f7-d287-4e1b-9e26-bf5548de447d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2659045891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2659045891
Directory	/workspace/21.keymgr_smoke/latest

Test location	/workspace/coverage/default/21.keymgr_stress_all.1862091195
Short name	T222
Test name
Test status
Simulation time	10864075666 ps
CPU time	35.46 seconds
Started	Feb 05 03:38:18 PM PST 24
Finished	Feb 05 03:39:03 PM PST 24
Peak memory	217000 kb
Host	smart-8a1e183c-20ab-4fda-b00a-a35634d14bdf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862091195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1862091195
Directory	/workspace/21.keymgr_stress_all/latest

Test location	/workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.452533351
Short name	T711
Test name
Test status
Simulation time	144317315 ps
CPU time	5.55 seconds
Started	Feb 05 03:38:17 PM PST 24
Finished	Feb 05 03:38:31 PM PST 24
Peak memory	220108 kb
Host	smart-18e80585-8fc9-4985-a9eb-ee5ea4955d56
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452533351 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.452533351
Directory	/workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.keymgr_sw_invalid_input.1871613702
Short name	T739
Test name
Test status
Simulation time	5050435081 ps
CPU time	10.8 seconds
Started	Feb 05 03:38:24 PM PST 24
Finished	Feb 05 03:38:42 PM PST 24
Peak memory	210140 kb
Host	smart-443d820c-73c0-492a-8c0f-4f3ecc43412a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871613702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1871613702
Directory	/workspace/21.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/21.keymgr_sync_async_fault_cross.3583938172
Short name	T52
Test name
Test status
Simulation time	1472766137 ps
CPU time	7.52 seconds
Started	Feb 05 03:38:23 PM PST 24
Finished	Feb 05 03:38:38 PM PST 24
Peak memory	211020 kb
Host	smart-fe5475ae-1923-4124-9328-c8256c896a9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583938172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3583938172
Directory	/workspace/21.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/22.keymgr_alert_test.3964473860
Short name	T633
Test name
Test status
Simulation time	13887240 ps
CPU time	0.74 seconds
Started	Feb 05 03:38:31 PM PST 24
Finished	Feb 05 03:38:37 PM PST 24
Peak memory	206080 kb
Host	smart-b8db129c-d2f5-4375-bb6c-dd813aecca1e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964473860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3964473860
Directory	/workspace/22.keymgr_alert_test/latest

Test location	/workspace/coverage/default/22.keymgr_custom_cm.2188937995
Short name	T737
Test name
Test status
Simulation time	1062822505 ps
CPU time	6.26 seconds
Started	Feb 05 03:38:24 PM PST 24
Finished	Feb 05 03:38:38 PM PST 24
Peak memory	214684 kb
Host	smart-34bbf0ce-7ee6-430b-a75f-8d8a290f993e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188937995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2188937995
Directory	/workspace/22.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/22.keymgr_hwsw_invalid_input.2471149777
Short name	T93
Test name
Test status
Simulation time	648848456 ps
CPU time	5.55 seconds
Started	Feb 05 03:38:25 PM PST 24
Finished	Feb 05 03:38:39 PM PST 24
Peak memory	214308 kb
Host	smart-160fd4c1-b147-4741-810c-51b93d0e7a5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2471149777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2471149777
Directory	/workspace/22.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/22.keymgr_kmac_rsp_err.1798592859
Short name	T187
Test name
Test status
Simulation time	186609092 ps
CPU time	4.74 seconds
Started	Feb 05 03:38:18 PM PST 24
Finished	Feb 05 03:38:32 PM PST 24
Peak memory	210928 kb
Host	smart-d73c4f21-692c-4d91-bdfa-4474572abc21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798592859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1798592859
Directory	/workspace/22.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/22.keymgr_lc_disable.2041183195
Short name	T738
Test name
Test status
Simulation time	25906103 ps
CPU time	2.12 seconds
Started	Feb 05 03:38:17 PM PST 24
Finished	Feb 05 03:38:27 PM PST 24
Peak memory	206136 kb
Host	smart-ccc16d12-c6d9-4c54-8eea-d2b0b035c93a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041183195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2041183195
Directory	/workspace/22.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/22.keymgr_random.1231717956
Short name	T569
Test name
Test status
Simulation time	169104525 ps
CPU time	6.72 seconds
Started	Feb 05 03:38:27 PM PST 24
Finished	Feb 05 03:38:41 PM PST 24
Peak memory	214384 kb
Host	smart-b37b23f5-295a-448b-b69d-f0a3dfa800aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231717956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1231717956
Directory	/workspace/22.keymgr_random/latest

Test location	/workspace/coverage/default/22.keymgr_sideload.3239913756
Short name	T880
Test name
Test status
Simulation time	57957047 ps
CPU time	3.18 seconds
Started	Feb 05 03:38:23 PM PST 24
Finished	Feb 05 03:38:33 PM PST 24
Peak memory	208380 kb
Host	smart-2df7fc56-799f-4d28-9807-7b9eacc041b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3239913756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3239913756
Directory	/workspace/22.keymgr_sideload/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_aes.2373872121
Short name	T827
Test name
Test status
Simulation time	191072641 ps
CPU time	7.11 seconds
Started	Feb 05 03:38:21 PM PST 24
Finished	Feb 05 03:38:36 PM PST 24
Peak memory	208080 kb
Host	smart-c414b04f-95b2-4157-9206-f20bb50f854b
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373872121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2373872121
Directory	/workspace/22.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_kmac.4170135715
Short name	T849
Test name
Test status
Simulation time	3296495008 ps
CPU time	35.1 seconds
Started	Feb 05 03:38:21 PM PST 24
Finished	Feb 05 03:39:04 PM PST 24
Peak memory	209016 kb
Host	smart-c255c1b2-7c4f-4278-b909-cc2b104c30fa
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170135715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.4170135715
Directory	/workspace/22.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_otbn.1489884113
Short name	T800
Test name
Test status
Simulation time	226336783 ps
CPU time	6.87 seconds
Started	Feb 05 03:38:18 PM PST 24
Finished	Feb 05 03:38:33 PM PST 24
Peak memory	207812 kb
Host	smart-12afa743-d9df-4cfd-85f0-3d554525b019
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489884113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1489884113
Directory	/workspace/22.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_protect.336595851
Short name	T724
Test name
Test status
Simulation time	31751752 ps
CPU time	2.07 seconds
Started	Feb 05 03:38:24 PM PST 24
Finished	Feb 05 03:38:33 PM PST 24
Peak memory	209684 kb
Host	smart-3249ff7b-b34a-44d0-ad52-d679de66e9c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336595851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.336595851
Directory	/workspace/22.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/22.keymgr_smoke.2747447879
Short name	T845
Test name
Test status
Simulation time	936554092 ps
CPU time	6.39 seconds
Started	Feb 05 03:38:16 PM PST 24
Finished	Feb 05 03:38:30 PM PST 24
Peak memory	207668 kb
Host	smart-18ae9146-854a-4a74-852b-b6a30470bc90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2747447879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2747447879
Directory	/workspace/22.keymgr_smoke/latest

Test location	/workspace/coverage/default/22.keymgr_stress_all.1837760410
Short name	T74
Test name
Test status
Simulation time	4439256652 ps
CPU time	59.28 seconds
Started	Feb 05 03:38:24 PM PST 24
Finished	Feb 05 03:39:30 PM PST 24
Peak memory	221604 kb
Host	smart-443d39ae-b5a3-4bc3-9fed-830222cf02a1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837760410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1837760410
Directory	/workspace/22.keymgr_stress_all/latest

Test location	/workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.132685149
Short name	T357
Test name
Test status
Simulation time	74895614 ps
CPU time	5.39 seconds
Started	Feb 05 03:38:27 PM PST 24
Finished	Feb 05 03:38:40 PM PST 24
Peak memory	223064 kb
Host	smart-2d318e20-7340-4d12-9060-33836bb7428d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132685149 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.132685149
Directory	/workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.keymgr_sw_invalid_input.2040579519
Short name	T952
Test name
Test status
Simulation time	277480910 ps
CPU time	6.77 seconds
Started	Feb 05 03:38:16 PM PST 24
Finished	Feb 05 03:38:31 PM PST 24
Peak memory	214272 kb
Host	smart-cb177fcd-5c33-44f6-9c8e-e7e11e8b2c82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040579519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2040579519
Directory	/workspace/22.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/22.keymgr_sync_async_fault_cross.2839834042
Short name	T591
Test name
Test status
Simulation time	903317139 ps
CPU time	5.31 seconds
Started	Feb 05 03:38:27 PM PST 24
Finished	Feb 05 03:38:39 PM PST 24
Peak memory	210904 kb
Host	smart-621d6b24-bd39-4633-8d4f-1f5c4f59b7bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839834042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2839834042
Directory	/workspace/22.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/23.keymgr_alert_test.3739103313
Short name	T892
Test name
Test status
Simulation time	16811097 ps
CPU time	0.87 seconds
Started	Feb 05 03:38:25 PM PST 24
Finished	Feb 05 03:38:34 PM PST 24
Peak memory	205800 kb
Host	smart-fea93162-bcfb-48f6-ad6d-e994a9b8ba82
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739103313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3739103313
Directory	/workspace/23.keymgr_alert_test/latest

Test location	/workspace/coverage/default/23.keymgr_cfg_regwen.3783612541
Short name	T369
Test name
Test status
Simulation time	130159490 ps
CPU time	7.57 seconds
Started	Feb 05 03:38:23 PM PST 24
Finished	Feb 05 03:38:39 PM PST 24
Peak memory	214340 kb
Host	smart-b7e6273c-2cd7-411c-83eb-99f511a80d08
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3783612541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3783612541
Directory	/workspace/23.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/23.keymgr_custom_cm.3860642670
Short name	T629
Test name
Test status
Simulation time	648831197 ps
CPU time	4.46 seconds
Started	Feb 05 03:38:24 PM PST 24
Finished	Feb 05 03:38:36 PM PST 24
Peak memory	221588 kb
Host	smart-e02a6c26-3c56-456a-827f-1a06dc3b8671
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3860642670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3860642670
Directory	/workspace/23.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/23.keymgr_direct_to_disabled.1467174210
Short name	T754
Test name
Test status
Simulation time	317347780 ps
CPU time	4.74 seconds
Started	Feb 05 03:38:32 PM PST 24
Finished	Feb 05 03:38:42 PM PST 24
Peak memory	209488 kb
Host	smart-dfffea25-860f-4fbd-ba78-8ff0bec0fd1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467174210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1467174210
Directory	/workspace/23.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/23.keymgr_hwsw_invalid_input.3307933551
Short name	T666
Test name
Test status
Simulation time	43988693 ps
CPU time	2.91 seconds
Started	Feb 05 03:38:27 PM PST 24
Finished	Feb 05 03:38:37 PM PST 24
Peak memory	209152 kb
Host	smart-6c1025cd-b053-4355-bf99-f01955bd0783
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3307933551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3307933551
Directory	/workspace/23.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/23.keymgr_kmac_rsp_err.1082795898
Short name	T269
Test name
Test status
Simulation time	186004339 ps
CPU time	4.89 seconds
Started	Feb 05 03:38:31 PM PST 24
Finished	Feb 05 03:38:41 PM PST 24
Peak memory	210864 kb
Host	smart-a5f77943-22ae-4b94-b5a8-491e98a5b970
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082795898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1082795898
Directory	/workspace/23.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/23.keymgr_lc_disable.4251107605
Short name	T602
Test name
Test status
Simulation time	160658033 ps
CPU time	2.62 seconds
Started	Feb 05 03:38:29 PM PST 24
Finished	Feb 05 03:38:38 PM PST 24
Peak memory	219960 kb
Host	smart-643aa4c8-19db-41ff-8fa5-6036a1fb776e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4251107605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4251107605
Directory	/workspace/23.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/23.keymgr_random.4071165431
Short name	T184
Test name
Test status
Simulation time	178163118 ps
CPU time	2.75 seconds
Started	Feb 05 03:38:28 PM PST 24
Finished	Feb 05 03:38:38 PM PST 24
Peak memory	209872 kb
Host	smart-7b451e16-cb39-4036-86b0-a03d65944f33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4071165431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.4071165431
Directory	/workspace/23.keymgr_random/latest

Test location	/workspace/coverage/default/23.keymgr_sideload.3781736294
Short name	T734
Test name
Test status
Simulation time	607578957 ps
CPU time	8.17 seconds
Started	Feb 05 03:38:30 PM PST 24
Finished	Feb 05 03:38:44 PM PST 24
Peak memory	206784 kb
Host	smart-5ce17247-62eb-4373-87f3-c1c6f912d9d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781736294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3781736294
Directory	/workspace/23.keymgr_sideload/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_aes.4104634454
Short name	T597
Test name
Test status
Simulation time	63000710 ps
CPU time	2.86 seconds
Started	Feb 05 03:38:30 PM PST 24
Finished	Feb 05 03:38:38 PM PST 24
Peak memory	208328 kb
Host	smart-b97c2c14-0bcc-4251-9551-d95d73cad67c
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104634454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.4104634454
Directory	/workspace/23.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_kmac.2709733415
Short name	T294
Test name
Test status
Simulation time	495858149 ps
CPU time	4.52 seconds
Started	Feb 05 03:38:31 PM PST 24
Finished	Feb 05 03:38:41 PM PST 24
Peak memory	208364 kb
Host	smart-db654b7a-615c-43e8-9b4b-db7ae3856222
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709733415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2709733415
Directory	/workspace/23.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_otbn.2788490867
Short name	T807
Test name
Test status
Simulation time	245910525 ps
CPU time	3.08 seconds
Started	Feb 05 03:38:28 PM PST 24
Finished	Feb 05 03:38:38 PM PST 24
Peak memory	206952 kb
Host	smart-e4fbb7bd-c3c3-4607-91f4-75e00cd59783
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788490867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2788490867
Directory	/workspace/23.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_protect.2985015761
Short name	T718
Test name
Test status
Simulation time	272698737 ps
CPU time	3.13 seconds
Started	Feb 05 03:38:32 PM PST 24
Finished	Feb 05 03:38:40 PM PST 24
Peak memory	207784 kb
Host	smart-077ef588-4e8a-4c3b-be97-9281214efc2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985015761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2985015761
Directory	/workspace/23.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/23.keymgr_smoke.105955020
Short name	T747
Test name
Test status
Simulation time	59613570 ps
CPU time	2.9 seconds
Started	Feb 05 03:38:27 PM PST 24
Finished	Feb 05 03:38:37 PM PST 24
Peak memory	208548 kb
Host	smart-a2f3d74f-c348-4107-8949-0b3ce5bf29e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105955020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.105955020
Directory	/workspace/23.keymgr_smoke/latest

Test location	/workspace/coverage/default/23.keymgr_stress_all.3702465823
Short name	T317
Test name
Test status
Simulation time	827782825 ps
CPU time	33.23 seconds
Started	Feb 05 03:38:29 PM PST 24
Finished	Feb 05 03:39:09 PM PST 24
Peak memory	222400 kb
Host	smart-539314a8-b8c9-4374-9e3b-418ddc36e570
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702465823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3702465823
Directory	/workspace/23.keymgr_stress_all/latest

Test location	/workspace/coverage/default/23.keymgr_sw_invalid_input.4059827170
Short name	T709
Test name
Test status
Simulation time	43746483 ps
CPU time	2.96 seconds
Started	Feb 05 03:38:24 PM PST 24
Finished	Feb 05 03:38:34 PM PST 24
Peak memory	206928 kb
Host	smart-65d67bd2-f20a-476d-a8b3-83d200598438
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4059827170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4059827170
Directory	/workspace/23.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/23.keymgr_sync_async_fault_cross.3012015323
Short name	T668
Test name
Test status
Simulation time	273619311 ps
CPU time	2.52 seconds
Started	Feb 05 03:38:30 PM PST 24
Finished	Feb 05 03:38:38 PM PST 24
Peak memory	210040 kb
Host	smart-9d612be0-23e5-425a-9dcb-eeedd1b52b7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012015323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3012015323
Directory	/workspace/23.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/24.keymgr_cfg_regwen.3627001228
Short name	T905
Test name
Test status
Simulation time	129875435 ps
CPU time	2.84 seconds
Started	Feb 05 03:38:34 PM PST 24
Finished	Feb 05 03:38:40 PM PST 24
Peak memory	215624 kb
Host	smart-a1a555f2-d348-4e56-839e-39ed6cf69597
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3627001228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3627001228
Directory	/workspace/24.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/24.keymgr_direct_to_disabled.3918233397
Short name	T401
Test name
Test status
Simulation time	108024362 ps
CPU time	4.18 seconds
Started	Feb 05 03:38:34 PM PST 24
Finished	Feb 05 03:38:42 PM PST 24
Peak memory	210324 kb
Host	smart-522d5eef-c6ee-492e-870f-a71031100ee6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918233397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3918233397
Directory	/workspace/24.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/24.keymgr_kmac_rsp_err.1026156884
Short name	T26
Test name
Test status
Simulation time	263340417 ps
CPU time	10.1 seconds
Started	Feb 05 03:38:33 PM PST 24
Finished	Feb 05 03:38:47 PM PST 24
Peak memory	214272 kb
Host	smart-8f4f7c9e-245d-42c5-99e9-14ffc187ad2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1026156884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1026156884
Directory	/workspace/24.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/24.keymgr_lc_disable.1991319396
Short name	T965
Test name
Test status
Simulation time	111743909 ps
CPU time	2.06 seconds
Started	Feb 05 03:38:29 PM PST 24
Finished	Feb 05 03:38:37 PM PST 24
Peak memory	215456 kb
Host	smart-60f61ffd-80e1-40f1-a625-d3bf36c8aec6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991319396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1991319396
Directory	/workspace/24.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/24.keymgr_random.3017309329
Short name	T802
Test name
Test status
Simulation time	6152265607 ps
CPU time	35.67 seconds
Started	Feb 05 03:38:32 PM PST 24
Finished	Feb 05 03:39:13 PM PST 24
Peak memory	208688 kb
Host	smart-43e031c6-6056-45ff-9780-80271b9be854
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017309329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3017309329
Directory	/workspace/24.keymgr_random/latest

Test location	/workspace/coverage/default/24.keymgr_sideload.1231629599
Short name	T723
Test name
Test status
Simulation time	361590591 ps
CPU time	4.01 seconds
Started	Feb 05 03:38:27 PM PST 24
Finished	Feb 05 03:38:39 PM PST 24
Peak memory	208556 kb
Host	smart-2b2f6c35-2833-40a9-abed-5229f2e14a4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231629599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1231629599
Directory	/workspace/24.keymgr_sideload/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_aes.3120962582
Short name	T692
Test name
Test status
Simulation time	98034283 ps
CPU time	2.87 seconds
Started	Feb 05 03:38:22 PM PST 24
Finished	Feb 05 03:38:33 PM PST 24
Peak memory	207376 kb
Host	smart-9654a7b9-a8c1-40e1-9e8b-d061f5e522b6
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120962582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3120962582
Directory	/workspace/24.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_kmac.1240982359
Short name	T643
Test name
Test status
Simulation time	9389230866 ps
CPU time	63.58 seconds
Started	Feb 05 03:38:26 PM PST 24
Finished	Feb 05 03:39:37 PM PST 24
Peak memory	209040 kb
Host	smart-3d9290c2-71ea-4c16-b00f-04d233ecc832
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240982359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1240982359
Directory	/workspace/24.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_otbn.2702961443
Short name	T236
Test name
Test status
Simulation time	10269036412 ps
CPU time	47.42 seconds
Started	Feb 05 03:38:31 PM PST 24
Finished	Feb 05 03:39:24 PM PST 24
Peak memory	209036 kb
Host	smart-06aff67f-4c11-44e0-91c6-e35f77abcf01
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702961443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2702961443
Directory	/workspace/24.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_protect.3622276026
Short name	T635
Test name
Test status
Simulation time	383192705 ps
CPU time	2.84 seconds
Started	Feb 05 03:38:32 PM PST 24
Finished	Feb 05 03:38:40 PM PST 24
Peak memory	215436 kb
Host	smart-117fb486-bca7-4ae7-bdbc-ea41089fa939
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622276026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3622276026
Directory	/workspace/24.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/24.keymgr_smoke.1171872105
Short name	T705
Test name
Test status
Simulation time	167031753 ps
CPU time	4.78 seconds
Started	Feb 05 03:38:26 PM PST 24
Finished	Feb 05 03:38:38 PM PST 24
Peak memory	207936 kb
Host	smart-180b1cca-2805-4731-adf8-8ae0217488ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171872105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1171872105
Directory	/workspace/24.keymgr_smoke/latest

Test location	/workspace/coverage/default/24.keymgr_stress_all.4112416870
Short name	T346
Test name
Test status
Simulation time	52989085 ps
CPU time	3.32 seconds
Started	Feb 05 03:38:32 PM PST 24
Finished	Feb 05 03:38:40 PM PST 24
Peak memory	208324 kb
Host	smart-220a39b1-f2b9-46b3-b512-4c9e1bc51103
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112416870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4112416870
Directory	/workspace/24.keymgr_stress_all/latest

Test location	/workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.872629786
Short name	T939
Test name
Test status
Simulation time	986761906 ps
CPU time	6.72 seconds
Started	Feb 05 03:38:34 PM PST 24
Finished	Feb 05 03:38:44 PM PST 24
Peak memory	219980 kb
Host	smart-69e33230-01b2-421b-be14-47d51063e338
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872629786 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.872629786
Directory	/workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.keymgr_sw_invalid_input.918923996
Short name	T215
Test name
Test status
Simulation time	41242341 ps
CPU time	2.68 seconds
Started	Feb 05 03:38:28 PM PST 24
Finished	Feb 05 03:38:37 PM PST 24
Peak memory	209544 kb
Host	smart-5bf591a1-a58c-4cf8-afae-9e6c322a234b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918923996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.918923996
Directory	/workspace/24.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/24.keymgr_sync_async_fault_cross.794324833
Short name	T573
Test name
Test status
Simulation time	338810746 ps
CPU time	4.02 seconds
Started	Feb 05 03:38:34 PM PST 24
Finished	Feb 05 03:38:42 PM PST 24
Peak memory	210616 kb
Host	smart-4cbc2803-07b8-46f1-a2c1-84e7a9a96730
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=794324833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.794324833
Directory	/workspace/24.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/25.keymgr_alert_test.1724631339
Short name	T407
Test name
Test status
Simulation time	44103372 ps
CPU time	0.74 seconds
Started	Feb 05 03:38:40 PM PST 24
Finished	Feb 05 03:38:43 PM PST 24
Peak memory	205872 kb
Host	smart-3629975c-96e2-4928-9e2e-ab18f237d0cc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724631339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1724631339
Directory	/workspace/25.keymgr_alert_test/latest

Test location	/workspace/coverage/default/25.keymgr_cfg_regwen.3660127039
Short name	T396
Test name
Test status
Simulation time	277169388 ps
CPU time	8 seconds
Started	Feb 05 03:38:33 PM PST 24
Finished	Feb 05 03:38:45 PM PST 24
Peak memory	214256 kb
Host	smart-b44a8d14-46fb-4d03-9137-ff861ced2682
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3660127039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3660127039
Directory	/workspace/25.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/25.keymgr_custom_cm.1810984876
Short name	T196
Test name
Test status
Simulation time	177177687 ps
CPU time	6.36 seconds
Started	Feb 05 03:38:33 PM PST 24
Finished	Feb 05 03:38:44 PM PST 24
Peak memory	222680 kb
Host	smart-6deaadb4-58d8-4f7e-bbab-3e49e6592a06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1810984876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1810984876
Directory	/workspace/25.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/25.keymgr_direct_to_disabled.4091293765
Short name	T349
Test name
Test status
Simulation time	34518641 ps
CPU time	1.29 seconds
Started	Feb 05 03:38:29 PM PST 24
Finished	Feb 05 03:38:36 PM PST 24
Peak memory	207076 kb
Host	smart-f528184c-89be-4289-ac6b-95411c5b422b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091293765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.4091293765
Directory	/workspace/25.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/25.keymgr_hwsw_invalid_input.574119104
Short name	T24
Test name
Test status
Simulation time	51998265 ps
CPU time	3.17 seconds
Started	Feb 05 03:38:33 PM PST 24
Finished	Feb 05 03:38:41 PM PST 24
Peak memory	208828 kb
Host	smart-3c35dbae-d727-4693-abdb-bdb8d135f364
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574119104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.574119104
Directory	/workspace/25.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/25.keymgr_kmac_rsp_err.3449864767
Short name	T334
Test name
Test status
Simulation time	1098503075 ps
CPU time	29.07 seconds
Started	Feb 05 03:38:34 PM PST 24
Finished	Feb 05 03:39:07 PM PST 24
Peak memory	217664 kb
Host	smart-fec895ad-745f-4a02-a05b-e689dc4fa6be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449864767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3449864767
Directory	/workspace/25.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/25.keymgr_lc_disable.513811850
Short name	T690
Test name
Test status
Simulation time	588062043 ps
CPU time	3.74 seconds
Started	Feb 05 03:38:32 PM PST 24
Finished	Feb 05 03:38:41 PM PST 24
Peak memory	209004 kb
Host	smart-562301f2-01ac-4ea0-8992-14f6464c0ef5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513811850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.513811850
Directory	/workspace/25.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/25.keymgr_sideload.670042570
Short name	T255
Test name
Test status
Simulation time	1546432046 ps
CPU time	29.19 seconds
Started	Feb 05 03:38:34 PM PST 24
Finished	Feb 05 03:39:07 PM PST 24
Peak memory	208800 kb
Host	smart-1918b727-bb84-4c5a-b7e4-e5670f2b901a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670042570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.670042570
Directory	/workspace/25.keymgr_sideload/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_aes.3846275025
Short name	T648
Test name
Test status
Simulation time	1876820008 ps
CPU time	25.4 seconds
Started	Feb 05 03:38:29 PM PST 24
Finished	Feb 05 03:39:01 PM PST 24
Peak memory	208224 kb
Host	smart-63683088-ccb6-4347-b810-2b0de89e1d35
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846275025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3846275025
Directory	/workspace/25.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_kmac.1805028569
Short name	T772
Test name
Test status
Simulation time	778268297 ps
CPU time	19.19 seconds
Started	Feb 05 03:38:29 PM PST 24
Finished	Feb 05 03:38:55 PM PST 24
Peak memory	208124 kb
Host	smart-75eebbbb-8e28-4919-84c5-7996a218654c
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805028569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1805028569
Directory	/workspace/25.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_otbn.4275836771
Short name	T912
Test name
Test status
Simulation time	134206403 ps
CPU time	4.45 seconds
Started	Feb 05 03:38:31 PM PST 24
Finished	Feb 05 03:38:41 PM PST 24
Peak memory	208648 kb
Host	smart-9cb8b323-fa48-4b5c-9bcd-6338bccd178b
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275836771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4275836771
Directory	/workspace/25.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_protect.1466071536
Short name	T742
Test name
Test status
Simulation time	428403408 ps
CPU time	9.78 seconds
Started	Feb 05 03:38:36 PM PST 24
Finished	Feb 05 03:38:49 PM PST 24
Peak memory	209452 kb
Host	smart-741e12ba-e350-4246-9c32-fcd8feb9d8b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1466071536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1466071536
Directory	/workspace/25.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/25.keymgr_smoke.3380727287
Short name	T966
Test name
Test status
Simulation time	130928409 ps
CPU time	2.58 seconds
Started	Feb 05 03:38:34 PM PST 24
Finished	Feb 05 03:38:40 PM PST 24
Peak memory	207064 kb
Host	smart-ce449fab-6cc6-43d4-9c6e-0e7d9325d61c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3380727287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3380727287
Directory	/workspace/25.keymgr_smoke/latest

Test location	/workspace/coverage/default/25.keymgr_stress_all.1928165120
Short name	T351
Test name
Test status
Simulation time	272301241 ps
CPU time	5.69 seconds
Started	Feb 05 03:38:37 PM PST 24
Finished	Feb 05 03:38:45 PM PST 24
Peak memory	210388 kb
Host	smart-12018691-2448-43e5-9f3a-842b50bd1cc6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928165120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1928165120
Directory	/workspace/25.keymgr_stress_all/latest

Test location	/workspace/coverage/default/25.keymgr_sw_invalid_input.1645034718
Short name	T799
Test name
Test status
Simulation time	108777433 ps
CPU time	4.67 seconds
Started	Feb 05 03:38:32 PM PST 24
Finished	Feb 05 03:38:41 PM PST 24
Peak memory	208820 kb
Host	smart-47788a61-4e3b-4804-8437-56f855585029
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645034718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1645034718
Directory	/workspace/25.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/25.keymgr_sync_async_fault_cross.1967776634
Short name	T763
Test name
Test status
Simulation time	176740254 ps
CPU time	2.47 seconds
Started	Feb 05 03:38:40 PM PST 24
Finished	Feb 05 03:38:44 PM PST 24
Peak memory	210484 kb
Host	smart-a6630536-4420-46a9-bedc-18c6365fd724
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967776634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1967776634
Directory	/workspace/25.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/26.keymgr_alert_test.2449128346
Short name	T596
Test name
Test status
Simulation time	74347836 ps
CPU time	0.86 seconds
Started	Feb 05 03:38:53 PM PST 24
Finished	Feb 05 03:38:55 PM PST 24
Peak memory	205868 kb
Host	smart-c535e75d-e4cc-4232-8138-b4ee78c518c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449128346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2449128346
Directory	/workspace/26.keymgr_alert_test/latest

Test location	/workspace/coverage/default/26.keymgr_custom_cm.3604669991
Short name	T200
Test name
Test status
Simulation time	291140247 ps
CPU time	4.87 seconds
Started	Feb 05 03:38:41 PM PST 24
Finished	Feb 05 03:38:48 PM PST 24
Peak memory	222556 kb
Host	smart-2318e0a2-7a2f-4dd7-b730-02306604fc43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604669991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3604669991
Directory	/workspace/26.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/26.keymgr_direct_to_disabled.1597405643
Short name	T263
Test name
Test status
Simulation time	108410145 ps
CPU time	3 seconds
Started	Feb 05 03:38:51 PM PST 24
Finished	Feb 05 03:38:55 PM PST 24
Peak memory	219772 kb
Host	smart-b242e6dd-188a-4da3-b335-240f5674fb9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1597405643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1597405643
Directory	/workspace/26.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/26.keymgr_hwsw_invalid_input.2464685952
Short name	T715
Test name
Test status
Simulation time	1199253348 ps
CPU time	4.98 seconds
Started	Feb 05 03:38:50 PM PST 24
Finished	Feb 05 03:38:57 PM PST 24
Peak memory	214284 kb
Host	smart-a50207db-a753-4002-821f-649645ff3ea1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2464685952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2464685952
Directory	/workspace/26.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/26.keymgr_lc_disable.4062029864
Short name	T209
Test name
Test status
Simulation time	331274468 ps
CPU time	4.25 seconds
Started	Feb 05 03:38:43 PM PST 24
Finished	Feb 05 03:38:49 PM PST 24
Peak memory	219864 kb
Host	smart-93e42b90-b088-45b0-bcfe-8ea47b0d0159
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062029864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.4062029864
Directory	/workspace/26.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/26.keymgr_random.530040989
Short name	T644
Test name
Test status
Simulation time	329478432 ps
CPU time	3.49 seconds
Started	Feb 05 03:38:37 PM PST 24
Finished	Feb 05 03:38:43 PM PST 24
Peak memory	208980 kb
Host	smart-7f00bd31-6fcb-4c53-9406-5e6aebc22409
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530040989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.530040989
Directory	/workspace/26.keymgr_random/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_aes.2679745552
Short name	T190
Test name
Test status
Simulation time	85660605 ps
CPU time	3.29 seconds
Started	Feb 05 03:38:36 PM PST 24
Finished	Feb 05 03:38:42 PM PST 24
Peak memory	208336 kb
Host	smart-5d59dcbc-0c26-4222-931e-114dc1c52da0
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679745552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2679745552
Directory	/workspace/26.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_kmac.4106932260
Short name	T642
Test name
Test status
Simulation time	288064369 ps
CPU time	3.67 seconds
Started	Feb 05 03:38:39 PM PST 24
Finished	Feb 05 03:38:44 PM PST 24
Peak memory	209008 kb
Host	smart-4ab21265-db6f-49e5-947f-d07ef8944789
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106932260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.4106932260
Directory	/workspace/26.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_otbn.3137720677
Short name	T304
Test name
Test status
Simulation time	155690683 ps
CPU time	5.73 seconds
Started	Feb 05 03:38:36 PM PST 24
Finished	Feb 05 03:38:45 PM PST 24
Peak memory	208112 kb
Host	smart-f955c1e3-92c8-47ca-a296-1409bdf82a4c
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137720677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3137720677
Directory	/workspace/26.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_protect.168112722
Short name	T303
Test name
Test status
Simulation time	275804798 ps
CPU time	5.91 seconds
Started	Feb 05 03:38:42 PM PST 24
Finished	Feb 05 03:38:49 PM PST 24
Peak memory	208480 kb
Host	smart-417dfc89-5665-411f-a0a9-b358449c218c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=168112722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.168112722
Directory	/workspace/26.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/26.keymgr_smoke.4181101250
Short name	T406
Test name
Test status
Simulation time	87015075 ps
CPU time	2.38 seconds
Started	Feb 05 03:38:37 PM PST 24
Finished	Feb 05 03:38:42 PM PST 24
Peak memory	206840 kb
Host	smart-cccd35be-1974-440d-91f9-3916c68469c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4181101250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.4181101250
Directory	/workspace/26.keymgr_smoke/latest

Test location	/workspace/coverage/default/26.keymgr_stress_all.2089424254
Short name	T740
Test name
Test status
Simulation time	880661540 ps
CPU time	21.25 seconds
Started	Feb 05 03:38:47 PM PST 24
Finished	Feb 05 03:39:09 PM PST 24
Peak memory	222356 kb
Host	smart-f9a1182e-f9c3-45d5-969e-1b24cb0550ca
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089424254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2089424254
Directory	/workspace/26.keymgr_stress_all/latest

Test location	/workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.952240314
Short name	T342
Test name
Test status
Simulation time	1902307576 ps
CPU time	5.12 seconds
Started	Feb 05 03:38:56 PM PST 24
Finished	Feb 05 03:39:04 PM PST 24
Peak memory	222124 kb
Host	smart-ca51e21f-4252-4792-9d0e-8271834a3e49
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952240314 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.952240314
Directory	/workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.keymgr_sw_invalid_input.1605820903
Short name	T624
Test name
Test status
Simulation time	242080816 ps
CPU time	5.16 seconds
Started	Feb 05 03:38:44 PM PST 24
Finished	Feb 05 03:38:50 PM PST 24
Peak memory	218508 kb
Host	smart-904deeba-a3d5-42fb-a817-a2297bc810e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605820903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1605820903
Directory	/workspace/26.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/26.keymgr_sync_async_fault_cross.2870914083
Short name	T34
Test name
Test status
Simulation time	328773827 ps
CPU time	2.53 seconds
Started	Feb 05 03:38:42 PM PST 24
Finished	Feb 05 03:38:46 PM PST 24
Peak memory	210308 kb
Host	smart-bc4be481-0161-4d18-a961-7ac8ab75138b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2870914083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2870914083
Directory	/workspace/26.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/27.keymgr_custom_cm.822229687
Short name	T33
Test name
Test status
Simulation time	173079763 ps
CPU time	4.77 seconds
Started	Feb 05 03:38:56 PM PST 24
Finished	Feb 05 03:39:02 PM PST 24
Peak memory	222964 kb
Host	smart-5c117d3f-71b4-4ef1-9112-636fdcba2914
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822229687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.822229687
Directory	/workspace/27.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/27.keymgr_direct_to_disabled.4108625545
Short name	T332
Test name
Test status
Simulation time	388531294 ps
CPU time	4 seconds
Started	Feb 05 03:38:56 PM PST 24
Finished	Feb 05 03:39:03 PM PST 24
Peak memory	207112 kb
Host	smart-9499e607-dc91-453e-bcae-c610d88eb15a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4108625545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.4108625545
Directory	/workspace/27.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/27.keymgr_hwsw_invalid_input.3047969199
Short name	T621
Test name
Test status
Simulation time	212817703 ps
CPU time	6.75 seconds
Started	Feb 05 03:38:52 PM PST 24
Finished	Feb 05 03:39:00 PM PST 24
Peak memory	214300 kb
Host	smart-3d199622-c727-4822-9b6a-cdb7234982a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047969199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3047969199
Directory	/workspace/27.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/27.keymgr_lc_disable.692847603
Short name	T756
Test name
Test status
Simulation time	315443927 ps
CPU time	4.31 seconds
Started	Feb 05 03:38:52 PM PST 24
Finished	Feb 05 03:38:57 PM PST 24
Peak memory	222492 kb
Host	smart-d799aff6-731b-402d-83ea-79d1bbc691c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692847603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.692847603
Directory	/workspace/27.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/27.keymgr_random.393670032
Short name	T252
Test name
Test status
Simulation time	168980742 ps
CPU time	4.53 seconds
Started	Feb 05 03:38:54 PM PST 24
Finished	Feb 05 03:39:00 PM PST 24
Peak memory	209888 kb
Host	smart-c2e7b5da-a3f8-4a51-a284-8272ac55e89f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393670032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.393670032
Directory	/workspace/27.keymgr_random/latest

Test location	/workspace/coverage/default/27.keymgr_sideload.4205658837
Short name	T835
Test name
Test status
Simulation time	1173535590 ps
CPU time	8.02 seconds
Started	Feb 05 03:38:52 PM PST 24
Finished	Feb 05 03:39:02 PM PST 24
Peak memory	207836 kb
Host	smart-378b579d-f5ba-4f6d-90ed-822f329cdab2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205658837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4205658837
Directory	/workspace/27.keymgr_sideload/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_aes.2510605471
Short name	T805
Test name
Test status
Simulation time	383673528 ps
CPU time	6.17 seconds
Started	Feb 05 03:38:55 PM PST 24
Finished	Feb 05 03:39:03 PM PST 24
Peak memory	208404 kb
Host	smart-3e7afe08-3c43-41b4-a260-cf28dae44135
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510605471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2510605471
Directory	/workspace/27.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_kmac.2930703228
Short name	T948
Test name
Test status
Simulation time	44478884 ps
CPU time	2.56 seconds
Started	Feb 05 03:38:53 PM PST 24
Finished	Feb 05 03:38:57 PM PST 24
Peak memory	206820 kb
Host	smart-573442f2-8e41-4303-8de5-124135b87987
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930703228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2930703228
Directory	/workspace/27.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_otbn.1201029351
Short name	T906
Test name
Test status
Simulation time	94153369 ps
CPU time	3.53 seconds
Started	Feb 05 03:38:58 PM PST 24
Finished	Feb 05 03:39:05 PM PST 24
Peak memory	206712 kb
Host	smart-bde2bb67-28c6-4df4-a4a4-8a1a72bc92dd
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201029351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1201029351
Directory	/workspace/27.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_protect.4026908701
Short name	T803
Test name
Test status
Simulation time	29886094 ps
CPU time	2 seconds
Started	Feb 05 03:38:56 PM PST 24
Finished	Feb 05 03:38:59 PM PST 24
Peak memory	215612 kb
Host	smart-3372e8b2-fdd9-4754-9c9c-6b3eddc3da7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026908701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.4026908701
Directory	/workspace/27.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/27.keymgr_smoke.1655111673
Short name	T617
Test name
Test status
Simulation time	82794614 ps
CPU time	1.87 seconds
Started	Feb 05 03:38:52 PM PST 24
Finished	Feb 05 03:38:56 PM PST 24
Peak memory	206836 kb
Host	smart-622f6e09-f34a-4a72-9420-bcccb326e3f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1655111673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1655111673
Directory	/workspace/27.keymgr_smoke/latest

Test location	/workspace/coverage/default/27.keymgr_stress_all.3707708530
Short name	T201
Test name
Test status
Simulation time	562228984 ps
CPU time	11.05 seconds
Started	Feb 05 03:38:50 PM PST 24
Finished	Feb 05 03:39:03 PM PST 24
Peak memory	222472 kb
Host	smart-53bf5e4f-edd0-49fd-8c8f-dfe7d7430230
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707708530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3707708530
Directory	/workspace/27.keymgr_stress_all/latest

Test location	/workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.4050701713
Short name	T696
Test name
Test status
Simulation time	1400437954 ps
CPU time	4.14 seconds
Started	Feb 05 03:38:57 PM PST 24
Finished	Feb 05 03:39:04 PM PST 24
Peak memory	222636 kb
Host	smart-fff25456-dbd3-470e-8c1c-4aaa56007e64
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050701713 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.4050701713
Directory	/workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.keymgr_sw_invalid_input.212132065
Short name	T949
Test name
Test status
Simulation time	145929078 ps
CPU time	2.57 seconds
Started	Feb 05 03:38:50 PM PST 24
Finished	Feb 05 03:38:54 PM PST 24
Peak memory	214256 kb
Host	smart-a14b0a88-d72c-4726-b024-6a29208da180
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=212132065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.212132065
Directory	/workspace/27.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/28.keymgr_alert_test.2606404061
Short name	T625
Test name
Test status
Simulation time	8504018 ps
CPU time	0.71 seconds
Started	Feb 05 03:38:56 PM PST 24
Finished	Feb 05 03:38:59 PM PST 24
Peak memory	205816 kb
Host	smart-b315b08d-7ed9-4624-b58d-66127d50bbb8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606404061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2606404061
Directory	/workspace/28.keymgr_alert_test/latest

Test location	/workspace/coverage/default/28.keymgr_cfg_regwen.1617161623
Short name	T213
Test name
Test status
Simulation time	36943084 ps
CPU time	2.99 seconds
Started	Feb 05 03:38:56 PM PST 24
Finished	Feb 05 03:39:02 PM PST 24
Peak memory	214092 kb
Host	smart-bc955fe9-00ae-476d-b819-1e7efc5a5dce
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1617161623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1617161623
Directory	/workspace/28.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/28.keymgr_custom_cm.591607386
Short name	T17
Test name
Test status
Simulation time	102426658 ps
CPU time	4.42 seconds
Started	Feb 05 03:38:57 PM PST 24
Finished	Feb 05 03:39:04 PM PST 24
Peak memory	209136 kb
Host	smart-14a9d70e-31d7-4302-9614-b3aeb6114c2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591607386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.591607386
Directory	/workspace/28.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/28.keymgr_direct_to_disabled.2547335553
Short name	T687
Test name
Test status
Simulation time	35851461 ps
CPU time	1.98 seconds
Started	Feb 05 03:38:52 PM PST 24
Finished	Feb 05 03:38:55 PM PST 24
Peak memory	214388 kb
Host	smart-3a91c560-2f9b-4c19-a9be-542f5f74858a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547335553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2547335553
Directory	/workspace/28.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/28.keymgr_hwsw_invalid_input.1471565336
Short name	T812
Test name
Test status
Simulation time	732452271 ps
CPU time	6.59 seconds
Started	Feb 05 03:38:55 PM PST 24
Finished	Feb 05 03:39:03 PM PST 24
Peak memory	214324 kb
Host	smart-98e9ea07-3d37-482d-8723-7bd67a30ce21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1471565336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1471565336
Directory	/workspace/28.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/28.keymgr_lc_disable.2498412902
Short name	T379
Test name
Test status
Simulation time	42659010 ps
CPU time	2.85 seconds
Started	Feb 05 03:38:47 PM PST 24
Finished	Feb 05 03:38:51 PM PST 24
Peak memory	214248 kb
Host	smart-7749b47a-f332-4b16-8e4d-0ae94affd516
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498412902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2498412902
Directory	/workspace/28.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/28.keymgr_random.1792929475
Short name	T677
Test name
Test status
Simulation time	274661957 ps
CPU time	8.46 seconds
Started	Feb 05 03:38:51 PM PST 24
Finished	Feb 05 03:39:01 PM PST 24
Peak memory	207680 kb
Host	smart-08bcb492-b6ae-43cf-af59-be701aefe22b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1792929475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1792929475
Directory	/workspace/28.keymgr_random/latest

Test location	/workspace/coverage/default/28.keymgr_sideload.3210157741
Short name	T775
Test name
Test status
Simulation time	8348490523 ps
CPU time	60.76 seconds
Started	Feb 05 03:38:54 PM PST 24
Finished	Feb 05 03:39:57 PM PST 24
Peak memory	208848 kb
Host	smart-57035985-6c28-4712-baa9-82065a1d1bcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210157741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3210157741
Directory	/workspace/28.keymgr_sideload/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_aes.3091693791
Short name	T558
Test name
Test status
Simulation time	545309994 ps
CPU time	9.72 seconds
Started	Feb 05 03:38:54 PM PST 24
Finished	Feb 05 03:39:05 PM PST 24
Peak memory	208236 kb
Host	smart-ff6a6ca7-beb5-459b-994c-8cfe9cb40e1c
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091693791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3091693791
Directory	/workspace/28.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_kmac.1360984210
Short name	T904
Test name
Test status
Simulation time	130204062 ps
CPU time	3.31 seconds
Started	Feb 05 03:38:52 PM PST 24
Finished	Feb 05 03:38:56 PM PST 24
Peak memory	208548 kb
Host	smart-b99d923b-31c2-409a-9487-f15a26913a70
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360984210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1360984210
Directory	/workspace/28.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_otbn.4092197015
Short name	T607
Test name
Test status
Simulation time	141367144 ps
CPU time	2.62 seconds
Started	Feb 05 03:38:58 PM PST 24
Finished	Feb 05 03:39:04 PM PST 24
Peak memory	206736 kb
Host	smart-6226b3a5-0ddd-4c71-9e5e-59fab15953b6
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092197015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4092197015
Directory	/workspace/28.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_protect.550610486
Short name	T320
Test name
Test status
Simulation time	92666721 ps
CPU time	2.12 seconds
Started	Feb 05 03:38:51 PM PST 24
Finished	Feb 05 03:38:55 PM PST 24
Peak memory	208148 kb
Host	smart-13d2f9f8-1453-44cf-9bbd-292b2fad2e06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550610486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.550610486
Directory	/workspace/28.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/28.keymgr_sw_invalid_input.2518263296
Short name	T752
Test name
Test status
Simulation time	1312485109 ps
CPU time	38.41 seconds
Started	Feb 05 03:38:51 PM PST 24
Finished	Feb 05 03:39:31 PM PST 24
Peak memory	208420 kb
Host	smart-aa470cc0-20bf-4bd0-bea2-208e3601661c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2518263296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2518263296
Directory	/workspace/28.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/28.keymgr_sync_async_fault_cross.3016004326
Short name	T683
Test name
Test status
Simulation time	328994403 ps
CPU time	3.43 seconds
Started	Feb 05 03:39:01 PM PST 24
Finished	Feb 05 03:39:07 PM PST 24
Peak memory	209844 kb
Host	smart-bf38a97f-b745-4b34-a90b-ecc0d3b66813
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3016004326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3016004326
Directory	/workspace/28.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/29.keymgr_alert_test.774285431
Short name	T846
Test name
Test status
Simulation time	32685514 ps
CPU time	0.74 seconds
Started	Feb 05 03:39:04 PM PST 24
Finished	Feb 05 03:39:12 PM PST 24
Peak memory	205628 kb
Host	smart-e0fb57d8-e3e1-4d22-893b-14ec5cf3ec20
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774285431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.774285431
Directory	/workspace/29.keymgr_alert_test/latest

Test location	/workspace/coverage/default/29.keymgr_cfg_regwen.1240359961
Short name	T289
Test name
Test status
Simulation time	51251262 ps
CPU time	3.79 seconds
Started	Feb 05 03:38:56 PM PST 24
Finished	Feb 05 03:39:03 PM PST 24
Peak memory	214280 kb
Host	smart-ef14e310-f03c-4d4c-a204-63802b307ef0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1240359961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1240359961
Directory	/workspace/29.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/29.keymgr_direct_to_disabled.290049455
Short name	T331
Test name
Test status
Simulation time	302301525 ps
CPU time	3.66 seconds
Started	Feb 05 03:38:59 PM PST 24
Finished	Feb 05 03:39:05 PM PST 24
Peak memory	208620 kb
Host	smart-d0137ea0-2f9b-44f6-b920-c84cd2c295db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290049455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.290049455
Directory	/workspace/29.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/29.keymgr_kmac_rsp_err.3040061663
Short name	T183
Test name
Test status
Simulation time	1572535365 ps
CPU time	12.12 seconds
Started	Feb 05 03:38:58 PM PST 24
Finished	Feb 05 03:39:14 PM PST 24
Peak memory	209948 kb
Host	smart-30cf801f-7f3b-44dc-93af-aab66f729413
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040061663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3040061663
Directory	/workspace/29.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/29.keymgr_lc_disable.1904066699
Short name	T823
Test name
Test status
Simulation time	99921168 ps
CPU time	2.96 seconds
Started	Feb 05 03:38:57 PM PST 24
Finished	Feb 05 03:39:03 PM PST 24
Peak memory	208176 kb
Host	smart-5fec39ab-3c15-4e18-9753-dde37722bdcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904066699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1904066699
Directory	/workspace/29.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/29.keymgr_random.1145562264
Short name	T699
Test name
Test status
Simulation time	686158471 ps
CPU time	9.44 seconds
Started	Feb 05 03:39:03 PM PST 24
Finished	Feb 05 03:39:16 PM PST 24
Peak memory	218312 kb
Host	smart-f94ac410-0671-46fe-aba9-6fdfaf2451e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145562264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1145562264
Directory	/workspace/29.keymgr_random/latest

Test location	/workspace/coverage/default/29.keymgr_sideload.2247310660
Short name	T645
Test name
Test status
Simulation time	4393945193 ps
CPU time	31.25 seconds
Started	Feb 05 03:38:55 PM PST 24
Finished	Feb 05 03:39:28 PM PST 24
Peak memory	208792 kb
Host	smart-1ce4e0dc-6e29-4701-85a4-d06b4399c2c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2247310660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2247310660
Directory	/workspace/29.keymgr_sideload/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_aes.3182576915
Short name	T857
Test name
Test status
Simulation time	46281016 ps
CPU time	1.95 seconds
Started	Feb 05 03:38:58 PM PST 24
Finished	Feb 05 03:39:04 PM PST 24
Peak memory	206796 kb
Host	smart-8ce8074c-bc3f-43aa-bce3-843f1acd5fb6
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182576915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3182576915
Directory	/workspace/29.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_otbn.1972134082
Short name	T78
Test name
Test status
Simulation time	1902642661 ps
CPU time	7.8 seconds
Started	Feb 05 03:38:58 PM PST 24
Finished	Feb 05 03:39:09 PM PST 24
Peak memory	208652 kb
Host	smart-1c38f459-7659-473d-9570-764b8c5ef2f1
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972134082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1972134082
Directory	/workspace/29.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_protect.2535036503
Short name	T680
Test name
Test status
Simulation time	117841944 ps
CPU time	2.87 seconds
Started	Feb 05 03:38:57 PM PST 24
Finished	Feb 05 03:39:03 PM PST 24
Peak memory	218148 kb
Host	smart-64cd17b7-0198-4408-bf00-5df460eb793c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2535036503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2535036503
Directory	/workspace/29.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/29.keymgr_smoke.3449343344
Short name	T910
Test name
Test status
Simulation time	136934316 ps
CPU time	3.8 seconds
Started	Feb 05 03:39:01 PM PST 24
Finished	Feb 05 03:39:07 PM PST 24
Peak memory	207656 kb
Host	smart-bf7f7983-72a2-490f-bfe9-f3e691a6e59d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449343344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3449343344
Directory	/workspace/29.keymgr_smoke/latest

Test location	/workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.965522320
Short name	T310
Test name
Test status
Simulation time	409870873 ps
CPU time	3.44 seconds
Started	Feb 05 03:39:03 PM PST 24
Finished	Feb 05 03:39:09 PM PST 24
Peak memory	222316 kb
Host	smart-65de3e6b-28cd-4d99-856c-e9cc970a72df
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965522320 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.965522320
Directory	/workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.keymgr_sw_invalid_input.2819606600
Short name	T899
Test name
Test status
Simulation time	313982315 ps
CPU time	3.93 seconds
Started	Feb 05 03:39:01 PM PST 24
Finished	Feb 05 03:39:08 PM PST 24
Peak memory	207160 kb
Host	smart-66e23d0b-e025-4a62-a5ca-7bf61501255c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819606600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2819606600
Directory	/workspace/29.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/29.keymgr_sync_async_fault_cross.851334221
Short name	T937
Test name
Test status
Simulation time	302788439 ps
CPU time	2.62 seconds
Started	Feb 05 03:39:01 PM PST 24
Finished	Feb 05 03:39:06 PM PST 24
Peak memory	210988 kb
Host	smart-6b888f0c-0a5b-4e3e-97bc-1e1abe899804
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851334221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.851334221
Directory	/workspace/29.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/3.keymgr_alert_test.3181805392
Short name	T554
Test name
Test status
Simulation time	82479975 ps
CPU time	0.87 seconds
Started	Feb 05 03:36:33 PM PST 24
Finished	Feb 05 03:36:49 PM PST 24
Peak memory	205840 kb
Host	smart-805d586c-645e-407a-a585-5f2702783e88
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181805392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3181805392
Directory	/workspace/3.keymgr_alert_test/latest

Test location	/workspace/coverage/default/3.keymgr_direct_to_disabled.3227153217
Short name	T576
Test name
Test status
Simulation time	462179715 ps
CPU time	6.66 seconds
Started	Feb 05 03:36:28 PM PST 24
Finished	Feb 05 03:36:53 PM PST 24
Peak memory	209176 kb
Host	smart-0906ff5e-9efd-46e4-952f-4578fee247ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227153217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3227153217
Directory	/workspace/3.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/3.keymgr_hwsw_invalid_input.142892138
Short name	T363
Test name
Test status
Simulation time	392767755 ps
CPU time	3.54 seconds
Started	Feb 05 03:36:29 PM PST 24
Finished	Feb 05 03:36:52 PM PST 24
Peak memory	209480 kb
Host	smart-853a9a53-5bc8-469a-a163-c6b81013c939
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=142892138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.142892138
Directory	/workspace/3.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/3.keymgr_sec_cm.4179121672
Short name	T13
Test name
Test status
Simulation time	1101283554 ps
CPU time	10.24 seconds
Started	Feb 05 03:36:35 PM PST 24
Finished	Feb 05 03:36:59 PM PST 24
Peak memory	230744 kb
Host	smart-b6f8f11f-795b-40a4-bf0b-c8f2b4cdbb74
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179121672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4179121672
Directory	/workspace/3.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/3.keymgr_sideload.2295984643
Short name	T339
Test name
Test status
Simulation time	99337664 ps
CPU time	2.16 seconds
Started	Feb 05 03:36:30 PM PST 24
Finished	Feb 05 03:36:51 PM PST 24
Peak memory	208524 kb
Host	smart-4813cafa-8b34-4cbc-866d-6eed2074e404
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295984643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2295984643
Directory	/workspace/3.keymgr_sideload/latest

Test location	/workspace/coverage/default/3.keymgr_sideload_aes.1860779209
Short name	T377
Test name
Test status
Simulation time	2794715534 ps
CPU time	7.79 seconds
Started	Feb 05 03:36:25 PM PST 24
Finished	Feb 05 03:36:49 PM PST 24
Peak memory	207952 kb
Host	smart-73440c2c-d224-44af-b267-827e209fbeba
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860779209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1860779209
Directory	/workspace/3.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/3.keymgr_sideload_kmac.3697067387
Short name	T258
Test name
Test status
Simulation time	40173140 ps
CPU time	1.75 seconds
Started	Feb 05 03:36:35 PM PST 24
Finished	Feb 05 03:36:51 PM PST 24
Peak memory	206660 kb
Host	smart-4d13f9dc-4852-4676-9c14-6e4f60607c7c
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697067387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3697067387
Directory	/workspace/3.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/3.keymgr_sideload_protect.3206221331
Short name	T789
Test name
Test status
Simulation time	52807157 ps
CPU time	2.78 seconds
Started	Feb 05 03:36:41 PM PST 24
Finished	Feb 05 03:36:53 PM PST 24
Peak memory	214272 kb
Host	smart-5830211d-9933-4960-9ed3-1723b761d7d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206221331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3206221331
Directory	/workspace/3.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/3.keymgr_smoke.3133689056
Short name	T622
Test name
Test status
Simulation time	65231406 ps
CPU time	2.83 seconds
Started	Feb 05 03:36:28 PM PST 24
Finished	Feb 05 03:36:50 PM PST 24
Peak memory	208096 kb
Host	smart-fd76bdc2-3f18-4e61-ac16-2ff00628a68c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3133689056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3133689056
Directory	/workspace/3.keymgr_smoke/latest

Test location	/workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3789678039
Short name	T130
Test name
Test status
Simulation time	166253800 ps
CPU time	2.81 seconds
Started	Feb 05 03:36:35 PM PST 24
Finished	Feb 05 03:36:51 PM PST 24
Peak memory	222652 kb
Host	smart-e700f0ef-3178-4e0d-83b3-0279c2ea3717
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789678039 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3789678039
Directory	/workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.keymgr_sw_invalid_input.1812774755
Short name	T585
Test name
Test status
Simulation time	91173488 ps
CPU time	4.1 seconds
Started	Feb 05 03:36:33 PM PST 24
Finished	Feb 05 03:36:53 PM PST 24
Peak memory	207900 kb
Host	smart-88921965-1402-48e4-9807-8efd9b8bcbf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1812774755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1812774755
Directory	/workspace/3.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/3.keymgr_sync_async_fault_cross.4254708636
Short name	T60
Test name
Test status
Simulation time	805319482 ps
CPU time	2.91 seconds
Started	Feb 05 03:36:36 PM PST 24
Finished	Feb 05 03:36:52 PM PST 24
Peak memory	210224 kb
Host	smart-36155cb6-1aa5-4113-922c-3e136b5640a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254708636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.4254708636
Directory	/workspace/3.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/30.keymgr_alert_test.583229492
Short name	T945
Test name
Test status
Simulation time	13098261 ps
CPU time	0.89 seconds
Started	Feb 05 03:39:08 PM PST 24
Finished	Feb 05 03:39:18 PM PST 24
Peak memory	205636 kb
Host	smart-66a2a72c-62bb-42ac-9b17-b18963a72bb3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583229492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.583229492
Directory	/workspace/30.keymgr_alert_test/latest

Test location	/workspace/coverage/default/30.keymgr_direct_to_disabled.3687697819
Short name	T62
Test name
Test status
Simulation time	3233295639 ps
CPU time	30.73 seconds
Started	Feb 05 03:39:04 PM PST 24
Finished	Feb 05 03:39:42 PM PST 24
Peak memory	208032 kb
Host	smart-7c0413ee-6dac-4102-b0dc-a16b5ffaf263
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687697819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3687697819
Directory	/workspace/30.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/30.keymgr_hwsw_invalid_input.2600286393
Short name	T967
Test name
Test status
Simulation time	260168624 ps
CPU time	8.79 seconds
Started	Feb 05 03:39:03 PM PST 24
Finished	Feb 05 03:39:15 PM PST 24
Peak memory	214212 kb
Host	smart-9aced736-5d21-4d06-b461-dfcdd6960540
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600286393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2600286393
Directory	/workspace/30.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/30.keymgr_lc_disable.1604398495
Short name	T50
Test name
Test status
Simulation time	470088198 ps
CPU time	3.54 seconds
Started	Feb 05 03:39:08 PM PST 24
Finished	Feb 05 03:39:20 PM PST 24
Peak memory	214204 kb
Host	smart-5261757c-ec3e-44bb-bdab-af9b97e97c2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604398495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1604398495
Directory	/workspace/30.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/30.keymgr_random.2939651701
Short name	T679
Test name
Test status
Simulation time	138344255 ps
CPU time	5.55 seconds
Started	Feb 05 03:39:03 PM PST 24
Finished	Feb 05 03:39:12 PM PST 24
Peak memory	214296 kb
Host	smart-f4f79cc4-a6d8-4c06-9747-37f14e02ac6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939651701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2939651701
Directory	/workspace/30.keymgr_random/latest

Test location	/workspace/coverage/default/30.keymgr_sideload.1065224894
Short name	T678
Test name
Test status
Simulation time	145621933 ps
CPU time	2.49 seconds
Started	Feb 05 03:39:05 PM PST 24
Finished	Feb 05 03:39:15 PM PST 24
Peak memory	206812 kb
Host	smart-db74a964-2cdc-4079-8995-664d3e80758c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1065224894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1065224894
Directory	/workspace/30.keymgr_sideload/latest

Test location	/workspace/coverage/default/30.keymgr_sideload_aes.1502039267
Short name	T771
Test name
Test status
Simulation time	170678142 ps
CPU time	6.73 seconds
Started	Feb 05 03:38:57 PM PST 24
Finished	Feb 05 03:39:07 PM PST 24
Peak memory	207808 kb
Host	smart-58d19b74-0ed0-482f-85c7-2e873dd34388
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502039267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1502039267
Directory	/workspace/30.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/30.keymgr_sideload_kmac.2794363950
Short name	T579
Test name
Test status
Simulation time	30194298 ps
CPU time	2.1 seconds
Started	Feb 05 03:38:56 PM PST 24
Finished	Feb 05 03:39:01 PM PST 24
Peak memory	208324 kb
Host	smart-2130cb68-9191-43ff-8403-72d3a8fb0d03
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794363950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2794363950
Directory	/workspace/30.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/30.keymgr_sideload_protect.423460925
Short name	T120
Test name
Test status
Simulation time	134464601 ps
CPU time	3.21 seconds
Started	Feb 05 03:39:01 PM PST 24
Finished	Feb 05 03:39:07 PM PST 24
Peak memory	208860 kb
Host	smart-4b6880f4-f530-4d65-9df3-6b26192a4390
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=423460925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.423460925
Directory	/workspace/30.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/30.keymgr_smoke.90640813
Short name	T871
Test name
Test status
Simulation time	71951827 ps
CPU time	2.4 seconds
Started	Feb 05 03:39:04 PM PST 24
Finished	Feb 05 03:39:15 PM PST 24
Peak memory	206856 kb
Host	smart-98fab8df-a450-4257-9d24-c5b3343bc7c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90640813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.90640813
Directory	/workspace/30.keymgr_smoke/latest

Test location	/workspace/coverage/default/30.keymgr_sw_invalid_input.1733171352
Short name	T178
Test name
Test status
Simulation time	104003257 ps
CPU time	2.61 seconds
Started	Feb 05 03:39:04 PM PST 24
Finished	Feb 05 03:39:14 PM PST 24
Peak memory	206956 kb
Host	smart-d561e861-f0a0-4497-b09d-1ad2981c0e18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733171352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1733171352
Directory	/workspace/30.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/30.keymgr_sync_async_fault_cross.3942877131
Short name	T381
Test name
Test status
Simulation time	375542629 ps
CPU time	1.84 seconds
Started	Feb 05 03:39:03 PM PST 24
Finished	Feb 05 03:39:08 PM PST 24
Peak memory	210300 kb
Host	smart-777b7161-84a8-4436-8893-7acb651f33e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3942877131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3942877131
Directory	/workspace/30.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/31.keymgr_alert_test.2314836593
Short name	T733
Test name
Test status
Simulation time	11434151 ps
CPU time	0.74 seconds
Started	Feb 05 03:39:09 PM PST 24
Finished	Feb 05 03:39:17 PM PST 24
Peak memory	205800 kb
Host	smart-6900dbdb-0c50-4374-9aec-f0576c8b5f2e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314836593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2314836593
Directory	/workspace/31.keymgr_alert_test/latest

Test location	/workspace/coverage/default/31.keymgr_direct_to_disabled.930743180
Short name	T701
Test name
Test status
Simulation time	61478398 ps
CPU time	2.54 seconds
Started	Feb 05 03:39:05 PM PST 24
Finished	Feb 05 03:39:17 PM PST 24
Peak memory	210152 kb
Host	smart-917e9b4f-0437-4fe2-9ff1-73b93446f67f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930743180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.930743180
Directory	/workspace/31.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/31.keymgr_lc_disable.921284769
Short name	T280
Test name
Test status
Simulation time	113794354 ps
CPU time	3.52 seconds
Started	Feb 05 03:39:11 PM PST 24
Finished	Feb 05 03:39:20 PM PST 24
Peak memory	214228 kb
Host	smart-cf6b27ca-200c-417e-90be-dd2bee30a704
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=921284769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.921284769
Directory	/workspace/31.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/31.keymgr_sideload.3079496292
Short name	T765
Test name
Test status
Simulation time	273166339 ps
CPU time	3.19 seconds
Started	Feb 05 03:39:05 PM PST 24
Finished	Feb 05 03:39:17 PM PST 24
Peak memory	208632 kb
Host	smart-4450fa73-3a80-4f93-aa07-b6caea202556
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079496292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3079496292
Directory	/workspace/31.keymgr_sideload/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_aes.2969248987
Short name	T950
Test name
Test status
Simulation time	1368749172 ps
CPU time	6.17 seconds
Started	Feb 05 03:39:06 PM PST 24
Finished	Feb 05 03:39:21 PM PST 24
Peak memory	208856 kb
Host	smart-67defbbc-19fd-4970-acfb-5089d24cbe5e
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969248987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2969248987
Directory	/workspace/31.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_kmac.1531611061
Short name	T719
Test name
Test status
Simulation time	47780571 ps
CPU time	2.76 seconds
Started	Feb 05 03:39:05 PM PST 24
Finished	Feb 05 03:39:17 PM PST 24
Peak memory	208312 kb
Host	smart-4bd9b350-4c56-46ba-b573-8e2dfa7368e3
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531611061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1531611061
Directory	/workspace/31.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_otbn.1245806967
Short name	T628
Test name
Test status
Simulation time	698411643 ps
CPU time	6.49 seconds
Started	Feb 05 03:39:06 PM PST 24
Finished	Feb 05 03:39:21 PM PST 24
Peak memory	206944 kb
Host	smart-2aca324c-6507-41ff-a9f6-74e264d01994
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245806967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1245806967
Directory	/workspace/31.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_protect.1951070911
Short name	T390
Test name
Test status
Simulation time	172080396 ps
CPU time	4.15 seconds
Started	Feb 05 03:39:02 PM PST 24
Finished	Feb 05 03:39:08 PM PST 24
Peak memory	209704 kb
Host	smart-a011bd0b-b8fc-49c7-b452-4db375171b5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1951070911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1951070911
Directory	/workspace/31.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/31.keymgr_smoke.1410443424
Short name	T586
Test name
Test status
Simulation time	119863704 ps
CPU time	3.05 seconds
Started	Feb 05 03:39:02 PM PST 24
Finished	Feb 05 03:39:08 PM PST 24
Peak memory	206636 kb
Host	smart-7d6a17ab-29e7-41e0-812d-4574ac4d1468
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410443424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1410443424
Directory	/workspace/31.keymgr_smoke/latest

Test location	/workspace/coverage/default/31.keymgr_stress_all.3229504366
Short name	T801
Test name
Test status
Simulation time	207844090 ps
CPU time	7.62 seconds
Started	Feb 05 03:39:11 PM PST 24
Finished	Feb 05 03:39:24 PM PST 24
Peak memory	208168 kb
Host	smart-7dbee53e-905f-4dd0-a880-0c620589888e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229504366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3229504366
Directory	/workspace/31.keymgr_stress_all/latest

Test location	/workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2203213846
Short name	T694
Test name
Test status
Simulation time	480534277 ps
CPU time	4.41 seconds
Started	Feb 05 03:39:04 PM PST 24
Finished	Feb 05 03:39:15 PM PST 24
Peak memory	222688 kb
Host	smart-1a81f562-fe99-481a-9e18-5bddc0a7e21e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203213846 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2203213846
Directory	/workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.keymgr_sw_invalid_input.2767425460
Short name	T391
Test name
Test status
Simulation time	3719093852 ps
CPU time	36.5 seconds
Started	Feb 05 03:39:04 PM PST 24
Finished	Feb 05 03:39:48 PM PST 24
Peak memory	220856 kb
Host	smart-8b9fed78-71a6-4edb-822a-3019dc5c29ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2767425460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2767425460
Directory	/workspace/31.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/31.keymgr_sync_async_fault_cross.2960632630
Short name	T565
Test name
Test status
Simulation time	350636978 ps
CPU time	2.75 seconds
Started	Feb 05 03:39:03 PM PST 24
Finished	Feb 05 03:39:08 PM PST 24
Peak memory	209880 kb
Host	smart-861cd9d9-f469-41b2-bf30-d3ea52a1866b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960632630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2960632630
Directory	/workspace/31.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/32.keymgr_alert_test.2895452782
Short name	T96
Test name
Test status
Simulation time	12087254 ps
CPU time	0.88 seconds
Started	Feb 05 03:39:11 PM PST 24
Finished	Feb 05 03:39:18 PM PST 24
Peak memory	205812 kb
Host	smart-e9396cda-bdd1-47ba-8978-86a545f949ed
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895452782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2895452782
Directory	/workspace/32.keymgr_alert_test/latest

Test location	/workspace/coverage/default/32.keymgr_custom_cm.901235058
Short name	T672
Test name
Test status
Simulation time	728604553 ps
CPU time	5.59 seconds
Started	Feb 05 03:39:12 PM PST 24
Finished	Feb 05 03:39:22 PM PST 24
Peak memory	214616 kb
Host	smart-3c24521a-8273-41c0-b4e7-dfc21c667795
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901235058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.901235058
Directory	/workspace/32.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/32.keymgr_direct_to_disabled.1169902659
Short name	T69
Test name
Test status
Simulation time	315528106 ps
CPU time	7.19 seconds
Started	Feb 05 03:39:12 PM PST 24
Finished	Feb 05 03:39:24 PM PST 24
Peak memory	209492 kb
Host	smart-115273a3-5fff-4deb-a4c5-d4fdf4ee1355
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169902659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1169902659
Directory	/workspace/32.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/32.keymgr_hwsw_invalid_input.753115345
Short name	T89
Test name
Test status
Simulation time	496990448 ps
CPU time	10.8 seconds
Started	Feb 05 03:39:13 PM PST 24
Finished	Feb 05 03:39:28 PM PST 24
Peak memory	214284 kb
Host	smart-9af5f01f-1fdd-4752-8bca-abe51826adf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=753115345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.753115345
Directory	/workspace/32.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/32.keymgr_kmac_rsp_err.1322842104
Short name	T335
Test name
Test status
Simulation time	109350535 ps
CPU time	3.97 seconds
Started	Feb 05 03:39:14 PM PST 24
Finished	Feb 05 03:39:23 PM PST 24
Peak memory	210376 kb
Host	smart-58b5f7d0-0536-424e-b4b3-0e249f33dc2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1322842104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1322842104
Directory	/workspace/32.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/32.keymgr_random.3791020745
Short name	T704
Test name
Test status
Simulation time	132172462 ps
CPU time	3.67 seconds
Started	Feb 05 03:39:14 PM PST 24
Finished	Feb 05 03:39:23 PM PST 24
Peak memory	209628 kb
Host	smart-69ded8fc-c53e-470c-8aff-6b5a786d35fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3791020745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3791020745
Directory	/workspace/32.keymgr_random/latest

Test location	/workspace/coverage/default/32.keymgr_sideload.1417035969
Short name	T931
Test name
Test status
Simulation time	229125898 ps
CPU time	6.86 seconds
Started	Feb 05 03:39:04 PM PST 24
Finished	Feb 05 03:39:20 PM PST 24
Peak memory	206648 kb
Host	smart-9c5ab6b3-e284-452d-abc1-4953b254a958
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417035969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1417035969
Directory	/workspace/32.keymgr_sideload/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_aes.2681730783
Short name	T295
Test name
Test status
Simulation time	308387157 ps
CPU time	3.82 seconds
Started	Feb 05 03:39:09 PM PST 24
Finished	Feb 05 03:39:21 PM PST 24
Peak memory	208620 kb
Host	smart-eb51da88-651a-4c9b-a51b-c8cd28aa62cd
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681730783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2681730783
Directory	/workspace/32.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_kmac.1414759903
Short name	T561
Test name
Test status
Simulation time	410734523 ps
CPU time	5.51 seconds
Started	Feb 05 03:39:05 PM PST 24
Finished	Feb 05 03:39:20 PM PST 24
Peak memory	208448 kb
Host	smart-47c7bd02-89e4-42e5-994e-089fe77dbc54
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414759903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1414759903
Directory	/workspace/32.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_otbn.4108218369
Short name	T854
Test name
Test status
Simulation time	27991376 ps
CPU time	2.08 seconds
Started	Feb 05 03:39:10 PM PST 24
Finished	Feb 05 03:39:19 PM PST 24
Peak memory	208572 kb
Host	smart-20eb0d75-451d-46e8-89e1-266e314066a7
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108218369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.4108218369
Directory	/workspace/32.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_protect.680289049
Short name	T192
Test name
Test status
Simulation time	125577605 ps
CPU time	3.21 seconds
Started	Feb 05 03:39:14 PM PST 24
Finished	Feb 05 03:39:22 PM PST 24
Peak memory	214268 kb
Host	smart-b5381479-0313-43fd-8d58-0124af897d3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680289049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.680289049
Directory	/workspace/32.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/32.keymgr_smoke.24487082
Short name	T964
Test name
Test status
Simulation time	60211591 ps
CPU time	2.93 seconds
Started	Feb 05 03:39:05 PM PST 24
Finished	Feb 05 03:39:17 PM PST 24
Peak memory	206588 kb
Host	smart-417bd7cf-5803-48a4-8630-eec97fcde1ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24487082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.24487082
Directory	/workspace/32.keymgr_smoke/latest

Test location	/workspace/coverage/default/32.keymgr_stress_all.4108086516
Short name	T608
Test name
Test status
Simulation time	587157955 ps
CPU time	6.11 seconds
Started	Feb 05 03:39:09 PM PST 24
Finished	Feb 05 03:39:23 PM PST 24
Peak memory	216928 kb
Host	smart-c64907ff-af63-4f3d-be0c-1d1a7a6293f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108086516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.4108086516
Directory	/workspace/32.keymgr_stress_all/latest

Test location	/workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3358083772
Short name	T784
Test name
Test status
Simulation time	151850624 ps
CPU time	6.12 seconds
Started	Feb 05 03:39:08 PM PST 24
Finished	Feb 05 03:39:23 PM PST 24
Peak memory	220044 kb
Host	smart-541b2c2b-e5f5-40b9-9dc0-6d96a494b98f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358083772 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3358083772
Directory	/workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.keymgr_sw_invalid_input.1327793376
Short name	T319
Test name
Test status
Simulation time	131485523 ps
CPU time	5.73 seconds
Started	Feb 05 03:39:08 PM PST 24
Finished	Feb 05 03:39:22 PM PST 24
Peak memory	209256 kb
Host	smart-7b1f3050-d839-4c9a-84cb-d95e779a8b31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1327793376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1327793376
Directory	/workspace/32.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/32.keymgr_sync_async_fault_cross.912036351
Short name	T940
Test name
Test status
Simulation time	99409889 ps
CPU time	2.65 seconds
Started	Feb 05 03:39:11 PM PST 24
Finished	Feb 05 03:39:19 PM PST 24
Peak memory	210444 kb
Host	smart-21155050-d276-4fea-9f75-7eb6fe465897
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912036351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.912036351
Directory	/workspace/32.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/33.keymgr_alert_test.2964393248
Short name	T651
Test name
Test status
Simulation time	27851569 ps
CPU time	0.9 seconds
Started	Feb 05 03:39:15 PM PST 24
Finished	Feb 05 03:39:24 PM PST 24
Peak memory	206048 kb
Host	smart-48e0fde3-6821-4a41-a95f-4514a75622c1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964393248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2964393248
Directory	/workspace/33.keymgr_alert_test/latest

Test location	/workspace/coverage/default/33.keymgr_cfg_regwen.659006391
Short name	T261
Test name
Test status
Simulation time	146218937 ps
CPU time	4.85 seconds
Started	Feb 05 03:39:21 PM PST 24
Finished	Feb 05 03:39:31 PM PST 24
Peak memory	214324 kb
Host	smart-24a88dd2-a752-4243-a798-a23ba825f5a7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=659006391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.659006391
Directory	/workspace/33.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/33.keymgr_custom_cm.2217306393
Short name	T35
Test name
Test status
Simulation time	118946564 ps
CPU time	4.82 seconds
Started	Feb 05 03:39:23 PM PST 24
Finished	Feb 05 03:39:31 PM PST 24
Peak memory	208756 kb
Host	smart-dd6afcdd-2ff7-49f5-b831-fc0cafb88609
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217306393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2217306393
Directory	/workspace/33.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/33.keymgr_direct_to_disabled.1181932197
Short name	T627
Test name
Test status
Simulation time	164516740 ps
CPU time	2.31 seconds
Started	Feb 05 03:39:16 PM PST 24
Finished	Feb 05 03:39:26 PM PST 24
Peak memory	210104 kb
Host	smart-25833e59-e87f-4307-af24-36ff8aa55eaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1181932197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1181932197
Directory	/workspace/33.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/33.keymgr_hwsw_invalid_input.2563213641
Short name	T674
Test name
Test status
Simulation time	7576113896 ps
CPU time	46.12 seconds
Started	Feb 05 03:39:18 PM PST 24
Finished	Feb 05 03:40:11 PM PST 24
Peak memory	209492 kb
Host	smart-168806b2-0cdf-4976-9d4e-2e40980a0468
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2563213641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2563213641
Directory	/workspace/33.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/33.keymgr_kmac_rsp_err.4253216025
Short name	T250
Test name
Test status
Simulation time	124319404 ps
CPU time	2.87 seconds
Started	Feb 05 03:39:20 PM PST 24
Finished	Feb 05 03:39:29 PM PST 24
Peak memory	210044 kb
Host	smart-6d53543b-f259-4c2d-b626-c1b3e7ea43a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253216025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4253216025
Directory	/workspace/33.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/33.keymgr_lc_disable.3559086640
Short name	T864
Test name
Test status
Simulation time	131721171 ps
CPU time	4.88 seconds
Started	Feb 05 03:39:20 PM PST 24
Finished	Feb 05 03:39:31 PM PST 24
Peak memory	210068 kb
Host	smart-55ec8fb3-d362-42c0-9b5f-cae7e1dd7cc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3559086640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3559086640
Directory	/workspace/33.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/33.keymgr_random.1097877588
Short name	T891
Test name
Test status
Simulation time	199542289 ps
CPU time	4.85 seconds
Started	Feb 05 03:39:17 PM PST 24
Finished	Feb 05 03:39:29 PM PST 24
Peak memory	209968 kb
Host	smart-7e79c5f5-bc90-4827-b6c8-fb852ffc8a38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097877588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1097877588
Directory	/workspace/33.keymgr_random/latest

Test location	/workspace/coverage/default/33.keymgr_sideload.4241152027
Short name	T599
Test name
Test status
Simulation time	210447021 ps
CPU time	5.8 seconds
Started	Feb 05 03:39:14 PM PST 24
Finished	Feb 05 03:39:25 PM PST 24
Peak memory	207872 kb
Host	smart-b412ee61-4503-46c6-bbb5-36f2830e8cf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241152027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4241152027
Directory	/workspace/33.keymgr_sideload/latest

Test location	/workspace/coverage/default/33.keymgr_sideload_aes.1375323820
Short name	T909
Test name
Test status
Simulation time	2032912100 ps
CPU time	16.35 seconds
Started	Feb 05 03:39:17 PM PST 24
Finished	Feb 05 03:39:40 PM PST 24
Peak memory	208608 kb
Host	smart-9a79ed12-6748-4b24-bdb0-674b7cb2d062
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375323820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1375323820
Directory	/workspace/33.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/33.keymgr_sideload_kmac.2605587773
Short name	T897
Test name
Test status
Simulation time	131371593 ps
CPU time	2.74 seconds
Started	Feb 05 03:39:19 PM PST 24
Finished	Feb 05 03:39:29 PM PST 24
Peak memory	208400 kb
Host	smart-1ab1a181-51a8-44b9-a131-efb6e4a2f2a2
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605587773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2605587773
Directory	/workspace/33.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/33.keymgr_sideload_otbn.338913699
Short name	T240
Test name
Test status
Simulation time	136205061 ps
CPU time	2.24 seconds
Started	Feb 05 03:39:15 PM PST 24
Finished	Feb 05 03:39:24 PM PST 24
Peak memory	206764 kb
Host	smart-f22b96ad-f7cf-44f6-8281-f96e8df882be
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338913699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.338913699
Directory	/workspace/33.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/33.keymgr_smoke.4222792905
Short name	T684
Test name
Test status
Simulation time	110543114 ps
CPU time	3.3 seconds
Started	Feb 05 03:39:14 PM PST 24
Finished	Feb 05 03:39:23 PM PST 24
Peak memory	207744 kb
Host	smart-968ddc51-524b-418e-8cb5-16c958860f63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222792905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.4222792905
Directory	/workspace/33.keymgr_smoke/latest

Test location	/workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2127004821
Short name	T942
Test name
Test status
Simulation time	178705606 ps
CPU time	4.89 seconds
Started	Feb 05 03:39:20 PM PST 24
Finished	Feb 05 03:39:31 PM PST 24
Peak memory	220288 kb
Host	smart-5549c7a5-1383-4566-bb51-457d7f9cabf5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127004821 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2127004821
Directory	/workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.keymgr_sw_invalid_input.299831332
Short name	T239
Test name
Test status
Simulation time	256321859 ps
CPU time	7.84 seconds
Started	Feb 05 03:39:20 PM PST 24
Finished	Feb 05 03:39:34 PM PST 24
Peak memory	214232 kb
Host	smart-69799f2b-89c5-4002-8853-8478c60de37a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=299831332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.299831332
Directory	/workspace/33.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/33.keymgr_sync_async_fault_cross.372839937
Short name	T776
Test name
Test status
Simulation time	2241960710 ps
CPU time	12.43 seconds
Started	Feb 05 03:39:18 PM PST 24
Finished	Feb 05 03:39:38 PM PST 24
Peak memory	210376 kb
Host	smart-2aaf6304-6f8c-4132-b1d5-8a09d2e523a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372839937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.372839937
Directory	/workspace/33.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/34.keymgr_alert_test.1600570414
Short name	T97
Test name
Test status
Simulation time	16014721 ps
CPU time	0.74 seconds
Started	Feb 05 03:39:17 PM PST 24
Finished	Feb 05 03:39:25 PM PST 24
Peak memory	205832 kb
Host	smart-68675041-da0e-4061-bb47-1f06cc8241b5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600570414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1600570414
Directory	/workspace/34.keymgr_alert_test/latest

Test location	/workspace/coverage/default/34.keymgr_direct_to_disabled.3853242751
Short name	T698
Test name
Test status
Simulation time	33021124 ps
CPU time	2.39 seconds
Started	Feb 05 03:39:18 PM PST 24
Finished	Feb 05 03:39:27 PM PST 24
Peak memory	207140 kb
Host	smart-0a63a9c8-4019-46ce-9592-2b8cab6afad4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3853242751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3853242751
Directory	/workspace/34.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/34.keymgr_hwsw_invalid_input.2952550401
Short name	T731
Test name
Test status
Simulation time	7150307470 ps
CPU time	19.63 seconds
Started	Feb 05 03:39:17 PM PST 24
Finished	Feb 05 03:39:44 PM PST 24
Peak memory	209676 kb
Host	smart-9dcbd522-7464-4fe1-9004-23e6164ced0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952550401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2952550401
Directory	/workspace/34.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/34.keymgr_lc_disable.3625666493
Short name	T837
Test name
Test status
Simulation time	439663360 ps
CPU time	3.44 seconds
Started	Feb 05 03:39:17 PM PST 24
Finished	Feb 05 03:39:28 PM PST 24
Peak memory	214320 kb
Host	smart-af83b5bd-2c69-4b34-917c-46e2b5a4d502
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3625666493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3625666493
Directory	/workspace/34.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/34.keymgr_random.1739041311
Short name	T996
Test name
Test status
Simulation time	1124151907 ps
CPU time	34.11 seconds
Started	Feb 05 03:39:15 PM PST 24
Finished	Feb 05 03:39:56 PM PST 24
Peak memory	210160 kb
Host	smart-06fbf092-2656-4d1a-98d6-a2742ff3480c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1739041311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1739041311
Directory	/workspace/34.keymgr_random/latest

Test location	/workspace/coverage/default/34.keymgr_sideload.1930391736
Short name	T315
Test name
Test status
Simulation time	176521867 ps
CPU time	5.23 seconds
Started	Feb 05 03:39:14 PM PST 24
Finished	Feb 05 03:39:24 PM PST 24
Peak memory	208672 kb
Host	smart-915631a3-451f-41c9-bf84-52651d574778
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930391736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1930391736
Directory	/workspace/34.keymgr_sideload/latest

Test location	/workspace/coverage/default/34.keymgr_sideload_aes.2843591094
Short name	T676
Test name
Test status
Simulation time	2221219615 ps
CPU time	17.15 seconds
Started	Feb 05 03:39:13 PM PST 24
Finished	Feb 05 03:39:36 PM PST 24
Peak memory	208964 kb
Host	smart-c4120928-a886-45f3-81c3-6e3102d4b93c
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843591094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2843591094
Directory	/workspace/34.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/34.keymgr_sideload_kmac.268126916
Short name	T563
Test name
Test status
Simulation time	122197373 ps
CPU time	2.58 seconds
Started	Feb 05 03:39:20 PM PST 24
Finished	Feb 05 03:39:29 PM PST 24
Peak memory	206724 kb
Host	smart-5632493f-8d66-4485-9a45-03eea3c59733
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268126916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.268126916
Directory	/workspace/34.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/34.keymgr_sideload_protect.6034458
Short name	T750
Test name
Test status
Simulation time	29229551 ps
CPU time	1.5 seconds
Started	Feb 05 03:39:14 PM PST 24
Finished	Feb 05 03:39:21 PM PST 24
Peak memory	215720 kb
Host	smart-9fc646fd-0aaa-45d0-b4d8-be093d388da4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6034458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.6034458
Directory	/workspace/34.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/34.keymgr_smoke.2041124659
Short name	T831
Test name
Test status
Simulation time	125593386 ps
CPU time	3.64 seconds
Started	Feb 05 03:39:18 PM PST 24
Finished	Feb 05 03:39:29 PM PST 24
Peak memory	208512 kb
Host	smart-4b794b66-2196-4d11-afce-6cacec047806
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041124659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2041124659
Directory	/workspace/34.keymgr_smoke/latest

Test location	/workspace/coverage/default/34.keymgr_sw_invalid_input.1337406330
Short name	T324
Test name
Test status
Simulation time	75961150 ps
CPU time	3.13 seconds
Started	Feb 05 03:39:18 PM PST 24
Finished	Feb 05 03:39:28 PM PST 24
Peak memory	207440 kb
Host	smart-a1daba57-b525-4a61-9bba-e7cb7ee896df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1337406330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1337406330
Directory	/workspace/34.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/34.keymgr_sync_async_fault_cross.2815493934
Short name	T935
Test name
Test status
Simulation time	233214579 ps
CPU time	4.96 seconds
Started	Feb 05 03:39:17 PM PST 24
Finished	Feb 05 03:39:29 PM PST 24
Peak memory	210116 kb
Host	smart-6feb14ff-3b7c-4eb6-aaa4-d2b5d8d211e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815493934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2815493934
Directory	/workspace/34.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/35.keymgr_alert_test.2167147050
Short name	T788
Test name
Test status
Simulation time	69018341 ps
CPU time	0.81 seconds
Started	Feb 05 03:39:31 PM PST 24
Finished	Feb 05 03:39:35 PM PST 24
Peak memory	205872 kb
Host	smart-5dcc2b66-67bd-4921-a50d-fa02e1e9e8ca
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167147050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2167147050
Directory	/workspace/35.keymgr_alert_test/latest

Test location	/workspace/coverage/default/35.keymgr_custom_cm.3902823034
Short name	T66
Test name
Test status
Simulation time	219426297 ps
CPU time	4.5 seconds
Started	Feb 05 03:39:29 PM PST 24
Finished	Feb 05 03:39:36 PM PST 24
Peak memory	220700 kb
Host	smart-0cf7df17-d917-4ccd-b4a1-3ad3b9e17a60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3902823034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3902823034
Directory	/workspace/35.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/35.keymgr_hwsw_invalid_input.3815201932
Short name	T968
Test name
Test status
Simulation time	149401330 ps
CPU time	5.21 seconds
Started	Feb 05 03:39:27 PM PST 24
Finished	Feb 05 03:39:33 PM PST 24
Peak memory	214208 kb
Host	smart-462a4817-7ceb-4b4e-805a-e15bf4d4b006
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3815201932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3815201932
Directory	/workspace/35.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/35.keymgr_kmac_rsp_err.456098622
Short name	T265
Test name
Test status
Simulation time	5696119015 ps
CPU time	47.42 seconds
Started	Feb 05 03:39:34 PM PST 24
Finished	Feb 05 03:40:25 PM PST 24
Peak memory	220976 kb
Host	smart-202c5f53-443a-4faf-8d1b-6ece9e44daee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456098622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.456098622
Directory	/workspace/35.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/35.keymgr_lc_disable.2714289658
Short name	T865
Test name
Test status
Simulation time	101083137 ps
CPU time	3.72 seconds
Started	Feb 05 03:39:28 PM PST 24
Finished	Feb 05 03:39:34 PM PST 24
Peak memory	214172 kb
Host	smart-18363f81-cf14-43cd-8362-5d393536e475
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714289658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2714289658
Directory	/workspace/35.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/35.keymgr_random.1353470575
Short name	T990
Test name
Test status
Simulation time	152485043 ps
CPU time	6.75 seconds
Started	Feb 05 03:39:34 PM PST 24
Finished	Feb 05 03:39:45 PM PST 24
Peak memory	218188 kb
Host	smart-2c61d317-b92b-4bd0-9ce1-a754b793ea69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353470575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1353470575
Directory	/workspace/35.keymgr_random/latest

Test location	/workspace/coverage/default/35.keymgr_sideload.1971777974
Short name	T675
Test name
Test status
Simulation time	159503158 ps
CPU time	3.17 seconds
Started	Feb 05 03:39:18 PM PST 24
Finished	Feb 05 03:39:28 PM PST 24
Peak memory	208636 kb
Host	smart-36d02bdd-aa0d-4fb9-aabf-1b17ef894578
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1971777974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1971777974
Directory	/workspace/35.keymgr_sideload/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_aes.3527357571
Short name	T341
Test name
Test status
Simulation time	714754964 ps
CPU time	5.62 seconds
Started	Feb 05 03:39:19 PM PST 24
Finished	Feb 05 03:39:31 PM PST 24
Peak memory	208624 kb
Host	smart-3ec40066-c162-46dd-8fcd-691e68297ff4
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527357571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3527357571
Directory	/workspace/35.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_kmac.1608181530
Short name	T226
Test name
Test status
Simulation time	88346884 ps
CPU time	1.9 seconds
Started	Feb 05 03:39:21 PM PST 24
Finished	Feb 05 03:39:28 PM PST 24
Peak memory	206932 kb
Host	smart-42ee8296-4ec8-4853-ad1b-e933b67d58e4
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608181530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1608181530
Directory	/workspace/35.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_otbn.226629137
Short name	T601
Test name
Test status
Simulation time	76178748 ps
CPU time	3.29 seconds
Started	Feb 05 03:39:30 PM PST 24
Finished	Feb 05 03:39:37 PM PST 24
Peak memory	208012 kb
Host	smart-5b023ece-599f-4adc-87f7-c17d5418f868
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226629137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.226629137
Directory	/workspace/35.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_protect.409785824
Short name	T916
Test name
Test status
Simulation time	78322609 ps
CPU time	2.1 seconds
Started	Feb 05 03:39:31 PM PST 24
Finished	Feb 05 03:39:36 PM PST 24
Peak memory	207460 kb
Host	smart-b309f0cc-a020-4905-a5eb-15d056b8818d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409785824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.409785824
Directory	/workspace/35.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/35.keymgr_smoke.3970822145
Short name	T713
Test name
Test status
Simulation time	786362899 ps
CPU time	9.77 seconds
Started	Feb 05 03:39:20 PM PST 24
Finished	Feb 05 03:39:36 PM PST 24
Peak memory	208100 kb
Host	smart-6a062831-74a5-42b4-b510-f2cf03e5cb09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970822145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3970822145
Directory	/workspace/35.keymgr_smoke/latest

Test location	/workspace/coverage/default/35.keymgr_stress_all.1534166476
Short name	T868
Test name
Test status
Simulation time	2289619427 ps
CPU time	28.21 seconds
Started	Feb 05 03:39:28 PM PST 24
Finished	Feb 05 03:39:59 PM PST 24
Peak memory	222500 kb
Host	smart-5653b1df-b651-4545-8a99-f3d2408e42e7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534166476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1534166476
Directory	/workspace/35.keymgr_stress_all/latest

Test location	/workspace/coverage/default/35.keymgr_sw_invalid_input.2221778210
Short name	T884
Test name
Test status
Simulation time	380123161 ps
CPU time	5.29 seconds
Started	Feb 05 03:39:27 PM PST 24
Finished	Feb 05 03:39:34 PM PST 24
Peak memory	207812 kb
Host	smart-1c99f359-eefd-48cb-9644-a6269e84f44e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221778210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2221778210
Directory	/workspace/35.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/35.keymgr_sync_async_fault_cross.1472668130
Short name	T636
Test name
Test status
Simulation time	327230272 ps
CPU time	6.91 seconds
Started	Feb 05 03:39:29 PM PST 24
Finished	Feb 05 03:39:38 PM PST 24
Peak memory	210880 kb
Host	smart-b2b12a4a-0bd1-4eb8-bdc9-5b9fcf8042c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1472668130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1472668130
Directory	/workspace/35.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/36.keymgr_alert_test.1753967003
Short name	T1006
Test name
Test status
Simulation time	66081865 ps
CPU time	0.73 seconds
Started	Feb 05 03:39:32 PM PST 24
Finished	Feb 05 03:39:36 PM PST 24
Peak memory	205848 kb
Host	smart-42132455-dfe1-443c-945b-d734bde330a2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753967003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1753967003
Directory	/workspace/36.keymgr_alert_test/latest

Test location	/workspace/coverage/default/36.keymgr_cfg_regwen.766902924
Short name	T212
Test name
Test status
Simulation time	11637163146 ps
CPU time	155.04 seconds
Started	Feb 05 03:39:28 PM PST 24
Finished	Feb 05 03:42:05 PM PST 24
Peak memory	214460 kb
Host	smart-27fa7f7e-8abe-4e87-ab40-fa5acbc8f82d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=766902924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.766902924
Directory	/workspace/36.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/36.keymgr_direct_to_disabled.1877346872
Short name	T907
Test name
Test status
Simulation time	295580364 ps
CPU time	3.78 seconds
Started	Feb 05 03:39:27 PM PST 24
Finished	Feb 05 03:39:32 PM PST 24
Peak memory	209592 kb
Host	smart-569807b1-c481-4589-857c-6c58bc9a4768
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877346872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1877346872
Directory	/workspace/36.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/36.keymgr_lc_disable.2044476331
Short name	T893
Test name
Test status
Simulation time	1566325865 ps
CPU time	11.43 seconds
Started	Feb 05 03:39:31 PM PST 24
Finished	Feb 05 03:39:46 PM PST 24
Peak memory	214316 kb
Host	smart-031ad5ec-a830-4946-9c12-ec4be52ad541
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2044476331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2044476331
Directory	/workspace/36.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/36.keymgr_random.2374703340
Short name	T667
Test name
Test status
Simulation time	438647489 ps
CPU time	4.57 seconds
Started	Feb 05 03:39:30 PM PST 24
Finished	Feb 05 03:39:37 PM PST 24
Peak memory	214276 kb
Host	smart-9a30e103-2544-4913-8df8-27dc7df16361
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374703340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2374703340
Directory	/workspace/36.keymgr_random/latest

Test location	/workspace/coverage/default/36.keymgr_sideload.4003960646
Short name	T232
Test name
Test status
Simulation time	110878583 ps
CPU time	2.99 seconds
Started	Feb 05 03:39:27 PM PST 24
Finished	Feb 05 03:39:32 PM PST 24
Peak memory	208872 kb
Host	smart-d9a47c9b-f939-4451-a5db-25bb812d6a41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003960646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.4003960646
Directory	/workspace/36.keymgr_sideload/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_aes.1403793742
Short name	T825
Test name
Test status
Simulation time	161643384 ps
CPU time	3.96 seconds
Started	Feb 05 03:39:27 PM PST 24
Finished	Feb 05 03:39:33 PM PST 24
Peak memory	206888 kb
Host	smart-de1327ad-7de6-4e05-acd4-ae60771c2047
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403793742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1403793742
Directory	/workspace/36.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_kmac.2272261449
Short name	T570
Test name
Test status
Simulation time	934732673 ps
CPU time	9.87 seconds
Started	Feb 05 03:39:32 PM PST 24
Finished	Feb 05 03:39:46 PM PST 24
Peak memory	208096 kb
Host	smart-ec88cb2b-ac4d-40f7-8d03-1d64426e1038
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272261449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2272261449
Directory	/workspace/36.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_otbn.2480146241
Short name	T577
Test name
Test status
Simulation time	538617120 ps
CPU time	18.35 seconds
Started	Feb 05 03:39:34 PM PST 24
Finished	Feb 05 03:39:56 PM PST 24
Peak memory	209012 kb
Host	smart-bb7f16bb-2fe0-4825-a20d-c832226b4e60
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480146241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2480146241
Directory	/workspace/36.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_protect.3509517111
Short name	T338
Test name
Test status
Simulation time	294707782 ps
CPU time	3.82 seconds
Started	Feb 05 03:39:32 PM PST 24
Finished	Feb 05 03:39:39 PM PST 24
Peak memory	214248 kb
Host	smart-bcb4d1c2-8872-4c3a-9e8d-3b237e07ed97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509517111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3509517111
Directory	/workspace/36.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/36.keymgr_smoke.421750744
Short name	T564
Test name
Test status
Simulation time	83008992 ps
CPU time	2.42 seconds
Started	Feb 05 03:39:32 PM PST 24
Finished	Feb 05 03:39:38 PM PST 24
Peak memory	206716 kb
Host	smart-1bff148d-aa8d-4434-9774-54ab9e144511
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=421750744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.421750744
Directory	/workspace/36.keymgr_smoke/latest

Test location	/workspace/coverage/default/36.keymgr_stress_all.2173496432
Short name	T896
Test name
Test status
Simulation time	1335778656 ps
CPU time	32.28 seconds
Started	Feb 05 03:39:31 PM PST 24
Finished	Feb 05 03:40:07 PM PST 24
Peak memory	219640 kb
Host	smart-bd140a83-7b9c-4078-8145-27c8adbb04b2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173496432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2173496432
Directory	/workspace/36.keymgr_stress_all/latest

Test location	/workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3395010258
Short name	T199
Test name
Test status
Simulation time	154363940 ps
CPU time	2.82 seconds
Started	Feb 05 03:39:30 PM PST 24
Finished	Feb 05 03:39:36 PM PST 24
Peak memory	222648 kb
Host	smart-495faa72-b494-4868-88b7-6c5fe820a18e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395010258 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3395010258
Directory	/workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.keymgr_sw_invalid_input.1705704237
Short name	T298
Test name
Test status
Simulation time	400911696 ps
CPU time	4.9 seconds
Started	Feb 05 03:39:32 PM PST 24
Finished	Feb 05 03:39:41 PM PST 24
Peak memory	207624 kb
Host	smart-4c6c76ce-e3a6-42c2-8205-eeed81ab0956
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705704237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1705704237
Directory	/workspace/36.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/36.keymgr_sync_async_fault_cross.1721804144
Short name	T53
Test name
Test status
Simulation time	431267941 ps
CPU time	4.52 seconds
Started	Feb 05 03:39:28 PM PST 24
Finished	Feb 05 03:39:35 PM PST 24
Peak memory	219276 kb
Host	smart-ce6b1e0b-440d-4f2b-8c2a-e5cc703f1d9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1721804144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1721804144
Directory	/workspace/36.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/37.keymgr_alert_test.2949839851
Short name	T917
Test name
Test status
Simulation time	54817901 ps
CPU time	0.79 seconds
Started	Feb 05 03:39:30 PM PST 24
Finished	Feb 05 03:39:34 PM PST 24
Peak memory	205852 kb
Host	smart-655b49c4-6112-4ddb-8418-e45f41837622
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949839851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2949839851
Directory	/workspace/37.keymgr_alert_test/latest

Test location	/workspace/coverage/default/37.keymgr_cfg_regwen.3925921215
Short name	T221
Test name
Test status
Simulation time	218168929 ps
CPU time	4.02 seconds
Started	Feb 05 03:39:27 PM PST 24
Finished	Feb 05 03:39:33 PM PST 24
Peak memory	215276 kb
Host	smart-fa08d5af-9b76-4e87-be52-b9ce1be5ad13
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3925921215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3925921215
Directory	/workspace/37.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/37.keymgr_hwsw_invalid_input.2045780911
Short name	T290
Test name
Test status
Simulation time	67422396 ps
CPU time	3.08 seconds
Started	Feb 05 03:39:35 PM PST 24
Finished	Feb 05 03:39:41 PM PST 24
Peak memory	219088 kb
Host	smart-7dbbef4c-71c9-4d43-a625-208f642a10da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2045780911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2045780911
Directory	/workspace/37.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/37.keymgr_kmac_rsp_err.3910686482
Short name	T181
Test name
Test status
Simulation time	105584579 ps
CPU time	4.94 seconds
Started	Feb 05 03:39:30 PM PST 24
Finished	Feb 05 03:39:38 PM PST 24
Peak memory	222412 kb
Host	smart-dd2fade8-667c-4be8-bbde-71009242aaaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910686482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3910686482
Directory	/workspace/37.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/37.keymgr_lc_disable.1435365270
Short name	T54
Test name
Test status
Simulation time	68428932 ps
CPU time	3.49 seconds
Started	Feb 05 03:39:31 PM PST 24
Finished	Feb 05 03:39:38 PM PST 24
Peak memory	220092 kb
Host	smart-38fb4cb1-23ca-4410-8296-c1e33d0f4865
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435365270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1435365270
Directory	/workspace/37.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/37.keymgr_random.3904538820
Short name	T612
Test name
Test status
Simulation time	868328538 ps
CPU time	10.57 seconds
Started	Feb 05 03:39:31 PM PST 24
Finished	Feb 05 03:39:44 PM PST 24
Peak memory	214288 kb
Host	smart-486b21d0-52f0-4b9f-8882-95311e7787f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3904538820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3904538820
Directory	/workspace/37.keymgr_random/latest

Test location	/workspace/coverage/default/37.keymgr_sideload.2234644405
Short name	T347
Test name
Test status
Simulation time	103256729 ps
CPU time	3.66 seconds
Started	Feb 05 03:39:31 PM PST 24
Finished	Feb 05 03:39:38 PM PST 24
Peak memory	206592 kb
Host	smart-8eb1bb0f-db15-40e4-ace0-de8ecc890d6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2234644405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2234644405
Directory	/workspace/37.keymgr_sideload/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_aes.2250751128
Short name	T372
Test name
Test status
Simulation time	653269105 ps
CPU time	4.04 seconds
Started	Feb 05 03:39:30 PM PST 24
Finished	Feb 05 03:39:37 PM PST 24
Peak memory	206836 kb
Host	smart-fa5a7848-c883-4652-9026-506c855bb950
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250751128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2250751128
Directory	/workspace/37.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_kmac.733561206
Short name	T614
Test name
Test status
Simulation time	104018995 ps
CPU time	3.01 seconds
Started	Feb 05 03:39:27 PM PST 24
Finished	Feb 05 03:39:32 PM PST 24
Peak memory	208440 kb
Host	smart-6215ac8b-0951-4ae6-90e4-e2f6d64a6d9e
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733561206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.733561206
Directory	/workspace/37.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_otbn.2910657088
Short name	T816
Test name
Test status
Simulation time	1400744299 ps
CPU time	36.01 seconds
Started	Feb 05 03:39:32 PM PST 24
Finished	Feb 05 03:40:11 PM PST 24
Peak memory	207940 kb
Host	smart-41e20367-ea08-441b-81c3-cd6503c66740
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910657088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2910657088
Directory	/workspace/37.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_protect.3209800545
Short name	T810
Test name
Test status
Simulation time	97423503 ps
CPU time	4.1 seconds
Started	Feb 05 03:39:30 PM PST 24
Finished	Feb 05 03:39:38 PM PST 24
Peak memory	218596 kb
Host	smart-a1c09297-0afa-481e-9b83-056704e60667
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3209800545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3209800545
Directory	/workspace/37.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/37.keymgr_smoke.3949314178
Short name	T866
Test name
Test status
Simulation time	22391896 ps
CPU time	1.66 seconds
Started	Feb 05 03:39:32 PM PST 24
Finished	Feb 05 03:39:37 PM PST 24
Peak memory	206736 kb
Host	smart-f2e481e1-6e15-4235-8577-103d9ff5bfa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3949314178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3949314178
Directory	/workspace/37.keymgr_smoke/latest

Test location	/workspace/coverage/default/37.keymgr_stress_all.2339659828
Short name	T234
Test name
Test status
Simulation time	6449799920 ps
CPU time	81.95 seconds
Started	Feb 05 03:39:39 PM PST 24
Finished	Feb 05 03:41:02 PM PST 24
Peak memory	216952 kb
Host	smart-4f3c2c97-190c-465d-a261-fe3467d20b1b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339659828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2339659828
Directory	/workspace/37.keymgr_stress_all/latest

Test location	/workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1707598186
Short name	T915
Test name
Test status
Simulation time	53423373 ps
CPU time	3.46 seconds
Started	Feb 05 03:39:28 PM PST 24
Finished	Feb 05 03:39:34 PM PST 24
Peak memory	222268 kb
Host	smart-6a26407a-b136-491d-9c47-37605b8d6135
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707598186 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1707598186
Directory	/workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.keymgr_sync_async_fault_cross.117019482
Short name	T603
Test name
Test status
Simulation time	83310516 ps
CPU time	1.69 seconds
Started	Feb 05 03:39:30 PM PST 24
Finished	Feb 05 03:39:35 PM PST 24
Peak memory	209852 kb
Host	smart-185123b7-d5cb-4ad2-906b-69647176b806
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=117019482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.117019482
Directory	/workspace/37.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/38.keymgr_alert_test.2515163831
Short name	T98
Test name
Test status
Simulation time	33626436 ps
CPU time	0.77 seconds
Started	Feb 05 03:39:33 PM PST 24
Finished	Feb 05 03:39:38 PM PST 24
Peak memory	205844 kb
Host	smart-d6988398-22af-4aa4-9234-a703842a9f8a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515163831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2515163831
Directory	/workspace/38.keymgr_alert_test/latest

Test location	/workspace/coverage/default/38.keymgr_direct_to_disabled.3626823913
Short name	T808
Test name
Test status
Simulation time	535960186 ps
CPU time	7.14 seconds
Started	Feb 05 03:39:32 PM PST 24
Finished	Feb 05 03:39:43 PM PST 24
Peak memory	218384 kb
Host	smart-82797691-db63-4d6c-9d15-814f3ffb94ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626823913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3626823913
Directory	/workspace/38.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/38.keymgr_kmac_rsp_err.2958767997
Short name	T270
Test name
Test status
Simulation time	92598104 ps
CPU time	4.71 seconds
Started	Feb 05 03:39:36 PM PST 24
Finished	Feb 05 03:39:44 PM PST 24
Peak memory	210320 kb
Host	smart-b7d651b3-1d2b-46fb-a61f-13ce7e676596
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2958767997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2958767997
Directory	/workspace/38.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/38.keymgr_random.2516823164
Short name	T394
Test name
Test status
Simulation time	116818432 ps
CPU time	5.09 seconds
Started	Feb 05 03:39:40 PM PST 24
Finished	Feb 05 03:39:46 PM PST 24
Peak memory	208996 kb
Host	smart-357628b6-552e-4840-9447-483bf5573e9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516823164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2516823164
Directory	/workspace/38.keymgr_random/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_aes.3856163264
Short name	T889
Test name
Test status
Simulation time	39255710 ps
CPU time	2.8 seconds
Started	Feb 05 03:39:30 PM PST 24
Finished	Feb 05 03:39:36 PM PST 24
Peak memory	208456 kb
Host	smart-eed69019-3382-4215-9792-b0c83f903340
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856163264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3856163264
Directory	/workspace/38.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_kmac.2977099338
Short name	T824
Test name
Test status
Simulation time	389530427 ps
CPU time	12.87 seconds
Started	Feb 05 03:39:28 PM PST 24
Finished	Feb 05 03:39:43 PM PST 24
Peak memory	208792 kb
Host	smart-ca706da4-7861-4f78-b785-866670faca05
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977099338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2977099338
Directory	/workspace/38.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_otbn.192657920
Short name	T640
Test name
Test status
Simulation time	235541015 ps
CPU time	2.49 seconds
Started	Feb 05 03:39:31 PM PST 24
Finished	Feb 05 03:39:37 PM PST 24
Peak memory	206864 kb
Host	smart-eec4eb0a-dfbc-404c-9515-80f52e67f26c
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192657920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.192657920
Directory	/workspace/38.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_protect.4263061328
Short name	T76
Test name
Test status
Simulation time	217108214 ps
CPU time	3.6 seconds
Started	Feb 05 03:39:38 PM PST 24
Finished	Feb 05 03:39:44 PM PST 24
Peak memory	218540 kb
Host	smart-a56b34aa-17d3-4d89-a612-156af878aeea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263061328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4263061328
Directory	/workspace/38.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/38.keymgr_smoke.2640712961
Short name	T821
Test name
Test status
Simulation time	43971500 ps
CPU time	2.48 seconds
Started	Feb 05 03:39:28 PM PST 24
Finished	Feb 05 03:39:32 PM PST 24
Peak memory	206936 kb
Host	smart-d00e43ed-e23f-408a-bfc6-a0dcf8263b18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640712961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2640712961
Directory	/workspace/38.keymgr_smoke/latest

Test location	/workspace/coverage/default/38.keymgr_stress_all.3822536433
Short name	T340
Test name
Test status
Simulation time	17763066169 ps
CPU time	115.52 seconds
Started	Feb 05 03:39:31 PM PST 24
Finished	Feb 05 03:41:30 PM PST 24
Peak memory	216432 kb
Host	smart-f2974c93-3cad-4938-a983-32fbc019c12d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822536433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3822536433
Directory	/workspace/38.keymgr_stress_all/latest

Test location	/workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.4032512858
Short name	T888
Test name
Test status
Simulation time	91196247 ps
CPU time	4.05 seconds
Started	Feb 05 03:39:32 PM PST 24
Finished	Feb 05 03:39:40 PM PST 24
Peak memory	219532 kb
Host	smart-2be2d44e-cf87-4877-b9f1-480dcdbeb8ac
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032512858 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.4032512858
Directory	/workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.keymgr_sw_invalid_input.2508748419
Short name	T840
Test name
Test status
Simulation time	67482853 ps
CPU time	4.45 seconds
Started	Feb 05 03:39:29 PM PST 24
Finished	Feb 05 03:39:36 PM PST 24
Peak memory	210284 kb
Host	smart-982fee01-3b11-4334-be95-0940dfb8cd8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2508748419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2508748419
Directory	/workspace/38.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/38.keymgr_sync_async_fault_cross.393378745
Short name	T618
Test name
Test status
Simulation time	143388489 ps
CPU time	2.51 seconds
Started	Feb 05 03:39:36 PM PST 24
Finished	Feb 05 03:39:41 PM PST 24
Peak memory	210200 kb
Host	smart-8fee1ef5-9267-4872-a7d8-4d49fdcfb58f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393378745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.393378745
Directory	/workspace/38.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/39.keymgr_alert_test.1974487269
Short name	T875
Test name
Test status
Simulation time	43786477 ps
CPU time	0.86 seconds
Started	Feb 05 03:39:36 PM PST 24
Finished	Feb 05 03:39:40 PM PST 24
Peak memory	205860 kb
Host	smart-0b5d7f1d-be41-4728-8762-755b5d631c30
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974487269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1974487269
Directory	/workspace/39.keymgr_alert_test/latest

Test location	/workspace/coverage/default/39.keymgr_custom_cm.1892804812
Short name	T770
Test name
Test status
Simulation time	511324671 ps
CPU time	11.02 seconds
Started	Feb 05 03:39:46 PM PST 24
Finished	Feb 05 03:39:59 PM PST 24
Peak memory	214224 kb
Host	smart-56e11d87-180d-4b62-b03d-cc58aeb1194c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1892804812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1892804812
Directory	/workspace/39.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/39.keymgr_direct_to_disabled.3929436025
Short name	T881
Test name
Test status
Simulation time	255904170 ps
CPU time	2.94 seconds
Started	Feb 05 03:39:46 PM PST 24
Finished	Feb 05 03:39:51 PM PST 24
Peak memory	209088 kb
Host	smart-1b36e459-7595-41b0-a86f-1db8380039b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929436025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3929436025
Directory	/workspace/39.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/39.keymgr_kmac_rsp_err.4130429756
Short name	T308
Test name
Test status
Simulation time	3101267676 ps
CPU time	9.38 seconds
Started	Feb 05 03:39:40 PM PST 24
Finished	Feb 05 03:39:51 PM PST 24
Peak memory	222480 kb
Host	smart-08ea9cf4-76b8-4ee3-a399-1cc2ea782559
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130429756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4130429756
Directory	/workspace/39.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/39.keymgr_random.2549348158
Short name	T243
Test name
Test status
Simulation time	580181071 ps
CPU time	8.47 seconds
Started	Feb 05 03:39:34 PM PST 24
Finished	Feb 05 03:39:46 PM PST 24
Peak memory	207664 kb
Host	smart-b5335179-583f-48a2-828d-f2ac27477ec8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2549348158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2549348158
Directory	/workspace/39.keymgr_random/latest

Test location	/workspace/coverage/default/39.keymgr_sideload.1092211708
Short name	T604
Test name
Test status
Simulation time	78544100 ps
CPU time	3.79 seconds
Started	Feb 05 03:39:37 PM PST 24
Finished	Feb 05 03:39:43 PM PST 24
Peak memory	208812 kb
Host	smart-3713409c-395a-4f7e-b362-ec22a6a7f956
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092211708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1092211708
Directory	/workspace/39.keymgr_sideload/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_aes.426566710
Short name	T584
Test name
Test status
Simulation time	204025567 ps
CPU time	4.49 seconds
Started	Feb 05 03:39:34 PM PST 24
Finished	Feb 05 03:39:42 PM PST 24
Peak memory	208984 kb
Host	smart-feb4ebb3-37b4-488f-b546-b51817175e05
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426566710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.426566710
Directory	/workspace/39.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_kmac.2677093366
Short name	T988
Test name
Test status
Simulation time	20736655 ps
CPU time	1.84 seconds
Started	Feb 05 03:39:33 PM PST 24
Finished	Feb 05 03:39:38 PM PST 24
Peak memory	206720 kb
Host	smart-2e3a964d-cc00-4e5b-910a-e2eeefc6bfad
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677093366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2677093366
Directory	/workspace/39.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_otbn.1189850907
Short name	T862
Test name
Test status
Simulation time	229015829 ps
CPU time	3.27 seconds
Started	Feb 05 03:39:34 PM PST 24
Finished	Feb 05 03:39:41 PM PST 24
Peak memory	208620 kb
Host	smart-71947972-da2d-4002-8fa2-91101cb454de
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189850907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1189850907
Directory	/workspace/39.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_protect.2157253973
Short name	T309
Test name
Test status
Simulation time	109221126 ps
CPU time	2.17 seconds
Started	Feb 05 03:39:39 PM PST 24
Finished	Feb 05 03:39:42 PM PST 24
Peak memory	214412 kb
Host	smart-e599c2b9-42c8-47b1-b63b-bcbbd42f20ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157253973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2157253973
Directory	/workspace/39.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/39.keymgr_smoke.3930187970
Short name	T794
Test name
Test status
Simulation time	49146818 ps
CPU time	2.7 seconds
Started	Feb 05 03:39:32 PM PST 24
Finished	Feb 05 03:39:39 PM PST 24
Peak memory	208368 kb
Host	smart-65ef805d-5db1-4f64-9bf6-40c3fad0bdff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3930187970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3930187970
Directory	/workspace/39.keymgr_smoke/latest

Test location	/workspace/coverage/default/39.keymgr_stress_all.4072697930
Short name	T49
Test name
Test status
Simulation time	3742984917 ps
CPU time	24.02 seconds
Started	Feb 05 03:39:37 PM PST 24
Finished	Feb 05 03:40:04 PM PST 24
Peak memory	222496 kb
Host	smart-22a66e38-516c-4732-8b08-059db7b94ad9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072697930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4072697930
Directory	/workspace/39.keymgr_stress_all/latest

Test location	/workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2934511043
Short name	T761
Test name
Test status
Simulation time	225045541 ps
CPU time	6.55 seconds
Started	Feb 05 03:39:33 PM PST 24
Finished	Feb 05 03:39:43 PM PST 24
Peak memory	222604 kb
Host	smart-003df799-d63e-4722-ae3f-995b5ad31221
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934511043 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2934511043
Directory	/workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.keymgr_sw_invalid_input.1838541695
Short name	T688
Test name
Test status
Simulation time	132067030 ps
CPU time	3.42 seconds
Started	Feb 05 03:39:37 PM PST 24
Finished	Feb 05 03:39:43 PM PST 24
Peak memory	209624 kb
Host	smart-43414511-9552-4e43-9c55-26b95978c205
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1838541695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1838541695
Directory	/workspace/39.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/39.keymgr_sync_async_fault_cross.1385774797
Short name	T782
Test name
Test status
Simulation time	113907075 ps
CPU time	1.87 seconds
Started	Feb 05 03:39:34 PM PST 24
Finished	Feb 05 03:39:40 PM PST 24
Peak memory	209804 kb
Host	smart-0789ec2c-b8c2-4dc5-90bd-8305c9f581a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385774797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1385774797
Directory	/workspace/39.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/4.keymgr_alert_test.1895199545
Short name	T777
Test name
Test status
Simulation time	24336486 ps
CPU time	0.77 seconds
Started	Feb 05 03:36:44 PM PST 24
Finished	Feb 05 03:36:52 PM PST 24
Peak memory	205820 kb
Host	smart-90b0c430-0f3a-4eb5-aa2f-cacbd4cb15d8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895199545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1895199545
Directory	/workspace/4.keymgr_alert_test/latest

Test location	/workspace/coverage/default/4.keymgr_cfg_regwen.873706573
Short name	T404
Test name
Test status
Simulation time	351921523 ps
CPU time	5.33 seconds
Started	Feb 05 03:36:35 PM PST 24
Finished	Feb 05 03:36:54 PM PST 24
Peak memory	214176 kb
Host	smart-d0b70643-6e5b-4cd5-a1dc-69d64a889afb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=873706573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.873706573
Directory	/workspace/4.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/4.keymgr_custom_cm.3740445902
Short name	T31
Test name
Test status
Simulation time	6365609794 ps
CPU time	54 seconds
Started	Feb 05 03:36:50 PM PST 24
Finished	Feb 05 03:37:49 PM PST 24
Peak memory	224172 kb
Host	smart-4794d2b3-6af6-443d-a9cd-a88cb7dc05b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3740445902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3740445902
Directory	/workspace/4.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/4.keymgr_direct_to_disabled.1704830277
Short name	T5
Test name
Test status
Simulation time	23713831 ps
CPU time	1.53 seconds
Started	Feb 05 03:36:42 PM PST 24
Finished	Feb 05 03:36:52 PM PST 24
Peak memory	206952 kb
Host	smart-36fad681-38e9-4f1b-b3de-64771f832a93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704830277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1704830277
Directory	/workspace/4.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/4.keymgr_hwsw_invalid_input.3607139687
Short name	T88
Test name
Test status
Simulation time	459250888 ps
CPU time	11.52 seconds
Started	Feb 05 03:36:44 PM PST 24
Finished	Feb 05 03:37:02 PM PST 24
Peak memory	220336 kb
Host	smart-e450845b-23f9-489a-8d14-16d314d47af2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607139687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3607139687
Directory	/workspace/4.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/4.keymgr_lc_disable.3207218295
Short name	T378
Test name
Test status
Simulation time	83755698 ps
CPU time	1.83 seconds
Started	Feb 05 03:36:36 PM PST 24
Finished	Feb 05 03:36:51 PM PST 24
Peak memory	218852 kb
Host	smart-1118e63a-07d4-48e4-819e-8dee5daa279f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207218295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3207218295
Directory	/workspace/4.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/4.keymgr_random.2926160027
Short name	T1002
Test name
Test status
Simulation time	1334924864 ps
CPU time	4.28 seconds
Started	Feb 05 03:36:38 PM PST 24
Finished	Feb 05 03:36:53 PM PST 24
Peak memory	208228 kb
Host	smart-7c942a36-1740-46a2-84eb-96887fb737ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926160027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2926160027
Directory	/workspace/4.keymgr_random/latest

Test location	/workspace/coverage/default/4.keymgr_sec_cm.2197574450
Short name	T101
Test name
Test status
Simulation time	2940720577 ps
CPU time	23.28 seconds
Started	Feb 05 03:36:44 PM PST 24
Finished	Feb 05 03:37:14 PM PST 24
Peak memory	239932 kb
Host	smart-7b37aea8-e253-4b9c-849d-7be4eb907d16
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197574450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2197574450
Directory	/workspace/4.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/4.keymgr_sideload.4167024327
Short name	T806
Test name
Test status
Simulation time	125191511 ps
CPU time	2.41 seconds
Started	Feb 05 03:36:34 PM PST 24
Finished	Feb 05 03:36:51 PM PST 24
Peak memory	206668 kb
Host	smart-e11d803d-7db3-41d6-ba38-fc6aca579915
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4167024327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.4167024327
Directory	/workspace/4.keymgr_sideload/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_aes.1953372594
Short name	T75
Test name
Test status
Simulation time	3681116150 ps
CPU time	8.86 seconds
Started	Feb 05 03:36:34 PM PST 24
Finished	Feb 05 03:36:58 PM PST 24
Peak memory	207892 kb
Host	smart-b6207b3a-503e-45b2-995d-5ed6ca56f40c
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953372594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1953372594
Directory	/workspace/4.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_kmac.1812078802
Short name	T781
Test name
Test status
Simulation time	1439428469 ps
CPU time	32.1 seconds
Started	Feb 05 03:36:35 PM PST 24
Finished	Feb 05 03:37:21 PM PST 24
Peak memory	208308 kb
Host	smart-93894c2d-bfcc-44ba-98eb-08b5adf7b504
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812078802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1812078802
Directory	/workspace/4.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_otbn.1740445455
Short name	T710
Test name
Test status
Simulation time	204740189 ps
CPU time	7.43 seconds
Started	Feb 05 03:36:36 PM PST 24
Finished	Feb 05 03:36:56 PM PST 24
Peak memory	208544 kb
Host	smart-520336bf-03e2-4dc0-8481-9e8da460e1c5
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740445455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1740445455
Directory	/workspace/4.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_protect.2120196581
Short name	T354
Test name
Test status
Simulation time	412270279 ps
CPU time	4.51 seconds
Started	Feb 05 03:36:48 PM PST 24
Finished	Feb 05 03:36:58 PM PST 24
Peak memory	209720 kb
Host	smart-abf152e8-1b12-47ca-afdf-be3e21edc481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120196581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2120196581
Directory	/workspace/4.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/4.keymgr_smoke.3748639942
Short name	T685
Test name
Test status
Simulation time	21395947 ps
CPU time	1.7 seconds
Started	Feb 05 03:36:34 PM PST 24
Finished	Feb 05 03:36:51 PM PST 24
Peak memory	206588 kb
Host	smart-c8d08b78-97c9-4021-b97c-57733e530f9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748639942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3748639942
Directory	/workspace/4.keymgr_smoke/latest

Test location	/workspace/coverage/default/4.keymgr_sw_invalid_input.1645312343
Short name	T717
Test name
Test status
Simulation time	260156553 ps
CPU time	7.74 seconds
Started	Feb 05 03:36:49 PM PST 24
Finished	Feb 05 03:37:02 PM PST 24
Peak memory	207288 kb
Host	smart-8825e46d-3319-488c-9958-4a872ad9da6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645312343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1645312343
Directory	/workspace/4.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/4.keymgr_sync_async_fault_cross.261018465
Short name	T575
Test name
Test status
Simulation time	377196940 ps
CPU time	2.84 seconds
Started	Feb 05 03:36:43 PM PST 24
Finished	Feb 05 03:36:53 PM PST 24
Peak memory	210796 kb
Host	smart-0d115633-33fb-47e1-aa98-a321e4ec6ce9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=261018465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.261018465
Directory	/workspace/4.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/40.keymgr_alert_test.2536356570
Short name	T605
Test name
Test status
Simulation time	58571816 ps
CPU time	0.78 seconds
Started	Feb 05 03:39:46 PM PST 24
Finished	Feb 05 03:39:48 PM PST 24
Peak memory	205864 kb
Host	smart-18a73824-ee36-4b7b-b4dd-dafccf7b42e9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536356570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2536356570
Directory	/workspace/40.keymgr_alert_test/latest

Test location	/workspace/coverage/default/40.keymgr_direct_to_disabled.3289106424
Short name	T833
Test name
Test status
Simulation time	237951448 ps
CPU time	2.65 seconds
Started	Feb 05 03:39:45 PM PST 24
Finished	Feb 05 03:39:49 PM PST 24
Peak memory	209808 kb
Host	smart-ca823e32-8a2b-4284-aa35-76d78ce58de7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3289106424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3289106424
Directory	/workspace/40.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/40.keymgr_hwsw_invalid_input.2733563079
Short name	T623
Test name
Test status
Simulation time	122772011 ps
CPU time	4.5 seconds
Started	Feb 05 03:39:44 PM PST 24
Finished	Feb 05 03:39:50 PM PST 24
Peak memory	221816 kb
Host	smart-6f019307-aedd-4e68-b789-ad66b38e895d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2733563079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2733563079
Directory	/workspace/40.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/40.keymgr_lc_disable.2386822271
Short name	T682
Test name
Test status
Simulation time	1139038033 ps
CPU time	3.55 seconds
Started	Feb 05 03:39:46 PM PST 24
Finished	Feb 05 03:39:51 PM PST 24
Peak memory	214284 kb
Host	smart-b78fb474-ed23-4e99-99e2-301dc3e8b023
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386822271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2386822271
Directory	/workspace/40.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/40.keymgr_sideload.28630142
Short name	T337
Test name
Test status
Simulation time	3731073150 ps
CPU time	11.12 seconds
Started	Feb 05 03:39:50 PM PST 24
Finished	Feb 05 03:40:03 PM PST 24
Peak memory	208516 kb
Host	smart-86de915a-0f62-4909-b6b3-c3654e88ed80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28630142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.28630142
Directory	/workspace/40.keymgr_sideload/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_aes.2484168291
Short name	T962
Test name
Test status
Simulation time	543514624 ps
CPU time	6.69 seconds
Started	Feb 05 03:39:45 PM PST 24
Finished	Feb 05 03:39:53 PM PST 24
Peak memory	208540 kb
Host	smart-2df4caa8-e0af-4572-aa53-ad3ce4535136
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484168291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2484168291
Directory	/workspace/40.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_kmac.2820914792
Short name	T842
Test name
Test status
Simulation time	101544519 ps
CPU time	3.77 seconds
Started	Feb 05 03:39:42 PM PST 24
Finished	Feb 05 03:39:47 PM PST 24
Peak memory	208652 kb
Host	smart-f6911307-f71a-46b1-8213-00e6bf989346
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820914792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2820914792
Directory	/workspace/40.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_otbn.1610130189
Short name	T903
Test name
Test status
Simulation time	146974560 ps
CPU time	3.62 seconds
Started	Feb 05 03:39:45 PM PST 24
Finished	Feb 05 03:39:50 PM PST 24
Peak memory	208432 kb
Host	smart-f729d40c-e053-4f35-a8fb-2f55308767b2
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610130189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1610130189
Directory	/workspace/40.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_protect.1698369769
Short name	T583
Test name
Test status
Simulation time	24022600 ps
CPU time	1.71 seconds
Started	Feb 05 03:39:47 PM PST 24
Finished	Feb 05 03:39:50 PM PST 24
Peak memory	209304 kb
Host	smart-733f247b-cfd1-498d-b831-4f8b889b3e8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1698369769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1698369769
Directory	/workspace/40.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/40.keymgr_stress_all.93777721
Short name	T589
Test name
Test status
Simulation time	333979561 ps
CPU time	4.5 seconds
Started	Feb 05 03:39:46 PM PST 24
Finished	Feb 05 03:39:52 PM PST 24
Peak memory	220204 kb
Host	smart-d5a02a3f-f983-4ac4-858d-7cbbce93d450
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93777721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.93777721
Directory	/workspace/40.keymgr_stress_all/latest

Test location	/workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.896440038
Short name	T611
Test name
Test status
Simulation time	335381314 ps
CPU time	2.35 seconds
Started	Feb 05 03:39:41 PM PST 24
Finished	Feb 05 03:39:45 PM PST 24
Peak memory	220764 kb
Host	smart-31e6d467-9598-4997-beae-8f9aba3e90e5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896440038 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.896440038
Directory	/workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.keymgr_sw_invalid_input.366600314
Short name	T908
Test name
Test status
Simulation time	439549236 ps
CPU time	5.14 seconds
Started	Feb 05 03:39:42 PM PST 24
Finished	Feb 05 03:39:49 PM PST 24
Peak memory	209676 kb
Host	smart-f42ac68d-9660-4d5f-989a-e2d77a362be2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366600314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.366600314
Directory	/workspace/40.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/40.keymgr_sync_async_fault_cross.2323808470
Short name	T154
Test name
Test status
Simulation time	30525890 ps
CPU time	2.05 seconds
Started	Feb 05 03:39:43 PM PST 24
Finished	Feb 05 03:39:47 PM PST 24
Peak memory	210128 kb
Host	smart-6727e344-cc4e-4b1b-a85b-2c177591b7be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323808470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2323808470
Directory	/workspace/40.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/41.keymgr_alert_test.1211666797
Short name	T722
Test name
Test status
Simulation time	55830448 ps
CPU time	0.85 seconds
Started	Feb 05 03:39:46 PM PST 24
Finished	Feb 05 03:39:48 PM PST 24
Peak memory	205892 kb
Host	smart-13000286-acc4-4f38-b867-ad3791f32934
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211666797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1211666797
Directory	/workspace/41.keymgr_alert_test/latest

Test location	/workspace/coverage/default/41.keymgr_custom_cm.2563368133
Short name	T1007
Test name
Test status
Simulation time	588167678 ps
CPU time	2.21 seconds
Started	Feb 05 03:40:01 PM PST 24
Finished	Feb 05 03:40:06 PM PST 24
Peak memory	210164 kb
Host	smart-880b2b66-59b8-4e28-92fb-2c810e9b4ec1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2563368133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2563368133
Directory	/workspace/41.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/41.keymgr_hwsw_invalid_input.508395283
Short name	T20
Test name
Test status
Simulation time	508943237 ps
CPU time	8.25 seconds
Started	Feb 05 03:39:51 PM PST 24
Finished	Feb 05 03:40:00 PM PST 24
Peak memory	209356 kb
Host	smart-e3c0b241-d8e4-4f7c-8acf-60002fa3a2d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508395283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.508395283
Directory	/workspace/41.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/41.keymgr_kmac_rsp_err.258293721
Short name	T48
Test name
Test status
Simulation time	1042788071 ps
CPU time	12.73 seconds
Started	Feb 05 03:39:48 PM PST 24
Finished	Feb 05 03:40:03 PM PST 24
Peak memory	210244 kb
Host	smart-be4c777f-7d17-41b4-9771-8cfb7f5e6131
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258293721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.258293721
Directory	/workspace/41.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/41.keymgr_lc_disable.1636016719
Short name	T580
Test name
Test status
Simulation time	273942964 ps
CPU time	3.54 seconds
Started	Feb 05 03:39:45 PM PST 24
Finished	Feb 05 03:39:50 PM PST 24
Peak memory	222480 kb
Host	smart-1bd750e3-5e05-44ed-8fd6-8e0b6bce51ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636016719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1636016719
Directory	/workspace/41.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/41.keymgr_random.4220085664
Short name	T670
Test name
Test status
Simulation time	228355342 ps
CPU time	3.85 seconds
Started	Feb 05 03:40:01 PM PST 24
Finished	Feb 05 03:40:07 PM PST 24
Peak memory	213920 kb
Host	smart-b646044d-d68e-4765-b49c-a567d3f6b15e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220085664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.4220085664
Directory	/workspace/41.keymgr_random/latest

Test location	/workspace/coverage/default/41.keymgr_sideload.2320290025
Short name	T188
Test name
Test status
Simulation time	60685972 ps
CPU time	3.07 seconds
Started	Feb 05 03:39:47 PM PST 24
Finished	Feb 05 03:39:52 PM PST 24
Peak memory	208016 kb
Host	smart-1e95c9e6-046d-425c-9929-ac486d9bcc07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320290025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2320290025
Directory	/workspace/41.keymgr_sideload/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_aes.1561154604
Short name	T972
Test name
Test status
Simulation time	5230395337 ps
CPU time	54.29 seconds
Started	Feb 05 03:39:47 PM PST 24
Finished	Feb 05 03:40:43 PM PST 24
Peak memory	209320 kb
Host	smart-ee0d6710-8cbd-4f83-ab54-c5feb634c0ad
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561154604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1561154604
Directory	/workspace/41.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_kmac.4208438540
Short name	T647
Test name
Test status
Simulation time	969778300 ps
CPU time	10.51 seconds
Started	Feb 05 03:39:50 PM PST 24
Finished	Feb 05 03:40:01 PM PST 24
Peak memory	208668 kb
Host	smart-61d2cf0c-4e89-43da-bf91-70d318e547b8
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208438540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.4208438540
Directory	/workspace/41.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_otbn.2521998464
Short name	T947
Test name
Test status
Simulation time	353171878 ps
CPU time	8.74 seconds
Started	Feb 05 03:39:49 PM PST 24
Finished	Feb 05 03:39:59 PM PST 24
Peak memory	207808 kb
Host	smart-036c8cbe-26be-4597-b9e7-9ae9a823889c
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521998464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2521998464
Directory	/workspace/41.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_protect.1912032419
Short name	T177
Test name
Test status
Simulation time	153672364 ps
CPU time	2.31 seconds
Started	Feb 05 03:39:47 PM PST 24
Finished	Feb 05 03:39:52 PM PST 24
Peak memory	215664 kb
Host	smart-ff5988c4-a2aa-474d-a8fd-6ef88eae8c06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1912032419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1912032419
Directory	/workspace/41.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/41.keymgr_smoke.1702071628
Short name	T712
Test name
Test status
Simulation time	155529959 ps
CPU time	3.59 seconds
Started	Feb 05 03:39:44 PM PST 24
Finished	Feb 05 03:39:48 PM PST 24
Peak memory	207936 kb
Host	smart-e10e5a46-87bb-4fab-a27c-568a662b7152
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1702071628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1702071628
Directory	/workspace/41.keymgr_smoke/latest

Test location	/workspace/coverage/default/41.keymgr_stress_all.1838684097
Short name	T63
Test name
Test status
Simulation time	322414710 ps
CPU time	15.47 seconds
Started	Feb 05 03:40:01 PM PST 24
Finished	Feb 05 03:40:19 PM PST 24
Peak memory	220020 kb
Host	smart-abd9fd68-428e-411f-a1ba-3434292eb86f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838684097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1838684097
Directory	/workspace/41.keymgr_stress_all/latest

Test location	/workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3868161101
Short name	T556
Test name
Test status
Simulation time	97231677 ps
CPU time	2.91 seconds
Started	Feb 05 03:40:01 PM PST 24
Finished	Feb 05 03:40:06 PM PST 24
Peak memory	222504 kb
Host	smart-cb4c08c2-2afc-44bf-8ca3-256b573f65b9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868161101 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3868161101
Directory	/workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.keymgr_sw_invalid_input.1125200925
Short name	T619
Test name
Test status
Simulation time	92990558 ps
CPU time	4.32 seconds
Started	Feb 05 03:39:46 PM PST 24
Finished	Feb 05 03:39:51 PM PST 24
Peak memory	209220 kb
Host	smart-bd5eb63e-a041-4acf-9bb8-a4d327cc47dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125200925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1125200925
Directory	/workspace/41.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/41.keymgr_sync_async_fault_cross.915364827
Short name	T18
Test name
Test status
Simulation time	578454247 ps
CPU time	2.12 seconds
Started	Feb 05 03:39:47 PM PST 24
Finished	Feb 05 03:39:52 PM PST 24
Peak memory	210176 kb
Host	smart-420d8328-08cc-4c47-b12a-92d6b6f2a7e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915364827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.915364827
Directory	/workspace/41.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/42.keymgr_alert_test.463095472
Short name	T818
Test name
Test status
Simulation time	30665896 ps
CPU time	0.91 seconds
Started	Feb 05 03:39:53 PM PST 24
Finished	Feb 05 03:39:55 PM PST 24
Peak memory	205872 kb
Host	smart-3e97c896-0bf7-458d-9daa-82c4930f965e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463095472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.463095472
Directory	/workspace/42.keymgr_alert_test/latest

Test location	/workspace/coverage/default/42.keymgr_cfg_regwen.1880175573
Short name	T259
Test name
Test status
Simulation time	59390817 ps
CPU time	3.48 seconds
Started	Feb 05 03:40:01 PM PST 24
Finished	Feb 05 03:40:07 PM PST 24
Peak memory	214892 kb
Host	smart-e1618035-b8bf-436e-a541-02754e057e33
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1880175573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1880175573
Directory	/workspace/42.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/42.keymgr_custom_cm.802709801
Short name	T37
Test name
Test status
Simulation time	125954675 ps
CPU time	3.34 seconds
Started	Feb 05 03:39:52 PM PST 24
Finished	Feb 05 03:39:57 PM PST 24
Peak memory	221084 kb
Host	smart-3433bfbd-cd73-436e-b40a-431897a099d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802709801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.802709801
Directory	/workspace/42.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/42.keymgr_direct_to_disabled.2295133769
Short name	T70
Test name
Test status
Simulation time	78754902 ps
CPU time	2.24 seconds
Started	Feb 05 03:39:46 PM PST 24
Finished	Feb 05 03:39:51 PM PST 24
Peak memory	209120 kb
Host	smart-ecddd45a-48e2-4505-aaaf-c54d56993153
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295133769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2295133769
Directory	/workspace/42.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/42.keymgr_hwsw_invalid_input.4184731937
Short name	T86
Test name
Test status
Simulation time	174002703 ps
CPU time	3.6 seconds
Started	Feb 05 03:39:52 PM PST 24
Finished	Feb 05 03:39:57 PM PST 24
Peak memory	209860 kb
Host	smart-d1c70bc3-cce7-4ee3-bf52-cd0e849109b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184731937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4184731937
Directory	/workspace/42.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/42.keymgr_lc_disable.358289929
Short name	T203
Test name
Test status
Simulation time	133438631 ps
CPU time	5.7 seconds
Started	Feb 05 03:40:01 PM PST 24
Finished	Feb 05 03:40:10 PM PST 24
Peak memory	210020 kb
Host	smart-f6f13401-e329-45a7-ab38-70361fc654cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=358289929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.358289929
Directory	/workspace/42.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/42.keymgr_random.2918883488
Short name	T368
Test name
Test status
Simulation time	5260954295 ps
CPU time	66.55 seconds
Started	Feb 05 03:39:47 PM PST 24
Finished	Feb 05 03:40:56 PM PST 24
Peak memory	208736 kb
Host	smart-a1531bf5-b018-40b6-b829-95c0fd80870d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918883488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2918883488
Directory	/workspace/42.keymgr_random/latest

Test location	/workspace/coverage/default/42.keymgr_sideload.2831430563
Short name	T242
Test name
Test status
Simulation time	82820804 ps
CPU time	2.79 seconds
Started	Feb 05 03:39:44 PM PST 24
Finished	Feb 05 03:39:48 PM PST 24
Peak memory	208672 kb
Host	smart-0d69f6e1-a923-4dd0-a95b-6b31fe022527
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831430563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2831430563
Directory	/workspace/42.keymgr_sideload/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_aes.958030982
Short name	T844
Test name
Test status
Simulation time	729131924 ps
CPU time	8.8 seconds
Started	Feb 05 03:39:47 PM PST 24
Finished	Feb 05 03:39:57 PM PST 24
Peak memory	208748 kb
Host	smart-76133b17-ea72-4e9a-932c-cf82f0167c82
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958030982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.958030982
Directory	/workspace/42.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_kmac.1051311421
Short name	T764
Test name
Test status
Simulation time	393675388 ps
CPU time	3.32 seconds
Started	Feb 05 03:40:01 PM PST 24
Finished	Feb 05 03:40:08 PM PST 24
Peak memory	206904 kb
Host	smart-325b8e10-d321-4c0d-8dbe-36f56f0edfbf
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051311421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1051311421
Directory	/workspace/42.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_otbn.3722196369
Short name	T217
Test name
Test status
Simulation time	279606895 ps
CPU time	1.83 seconds
Started	Feb 05 03:39:44 PM PST 24
Finished	Feb 05 03:39:47 PM PST 24
Peak memory	206968 kb
Host	smart-1fd163e5-503c-446d-961a-f378855e7727
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722196369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3722196369
Directory	/workspace/42.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_protect.2045987102
Short name	T613
Test name
Test status
Simulation time	93774372 ps
CPU time	2.43 seconds
Started	Feb 05 03:39:54 PM PST 24
Finished	Feb 05 03:39:59 PM PST 24
Peak memory	209196 kb
Host	smart-a7c65c5c-9c80-4bec-afd5-e56f97f58031
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2045987102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2045987102
Directory	/workspace/42.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/42.keymgr_smoke.1959782381
Short name	T870
Test name
Test status
Simulation time	76305422 ps
CPU time	2.67 seconds
Started	Feb 05 03:39:48 PM PST 24
Finished	Feb 05 03:39:52 PM PST 24
Peak memory	208324 kb
Host	smart-826d5c8a-2570-490c-b4b6-14ab214810e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1959782381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1959782381
Directory	/workspace/42.keymgr_smoke/latest

Test location	/workspace/coverage/default/42.keymgr_sw_invalid_input.376854224
Short name	T981
Test name
Test status
Simulation time	76126027 ps
CPU time	4.23 seconds
Started	Feb 05 03:40:01 PM PST 24
Finished	Feb 05 03:40:07 PM PST 24
Peak memory	214348 kb
Host	smart-1336c605-3d74-4c94-ac23-6160565a9038
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376854224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.376854224
Directory	/workspace/42.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/43.keymgr_alert_test.2604336140
Short name	T759
Test name
Test status
Simulation time	20259363 ps
CPU time	0.75 seconds
Started	Feb 05 03:39:56 PM PST 24
Finished	Feb 05 03:40:01 PM PST 24
Peak memory	205848 kb
Host	smart-5d12c180-faa5-4334-8d2d-ae2e2300662c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604336140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2604336140
Directory	/workspace/43.keymgr_alert_test/latest

Test location	/workspace/coverage/default/43.keymgr_cfg_regwen.751914877
Short name	T386
Test name
Test status
Simulation time	191174856 ps
CPU time	3.66 seconds
Started	Feb 05 03:39:52 PM PST 24
Finished	Feb 05 03:39:57 PM PST 24
Peak memory	214232 kb
Host	smart-99125fbc-8b66-4cb3-9e11-390e34940058
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=751914877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.751914877
Directory	/workspace/43.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/43.keymgr_custom_cm.1111243223
Short name	T984
Test name
Test status
Simulation time	470939401 ps
CPU time	12.73 seconds
Started	Feb 05 03:39:57 PM PST 24
Finished	Feb 05 03:40:14 PM PST 24
Peak memory	219148 kb
Host	smart-f5a650e4-b8d1-4b8c-992c-19ec7847c5d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111243223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1111243223
Directory	/workspace/43.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/43.keymgr_direct_to_disabled.959647122
Short name	T768
Test name
Test status
Simulation time	23176475 ps
CPU time	1.57 seconds
Started	Feb 05 03:39:55 PM PST 24
Finished	Feb 05 03:39:59 PM PST 24
Peak memory	218516 kb
Host	smart-7f8c19e7-8bd4-4e37-8baf-38f32bc46c7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=959647122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.959647122
Directory	/workspace/43.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/43.keymgr_hwsw_invalid_input.963832381
Short name	T316
Test name
Test status
Simulation time	9877054680 ps
CPU time	22.48 seconds
Started	Feb 05 03:39:57 PM PST 24
Finished	Feb 05 03:40:24 PM PST 24
Peak memory	214276 kb
Host	smart-89fd3d48-3576-4a28-9eb0-feb53a6e0248
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963832381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.963832381
Directory	/workspace/43.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/43.keymgr_kmac_rsp_err.2177779552
Short name	T288
Test name
Test status
Simulation time	138866519 ps
CPU time	6.12 seconds
Started	Feb 05 03:39:55 PM PST 24
Finished	Feb 05 03:40:03 PM PST 24
Peak memory	222420 kb
Host	smart-01b0a2bd-97ea-4406-9c9a-bb14087af33c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2177779552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2177779552
Directory	/workspace/43.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/43.keymgr_lc_disable.842236805
Short name	T345
Test name
Test status
Simulation time	1285072488 ps
CPU time	5.31 seconds
Started	Feb 05 03:40:02 PM PST 24
Finished	Feb 05 03:40:16 PM PST 24
Peak memory	220152 kb
Host	smart-d369d684-02f3-4ef9-b79d-fce5bddbb0c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842236805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.842236805
Directory	/workspace/43.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/43.keymgr_random.3167195955
Short name	T994
Test name
Test status
Simulation time	426388638 ps
CPU time	4.96 seconds
Started	Feb 05 03:39:54 PM PST 24
Finished	Feb 05 03:40:02 PM PST 24
Peak memory	209016 kb
Host	smart-315cd9bb-458d-4055-9ee5-f5872fe1e656
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3167195955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3167195955
Directory	/workspace/43.keymgr_random/latest

Test location	/workspace/coverage/default/43.keymgr_sideload.2447622376
Short name	T877
Test name
Test status
Simulation time	82350213 ps
CPU time	3.06 seconds
Started	Feb 05 03:39:50 PM PST 24
Finished	Feb 05 03:39:55 PM PST 24
Peak memory	208364 kb
Host	smart-1270da06-cf3d-43ee-a6a5-034ce88a3b14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447622376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2447622376
Directory	/workspace/43.keymgr_sideload/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_aes.2121851933
Short name	T652
Test name
Test status
Simulation time	87464335 ps
CPU time	4.07 seconds
Started	Feb 05 03:39:49 PM PST 24
Finished	Feb 05 03:39:54 PM PST 24
Peak memory	208444 kb
Host	smart-799ab7b4-adef-43e5-ae3b-09d4c5339b64
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121851933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2121851933
Directory	/workspace/43.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_kmac.922491583
Short name	T587
Test name
Test status
Simulation time	311737279 ps
CPU time	4.39 seconds
Started	Feb 05 03:39:52 PM PST 24
Finished	Feb 05 03:39:57 PM PST 24
Peak memory	207960 kb
Host	smart-b855507c-02a2-4bf6-a276-34c585383d5e
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922491583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.922491583
Directory	/workspace/43.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_otbn.1281526387
Short name	T804
Test name
Test status
Simulation time	183200892 ps
CPU time	2.71 seconds
Started	Feb 05 03:39:49 PM PST 24
Finished	Feb 05 03:39:53 PM PST 24
Peak memory	206772 kb
Host	smart-f1707398-f38b-461c-90c5-6552767f2bb6
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281526387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1281526387
Directory	/workspace/43.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_protect.996896727
Short name	T193
Test name
Test status
Simulation time	968927580 ps
CPU time	11.13 seconds
Started	Feb 05 03:39:57 PM PST 24
Finished	Feb 05 03:40:13 PM PST 24
Peak memory	214384 kb
Host	smart-89936f7a-fa15-4d91-8795-65291d05bc2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996896727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.996896727
Directory	/workspace/43.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/43.keymgr_smoke.2328909562
Short name	T550
Test name
Test status
Simulation time	817024602 ps
CPU time	5.37 seconds
Started	Feb 05 03:39:52 PM PST 24
Finished	Feb 05 03:39:58 PM PST 24
Peak memory	206748 kb
Host	smart-31aeb451-50fc-4e9b-a152-90e7cb444aa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2328909562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2328909562
Directory	/workspace/43.keymgr_smoke/latest

Test location	/workspace/coverage/default/43.keymgr_stress_all.2363019053
Short name	T297
Test name
Test status
Simulation time	131699688 ps
CPU time	5.89 seconds
Started	Feb 05 03:39:57 PM PST 24
Finished	Feb 05 03:40:07 PM PST 24
Peak memory	217572 kb
Host	smart-1e8a09c3-bf8c-4bf8-8acb-47384fffc765
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363019053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2363019053
Directory	/workspace/43.keymgr_stress_all/latest

Test location	/workspace/coverage/default/43.keymgr_sw_invalid_input.137134413
Short name	T641
Test name
Test status
Simulation time	233605840 ps
CPU time	4.98 seconds
Started	Feb 05 03:39:57 PM PST 24
Finished	Feb 05 03:40:07 PM PST 24
Peak memory	218348 kb
Host	smart-73082a79-0de0-4e91-81b5-774ebbf45cf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137134413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.137134413
Directory	/workspace/43.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/43.keymgr_sync_async_fault_cross.1736457156
Short name	T832
Test name
Test status
Simulation time	159365443 ps
CPU time	2.78 seconds
Started	Feb 05 03:39:56 PM PST 24
Finished	Feb 05 03:40:04 PM PST 24
Peak memory	210484 kb
Host	smart-38499d29-739c-4eea-839a-7007013766bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1736457156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1736457156
Directory	/workspace/43.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/44.keymgr_alert_test.175243137
Short name	T549
Test name
Test status
Simulation time	18228344 ps
CPU time	0.85 seconds
Started	Feb 05 03:40:12 PM PST 24
Finished	Feb 05 03:40:18 PM PST 24
Peak memory	205340 kb
Host	smart-8b53e643-2cbe-449b-bf67-59b92c56077c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175243137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.175243137
Directory	/workspace/44.keymgr_alert_test/latest

Test location	/workspace/coverage/default/44.keymgr_cfg_regwen.972263686
Short name	T348
Test name
Test status
Simulation time	56377593 ps
CPU time	4.05 seconds
Started	Feb 05 03:40:02 PM PST 24
Finished	Feb 05 03:40:08 PM PST 24
Peak memory	214220 kb
Host	smart-88f62c41-31bf-4dae-a46e-d69e9bc9d023
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=972263686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.972263686
Directory	/workspace/44.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/44.keymgr_direct_to_disabled.2623768219
Short name	T941
Test name
Test status
Simulation time	140425837 ps
CPU time	2.28 seconds
Started	Feb 05 03:39:56 PM PST 24
Finished	Feb 05 03:40:03 PM PST 24
Peak memory	209260 kb
Host	smart-fdc7e514-36e7-4e98-925f-8933fa0d7c89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623768219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2623768219
Directory	/workspace/44.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/44.keymgr_random.2163756223
Short name	T798
Test name
Test status
Simulation time	952341918 ps
CPU time	4.75 seconds
Started	Feb 05 03:39:55 PM PST 24
Finished	Feb 05 03:40:04 PM PST 24
Peak memory	214368 kb
Host	smart-d75b8621-4c20-438f-ac9f-20f9212d19ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163756223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2163756223
Directory	/workspace/44.keymgr_random/latest

Test location	/workspace/coverage/default/44.keymgr_sideload.2645138368
Short name	T885
Test name
Test status
Simulation time	1510347022 ps
CPU time	6.45 seconds
Started	Feb 05 03:39:57 PM PST 24
Finished	Feb 05 03:40:08 PM PST 24
Peak memory	207280 kb
Host	smart-71e05b94-f60c-479d-926e-978770ba83f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2645138368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2645138368
Directory	/workspace/44.keymgr_sideload/latest

Test location	/workspace/coverage/default/44.keymgr_sideload_kmac.1565772024
Short name	T934
Test name
Test status
Simulation time	896176552 ps
CPU time	9.25 seconds
Started	Feb 05 03:39:56 PM PST 24
Finished	Feb 05 03:40:10 PM PST 24
Peak memory	207896 kb
Host	smart-795d4c99-07ac-4f25-939a-3c20d0b0ca09
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565772024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1565772024
Directory	/workspace/44.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/44.keymgr_sideload_otbn.644865380
Short name	T256
Test name
Test status
Simulation time	83910374 ps
CPU time	3.75 seconds
Started	Feb 05 03:39:57 PM PST 24
Finished	Feb 05 03:40:05 PM PST 24
Peak memory	208364 kb
Host	smart-2aa4aa05-c720-4dca-94b8-866fc93d57ad
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644865380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.644865380
Directory	/workspace/44.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/44.keymgr_sideload_protect.3117616641
Short name	T919
Test name
Test status
Simulation time	91470254 ps
CPU time	1.64 seconds
Started	Feb 05 03:40:01 PM PST 24
Finished	Feb 05 03:40:05 PM PST 24
Peak memory	207892 kb
Host	smart-0964cd2e-7962-4d92-bdc9-401e13189b2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3117616641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3117616641
Directory	/workspace/44.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/44.keymgr_smoke.3760961896
Short name	T578
Test name
Test status
Simulation time	307577867 ps
CPU time	4.61 seconds
Started	Feb 05 03:39:55 PM PST 24
Finished	Feb 05 03:40:04 PM PST 24
Peak memory	206664 kb
Host	smart-a0b13a5e-1619-4b7f-a541-14b70e9bdf3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760961896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3760961896
Directory	/workspace/44.keymgr_smoke/latest

Test location	/workspace/coverage/default/44.keymgr_sw_invalid_input.2828148479
Short name	T367
Test name
Test status
Simulation time	449675601 ps
CPU time	7.21 seconds
Started	Feb 05 03:40:02 PM PST 24
Finished	Feb 05 03:40:12 PM PST 24
Peak memory	208876 kb
Host	smart-e586e336-3b6f-4aab-9550-e7c4c7941f2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828148479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2828148479
Directory	/workspace/44.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/44.keymgr_sync_async_fault_cross.2968955318
Short name	T869
Test name
Test status
Simulation time	593360216 ps
CPU time	4.44 seconds
Started	Feb 05 03:39:57 PM PST 24
Finished	Feb 05 03:40:06 PM PST 24
Peak memory	210360 kb
Host	smart-1b263b04-c905-4625-87b5-1317db630d1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968955318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2968955318
Directory	/workspace/44.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/45.keymgr_alert_test.3309757857
Short name	T751
Test name
Test status
Simulation time	24110350 ps
CPU time	0.89 seconds
Started	Feb 05 03:40:03 PM PST 24
Finished	Feb 05 03:40:14 PM PST 24
Peak memory	205876 kb
Host	smart-6ed9ddb5-0426-4ac3-8708-d7aaccafa8e2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309757857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3309757857
Directory	/workspace/45.keymgr_alert_test/latest

Test location	/workspace/coverage/default/45.keymgr_cfg_regwen.403216491
Short name	T284
Test name
Test status
Simulation time	3128932805 ps
CPU time	164.34 seconds
Started	Feb 05 03:40:05 PM PST 24
Finished	Feb 05 03:43:00 PM PST 24
Peak memory	214872 kb
Host	smart-dbc682e1-2962-455e-aa84-359aa0cb3bcb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=403216491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.403216491
Directory	/workspace/45.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/45.keymgr_direct_to_disabled.1186768326
Short name	T245
Test name
Test status
Simulation time	1659955126 ps
CPU time	20.77 seconds
Started	Feb 05 03:40:05 PM PST 24
Finished	Feb 05 03:40:37 PM PST 24
Peak memory	217472 kb
Host	smart-c1da5de1-3b77-448f-8e7d-5d99e56547d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186768326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1186768326
Directory	/workspace/45.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/45.keymgr_lc_disable.3792161080
Short name	T745
Test name
Test status
Simulation time	73298870 ps
CPU time	3.5 seconds
Started	Feb 05 03:40:13 PM PST 24
Finished	Feb 05 03:40:21 PM PST 24
Peak memory	220064 kb
Host	smart-71e47caf-42a4-461c-b592-d1537a5a7e5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792161080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3792161080
Directory	/workspace/45.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/45.keymgr_random.131714959
Short name	T883
Test name
Test status
Simulation time	100818836 ps
CPU time	2.76 seconds
Started	Feb 05 03:40:12 PM PST 24
Finished	Feb 05 03:40:20 PM PST 24
Peak memory	208436 kb
Host	smart-63c45959-8783-4fb2-bddd-d44d35610ec9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=131714959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.131714959
Directory	/workspace/45.keymgr_random/latest

Test location	/workspace/coverage/default/45.keymgr_sideload.2658459062
Short name	T778
Test name
Test status
Simulation time	61824597 ps
CPU time	3.14 seconds
Started	Feb 05 03:40:04 PM PST 24
Finished	Feb 05 03:40:18 PM PST 24
Peak memory	206856 kb
Host	smart-66f23595-b3b1-44b9-9a21-e8c918e52be5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658459062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2658459062
Directory	/workspace/45.keymgr_sideload/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_aes.3123564721
Short name	T620
Test name
Test status
Simulation time	384439232 ps
CPU time	9.73 seconds
Started	Feb 05 03:40:12 PM PST 24
Finished	Feb 05 03:40:26 PM PST 24
Peak memory	208252 kb
Host	smart-be56dee5-51be-4c3d-b763-51e6cd61495f
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123564721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3123564721
Directory	/workspace/45.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_kmac.3356273528
Short name	T955
Test name
Test status
Simulation time	2159399978 ps
CPU time	52.96 seconds
Started	Feb 05 03:40:02 PM PST 24
Finished	Feb 05 03:40:57 PM PST 24
Peak memory	208204 kb
Host	smart-392f605b-cf00-48fb-83cd-d71190c94564
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356273528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3356273528
Directory	/workspace/45.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_otbn.2973373144
Short name	T293
Test name
Test status
Simulation time	550713846 ps
CPU time	6.61 seconds
Started	Feb 05 03:40:04 PM PST 24
Finished	Feb 05 03:40:21 PM PST 24
Peak memory	208572 kb
Host	smart-2da172c1-c027-4df5-9c3d-b65ac50b6efc
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973373144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2973373144
Directory	/workspace/45.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_protect.3726414684
Short name	T669
Test name
Test status
Simulation time	432798251 ps
CPU time	3.34 seconds
Started	Feb 05 03:40:06 PM PST 24
Finished	Feb 05 03:40:20 PM PST 24
Peak memory	215676 kb
Host	smart-c1a4024b-ed1c-4bd0-aeb4-177ad4bd2b55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3726414684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3726414684
Directory	/workspace/45.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/45.keymgr_smoke.3583416799
Short name	T615
Test name
Test status
Simulation time	498422245 ps
CPU time	11.94 seconds
Started	Feb 05 03:40:12 PM PST 24
Finished	Feb 05 03:40:29 PM PST 24
Peak memory	208440 kb
Host	smart-14627481-21e9-4634-a816-e6b9870f004e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583416799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3583416799
Directory	/workspace/45.keymgr_smoke/latest

Test location	/workspace/coverage/default/45.keymgr_stress_all.2342939791
Short name	T861
Test name
Test status
Simulation time	3460292265 ps
CPU time	33.22 seconds
Started	Feb 05 03:40:04 PM PST 24
Finished	Feb 05 03:40:48 PM PST 24
Peak memory	214340 kb
Host	smart-5200514c-5cfa-4c50-8794-7c13a70f8888
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342939791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2342939791
Directory	/workspace/45.keymgr_stress_all/latest

Test location	/workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3748649519
Short name	T856
Test name
Test status
Simulation time	195524616 ps
CPU time	8.14 seconds
Started	Feb 05 03:40:02 PM PST 24
Finished	Feb 05 03:40:13 PM PST 24
Peak memory	223568 kb
Host	smart-f65e9a52-e516-4d81-8008-3ee12dcb4a6d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748649519 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3748649519
Directory	/workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.keymgr_sync_async_fault_cross.2760320333
Short name	T639
Test name
Test status
Simulation time	89301840 ps
CPU time	3.42 seconds
Started	Feb 05 03:40:03 PM PST 24
Finished	Feb 05 03:40:17 PM PST 24
Peak memory	210016 kb
Host	smart-66e935e9-c393-4c1d-a1af-1b2aa7820892
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760320333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2760320333
Directory	/workspace/45.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/46.keymgr_alert_test.2849614450
Short name	T557
Test name
Test status
Simulation time	11606341 ps
CPU time	0.9 seconds
Started	Feb 05 03:40:16 PM PST 24
Finished	Feb 05 03:40:20 PM PST 24
Peak memory	205792 kb
Host	smart-6093fed3-824b-40b5-aa0b-ec1cdf25a652
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849614450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2849614450
Directory	/workspace/46.keymgr_alert_test/latest

Test location	/workspace/coverage/default/46.keymgr_custom_cm.742962754
Short name	T895
Test name
Test status
Simulation time	92264273 ps
CPU time	1.89 seconds
Started	Feb 05 03:40:13 PM PST 24
Finished	Feb 05 03:40:19 PM PST 24
Peak memory	218884 kb
Host	smart-9f0a139e-b156-4ce7-bcfe-10d5384a4980
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742962754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.742962754
Directory	/workspace/46.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/46.keymgr_direct_to_disabled.2611960215
Short name	T46
Test name
Test status
Simulation time	3190743582 ps
CPU time	29.57 seconds
Started	Feb 05 03:40:13 PM PST 24
Finished	Feb 05 03:40:47 PM PST 24
Peak memory	209840 kb
Host	smart-8d49a87a-aa72-44a0-a14d-752ac6109b16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2611960215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2611960215
Directory	/workspace/46.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/46.keymgr_hwsw_invalid_input.859521968
Short name	T873
Test name
Test status
Simulation time	171527153 ps
CPU time	4.29 seconds
Started	Feb 05 03:40:16 PM PST 24
Finished	Feb 05 03:40:23 PM PST 24
Peak memory	208640 kb
Host	smart-e7282dd5-6ae2-4cbc-8ffb-091f4e8384ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=859521968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.859521968
Directory	/workspace/46.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/46.keymgr_kmac_rsp_err.1754209463
Short name	T267
Test name
Test status
Simulation time	1175376474 ps
CPU time	32.54 seconds
Started	Feb 05 03:40:11 PM PST 24
Finished	Feb 05 03:40:49 PM PST 24
Peak memory	222368 kb
Host	smart-3c04db8e-9e43-48bb-96c0-331f1fe4065d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754209463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1754209463
Directory	/workspace/46.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/46.keymgr_lc_disable.2539651584
Short name	T55
Test name
Test status
Simulation time	379934055 ps
CPU time	3.72 seconds
Started	Feb 05 03:40:12 PM PST 24
Finished	Feb 05 03:40:20 PM PST 24
Peak memory	222556 kb
Host	smart-52e6d770-1041-4b64-8e70-576f2eb8e25d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2539651584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2539651584
Directory	/workspace/46.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/46.keymgr_random.2234652698
Short name	T951
Test name
Test status
Simulation time	47318342 ps
CPU time	2.85 seconds
Started	Feb 05 03:40:16 PM PST 24
Finished	Feb 05 03:40:22 PM PST 24
Peak memory	208856 kb
Host	smart-cdace91c-3552-4157-acf2-a24b6abb0cb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2234652698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2234652698
Directory	/workspace/46.keymgr_random/latest

Test location	/workspace/coverage/default/46.keymgr_sideload.3464809867
Short name	T758
Test name
Test status
Simulation time	65703627 ps
CPU time	3.36 seconds
Started	Feb 05 03:40:04 PM PST 24
Finished	Feb 05 03:40:18 PM PST 24
Peak memory	208772 kb
Host	smart-91019ae4-04b1-40b1-a5a8-c56aa575543a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3464809867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3464809867
Directory	/workspace/46.keymgr_sideload/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_aes.3142539056
Short name	T637
Test name
Test status
Simulation time	63950658 ps
CPU time	3.29 seconds
Started	Feb 05 03:40:09 PM PST 24
Finished	Feb 05 03:40:20 PM PST 24
Peak memory	208940 kb
Host	smart-3ffe3446-7132-4d55-936a-a8cb3a9af584
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142539056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3142539056
Directory	/workspace/46.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_kmac.2561419952
Short name	T329
Test name
Test status
Simulation time	844103265 ps
CPU time	3.66 seconds
Started	Feb 05 03:40:05 PM PST 24
Finished	Feb 05 03:40:20 PM PST 24
Peak memory	208708 kb
Host	smart-e66e3842-9cc4-423a-bb2a-fc1e519088c8
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561419952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2561419952
Directory	/workspace/46.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_otbn.3151732909
Short name	T766
Test name
Test status
Simulation time	66977596 ps
CPU time	3.19 seconds
Started	Feb 05 03:40:12 PM PST 24
Finished	Feb 05 03:40:20 PM PST 24
Peak memory	208660 kb
Host	smart-a4c34763-8106-49b3-80ec-75006bb7703e
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151732909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3151732909
Directory	/workspace/46.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_protect.2805552046
Short name	T732
Test name
Test status
Simulation time	60405409 ps
CPU time	2.75 seconds
Started	Feb 05 03:40:14 PM PST 24
Finished	Feb 05 03:40:21 PM PST 24
Peak memory	220728 kb
Host	smart-abbd1a2a-1028-4c48-bd46-a0eede2716e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2805552046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2805552046
Directory	/workspace/46.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/46.keymgr_smoke.899382198
Short name	T656
Test name
Test status
Simulation time	258659843 ps
CPU time	5.55 seconds
Started	Feb 05 03:40:05 PM PST 24
Finished	Feb 05 03:40:22 PM PST 24
Peak memory	208508 kb
Host	smart-12fd08e5-5a98-4595-9884-9552ceab5506
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899382198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.899382198
Directory	/workspace/46.keymgr_smoke/latest

Test location	/workspace/coverage/default/46.keymgr_stress_all.1121049796
Short name	T938
Test name
Test status
Simulation time	328212920 ps
CPU time	12.03 seconds
Started	Feb 05 03:40:19 PM PST 24
Finished	Feb 05 03:40:33 PM PST 24
Peak memory	214960 kb
Host	smart-7c51a0cf-eadf-40b0-bc9c-684fcb366f2c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121049796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1121049796
Directory	/workspace/46.keymgr_stress_all/latest

Test location	/workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3484213312
Short name	T353
Test name
Test status
Simulation time	1015542052 ps
CPU time	5.68 seconds
Started	Feb 05 03:40:10 PM PST 24
Finished	Feb 05 03:40:22 PM PST 24
Peak memory	222648 kb
Host	smart-b9b986d7-ce61-45c9-aeb6-1696c371e3af
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484213312 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3484213312
Directory	/workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.keymgr_sw_invalid_input.3846706698
Short name	T283
Test name
Test status
Simulation time	516614414 ps
CPU time	4.82 seconds
Started	Feb 05 03:40:27 PM PST 24
Finished	Feb 05 03:40:36 PM PST 24
Peak memory	218048 kb
Host	smart-4e02889d-bb9b-4afc-991d-71e40024d24e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846706698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3846706698
Directory	/workspace/46.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/46.keymgr_sync_async_fault_cross.4204197600
Short name	T983
Test name
Test status
Simulation time	272148935 ps
CPU time	2.45 seconds
Started	Feb 05 03:40:14 PM PST 24
Finished	Feb 05 03:40:20 PM PST 24
Peak memory	210072 kb
Host	smart-74f3d8e1-27b1-42fd-b5c8-0c9042169e63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4204197600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.4204197600
Directory	/workspace/46.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/47.keymgr_alert_test.4087478477
Short name	T663
Test name
Test status
Simulation time	45217256 ps
CPU time	0.86 seconds
Started	Feb 05 03:40:11 PM PST 24
Finished	Feb 05 03:40:17 PM PST 24
Peak memory	205776 kb
Host	smart-36c8576b-d69b-4299-897f-9aa9cbd11f18
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087478477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4087478477
Directory	/workspace/47.keymgr_alert_test/latest

Test location	/workspace/coverage/default/47.keymgr_direct_to_disabled.3582259803
Short name	T291
Test name
Test status
Simulation time	221073709 ps
CPU time	6.04 seconds
Started	Feb 05 03:40:15 PM PST 24
Finished	Feb 05 03:40:25 PM PST 24
Peak memory	210168 kb
Host	smart-2046ec07-e6be-48ac-a76b-9486d4116cd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582259803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3582259803
Directory	/workspace/47.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/47.keymgr_hwsw_invalid_input.1089687998
Short name	T867
Test name
Test status
Simulation time	1746355737 ps
CPU time	18.25 seconds
Started	Feb 05 03:40:14 PM PST 24
Finished	Feb 05 03:40:36 PM PST 24
Peak memory	221580 kb
Host	smart-76c75890-d007-488f-99aa-39b8b2cb118a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089687998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1089687998
Directory	/workspace/47.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/47.keymgr_kmac_rsp_err.1671201085
Short name	T229
Test name
Test status
Simulation time	264595535 ps
CPU time	8.9 seconds
Started	Feb 05 03:40:10 PM PST 24
Finished	Feb 05 03:40:25 PM PST 24
Peak memory	214312 kb
Host	smart-9d5c7ec8-c9bb-4e7c-9d8a-79e9168c3192
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671201085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1671201085
Directory	/workspace/47.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/47.keymgr_lc_disable.2728923141
Short name	T206
Test name
Test status
Simulation time	139621513 ps
CPU time	3.59 seconds
Started	Feb 05 03:40:13 PM PST 24
Finished	Feb 05 03:40:21 PM PST 24
Peak memory	220224 kb
Host	smart-c4a2aefc-a059-4a5b-a1db-dde166c0eb16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728923141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2728923141
Directory	/workspace/47.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/47.keymgr_random.3236529681
Short name	T860
Test name
Test status
Simulation time	454065947 ps
CPU time	5.12 seconds
Started	Feb 05 03:40:13 PM PST 24
Finished	Feb 05 03:40:22 PM PST 24
Peak memory	210228 kb
Host	smart-9fef93c5-c663-4c23-8450-132700812aad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236529681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3236529681
Directory	/workspace/47.keymgr_random/latest

Test location	/workspace/coverage/default/47.keymgr_sideload.2022054331
Short name	T574
Test name
Test status
Simulation time	42104715 ps
CPU time	2.49 seconds
Started	Feb 05 03:40:14 PM PST 24
Finished	Feb 05 03:40:20 PM PST 24
Peak memory	207544 kb
Host	smart-74ff1944-8334-4ef3-8268-ef0f63092ed0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2022054331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2022054331
Directory	/workspace/47.keymgr_sideload/latest

Test location	/workspace/coverage/default/47.keymgr_sideload_aes.351442326
Short name	T638
Test name
Test status
Simulation time	207947894 ps
CPU time	7.93 seconds
Started	Feb 05 03:40:11 PM PST 24
Finished	Feb 05 03:40:25 PM PST 24
Peak memory	208332 kb
Host	smart-3a50bfa9-792b-49aa-9c69-eda09640e68a
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351442326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.351442326
Directory	/workspace/47.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/47.keymgr_sideload_kmac.2130253622
Short name	T790
Test name
Test status
Simulation time	670066564 ps
CPU time	7.1 seconds
Started	Feb 05 03:40:15 PM PST 24
Finished	Feb 05 03:40:25 PM PST 24
Peak memory	207928 kb
Host	smart-3d3095be-2b9d-4f3e-9d4a-aea25d9b1be3
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130253622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2130253622
Directory	/workspace/47.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/47.keymgr_sideload_otbn.2952475285
Short name	T102
Test name
Test status
Simulation time	229912421 ps
CPU time	6.74 seconds
Started	Feb 05 03:40:15 PM PST 24
Finished	Feb 05 03:40:25 PM PST 24
Peak memory	208924 kb
Host	smart-de21a0f8-d412-4d26-82d3-1222584b3bcd
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952475285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2952475285
Directory	/workspace/47.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/47.keymgr_smoke.2682430027
Short name	T658
Test name
Test status
Simulation time	1778312811 ps
CPU time	26.94 seconds
Started	Feb 05 03:40:10 PM PST 24
Finished	Feb 05 03:40:44 PM PST 24
Peak memory	207780 kb
Host	smart-4520513d-45c3-4fd3-9ece-307691c4990c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2682430027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2682430027
Directory	/workspace/47.keymgr_smoke/latest

Test location	/workspace/coverage/default/47.keymgr_stress_all.1869582349
Short name	T811
Test name
Test status
Simulation time	140521321 ps
CPU time	2.24 seconds
Started	Feb 05 03:40:09 PM PST 24
Finished	Feb 05 03:40:19 PM PST 24
Peak memory	208752 kb
Host	smart-3a38f5af-94da-4fb9-bc4f-44dd66a3ff2c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869582349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1869582349
Directory	/workspace/47.keymgr_stress_all/latest

Test location	/workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.302230697
Short name	T208
Test name
Test status
Simulation time	656578594 ps
CPU time	6.09 seconds
Started	Feb 05 03:40:09 PM PST 24
Finished	Feb 05 03:40:23 PM PST 24
Peak memory	222612 kb
Host	smart-378cc156-739b-4c05-bf84-5ec2e862d1f3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302230697 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.302230697
Directory	/workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.keymgr_alert_test.3953033055
Short name	T728
Test name
Test status
Simulation time	32593397 ps
CPU time	0.81 seconds
Started	Feb 05 03:40:36 PM PST 24
Finished	Feb 05 03:40:38 PM PST 24
Peak memory	205780 kb
Host	smart-7fc85609-9003-4701-a341-f2a907579e45
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953033055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3953033055
Directory	/workspace/48.keymgr_alert_test/latest

Test location	/workspace/coverage/default/48.keymgr_cfg_regwen.2390400616
Short name	T83
Test name
Test status
Simulation time	42668175 ps
CPU time	3.29 seconds
Started	Feb 05 03:40:39 PM PST 24
Finished	Feb 05 03:40:43 PM PST 24
Peak memory	214296 kb
Host	smart-e82353cd-ce56-439b-940f-12d431c9d50c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2390400616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2390400616
Directory	/workspace/48.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/48.keymgr_custom_cm.2525225233
Short name	T27
Test name
Test status
Simulation time	60857758 ps
CPU time	3.69 seconds
Started	Feb 05 03:40:42 PM PST 24
Finished	Feb 05 03:40:49 PM PST 24
Peak memory	210704 kb
Host	smart-d2b497dc-d9c8-4018-b782-0593504d0b02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525225233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2525225233
Directory	/workspace/48.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/48.keymgr_direct_to_disabled.3394695607
Short name	T813
Test name
Test status
Simulation time	494076737 ps
CPU time	12.22 seconds
Started	Feb 05 03:40:34 PM PST 24
Finished	Feb 05 03:40:48 PM PST 24
Peak memory	208524 kb
Host	smart-f61bb31a-d7f1-46a3-8afa-f11821a83f43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3394695607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3394695607
Directory	/workspace/48.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/48.keymgr_hwsw_invalid_input.3570793037
Short name	T646
Test name
Test status
Simulation time	2765204588 ps
CPU time	67.2 seconds
Started	Feb 05 03:40:34 PM PST 24
Finished	Feb 05 03:41:43 PM PST 24
Peak memory	214504 kb
Host	smart-4d3ebc7c-4ead-475e-bec8-34763a18042b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570793037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3570793037
Directory	/workspace/48.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/48.keymgr_kmac_rsp_err.1447890562
Short name	T176
Test name
Test status
Simulation time	189965614 ps
CPU time	6 seconds
Started	Feb 05 03:40:20 PM PST 24
Finished	Feb 05 03:40:28 PM PST 24
Peak memory	210236 kb
Host	smart-3c8314fd-865f-43f6-b8b9-7fe5b77a013d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447890562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1447890562
Directory	/workspace/48.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/48.keymgr_lc_disable.1002897419
Short name	T700
Test name
Test status
Simulation time	138846305 ps
CPU time	2.01 seconds
Started	Feb 05 03:40:20 PM PST 24
Finished	Feb 05 03:40:24 PM PST 24
Peak memory	206324 kb
Host	smart-f882c66b-e812-409f-b82c-50ad2d85aabf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002897419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1002897419
Directory	/workspace/48.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/48.keymgr_random.447918618
Short name	T326
Test name
Test status
Simulation time	54212846 ps
CPU time	3.38 seconds
Started	Feb 05 03:40:38 PM PST 24
Finished	Feb 05 03:40:43 PM PST 24
Peak memory	207448 kb
Host	smart-49a02274-ab12-49b0-978c-fd36b59c373b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447918618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.447918618
Directory	/workspace/48.keymgr_random/latest

Test location	/workspace/coverage/default/48.keymgr_sideload.2987258627
Short name	T285
Test name
Test status
Simulation time	24527750 ps
CPU time	1.83 seconds
Started	Feb 05 03:40:15 PM PST 24
Finished	Feb 05 03:40:21 PM PST 24
Peak memory	206956 kb
Host	smart-a7d161d7-3cdb-47bd-b25c-378ba49f1c5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987258627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2987258627
Directory	/workspace/48.keymgr_sideload/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_aes.2663351143
Short name	T189
Test name
Test status
Simulation time	289968896 ps
CPU time	3.56 seconds
Started	Feb 05 03:40:22 PM PST 24
Finished	Feb 05 03:40:27 PM PST 24
Peak memory	208516 kb
Host	smart-b9442163-68d2-43b4-bf8c-ef530c923ff3
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663351143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2663351143
Directory	/workspace/48.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_kmac.4131705656
Short name	T927
Test name
Test status
Simulation time	4090395835 ps
CPU time	16.67 seconds
Started	Feb 05 03:40:14 PM PST 24
Finished	Feb 05 03:40:35 PM PST 24
Peak memory	208112 kb
Host	smart-b50a9cfd-8f09-4396-adc7-5805b4d95eb2
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131705656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4131705656
Directory	/workspace/48.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_otbn.2389701319
Short name	T898
Test name
Test status
Simulation time	487185963 ps
CPU time	16.18 seconds
Started	Feb 05 03:40:15 PM PST 24
Finished	Feb 05 03:40:34 PM PST 24
Peak memory	208660 kb
Host	smart-5dbafff3-271c-46b8-964d-1b06ec48d0ca
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389701319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2389701319
Directory	/workspace/48.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_protect.2527357342
Short name	T313
Test name
Test status
Simulation time	300013948 ps
CPU time	5.03 seconds
Started	Feb 05 03:40:20 PM PST 24
Finished	Feb 05 03:40:27 PM PST 24
Peak memory	209752 kb
Host	smart-6d7bb13a-331e-485f-be07-995b2767f6a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527357342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2527357342
Directory	/workspace/48.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/48.keymgr_smoke.3606751468
Short name	T1004
Test name
Test status
Simulation time	241938039 ps
CPU time	6.84 seconds
Started	Feb 05 03:40:20 PM PST 24
Finished	Feb 05 03:40:29 PM PST 24
Peak memory	207800 kb
Host	smart-5fb00974-48c7-4b8f-9cd7-6124578eb344
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606751468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3606751468
Directory	/workspace/48.keymgr_smoke/latest

Test location	/workspace/coverage/default/48.keymgr_stress_all.361619237
Short name	T380
Test name
Test status
Simulation time	611809902 ps
CPU time	13.41 seconds
Started	Feb 05 03:40:22 PM PST 24
Finished	Feb 05 03:40:36 PM PST 24
Peak memory	216292 kb
Host	smart-91cb4759-c2c8-45eb-9d3f-bc77b270874a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361619237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.361619237
Directory	/workspace/48.keymgr_stress_all/latest

Test location	/workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.291273782
Short name	T852
Test name
Test status
Simulation time	535376720 ps
CPU time	12.45 seconds
Started	Feb 05 03:40:27 PM PST 24
Finished	Feb 05 03:40:44 PM PST 24
Peak memory	222516 kb
Host	smart-61face32-4806-4857-915b-6f0aed0a82ad
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291273782 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.291273782
Directory	/workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.keymgr_sw_invalid_input.1495281627
Short name	T890
Test name
Test status
Simulation time	364894538 ps
CPU time	4.5 seconds
Started	Feb 05 03:40:27 PM PST 24
Finished	Feb 05 03:40:36 PM PST 24
Peak memory	219904 kb
Host	smart-d4125223-ded1-4bc1-b320-4cb3c5b1804f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1495281627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1495281627
Directory	/workspace/48.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/48.keymgr_sync_async_fault_cross.1608441537
Short name	T59
Test name
Test status
Simulation time	77995282 ps
CPU time	2.42 seconds
Started	Feb 05 03:40:19 PM PST 24
Finished	Feb 05 03:40:22 PM PST 24
Peak memory	210368 kb
Host	smart-ba62a8da-d640-4c61-978e-a2d0c3277538
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608441537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1608441537
Directory	/workspace/48.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/49.keymgr_alert_test.1713391958
Short name	T630
Test name
Test status
Simulation time	12710358 ps
CPU time	0.89 seconds
Started	Feb 05 03:40:45 PM PST 24
Finished	Feb 05 03:40:52 PM PST 24
Peak memory	205892 kb
Host	smart-59daa24a-dc4d-44a7-a860-6f910c4f221f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713391958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1713391958
Directory	/workspace/49.keymgr_alert_test/latest

Test location	/workspace/coverage/default/49.keymgr_cfg_regwen.3862786792
Short name	T402
Test name
Test status
Simulation time	192471490 ps
CPU time	3.75 seconds
Started	Feb 05 03:40:19 PM PST 24
Finished	Feb 05 03:40:25 PM PST 24
Peak memory	214360 kb
Host	smart-8e6b35c0-cc4e-43dc-890e-cd5047068ea5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3862786792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3862786792
Directory	/workspace/49.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/49.keymgr_custom_cm.2616432842
Short name	T872
Test name
Test status
Simulation time	507092760 ps
CPU time	4.14 seconds
Started	Feb 05 03:40:23 PM PST 24
Finished	Feb 05 03:40:28 PM PST 24
Peak memory	214532 kb
Host	smart-ba487939-9359-4844-a60f-fd679953e04d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616432842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2616432842
Directory	/workspace/49.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/49.keymgr_direct_to_disabled.3044347436
Short name	T333
Test name
Test status
Simulation time	547762619 ps
CPU time	5.61 seconds
Started	Feb 05 03:40:43 PM PST 24
Finished	Feb 05 03:40:53 PM PST 24
Peak memory	218240 kb
Host	smart-24d93641-5c43-4a02-9b4b-63570fbc6156
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044347436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3044347436
Directory	/workspace/49.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/49.keymgr_hwsw_invalid_input.1034086989
Short name	T974
Test name
Test status
Simulation time	44406093 ps
CPU time	3.02 seconds
Started	Feb 05 03:40:38 PM PST 24
Finished	Feb 05 03:40:41 PM PST 24
Peak memory	214316 kb
Host	smart-9781a0f8-8ebb-4604-9073-27797ba20762
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1034086989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1034086989
Directory	/workspace/49.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/49.keymgr_kmac_rsp_err.2569925401
Short name	T819
Test name
Test status
Simulation time	13299815671 ps
CPU time	48 seconds
Started	Feb 05 03:40:19 PM PST 24
Finished	Feb 05 03:41:09 PM PST 24
Peak memory	222496 kb
Host	smart-0388c4e6-76da-49d8-a61e-add75a77dbfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569925401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2569925401
Directory	/workspace/49.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/49.keymgr_lc_disable.2320291610
Short name	T913
Test name
Test status
Simulation time	74893095 ps
CPU time	2.41 seconds
Started	Feb 05 03:40:16 PM PST 24
Finished	Feb 05 03:40:21 PM PST 24
Peak memory	214824 kb
Host	smart-b7239004-4ec5-4bd4-8479-4c6a70ae0834
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320291610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2320291610
Directory	/workspace/49.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/49.keymgr_random.1669842887
Short name	T686
Test name
Test status
Simulation time	387696690 ps
CPU time	5.03 seconds
Started	Feb 05 03:40:25 PM PST 24
Finished	Feb 05 03:40:31 PM PST 24
Peak memory	209040 kb
Host	smart-6235c429-e2f4-433d-8724-c37e9390f87c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669842887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1669842887
Directory	/workspace/49.keymgr_random/latest

Test location	/workspace/coverage/default/49.keymgr_sideload.73347802
Short name	T588
Test name
Test status
Simulation time	293576813 ps
CPU time	3.56 seconds
Started	Feb 05 03:40:27 PM PST 24
Finished	Feb 05 03:40:35 PM PST 24
Peak memory	208648 kb
Host	smart-08062832-867d-4c0f-8e56-e3fa2425d81b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73347802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.73347802
Directory	/workspace/49.keymgr_sideload/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_aes.4267911844
Short name	T4
Test name
Test status
Simulation time	154115056 ps
CPU time	2.87 seconds
Started	Feb 05 03:40:29 PM PST 24
Finished	Feb 05 03:40:35 PM PST 24
Peak memory	208832 kb
Host	smart-afc705c5-e6d9-4a0e-8c5b-348f6f26e429
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267911844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4267911844
Directory	/workspace/49.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_kmac.2766750411
Short name	T991
Test name
Test status
Simulation time	802250233 ps
CPU time	12.04 seconds
Started	Feb 05 03:40:25 PM PST 24
Finished	Feb 05 03:40:40 PM PST 24
Peak memory	208112 kb
Host	smart-96db3c08-abf1-46f7-94aa-245dd384f55b
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766750411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2766750411
Directory	/workspace/49.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_otbn.121000084
Short name	T662
Test name
Test status
Simulation time	51220368 ps
CPU time	2.79 seconds
Started	Feb 05 03:40:27 PM PST 24
Finished	Feb 05 03:40:34 PM PST 24
Peak memory	206968 kb
Host	smart-a77661ec-51f6-4271-9488-f83a95f23417
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121000084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.121000084
Directory	/workspace/49.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_protect.2200578639
Short name	T238
Test name
Test status
Simulation time	84393572 ps
CPU time	2.68 seconds
Started	Feb 05 03:40:26 PM PST 24
Finished	Feb 05 03:40:33 PM PST 24
Peak memory	218228 kb
Host	smart-d658e491-3d69-4bbe-a978-f12b879a0a58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2200578639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2200578639
Directory	/workspace/49.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/49.keymgr_smoke.1995354820
Short name	T820
Test name
Test status
Simulation time	99885353 ps
CPU time	3.97 seconds
Started	Feb 05 03:40:25 PM PST 24
Finished	Feb 05 03:40:30 PM PST 24
Peak memory	208644 kb
Host	smart-9c676f62-7e28-404d-997c-816b377fa97f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995354820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1995354820
Directory	/workspace/49.keymgr_smoke/latest

Test location	/workspace/coverage/default/49.keymgr_sw_invalid_input.4187360766
Short name	T902
Test name
Test status
Simulation time	1861550229 ps
CPU time	9.83 seconds
Started	Feb 05 03:40:20 PM PST 24
Finished	Feb 05 03:40:32 PM PST 24
Peak memory	209012 kb
Host	smart-6f7e9a31-30ec-46c7-9674-fe23f25718b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187360766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.4187360766
Directory	/workspace/49.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/49.keymgr_sync_async_fault_cross.81319486
Short name	T606
Test name
Test status
Simulation time	208813425 ps
CPU time	2.55 seconds
Started	Feb 05 03:40:18 PM PST 24
Finished	Feb 05 03:40:22 PM PST 24
Peak memory	210124 kb
Host	smart-cd31aa3e-ae8d-40df-8e78-4f36b928bcde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81319486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.81319486
Directory	/workspace/49.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/5.keymgr_alert_test.3486773668
Short name	T3
Test name
Test status
Simulation time	15018665 ps
CPU time	0.76 seconds
Started	Feb 05 03:36:51 PM PST 24
Finished	Feb 05 03:36:57 PM PST 24
Peak memory	206072 kb
Host	smart-26b23834-33e6-425c-8fd7-e3167316d0d8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486773668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3486773668
Directory	/workspace/5.keymgr_alert_test/latest

Test location	/workspace/coverage/default/5.keymgr_cfg_regwen.310870907
Short name	T918
Test name
Test status
Simulation time	115535043 ps
CPU time	4.56 seconds
Started	Feb 05 03:36:50 PM PST 24
Finished	Feb 05 03:37:00 PM PST 24
Peak memory	215020 kb
Host	smart-2d57bba7-8ab7-4e7c-ac41-ad47d6056bad
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=310870907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.310870907
Directory	/workspace/5.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/5.keymgr_direct_to_disabled.767424554
Short name	T568
Test name
Test status
Simulation time	25174278 ps
CPU time	1.85 seconds
Started	Feb 05 03:36:50 PM PST 24
Finished	Feb 05 03:36:57 PM PST 24
Peak memory	206868 kb
Host	smart-4e946d73-4c3e-4e08-835a-150723990f5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=767424554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.767424554
Directory	/workspace/5.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/5.keymgr_hwsw_invalid_input.4090579224
Short name	T925
Test name
Test status
Simulation time	164340949 ps
CPU time	3.2 seconds
Started	Feb 05 03:36:55 PM PST 24
Finished	Feb 05 03:37:01 PM PST 24
Peak memory	208600 kb
Host	smart-b93f73df-1e3e-4100-a930-f25fc4290bf2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090579224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4090579224
Directory	/workspace/5.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/5.keymgr_kmac_rsp_err.581582837
Short name	T85
Test name
Test status
Simulation time	3341505091 ps
CPU time	36.32 seconds
Started	Feb 05 03:36:50 PM PST 24
Finished	Feb 05 03:37:31 PM PST 24
Peak memory	222420 kb
Host	smart-446e1c31-7020-4e75-9ca3-898ae76b9007
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581582837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.581582837
Directory	/workspace/5.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/5.keymgr_lc_disable.2534922955
Short name	T729
Test name
Test status
Simulation time	150027486 ps
CPU time	1.8 seconds
Started	Feb 05 03:36:54 PM PST 24
Finished	Feb 05 03:36:59 PM PST 24
Peak memory	214344 kb
Host	smart-e6190382-eeec-4400-b650-0a78d73cfb32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534922955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2534922955
Directory	/workspace/5.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/5.keymgr_random.108191877
Short name	T572
Test name
Test status
Simulation time	346805557 ps
CPU time	5.07 seconds
Started	Feb 05 03:36:48 PM PST 24
Finished	Feb 05 03:36:58 PM PST 24
Peak memory	207164 kb
Host	smart-d777ff1d-cc66-4f4d-b950-c8315a913303
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108191877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.108191877
Directory	/workspace/5.keymgr_random/latest

Test location	/workspace/coverage/default/5.keymgr_sideload.397063997
Short name	T632
Test name
Test status
Simulation time	121820042 ps
CPU time	3.13 seconds
Started	Feb 05 03:36:47 PM PST 24
Finished	Feb 05 03:36:56 PM PST 24
Peak memory	206728 kb
Host	smart-c9fbd60a-7c13-478b-aa06-82b5b8d8ce4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397063997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.397063997
Directory	/workspace/5.keymgr_sideload/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_aes.2391913449
Short name	T109
Test name
Test status
Simulation time	131714289 ps
CPU time	2.62 seconds
Started	Feb 05 03:36:46 PM PST 24
Finished	Feb 05 03:36:55 PM PST 24
Peak memory	206932 kb
Host	smart-99f95e6e-fe86-4ec4-b652-9d2b6d9c06c6
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391913449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2391913449
Directory	/workspace/5.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_kmac.434689675
Short name	T275
Test name
Test status
Simulation time	287504031 ps
CPU time	8.26 seconds
Started	Feb 05 03:36:45 PM PST 24
Finished	Feb 05 03:37:00 PM PST 24
Peak memory	208380 kb
Host	smart-a0683575-22e2-4346-8606-ce18e120ad57
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434689675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.434689675
Directory	/workspace/5.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_otbn.417061192
Short name	T956
Test name
Test status
Simulation time	73497219 ps
CPU time	3.42 seconds
Started	Feb 05 03:36:47 PM PST 24
Finished	Feb 05 03:36:56 PM PST 24
Peak memory	207840 kb
Host	smart-021c5de4-c412-4b56-a9be-e9b4b17ca4e8
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417061192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.417061192
Directory	/workspace/5.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_protect.730002510
Short name	T286
Test name
Test status
Simulation time	394327576 ps
CPU time	3.74 seconds
Started	Feb 05 03:36:49 PM PST 24
Finished	Feb 05 03:36:58 PM PST 24
Peak memory	215620 kb
Host	smart-d69c3e42-0953-4a08-99f5-5a1e4d9e36a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=730002510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.730002510
Directory	/workspace/5.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/5.keymgr_smoke.2382595166
Short name	T661
Test name
Test status
Simulation time	107062804 ps
CPU time	4.62 seconds
Started	Feb 05 03:36:48 PM PST 24
Finished	Feb 05 03:36:57 PM PST 24
Peak memory	207116 kb
Host	smart-03dddb99-e7bb-499b-9b44-4ea418ccbada
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2382595166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2382595166
Directory	/workspace/5.keymgr_smoke/latest

Test location	/workspace/coverage/default/5.keymgr_stress_all.213931305
Short name	T211
Test name
Test status
Simulation time	638948899 ps
CPU time	16.02 seconds
Started	Feb 05 03:36:49 PM PST 24
Finished	Feb 05 03:37:10 PM PST 24
Peak memory	216396 kb
Host	smart-81096996-f12b-4eb4-941f-363ce1138a61
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213931305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.213931305
Directory	/workspace/5.keymgr_stress_all/latest

Test location	/workspace/coverage/default/5.keymgr_sw_invalid_input.2783317645
Short name	T998
Test name
Test status
Simulation time	952929348 ps
CPU time	7.91 seconds
Started	Feb 05 03:36:50 PM PST 24
Finished	Feb 05 03:37:03 PM PST 24
Peak memory	208900 kb
Host	smart-979dd2ac-6682-4dda-8f96-d6174e2a992f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783317645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2783317645
Directory	/workspace/5.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/5.keymgr_sync_async_fault_cross.1083165771
Short name	T943
Test name
Test status
Simulation time	1690968659 ps
CPU time	15.8 seconds
Started	Feb 05 03:36:48 PM PST 24
Finished	Feb 05 03:37:09 PM PST 24
Peak memory	210748 kb
Host	smart-06fb4c79-199f-492b-af4f-dcc0d88184ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083165771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1083165771
Directory	/workspace/5.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/6.keymgr_alert_test.3745010516
Short name	T562
Test name
Test status
Simulation time	27211778 ps
CPU time	0.86 seconds
Started	Feb 05 03:37:04 PM PST 24
Finished	Feb 05 03:37:06 PM PST 24
Peak memory	205880 kb
Host	smart-0d77030e-1839-40c6-a75d-23c10332ec3d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745010516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3745010516
Directory	/workspace/6.keymgr_alert_test/latest

Test location	/workspace/coverage/default/6.keymgr_cfg_regwen.1783233237
Short name	T343
Test name
Test status
Simulation time	629844918 ps
CPU time	9.04 seconds
Started	Feb 05 03:36:54 PM PST 24
Finished	Feb 05 03:37:06 PM PST 24
Peak memory	214316 kb
Host	smart-c0fb9b6a-270b-4df3-9494-081359de044f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1783233237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1783233237
Directory	/workspace/6.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/6.keymgr_custom_cm.1582075682
Short name	T993
Test name
Test status
Simulation time	470740108 ps
CPU time	5.49 seconds
Started	Feb 05 03:36:54 PM PST 24
Finished	Feb 05 03:37:03 PM PST 24
Peak memory	219640 kb
Host	smart-a1ebe996-aed5-48a0-87a8-229bb0f5042a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582075682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1582075682
Directory	/workspace/6.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/6.keymgr_direct_to_disabled.1824895578
Short name	T691
Test name
Test status
Simulation time	120318280 ps
CPU time	3.23 seconds
Started	Feb 05 03:36:55 PM PST 24
Finished	Feb 05 03:37:01 PM PST 24
Peak memory	209040 kb
Host	smart-a5189ed7-8027-46b2-be3e-8fff7106e5a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1824895578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1824895578
Directory	/workspace/6.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/6.keymgr_kmac_rsp_err.1917531633
Short name	T247
Test name
Test status
Simulation time	153527183 ps
CPU time	6.26 seconds
Started	Feb 05 03:36:54 PM PST 24
Finished	Feb 05 03:37:04 PM PST 24
Peak memory	214284 kb
Host	smart-640ce9b2-e0b0-4681-85ba-5f6b6e56ef39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1917531633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1917531633
Directory	/workspace/6.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/6.keymgr_lc_disable.1143929834
Short name	T953
Test name
Test status
Simulation time	2657014594 ps
CPU time	24.45 seconds
Started	Feb 05 03:36:55 PM PST 24
Finished	Feb 05 03:37:23 PM PST 24
Peak memory	217344 kb
Host	smart-f9e3acea-3fea-4c75-aaeb-cb03431c69d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143929834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1143929834
Directory	/workspace/6.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/6.keymgr_random.2978670227
Short name	T655
Test name
Test status
Simulation time	835414594 ps
CPU time	2.87 seconds
Started	Feb 05 03:36:56 PM PST 24
Finished	Feb 05 03:37:02 PM PST 24
Peak memory	207076 kb
Host	smart-b55a6144-f194-4e2e-908b-1c57563ce83e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2978670227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2978670227
Directory	/workspace/6.keymgr_random/latest

Test location	/workspace/coverage/default/6.keymgr_sideload.2776199752
Short name	T299
Test name
Test status
Simulation time	951183167 ps
CPU time	33.11 seconds
Started	Feb 05 03:36:54 PM PST 24
Finished	Feb 05 03:37:30 PM PST 24
Peak memory	208272 kb
Host	smart-1180892a-171d-41e7-aabb-a0fd5568ee0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2776199752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2776199752
Directory	/workspace/6.keymgr_sideload/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_aes.346923248
Short name	T559
Test name
Test status
Simulation time	411938199 ps
CPU time	6.77 seconds
Started	Feb 05 03:36:55 PM PST 24
Finished	Feb 05 03:37:05 PM PST 24
Peak memory	208296 kb
Host	smart-e369f6dc-c380-45a9-9bb8-84a88595ee78
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346923248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.346923248
Directory	/workspace/6.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_kmac.2821660050
Short name	T322
Test name
Test status
Simulation time	120371972 ps
CPU time	4.18 seconds
Started	Feb 05 03:36:55 PM PST 24
Finished	Feb 05 03:37:02 PM PST 24
Peak memory	206720 kb
Host	smart-59c3fb1c-ff11-4bfe-a313-ff915cc28860
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821660050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2821660050
Directory	/workspace/6.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_otbn.4147336026
Short name	T924
Test name
Test status
Simulation time	149648939 ps
CPU time	4.62 seconds
Started	Feb 05 03:36:55 PM PST 24
Finished	Feb 05 03:37:03 PM PST 24
Peak memory	208488 kb
Host	smart-ecc8ad3c-9738-49a6-b75e-a66f7c6a4f82
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147336026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4147336026
Directory	/workspace/6.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_protect.2333577795
Short name	T841
Test name
Test status
Simulation time	76681662 ps
CPU time	2.46 seconds
Started	Feb 05 03:36:55 PM PST 24
Finished	Feb 05 03:37:01 PM PST 24
Peak memory	214304 kb
Host	smart-493ec9ae-455b-4275-8a0c-1d55d4e4adac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333577795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2333577795
Directory	/workspace/6.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3280169114
Short name	T749
Test name
Test status
Simulation time	232001165 ps
CPU time	4.13 seconds
Started	Feb 05 03:37:00 PM PST 24
Finished	Feb 05 03:37:06 PM PST 24
Peak memory	219104 kb
Host	smart-e747bf9a-2732-48cc-b2d3-cac1df95c9b8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280169114 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3280169114
Directory	/workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.keymgr_sw_invalid_input.1251513068
Short name	T325
Test name
Test status
Simulation time	288755962 ps
CPU time	8.62 seconds
Started	Feb 05 03:36:54 PM PST 24
Finished	Feb 05 03:37:06 PM PST 24
Peak memory	208484 kb
Host	smart-f5272776-5d49-4642-97b3-c8e1a50d63e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1251513068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1251513068
Directory	/workspace/6.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/6.keymgr_sync_async_fault_cross.3217741421
Short name	T730
Test name
Test status
Simulation time	237296518 ps
CPU time	2.24 seconds
Started	Feb 05 03:36:52 PM PST 24
Finished	Feb 05 03:36:59 PM PST 24
Peak memory	210012 kb
Host	smart-36561bc3-27bc-4d32-bc49-cc943e8d96c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217741421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3217741421
Directory	/workspace/6.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/7.keymgr_alert_test.1401107785
Short name	T815
Test name
Test status
Simulation time	19796559 ps
CPU time	0.77 seconds
Started	Feb 05 03:37:14 PM PST 24
Finished	Feb 05 03:37:22 PM PST 24
Peak memory	205880 kb
Host	smart-f885fae0-b9a0-4d68-b972-9f4264ef2fce
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401107785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1401107785
Directory	/workspace/7.keymgr_alert_test/latest

Test location	/workspace/coverage/default/7.keymgr_cfg_regwen.3231955892
Short name	T398
Test name
Test status
Simulation time	54171751 ps
CPU time	2.44 seconds
Started	Feb 05 03:37:02 PM PST 24
Finished	Feb 05 03:37:07 PM PST 24
Peak memory	214328 kb
Host	smart-b446798d-1804-49a5-9996-0148b73dc8ff
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3231955892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3231955892
Directory	/workspace/7.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/7.keymgr_custom_cm.3578875783
Short name	T878
Test name
Test status
Simulation time	57859111 ps
CPU time	3.19 seconds
Started	Feb 05 03:37:13 PM PST 24
Finished	Feb 05 03:37:24 PM PST 24
Peak memory	210620 kb
Host	smart-585379ec-73fe-4980-ae22-a74478952a9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3578875783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3578875783
Directory	/workspace/7.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/7.keymgr_direct_to_disabled.1751046556
Short name	T954
Test name
Test status
Simulation time	5496197593 ps
CPU time	18.69 seconds
Started	Feb 05 03:37:03 PM PST 24
Finished	Feb 05 03:37:24 PM PST 24
Peak memory	208680 kb
Host	smart-1b3f9570-524f-43db-9560-6bf7e1992651
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751046556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1751046556
Directory	/workspace/7.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/7.keymgr_hwsw_invalid_input.160320746
Short name	T314
Test name
Test status
Simulation time	192761351 ps
CPU time	3.91 seconds
Started	Feb 05 03:37:12 PM PST 24
Finished	Feb 05 03:37:25 PM PST 24
Peak memory	214232 kb
Host	smart-56b99344-707a-498b-9141-69f668df5277
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=160320746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.160320746
Directory	/workspace/7.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/7.keymgr_random.2272314466
Short name	T721
Test name
Test status
Simulation time	790689643 ps
CPU time	11.35 seconds
Started	Feb 05 03:37:02 PM PST 24
Finished	Feb 05 03:37:17 PM PST 24
Peak memory	208696 kb
Host	smart-eb0a8985-f870-4ef2-b722-341af01b2ee7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2272314466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2272314466
Directory	/workspace/7.keymgr_random/latest

Test location	/workspace/coverage/default/7.keymgr_sideload.1756835739
Short name	T762
Test name
Test status
Simulation time	317778593 ps
CPU time	2.94 seconds
Started	Feb 05 03:37:00 PM PST 24
Finished	Feb 05 03:37:05 PM PST 24
Peak memory	206880 kb
Host	smart-bee1c5b8-8e17-4763-bd5c-3a2d92705a69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1756835739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1756835739
Directory	/workspace/7.keymgr_sideload/latest

Test location	/workspace/coverage/default/7.keymgr_sideload_aes.4116955607
Short name	T932
Test name
Test status
Simulation time	124211831 ps
CPU time	2.42 seconds
Started	Feb 05 03:37:02 PM PST 24
Finished	Feb 05 03:37:08 PM PST 24
Peak memory	206884 kb
Host	smart-b1600145-6112-468d-b5d4-e45b7532aae3
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116955607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.4116955607
Directory	/workspace/7.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/7.keymgr_sideload_kmac.3804814752
Short name	T830
Test name
Test status
Simulation time	1242770866 ps
CPU time	38.29 seconds
Started	Feb 05 03:37:01 PM PST 24
Finished	Feb 05 03:37:43 PM PST 24
Peak memory	208436 kb
Host	smart-cffa3ee6-509a-4090-b5d5-599b1db6ae1c
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804814752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3804814752
Directory	/workspace/7.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/7.keymgr_sideload_protect.1332468033
Short name	T829
Test name
Test status
Simulation time	21006063 ps
CPU time	1.8 seconds
Started	Feb 05 03:37:13 PM PST 24
Finished	Feb 05 03:37:23 PM PST 24
Peak memory	215540 kb
Host	smart-ceb2af80-533f-415b-8d4a-353dddfe9aab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332468033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1332468033
Directory	/workspace/7.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/7.keymgr_smoke.3372252045
Short name	T744
Test name
Test status
Simulation time	453576256 ps
CPU time	3.48 seconds
Started	Feb 05 03:37:04 PM PST 24
Finished	Feb 05 03:37:09 PM PST 24
Peak memory	208348 kb
Host	smart-b06d6304-f264-48f4-9879-77d68aea9c86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372252045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3372252045
Directory	/workspace/7.keymgr_smoke/latest

Test location	/workspace/coverage/default/7.keymgr_sw_invalid_input.689148685
Short name	T336
Test name
Test status
Simulation time	4199581705 ps
CPU time	46.94 seconds
Started	Feb 05 03:37:11 PM PST 24
Finished	Feb 05 03:38:07 PM PST 24
Peak memory	210096 kb
Host	smart-03294ad1-cb92-4c7c-b6f3-7e23da321a6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689148685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.689148685
Directory	/workspace/7.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/7.keymgr_sync_async_fault_cross.3372726775
Short name	T131
Test name
Test status
Simulation time	288477435 ps
CPU time	10.09 seconds
Started	Feb 05 03:37:08 PM PST 24
Finished	Feb 05 03:37:19 PM PST 24
Peak memory	211012 kb
Host	smart-f57aefc1-f3e6-4b9d-ae8d-cac96431d832
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372726775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3372726775
Directory	/workspace/7.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/8.keymgr_alert_test.1814716621
Short name	T855
Test name
Test status
Simulation time	10064951 ps
CPU time	0.94 seconds
Started	Feb 05 03:37:17 PM PST 24
Finished	Feb 05 03:37:23 PM PST 24
Peak memory	205868 kb
Host	smart-7ddc264e-bf05-4eda-8ea3-75e6a22cfd94
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814716621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1814716621
Directory	/workspace/8.keymgr_alert_test/latest

Test location	/workspace/coverage/default/8.keymgr_cfg_regwen.2324012051
Short name	T395
Test name
Test status
Simulation time	34634757 ps
CPU time	2.59 seconds
Started	Feb 05 03:37:09 PM PST 24
Finished	Feb 05 03:37:13 PM PST 24
Peak memory	214796 kb
Host	smart-2d597705-e358-4514-8028-9481f6ea38d4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2324012051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2324012051
Directory	/workspace/8.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/8.keymgr_custom_cm.4134654145
Short name	T879
Test name
Test status
Simulation time	261821529 ps
CPU time	6.78 seconds
Started	Feb 05 03:37:13 PM PST 24
Finished	Feb 05 03:37:28 PM PST 24
Peak memory	210048 kb
Host	smart-a9fbfa58-2e63-4d7f-b3e7-ace4d8922985
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134654145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.4134654145
Directory	/workspace/8.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/8.keymgr_direct_to_disabled.2556620268
Short name	T757
Test name
Test status
Simulation time	978578216 ps
CPU time	10.03 seconds
Started	Feb 05 03:37:12 PM PST 24
Finished	Feb 05 03:37:31 PM PST 24
Peak memory	207976 kb
Host	smart-c734fbbb-4e4a-4624-bff5-7c7e29892c27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556620268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2556620268
Directory	/workspace/8.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/8.keymgr_hwsw_invalid_input.687075764
Short name	T92
Test name
Test status
Simulation time	216094345 ps
CPU time	3.7 seconds
Started	Feb 05 03:37:17 PM PST 24
Finished	Feb 05 03:37:26 PM PST 24
Peak memory	208976 kb
Host	smart-4cdf5e02-a478-4e72-9623-f1b9e8396c12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687075764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.687075764
Directory	/workspace/8.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/8.keymgr_kmac_rsp_err.2545230334
Short name	T366
Test name
Test status
Simulation time	46844482 ps
CPU time	2.6 seconds
Started	Feb 05 03:37:12 PM PST 24
Finished	Feb 05 03:37:23 PM PST 24
Peak memory	210832 kb
Host	smart-a1124d57-7d99-4d5f-abbc-65bd4ce12c8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545230334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2545230334
Directory	/workspace/8.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/8.keymgr_lc_disable.2996363145
Short name	T992
Test name
Test status
Simulation time	158586051 ps
CPU time	3.89 seconds
Started	Feb 05 03:37:12 PM PST 24
Finished	Feb 05 03:37:25 PM PST 24
Peak memory	219984 kb
Host	smart-54d5fba0-f57a-4247-a23b-6b4754c485bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996363145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2996363145
Directory	/workspace/8.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/8.keymgr_random.1218012465
Short name	T979
Test name
Test status
Simulation time	288124822 ps
CPU time	6.4 seconds
Started	Feb 05 03:37:09 PM PST 24
Finished	Feb 05 03:37:16 PM PST 24
Peak memory	209800 kb
Host	smart-6a76ee0d-b13c-4679-b137-7687a7305841
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1218012465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1218012465
Directory	/workspace/8.keymgr_random/latest

Test location	/workspace/coverage/default/8.keymgr_sideload.2365412803
Short name	T219
Test name
Test status
Simulation time	378272980 ps
CPU time	5.66 seconds
Started	Feb 05 03:37:08 PM PST 24
Finished	Feb 05 03:37:14 PM PST 24
Peak memory	207996 kb
Host	smart-6c0893c7-8712-4b4d-8fa6-0e46c952c457
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365412803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2365412803
Directory	/workspace/8.keymgr_sideload/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_aes.1075269158
Short name	T748
Test name
Test status
Simulation time	27672372 ps
CPU time	2.35 seconds
Started	Feb 05 03:37:08 PM PST 24
Finished	Feb 05 03:37:11 PM PST 24
Peak memory	208752 kb
Host	smart-17f62ec1-8ece-4b9a-90cc-4331be1cc77b
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075269158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1075269158
Directory	/workspace/8.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_kmac.690073155
Short name	T657
Test name
Test status
Simulation time	377745595 ps
CPU time	3.26 seconds
Started	Feb 05 03:37:12 PM PST 24
Finished	Feb 05 03:37:24 PM PST 24
Peak memory	207168 kb
Host	smart-0f797151-738d-49fe-a0b4-eed6166fe3e9
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690073155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.690073155
Directory	/workspace/8.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_otbn.3338745377
Short name	T373
Test name
Test status
Simulation time	625130292 ps
CPU time	8.28 seconds
Started	Feb 05 03:37:09 PM PST 24
Finished	Feb 05 03:37:18 PM PST 24
Peak memory	208736 kb
Host	smart-92b6a965-5cff-4bfc-8bb9-40d2a83f9d25
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338745377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3338745377
Directory	/workspace/8.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_protect.2404574867
Short name	T216
Test name
Test status
Simulation time	241707914 ps
CPU time	2.95 seconds
Started	Feb 05 03:37:13 PM PST 24
Finished	Feb 05 03:37:24 PM PST 24
Peak memory	207768 kb
Host	smart-713841fc-648c-4258-a312-946a74616044
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2404574867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2404574867
Directory	/workspace/8.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/8.keymgr_smoke.980202314
Short name	T566
Test name
Test status
Simulation time	1089564630 ps
CPU time	7.46 seconds
Started	Feb 05 03:37:09 PM PST 24
Finished	Feb 05 03:37:18 PM PST 24
Peak memory	207972 kb
Host	smart-aad7a84f-c9e9-4e52-a161-22c823744e63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980202314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.980202314
Directory	/workspace/8.keymgr_smoke/latest

Test location	/workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.771485567
Short name	T853
Test name
Test status
Simulation time	373760114 ps
CPU time	5.53 seconds
Started	Feb 05 03:37:12 PM PST 24
Finished	Feb 05 03:37:26 PM PST 24
Peak memory	222372 kb
Host	smart-8b4084b1-ff62-434f-b607-6cc325248bd5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771485567 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.771485567
Directory	/workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.keymgr_sw_invalid_input.2636267216
Short name	T774
Test name
Test status
Simulation time	148286302 ps
CPU time	4.03 seconds
Started	Feb 05 03:37:14 PM PST 24
Finished	Feb 05 03:37:26 PM PST 24
Peak memory	218188 kb
Host	smart-8e6467f9-aa69-4c2f-9405-ed412c2eb830
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2636267216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2636267216
Directory	/workspace/8.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/8.keymgr_sync_async_fault_cross.2725787892
Short name	T741
Test name
Test status
Simulation time	197675114 ps
CPU time	4.08 seconds
Started	Feb 05 03:37:15 PM PST 24
Finished	Feb 05 03:37:26 PM PST 24
Peak memory	210256 kb
Host	smart-018a834f-6590-4f6b-bdb3-31f54c4ceed9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725787892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2725787892
Directory	/workspace/8.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/9.keymgr_cfg_regwen.1851833395
Short name	T257
Test name
Test status
Simulation time	753796338 ps
CPU time	4.44 seconds
Started	Feb 05 03:37:13 PM PST 24
Finished	Feb 05 03:37:25 PM PST 24
Peak memory	214628 kb
Host	smart-6f1829ef-ab02-4f96-86cf-6b71fcd1a504
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1851833395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1851833395
Directory	/workspace/9.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/9.keymgr_custom_cm.926264536
Short name	T10
Test name
Test status
Simulation time	138425221 ps
CPU time	3.47 seconds
Started	Feb 05 03:37:34 PM PST 24
Finished	Feb 05 03:37:40 PM PST 24
Peak memory	221440 kb
Host	smart-14d7d3da-82ce-4294-82c5-fd8cf7ff5c14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926264536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.926264536
Directory	/workspace/9.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/9.keymgr_direct_to_disabled.3345501873
Short name	T944
Test name
Test status
Simulation time	494029939 ps
CPU time	3.19 seconds
Started	Feb 05 03:37:26 PM PST 24
Finished	Feb 05 03:37:31 PM PST 24
Peak memory	208168 kb
Host	smart-1f08812a-c811-462a-b5dd-d65fe74b9b70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3345501873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3345501873
Directory	/workspace/9.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/9.keymgr_kmac_rsp_err.4280412397
Short name	T760
Test name
Test status
Simulation time	639775451 ps
CPU time	3.04 seconds
Started	Feb 05 03:37:26 PM PST 24
Finished	Feb 05 03:37:31 PM PST 24
Peak memory	209484 kb
Host	smart-5a431402-c377-4148-9537-0224de82627c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280412397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.4280412397
Directory	/workspace/9.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/9.keymgr_random.1110256046
Short name	T773
Test name
Test status
Simulation time	337372532 ps
CPU time	9.62 seconds
Started	Feb 05 03:37:12 PM PST 24
Finished	Feb 05 03:37:30 PM PST 24
Peak memory	208504 kb
Host	smart-fce493f9-91c6-423e-8bf2-44546b04cc1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110256046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1110256046
Directory	/workspace/9.keymgr_random/latest

Test location	/workspace/coverage/default/9.keymgr_sideload.3580428628
Short name	T327
Test name
Test status
Simulation time	75654902 ps
CPU time	2.46 seconds
Started	Feb 05 03:37:16 PM PST 24
Finished	Feb 05 03:37:24 PM PST 24
Peak memory	206900 kb
Host	smart-444818bd-d497-4860-810a-e86f3f72e71f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580428628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3580428628
Directory	/workspace/9.keymgr_sideload/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_aes.3766775192
Short name	T858
Test name
Test status
Simulation time	21103281 ps
CPU time	1.85 seconds
Started	Feb 05 03:37:13 PM PST 24
Finished	Feb 05 03:37:23 PM PST 24
Peak memory	207336 kb
Host	smart-6d7cfdfe-22eb-49b8-8058-9ac0672186eb
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766775192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3766775192
Directory	/workspace/9.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_kmac.3896207622
Short name	T926
Test name
Test status
Simulation time	64107255 ps
CPU time	2.83 seconds
Started	Feb 05 03:37:15 PM PST 24
Finished	Feb 05 03:37:24 PM PST 24
Peak memory	207860 kb
Host	smart-2169d5cc-0914-4e07-b7a4-8865072ed3c6
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896207622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3896207622
Directory	/workspace/9.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_otbn.571442619
Short name	T933
Test name
Test status
Simulation time	2060571179 ps
CPU time	11.78 seconds
Started	Feb 05 03:37:16 PM PST 24
Finished	Feb 05 03:37:34 PM PST 24
Peak memory	208116 kb
Host	smart-b155163a-954f-42f6-b008-188a01f2922e
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571442619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.571442619
Directory	/workspace/9.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_protect.598199916
Short name	T631
Test name
Test status
Simulation time	90182379 ps
CPU time	1.92 seconds
Started	Feb 05 03:37:34 PM PST 24
Finished	Feb 05 03:37:38 PM PST 24
Peak memory	214308 kb
Host	smart-a3156595-e4e1-42f7-aa77-33da673718db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=598199916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.598199916
Directory	/workspace/9.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/9.keymgr_smoke.1035008078
Short name	T665
Test name
Test status
Simulation time	224755722 ps
CPU time	5.68 seconds
Started	Feb 05 03:37:12 PM PST 24
Finished	Feb 05 03:37:26 PM PST 24
Peak memory	207700 kb
Host	smart-e7c0b051-3ac7-41eb-9d67-0a4410722049
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035008078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1035008078
Directory	/workspace/9.keymgr_smoke/latest

Test location	/workspace/coverage/default/9.keymgr_stress_all.3096988422
Short name	T205
Test name
Test status
Simulation time	417453597 ps
CPU time	14.49 seconds
Started	Feb 05 03:37:26 PM PST 24
Finished	Feb 05 03:37:42 PM PST 24
Peak memory	219668 kb
Host	smart-ce45de93-8797-427b-b22f-d6c731ba909c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096988422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3096988422
Directory	/workspace/9.keymgr_stress_all/latest

Test location	/workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3660024149
Short name	T900
Test name
Test status
Simulation time	545392448 ps
CPU time	3.92 seconds
Started	Feb 05 03:37:23 PM PST 24
Finished	Feb 05 03:37:28 PM PST 24
Peak memory	222756 kb
Host	smart-d1e37a6e-eee2-469a-917e-6fe3d7c004cb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660024149 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3660024149
Directory	/workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.keymgr_sw_invalid_input.1832423419
Short name	T233
Test name
Test status
Simulation time	645118152 ps
CPU time	5.61 seconds
Started	Feb 05 03:37:27 PM PST 24
Finished	Feb 05 03:37:34 PM PST 24
Peak memory	219708 kb
Host	smart-442aee04-5d7e-4624-8c24-4bdbc275e58b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832423419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1832423419
Directory	/workspace/9.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/9.keymgr_sync_async_fault_cross.2502142111
Short name	T14
Test name
Test status
Simulation time	94083668 ps
CPU time	2.49 seconds
Started	Feb 05 03:37:29 PM PST 24
Finished	Feb 05 03:37:33 PM PST 24
Peak memory	210432 kb
Host	smart-eda03f6e-72b6-4d6b-a3fc-70fefb6ffaef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502142111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2502142111
Directory	/workspace/9.keymgr_sync_async_fault_cross/latest