Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10378

1

T1

11

T2

21

T15

13

auto[Attestation]

7194

1

T1

6

T2

2

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2550	1			T4	3		T5	4		T16	2
auto[Aes]	3165	1			T3	2		T4	2		T5	5
auto[Kmac]	3205	1			T5	4		T23	5		T39	3
auto[Otbn]	3155	1			T1	17		T2	23		T15	17

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7049	1			T1	8		T2	8		T3	3
auto[OpGenId]	5497	1			T3	1		T4	9		T5	7
auto[OpGenSwOut]	5430	1			T3	1		T4	3		T5	4
auto[OpGenHwOut]	6645	1			T1	17		T2	23		T3	1
auto[OpDisable]	118	1			T43	1		T25	1		T44	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9089

1

T1

8

T2

8

T3

5

auto[OpDoneFail]

15650

1

T1

17

T2

23

T3

1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5901	1			T1	10		T2	16		T3	1
auto[StInit]	4042	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	2696	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2265	1			T1	2		T2	2		T3	1
auto[StOwnerKey]	2113	1			T1	2		T2	2		T15	2
auto[StDisabled]	6652	1			T1	7		T2	7		T15	7
auto[StInvalid]	1070	1			T36	32		T190	25		T97	35

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	280	1			T16	1		T25	2		T128	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	109	1			T43	1		T129	1		T47	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	66	1			T40	1		T25	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	64	1			T25	1		T47	2		T191	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T4	1		T25	4		T47	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	181	1			T85	1		T192	1		T25	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	33	1			T97	2		T193	1		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	281	1			T16	1		T49	3		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	94	1			T5	1		T43	1		T47	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	65	1			T192	2		T195	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	54	1			T101	1		T43	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	47	1			T127	1		T192	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	204	1			T85	1		T39	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	23	1			T190	1		T193	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	294	1			T40	3		T49	3		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	121	1			T5	1		T39	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	70	1			T43	2		T25	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	60	1			T192	1		T25	1		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	53	1			T40	1		T43	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	180	1			T40	1		T127	1		T25	5
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	42	1			T36	3		T190	2		T97	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	294	1			T43	5		T25	5		T102	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	102	1			T85	1		T101	1		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	69	1			T39	1		T102	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T85	1		T198	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	53	1			T47	2		T199	1		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	169	1			T4	1		T198	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	51	1			T36	2		T190	2		T97	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	65	1			T43	1		T25	6		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T5	1		T16	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	64	1			T85	1		T39	1		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T25	1		T201	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T192	1		T31	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	187	1			T198	1		T25	4		T129	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	29	1			T97	2		T194	1		T202	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	80	1			T43	1		T25	3		T47	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	95	1			T3	1		T102	1		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	75	1			T17	1		T101	1		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	52	1			T47	1		T80	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	52	1			T132	1		T25	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	185	1			T133	1		T192	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	39	1			T36	1		T190	2		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	75	1			T25	4		T47	4		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	119	1			T5	1		T30	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	73	1			T23	1		T131	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	33	1			T23	1		T25	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	67	1			T133	1		T192	2		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	169	1			T40	2		T132	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	26	1			T97	1		T205	3		T90	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	75	1			T25	4		T47	5		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	109	1			T25	2		T201	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	65	1			T16	1		T40	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	42	1			T43	1		T191	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	49	1			T4	1		T198	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	151	1			T39	1		T207	1		T43	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	41	1			T36	4		T97	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	251	1			T5	1		T43	2		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	103	1			T25	2		T201	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	66	1			T23	1		T40	1		T43	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	38	1			T43	1		T47	4		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	32	1			T192	1		T43	1		T148	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	175	1			T127	1		T43	1		T147	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	38	1			T190	2		T97	3		T98	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	465	1			T5	1		T210	6		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	128	1			T5	3		T17	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	78	1			T16	1		T30	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	91	1			T38	1		T210	1		T181	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	84	1			T210	1		T25	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	220	1			T38	2		T39	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	36	1			T190	1		T97	1		T98	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	457	1			T5	1		T192	1		T25	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	123	1			T207	1		T43	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	107	1			T40	1		T25	1		T102	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	78	1			T43	1		T212	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	84	1			T25	1		T214	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	245	1			T40	1		T25	4		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T36	1		T208	2		T194	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	390	1			T1	9		T2	15		T15	9
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	127	1			T2	1		T15	1		T43	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	91	1			T2	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T2	1		T192	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	274	1			T1	1		T2	2		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	39	1			T36	2		T190	3		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	48	1			T43	1		T25	4		T50	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	124	1			T5	2		T17	1		T101	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	54	1			T4	1		T39	2		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	50	1			T127	1		T43	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	47	1			T25	1		T148	1		T135	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	131	1			T4	1		T39	2		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	26	1			T190	1		T97	1		T193	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	41	1			T25	3		T209	1		T217	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	121	1			T4	1		T38	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	102	1			T3	1		T38	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	74	1			T25	1		T182	1		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	78	1			T38	1		T207	1		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	281	1			T4	1		T38	2		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	20	1			T97	2		T205	1		T202	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	62	1			T25	4		T50	1		T208	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	131	1			T5	1		T23	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	95	1			T23	1		T43	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T23	1		T207	1		T219	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	80	1			T43	1		T25	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	220	1			T39	2		T132	1		T25	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	25	1			T190	1		T97	1		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	52	1			T25	4		T50	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	136	1			T1	1		T5	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	107	1			T1	1		T4	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T1	1		T15	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	75	1			T15	1		T47	2		T215	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	239	1			T1	3		T2	2		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T36	2		T97	1		T193	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	180	1			T4	1		T40	1		T25	5
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	612	1			T16	1		T85	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	158	1			T101	1		T127	1		T192	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	610	1			T5	1		T16	1		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	170	1			T40	1		T192	1		T43	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	650	1			T5	1		T39	1		T40	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	166	1			T85	1		T39	1		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	637	1			T4	1		T85	1		T101	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	172	1			T85	1		T39	1		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	403	1			T5	1		T16	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	168	1			T17	1		T132	1		T101	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	410	1			T3	1		T133	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	162	1			T23	2		T133	1		T192	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	400	1			T5	1		T40	2		T132	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	146	1			T4	1		T16	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	386	1			T39	1		T207	1		T43	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	126	1			T23	1		T40	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	577	1			T5	1		T127	1		T43	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	240	1			T16	1		T38	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	862	1			T5	4		T17	1		T38	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	260	1			T40	1		T43	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	862	1			T5	1		T40	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	253	1			T1	1		T2	3		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	844	1			T1	10		T2	18		T15	12
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	136	1			T4	1		T39	2		T127	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	344	1			T4	1		T5	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	236	1			T3	1		T38	2		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	481	1			T4	2		T38	3		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	255	1			T23	2		T207	1		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	446	1			T5	1		T23	1		T39	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	252	1			T1	2		T15	2		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	471	1			T1	4		T2	2		T15	2