Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28453

1

T1

29

T2

37

T3

9

auto[1]

306

1

T4

5

T130

6

T147

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	28462	1			T1	29		T2	37		T3	9
auto[134217728:268435455]	8	1			T130	1		T135	1		T248	1
auto[268435456:402653183]	13	1			T135	1		T272	1		T425	1
auto[402653184:536870911]	4	1			T148	1		T359	2		T387	1
auto[536870912:671088639]	8	1			T272	1		T377	1		T426	1
auto[671088640:805306367]	10	1			T134	1		T346	1		T427	3
auto[805306368:939524095]	9	1			T247	1		T300	1		T346	1
auto[939524096:1073741823]	8	1			T200	1		T277	1		T248	2
auto[1073741824:1207959551]	8	1			T247	1		T272	1		T305	1
auto[1207959552:1342177279]	5	1			T107	1		T334	2		T428	1
auto[1342177280:1476395007]	12	1			T147	1		T247	2		T135	1
auto[1476395008:1610612735]	13	1			T134	1		T247	1		T200	1
auto[1610612736:1744830463]	9	1			T4	1		T148	1		T135	1
auto[1744830464:1879048191]	10	1			T147	1		T134	1		T135	1
auto[1879048192:2013265919]	12	1			T247	1		T135	1		T277	1
auto[2013265920:2147483647]	9	1			T148	1		T135	1		T393	1
auto[2147483648:2281701375]	9	1			T134	1		T277	1		T359	1
auto[2281701376:2415919103]	15	1			T4	1		T130	1		T147	2
auto[2415919104:2550136831]	6	1			T239	1		T377	2		T334	2
auto[2550136832:2684354559]	15	1			T4	1		T130	1		T147	2
auto[2684354560:2818572287]	9	1			T130	1		T134	1		T135	1
auto[2818572288:2952790015]	10	1			T135	1		T395	1		T359	1
auto[2952790016:3087007743]	6	1			T239	1		T107	2		T240	1
auto[3087007744:3221225471]	7	1			T130	1		T147	1		T200	1
auto[3221225472:3355443199]	7	1			T4	1		T148	2		T200	1
auto[3355443200:3489660927]	11	1			T4	1		T136	1		T272	1
auto[3489660928:3623878655]	14	1			T147	1		T247	1		T272	1
auto[3623878656:3758096383]	14	1			T130	1		T247	1		T272	1
auto[3758096384:3892314111]	9	1			T148	1		T134	1		T247	1
auto[3892314112:4026531839]	9	1			T134	1		T393	3		T390	1
auto[4026531840:4160749567]	9	1			T305	1		T300	1		T240	1
auto[4160749568:4294967295]	9	1			T277	1		T429	1		T430	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	28453	1			T1	29		T2	37		T3	9
auto[0:134217727]	auto[1]	9	1			T247	1		T272	1		T393	1
auto[134217728:268435455]	auto[1]	8	1			T130	1		T135	1		T248	1
auto[268435456:402653183]	auto[1]	13	1			T135	1		T272	1		T425	1
auto[402653184:536870911]	auto[1]	4	1			T148	1		T359	2		T387	1
auto[536870912:671088639]	auto[1]	8	1			T272	1		T377	1		T426	1
auto[671088640:805306367]	auto[1]	10	1			T134	1		T346	1		T427	3
auto[805306368:939524095]	auto[1]	9	1			T247	1		T300	1		T346	1
auto[939524096:1073741823]	auto[1]	8	1			T200	1		T277	1		T248	2
auto[1073741824:1207959551]	auto[1]	8	1			T247	1		T272	1		T305	1
auto[1207959552:1342177279]	auto[1]	5	1			T107	1		T334	2		T428	1
auto[1342177280:1476395007]	auto[1]	12	1			T147	1		T247	2		T135	1
auto[1476395008:1610612735]	auto[1]	13	1			T134	1		T247	1		T200	1
auto[1610612736:1744830463]	auto[1]	9	1			T4	1		T148	1		T135	1
auto[1744830464:1879048191]	auto[1]	10	1			T147	1		T134	1		T135	1
auto[1879048192:2013265919]	auto[1]	12	1			T247	1		T135	1		T277	1
auto[2013265920:2147483647]	auto[1]	9	1			T148	1		T135	1		T393	1
auto[2147483648:2281701375]	auto[1]	9	1			T134	1		T277	1		T359	1
auto[2281701376:2415919103]	auto[1]	15	1			T4	1		T130	1		T147	2
auto[2415919104:2550136831]	auto[1]	6	1			T239	1		T377	2		T334	2
auto[2550136832:2684354559]	auto[1]	15	1			T4	1		T130	1		T147	2
auto[2684354560:2818572287]	auto[1]	9	1			T130	1		T134	1		T135	1
auto[2818572288:2952790015]	auto[1]	10	1			T135	1		T395	1		T359	1
auto[2952790016:3087007743]	auto[1]	6	1			T239	1		T107	2		T240	1
auto[3087007744:3221225471]	auto[1]	7	1			T130	1		T147	1		T200	1
auto[3221225472:3355443199]	auto[1]	7	1			T4	1		T148	2		T200	1
auto[3355443200:3489660927]	auto[1]	11	1			T4	1		T136	1		T272	1
auto[3489660928:3623878655]	auto[1]	14	1			T147	1		T247	1		T272	1
auto[3623878656:3758096383]	auto[1]	14	1			T130	1		T247	1		T272	1
auto[3758096384:3892314111]	auto[1]	9	1			T148	1		T134	1		T247	1
auto[3892314112:4026531839]	auto[1]	9	1			T134	1		T393	3		T390	1
auto[4026531840:4160749567]	auto[1]	9	1			T305	1		T300	1		T240	1
auto[4160749568:4294967295]	auto[1]	9	1			T277	1		T429	1		T430	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1528

1

T4

2

T16

1

T23

2

auto[1]

1582

1

T4

3

T6

2

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T40	1		T25	1		T219	1
auto[134217728:268435455]	98	1			T40	1		T192	1		T25	1
auto[268435456:402653183]	102	1			T4	1		T40	1		T47	3
auto[402653184:536870911]	80	1			T25	2		T130	1		T47	1
auto[536870912:671088639]	94	1			T4	1		T6	1		T43	1
auto[671088640:805306367]	86	1			T130	1		T201	2		T47	1
auto[805306368:939524095]	98	1			T101	1		T43	1		T25	3
auto[939524096:1073741823]	119	1			T4	1		T16	1		T23	2
auto[1073741824:1207959551]	102	1			T39	1		T192	1		T43	1
auto[1207959552:1342177279]	97	1			T39	1		T49	1		T25	2
auto[1342177280:1476395007]	107	1			T6	1		T192	1		T43	1
auto[1476395008:1610612735]	79	1			T25	1		T47	1		T21	1
auto[1610612736:1744830463]	90	1			T131	1		T147	1		T47	2
auto[1744830464:1879048191]	90	1			T101	1		T43	1		T25	1
auto[1879048192:2013265919]	103	1			T24	1		T192	1		T25	1
auto[2013265920:2147483647]	94	1			T39	1		T192	1		T43	1
auto[2147483648:2281701375]	87	1			T25	2		T115	1		T47	2
auto[2281701376:2415919103]	87	1			T49	1		T43	1		T47	1
auto[2415919104:2550136831]	106	1			T5	1		T25	1		T130	1
auto[2550136832:2684354559]	84	1			T25	3		T102	1		T201	1
auto[2684354560:2818572287]	100	1			T40	1		T25	1		T47	3
auto[2818572288:2952790015]	103	1			T16	1		T25	3		T131	1
auto[2952790016:3087007743]	100	1			T25	1		T131	1		T47	3
auto[3087007744:3221225471]	104	1			T40	1		T43	2		T25	2
auto[3221225472:3355443199]	95	1			T16	1		T23	1		T25	4
auto[3355443200:3489660927]	105	1			T25	1		T44	1		T147	1
auto[3489660928:3623878655]	89	1			T4	2		T219	1		T47	2
auto[3623878656:3758096383]	99	1			T5	1		T39	1		T25	2
auto[3758096384:3892314111]	87	1			T25	2		T130	1		T148	1
auto[3892314112:4026531839]	121	1			T43	1		T25	5		T131	1
auto[4026531840:4160749567]	108	1			T49	1		T192	1		T102	1
auto[4160749568:4294967295]	99	1			T5	1		T24	1		T192	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T25	1		T47	1		T7	1
auto[0:134217727]	auto[1]	45	1			T40	1		T219	1		T47	2
auto[134217728:268435455]	auto[0]	38	1			T192	1		T47	1		T48	1
auto[134217728:268435455]	auto[1]	60	1			T40	1		T25	1		T219	1
auto[268435456:402653183]	auto[0]	55	1			T4	1		T40	1		T47	1
auto[268435456:402653183]	auto[1]	47	1			T47	2		T52	1		T22	1
auto[402653184:536870911]	auto[0]	32	1			T47	1		T396	1		T51	1
auto[402653184:536870911]	auto[1]	48	1			T25	2		T130	1		T243	1
auto[536870912:671088639]	auto[0]	44	1			T25	1		T255	1		T53	1
auto[536870912:671088639]	auto[1]	50	1			T4	1		T6	1		T43	1
auto[671088640:805306367]	auto[0]	38	1			T201	1		T47	1		T19	1
auto[671088640:805306367]	auto[1]	48	1			T130	1		T201	1		T309	1
auto[805306368:939524095]	auto[0]	53	1			T101	1		T25	1		T36	1
auto[805306368:939524095]	auto[1]	45	1			T43	1		T25	2		T47	1
auto[939524096:1073741823]	auto[0]	61	1			T23	2		T43	1		T48	1
auto[939524096:1073741823]	auto[1]	58	1			T4	1		T16	1		T43	2
auto[1073741824:1207959551]	auto[0]	53	1			T192	1		T25	1		T130	1
auto[1073741824:1207959551]	auto[1]	49	1			T39	1		T43	1		T47	1
auto[1207959552:1342177279]	auto[0]	50	1			T25	1		T28	1		T261	1
auto[1207959552:1342177279]	auto[1]	47	1			T39	1		T49	1		T25	1
auto[1342177280:1476395007]	auto[0]	53	1			T43	1		T25	1		T47	1
auto[1342177280:1476395007]	auto[1]	54	1			T6	1		T192	1		T25	2
auto[1476395008:1610612735]	auto[0]	35	1			T25	1		T21	1		T431	1
auto[1476395008:1610612735]	auto[1]	44	1			T47	1		T199	1		T80	1
auto[1610612736:1744830463]	auto[0]	45	1			T131	1		T147	1		T47	2
auto[1610612736:1744830463]	auto[1]	45	1			T8	1		T299	1		T245	1
auto[1744830464:1879048191]	auto[0]	42	1			T101	1		T21	1		T116	1
auto[1744830464:1879048191]	auto[1]	48	1			T43	1		T25	1		T47	1
auto[1879048192:2013265919]	auto[0]	50	1			T25	1		T36	1		T53	1
auto[1879048192:2013265919]	auto[1]	53	1			T24	1		T192	1		T47	1
auto[2013265920:2147483647]	auto[0]	52	1			T192	1		T43	1		T131	1
auto[2013265920:2147483647]	auto[1]	42	1			T39	1		T130	1		T418	1
auto[2147483648:2281701375]	auto[0]	42	1			T25	1		T47	1		T36	2
auto[2147483648:2281701375]	auto[1]	45	1			T25	1		T115	1		T47	1
auto[2281701376:2415919103]	auto[0]	35	1			T49	1		T47	1		T86	1
auto[2281701376:2415919103]	auto[1]	52	1			T43	1		T255	1		T116	1
auto[2415919104:2550136831]	auto[0]	50	1			T47	2		T116	1		T60	1
auto[2415919104:2550136831]	auto[1]	56	1			T5	1		T25	1		T130	1
auto[2550136832:2684354559]	auto[0]	46	1			T25	2		T134	1		T60	1
auto[2550136832:2684354559]	auto[1]	38	1			T25	1		T102	1		T201	1
auto[2684354560:2818572287]	auto[0]	55	1			T25	1		T47	1		T53	1
auto[2684354560:2818572287]	auto[1]	45	1			T40	1		T47	2		T86	1
auto[2818572288:2952790015]	auto[0]	50	1			T16	1		T25	1		T44	1
auto[2818572288:2952790015]	auto[1]	53	1			T25	2		T131	1		T148	3
auto[2952790016:3087007743]	auto[0]	43	1			T47	1		T50	1		T41	1
auto[2952790016:3087007743]	auto[1]	57	1			T25	1		T131	1		T47	2
auto[3087007744:3221225471]	auto[0]	54	1			T43	1		T25	2		T130	1
auto[3087007744:3221225471]	auto[1]	50	1			T40	1		T43	1		T130	1
auto[3221225472:3355443199]	auto[0]	51	1			T25	2		T47	1		T432	1
auto[3221225472:3355443199]	auto[1]	44	1			T16	1		T23	1		T25	2
auto[3355443200:3489660927]	auto[0]	53	1			T147	1		T36	1		T195	2
auto[3355443200:3489660927]	auto[1]	52	1			T25	1		T44	1		T47	2
auto[3489660928:3623878655]	auto[0]	49	1			T4	1		T219	1		T47	1
auto[3489660928:3623878655]	auto[1]	40	1			T4	1		T47	1		T255	1
auto[3623878656:3758096383]	auto[0]	44	1			T39	1		T130	1		T47	3
auto[3623878656:3758096383]	auto[1]	55	1			T5	1		T25	2		T201	2
auto[3758096384:3892314111]	auto[0]	40	1			T25	2		T130	1		T53	1
auto[3758096384:3892314111]	auto[1]	47	1			T148	1		T47	2		T225	1
auto[3892314112:4026531839]	auto[0]	53	1			T25	4		T47	1		T36	1
auto[3892314112:4026531839]	auto[1]	68	1			T43	1		T25	1		T131	1
auto[4026531840:4160749567]	auto[0]	63	1			T192	1		T102	1		T201	1
auto[4026531840:4160749567]	auto[1]	45	1			T49	1		T36	1		T7	1
auto[4160749568:4294967295]	auto[0]	47	1			T25	3		T201	1		T47	1
auto[4160749568:4294967295]	auto[1]	52	1			T5	1		T24	1		T192	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1533

1

T4

3

T16

1

T23

1

auto[1]

1573

1

T4

2

T6

2

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	86	1			T148	2		T47	1		T255	1
auto[134217728:268435455]	69	1			T43	1		T25	1		T201	1
auto[268435456:402653183]	90	1			T16	1		T192	1		T25	1
auto[402653184:536870911]	96	1			T40	1		T25	2		T47	1
auto[536870912:671088639]	95	1			T6	1		T25	1		T148	1
auto[671088640:805306367]	98	1			T39	1		T49	2		T43	1
auto[805306368:939524095]	97	1			T16	1		T192	1		T25	2
auto[939524096:1073741823]	87	1			T43	1		T25	4		T47	3
auto[1073741824:1207959551]	95	1			T24	1		T43	1		T130	1
auto[1207959552:1342177279]	116	1			T101	1		T43	2		T44	1
auto[1342177280:1476395007]	85	1			T201	1		T47	2		T116	1
auto[1476395008:1610612735]	92	1			T25	1		T102	1		T115	1
auto[1610612736:1744830463]	76	1			T5	1		T192	1		T25	1
auto[1744830464:1879048191]	92	1			T16	1		T39	1		T25	3
auto[1879048192:2013265919]	108	1			T49	1		T43	1		T25	1
auto[2013265920:2147483647]	91	1			T101	1		T192	1		T25	1
auto[2147483648:2281701375]	124	1			T5	1		T23	1		T24	1
auto[2281701376:2415919103]	84	1			T4	1		T25	1		T219	1
auto[2415919104:2550136831]	85	1			T4	1		T40	1		T25	2
auto[2550136832:2684354559]	106	1			T39	1		T40	1		T25	3
auto[2684354560:2818572287]	89	1			T25	1		T131	1		T47	1
auto[2818572288:2952790015]	98	1			T4	1		T40	1		T25	1
auto[2952790016:3087007743]	110	1			T4	1		T6	1		T25	1
auto[3087007744:3221225471]	89	1			T25	5		T130	2		T201	1
auto[3221225472:3355443199]	111	1			T39	1		T43	4		T25	2
auto[3355443200:3489660927]	116	1			T25	2		T44	1		T21	1
auto[3489660928:3623878655]	99	1			T43	1		T131	2		T47	2
auto[3623878656:3758096383]	123	1			T4	1		T25	1		T130	1
auto[3758096384:3892314111]	92	1			T5	1		T23	1		T40	1
auto[3892314112:4026531839]	92	1			T25	2		T130	1		T201	1
auto[4026531840:4160749567]	102	1			T23	1		T192	2		T25	2
auto[4160749568:4294967295]	113	1			T192	1		T25	3		T102	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T42	1		T245	1		T216	1
auto[0:134217727]	auto[1]	48	1			T148	2		T47	1		T255	1
auto[134217728:268435455]	auto[0]	33	1			T43	1		T25	1		T47	1
auto[134217728:268435455]	auto[1]	36	1			T201	1		T86	1		T60	1
auto[268435456:402653183]	auto[0]	46	1			T192	1		T201	1		T47	1
auto[268435456:402653183]	auto[1]	44	1			T16	1		T25	1		T47	3
auto[402653184:536870911]	auto[0]	51	1			T25	1		T47	1		T116	1
auto[402653184:536870911]	auto[1]	45	1			T40	1		T25	1		T53	1
auto[536870912:671088639]	auto[0]	44	1			T25	1		T209	1		T87	1
auto[536870912:671088639]	auto[1]	51	1			T6	1		T148	1		T220	1
auto[671088640:805306367]	auto[0]	38	1			T49	1		T66	1		T10	1
auto[671088640:805306367]	auto[1]	60	1			T39	1		T49	1		T43	1
auto[805306368:939524095]	auto[0]	50	1			T25	1		T130	1		T219	1
auto[805306368:939524095]	auto[1]	47	1			T16	1		T192	1		T25	1
auto[939524096:1073741823]	auto[0]	44	1			T25	1		T47	1		T136	1
auto[939524096:1073741823]	auto[1]	43	1			T43	1		T25	3		T47	2
auto[1073741824:1207959551]	auto[0]	43	1			T47	1		T396	1		T347	1
auto[1073741824:1207959551]	auto[1]	52	1			T24	1		T43	1		T130	1
auto[1207959552:1342177279]	auto[0]	58	1			T101	1		T43	1		T44	1
auto[1207959552:1342177279]	auto[1]	58	1			T43	1		T255	1		T86	1
auto[1342177280:1476395007]	auto[0]	42	1			T47	1		T99	1		T249	1
auto[1342177280:1476395007]	auto[1]	43	1			T201	1		T47	1		T116	1
auto[1476395008:1610612735]	auto[0]	45	1			T102	1		T47	1		T21	1
auto[1476395008:1610612735]	auto[1]	47	1			T25	1		T115	1		T44	1
auto[1610612736:1744830463]	auto[0]	38	1			T25	1		T147	1		T36	1
auto[1610612736:1744830463]	auto[1]	38	1			T5	1		T192	1		T148	1
auto[1744830464:1879048191]	auto[0]	52	1			T16	1		T25	3		T47	2
auto[1744830464:1879048191]	auto[1]	40	1			T39	1		T130	1		T148	1
auto[1879048192:2013265919]	auto[0]	44	1			T49	1		T7	1		T195	1
auto[1879048192:2013265919]	auto[1]	64	1			T43	1		T25	1		T47	1
auto[2013265920:2147483647]	auto[0]	44	1			T101	1		T192	1		T47	1
auto[2013265920:2147483647]	auto[1]	47	1			T25	1		T131	1		T201	1
auto[2147483648:2281701375]	auto[0]	67	1			T43	2		T25	1		T130	1
auto[2147483648:2281701375]	auto[1]	57	1			T5	1		T23	1		T24	1
auto[2281701376:2415919103]	auto[0]	51	1			T219	1		T21	1		T220	1
auto[2281701376:2415919103]	auto[1]	33	1			T4	1		T25	1		T47	1
auto[2415919104:2550136831]	auto[0]	42	1			T4	1		T25	1		T432	1
auto[2415919104:2550136831]	auto[1]	43	1			T40	1		T25	1		T403	1
auto[2550136832:2684354559]	auto[0]	53	1			T39	1		T40	1		T25	3
auto[2550136832:2684354559]	auto[1]	53	1			T47	2		T255	1		T116	1
auto[2684354560:2818572287]	auto[0]	44	1			T131	1		T48	1		T255	1
auto[2684354560:2818572287]	auto[1]	45	1			T25	1		T47	1		T195	1
auto[2818572288:2952790015]	auto[0]	50	1			T4	1		T25	1		T131	1
auto[2818572288:2952790015]	auto[1]	48	1			T40	1		T44	1		T47	2
auto[2952790016:3087007743]	auto[0]	54	1			T4	1		T25	1		T102	1
auto[2952790016:3087007743]	auto[1]	56	1			T6	1		T47	1		T19	1
auto[3087007744:3221225471]	auto[0]	61	1			T25	4		T130	1		T201	1
auto[3087007744:3221225471]	auto[1]	28	1			T25	1		T130	1		T47	1
auto[3221225472:3355443199]	auto[0]	57	1			T43	1		T25	1		T102	1
auto[3221225472:3355443199]	auto[1]	54	1			T39	1		T43	3		T25	1
auto[3355443200:3489660927]	auto[0]	60	1			T25	1		T21	1		T63	1
auto[3355443200:3489660927]	auto[1]	56	1			T25	1		T44	1		T19	1
auto[3489660928:3623878655]	auto[0]	43	1			T131	1		T47	1		T48	1
auto[3489660928:3623878655]	auto[1]	56	1			T43	1		T131	1		T47	1
auto[3623878656:3758096383]	auto[0]	55	1			T25	1		T44	1		T47	2
auto[3623878656:3758096383]	auto[1]	68	1			T4	1		T130	1		T134	1
auto[3758096384:3892314111]	auto[0]	44	1			T47	1		T21	1		T36	1
auto[3758096384:3892314111]	auto[1]	48	1			T5	1		T23	1		T40	1
auto[3892314112:4026531839]	auto[0]	40	1			T130	1		T201	1		T52	1
auto[3892314112:4026531839]	auto[1]	52	1			T25	2		T47	1		T63	1
auto[4026531840:4160749567]	auto[0]	47	1			T23	1		T192	2		T47	2
auto[4026531840:4160749567]	auto[1]	55	1			T25	2		T130	1		T47	1
auto[4160749568:4294967295]	auto[0]	55	1			T25	2		T80	1		T272	1
auto[4160749568:4294967295]	auto[1]	58	1			T192	1		T25	1		T102	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1509

1

T4

3

T16

1

T23

2

auto[1]

1604

1

T4

2

T6

2

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T25	1		T130	1		T44	1
auto[134217728:268435455]	106	1			T24	1		T192	1		T25	3
auto[268435456:402653183]	104	1			T4	1		T25	1		T102	1
auto[402653184:536870911]	89	1			T5	2		T43	1		T25	1
auto[536870912:671088639]	113	1			T16	1		T49	1		T43	1
auto[671088640:805306367]	112	1			T23	1		T43	1		T25	1
auto[805306368:939524095]	68	1			T23	1		T39	1		T25	1
auto[939524096:1073741823]	98	1			T43	1		T25	2		T130	1
auto[1073741824:1207959551]	82	1			T25	3		T47	1		T199	1
auto[1207959552:1342177279]	85	1			T25	1		T131	1		T47	2
auto[1342177280:1476395007]	110	1			T43	1		T102	1		T47	1
auto[1476395008:1610612735]	96	1			T192	1		T25	1		T219	1
auto[1610612736:1744830463]	93	1			T192	1		T43	1		T25	2
auto[1744830464:1879048191]	109	1			T25	1		T130	1		T201	1
auto[1879048192:2013265919]	88	1			T101	1		T49	1		T25	1
auto[2013265920:2147483647]	93	1			T4	1		T25	1		T44	1
auto[2147483648:2281701375]	97	1			T43	1		T25	4		T130	2
auto[2281701376:2415919103]	107	1			T25	2		T44	1		T47	1
auto[2415919104:2550136831]	100	1			T6	1		T5	1		T40	1
auto[2550136832:2684354559]	90	1			T4	1		T192	1		T25	3
auto[2684354560:2818572287]	111	1			T39	1		T40	2		T25	3
auto[2818572288:2952790015]	98	1			T47	1		T19	1		T52	2
auto[2952790016:3087007743]	100	1			T6	1		T43	1		T25	1
auto[3087007744:3221225471]	94	1			T4	1		T43	2		T131	1
auto[3221225472:3355443199]	101	1			T16	1		T39	1		T25	2
auto[3355443200:3489660927]	94	1			T43	1		T25	1		T115	1
auto[3489660928:3623878655]	99	1			T4	1		T24	1		T43	1
auto[3623878656:3758096383]	87	1			T40	1		T49	1		T192	1
auto[3758096384:3892314111]	99	1			T39	1		T25	1		T130	1
auto[3892314112:4026531839]	94	1			T23	1		T25	1		T47	2
auto[4026531840:4160749567]	95	1			T101	1		T192	1		T102	1
auto[4160749568:4294967295]	104	1			T40	1		T43	1		T25	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T25	1		T130	1		T148	1
auto[0:134217727]	auto[1]	43	1			T44	1		T60	1		T84	1
auto[134217728:268435455]	auto[0]	57	1			T192	1		T25	2		T131	1
auto[134217728:268435455]	auto[1]	49	1			T24	1		T25	1		T195	1
auto[268435456:402653183]	auto[0]	56	1			T4	1		T201	1		T47	1
auto[268435456:402653183]	auto[1]	48	1			T25	1		T102	1		T255	1
auto[402653184:536870911]	auto[0]	44	1			T25	1		T47	1		T432	1
auto[402653184:536870911]	auto[1]	45	1			T5	2		T43	1		T47	1
auto[536870912:671088639]	auto[0]	44	1			T130	1		T219	1		T191	1
auto[536870912:671088639]	auto[1]	69	1			T16	1		T49	1		T43	1
auto[671088640:805306367]	auto[0]	52	1			T47	1		T48	1		T53	2
auto[671088640:805306367]	auto[1]	60	1			T23	1		T43	1		T25	1
auto[805306368:939524095]	auto[0]	35	1			T23	1		T25	1		T47	2
auto[805306368:939524095]	auto[1]	33	1			T39	1		T47	1		T22	1
auto[939524096:1073741823]	auto[0]	45	1			T25	2		T130	1		T47	1
auto[939524096:1073741823]	auto[1]	53	1			T43	1		T47	3		T36	1
auto[1073741824:1207959551]	auto[0]	42	1			T25	1		T53	1		T22	1
auto[1073741824:1207959551]	auto[1]	40	1			T25	2		T47	1		T199	1
auto[1207959552:1342177279]	auto[0]	47	1			T131	1		T47	1		T256	1
auto[1207959552:1342177279]	auto[1]	38	1			T25	1		T47	1		T52	1
auto[1342177280:1476395007]	auto[0]	46	1			T102	1		T63	1		T53	1
auto[1342177280:1476395007]	auto[1]	64	1			T43	1		T47	1		T116	1
auto[1476395008:1610612735]	auto[0]	44	1			T25	1		T47	1		T136	1
auto[1476395008:1610612735]	auto[1]	52	1			T192	1		T219	1		T47	3
auto[1610612736:1744830463]	auto[0]	47	1			T25	1		T48	1		T248	1
auto[1610612736:1744830463]	auto[1]	46	1			T192	1		T43	1		T25	1
auto[1744830464:1879048191]	auto[0]	59	1			T25	1		T201	1		T21	1
auto[1744830464:1879048191]	auto[1]	50	1			T130	1		T47	1		T134	1
auto[1879048192:2013265919]	auto[0]	36	1			T47	1		T36	1		T221	1
auto[1879048192:2013265919]	auto[1]	52	1			T101	1		T49	1		T25	1
auto[2013265920:2147483647]	auto[0]	44	1			T25	1		T44	1		T148	1
auto[2013265920:2147483647]	auto[1]	49	1			T4	1		T148	1		T255	1
auto[2147483648:2281701375]	auto[0]	50	1			T25	3		T130	1		T47	2
auto[2147483648:2281701375]	auto[1]	47	1			T43	1		T25	1		T130	1
auto[2281701376:2415919103]	auto[0]	53	1			T25	1		T21	1		T53	1
auto[2281701376:2415919103]	auto[1]	54	1			T25	1		T44	1		T47	1
auto[2415919104:2550136831]	auto[0]	42	1			T192	1		T130	1		T201	1
auto[2415919104:2550136831]	auto[1]	58	1			T6	1		T5	1		T40	1
auto[2550136832:2684354559]	auto[0]	39	1			T4	1		T25	1		T201	1
auto[2550136832:2684354559]	auto[1]	51	1			T192	1		T25	2		T130	1
auto[2684354560:2818572287]	auto[0]	55	1			T25	1		T130	1		T47	2
auto[2684354560:2818572287]	auto[1]	56	1			T39	1		T40	2		T25	2
auto[2818572288:2952790015]	auto[0]	48	1			T47	1		T19	1		T60	1
auto[2818572288:2952790015]	auto[1]	50	1			T52	2		T242	1		T195	1
auto[2952790016:3087007743]	auto[0]	43	1			T21	1		T195	1		T88	2
auto[2952790016:3087007743]	auto[1]	57	1			T6	1		T43	1		T25	1
auto[3087007744:3221225471]	auto[0]	46	1			T4	1		T43	1		T47	2
auto[3087007744:3221225471]	auto[1]	48	1			T43	1		T131	1		T47	1
auto[3221225472:3355443199]	auto[0]	50	1			T16	1		T39	1		T25	1
auto[3221225472:3355443199]	auto[1]	51	1			T25	1		T86	1		T243	1
auto[3355443200:3489660927]	auto[0]	48	1			T43	1		T277	1		T97	1
auto[3355443200:3489660927]	auto[1]	46	1			T25	1		T115	1		T48	1
auto[3489660928:3623878655]	auto[0]	51	1			T43	1		T36	1		T396	1
auto[3489660928:3623878655]	auto[1]	48	1			T4	1		T24	1		T25	4
auto[3623878656:3758096383]	auto[0]	40	1			T49	1		T43	1		T147	1
auto[3623878656:3758096383]	auto[1]	47	1			T40	1		T192	1		T25	1
auto[3758096384:3892314111]	auto[0]	52	1			T25	1		T219	1		T47	3
auto[3758096384:3892314111]	auto[1]	47	1			T39	1		T130	1		T47	2
auto[3892314112:4026531839]	auto[0]	47	1			T23	1		T25	1		T47	2
auto[3892314112:4026531839]	auto[1]	47	1			T418	1		T190	1		T50	2
auto[4026531840:4160749567]	auto[0]	44	1			T101	1		T192	1		T47	1
auto[4026531840:4160749567]	auto[1]	51	1			T102	1		T47	1		T262	2
auto[4160749568:4294967295]	auto[0]	49	1			T40	1		T25	1		T131	1
auto[4160749568:4294967295]	auto[1]	55	1			T43	1		T134	1		T135	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1534

1

T4

2

T16

1

T23

2

auto[1]

1577

1

T4

3

T6

2

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	80	1			T25	1		T130	1		T201	1
auto[134217728:268435455]	96	1			T25	2		T102	1		T148	1
auto[268435456:402653183]	94	1			T192	1		T43	1		T25	2
auto[402653184:536870911]	94	1			T16	1		T23	1		T43	1
auto[536870912:671088639]	103	1			T4	1		T25	1		T102	1
auto[671088640:805306367]	101	1			T25	1		T148	1		T201	1
auto[805306368:939524095]	102	1			T43	1		T25	1		T130	1
auto[939524096:1073741823]	99	1			T4	1		T6	1		T24	1
auto[1073741824:1207959551]	101	1			T6	1		T39	1		T25	1
auto[1207959552:1342177279]	99	1			T39	1		T43	2		T25	2
auto[1342177280:1476395007]	102	1			T25	2		T47	1		T48	1
auto[1476395008:1610612735]	96	1			T43	1		T25	1		T131	1
auto[1610612736:1744830463]	97	1			T43	2		T25	1		T130	1
auto[1744830464:1879048191]	80	1			T23	1		T40	1		T25	2
auto[1879048192:2013265919]	99	1			T40	1		T130	1		T47	5
auto[2013265920:2147483647]	99	1			T16	1		T39	1		T40	1
auto[2147483648:2281701375]	103	1			T5	1		T23	1		T25	3
auto[2281701376:2415919103]	101	1			T43	1		T219	1		T47	3
auto[2415919104:2550136831]	100	1			T4	1		T40	1		T25	2
auto[2550136832:2684354559]	95	1			T4	1		T40	1		T25	1
auto[2684354560:2818572287]	94	1			T5	1		T192	1		T43	1
auto[2818572288:2952790015]	107	1			T101	1		T192	1		T43	1
auto[2952790016:3087007743]	88	1			T49	1		T130	1		T195	1
auto[3087007744:3221225471]	105	1			T5	1		T49	2		T192	1
auto[3221225472:3355443199]	105	1			T24	1		T25	5		T130	2
auto[3355443200:3489660927]	112	1			T192	2		T25	1		T130	1
auto[3489660928:3623878655]	100	1			T25	2		T115	1		T116	1
auto[3623878656:3758096383]	101	1			T39	1		T25	1		T44	1
auto[3758096384:3892314111]	105	1			T4	1		T43	1		T25	1
auto[3892314112:4026531839]	99	1			T101	1		T102	1		T44	1
auto[4026531840:4160749567]	87	1			T25	2		T131	1		T219	1
auto[4160749568:4294967295]	67	1			T43	1		T25	1		T44	1