Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2692

1

T4

5

T5

3

T16

2

auto[1]

281

1

T4

7

T130

5

T147

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	73	1			T5	1		T192	1		T25	2
auto[134217728:268435455]	85	1			T130	2		T147	1		T47	2
auto[268435456:402653183]	91	1			T43	2		T25	1		T130	1
auto[402653184:536870911]	94	1			T4	1		T23	1		T39	1
auto[536870912:671088639]	80	1			T4	1		T23	1		T43	1
auto[671088640:805306367]	100	1			T25	1		T102	1		T147	1
auto[805306368:939524095]	73	1			T130	1		T44	1		T147	1
auto[939524096:1073741823]	94	1			T4	2		T40	1		T25	1
auto[1073741824:1207959551]	91	1			T4	1		T39	1		T40	1
auto[1207959552:1342177279]	88	1			T192	2		T25	2		T130	1
auto[1342177280:1476395007]	100	1			T49	1		T192	1		T25	3
auto[1476395008:1610612735]	94	1			T39	1		T25	1		T47	2
auto[1610612736:1744830463]	97	1			T39	1		T43	1		T47	1
auto[1744830464:1879048191]	105	1			T4	1		T23	1		T49	1
auto[1879048192:2013265919]	81	1			T4	1		T25	2		T47	3
auto[2013265920:2147483647]	96	1			T25	2		T131	1		T102	1
auto[2147483648:2281701375]	103	1			T47	1		T21	1		T36	2
auto[2281701376:2415919103]	97	1			T192	1		T43	1		T25	3
auto[2415919104:2550136831]	100	1			T43	1		T25	1		T44	1
auto[2550136832:2684354559]	88	1			T130	2		T102	1		T47	1
auto[2684354560:2818572287]	102	1			T25	2		T130	2		T148	1
auto[2818572288:2952790015]	98	1			T40	1		T43	2		T130	1
auto[2952790016:3087007743]	94	1			T4	1		T16	1		T40	1
auto[3087007744:3221225471]	98	1			T40	1		T101	1		T192	1
auto[3221225472:3355443199]	102	1			T25	2		T147	1		T135	1
auto[3355443200:3489660927]	95	1			T4	1		T43	1		T25	1
auto[3489660928:3623878655]	96	1			T5	1		T25	1		T148	1
auto[3623878656:3758096383]	100	1			T24	1		T43	1		T25	1
auto[3758096384:3892314111]	105	1			T4	1		T192	1		T43	1
auto[3892314112:4026531839]	91	1			T4	1		T101	1		T130	1
auto[4026531840:4160749567]	81	1			T4	1		T25	1		T130	2
auto[4160749568:4294967295]	81	1			T5	1		T16	1		T25	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	69	1			T5	1		T192	1		T25	2
auto[0:134217727]	auto[1]	4	1			T272	1		T107	1		T437	1
auto[134217728:268435455]	auto[0]	77	1			T47	2		T53	1		T195	1
auto[134217728:268435455]	auto[1]	8	1			T130	2		T147	1		T200	1
auto[268435456:402653183]	auto[0]	76	1			T43	2		T25	1		T130	1
auto[268435456:402653183]	auto[1]	15	1			T148	1		T134	1		T135	2
auto[402653184:536870911]	auto[0]	88	1			T23	1		T39	1		T25	1
auto[402653184:536870911]	auto[1]	6	1			T4	1		T136	1		T277	1
auto[536870912:671088639]	auto[0]	72	1			T23	1		T43	1		T25	2
auto[536870912:671088639]	auto[1]	8	1			T4	1		T427	1		T333	2
auto[671088640:805306367]	auto[0]	87	1			T25	1		T102	1		T47	1
auto[671088640:805306367]	auto[1]	13	1			T147	1		T136	1		T277	1
auto[805306368:939524095]	auto[0]	63	1			T44	1		T147	1		T255	1
auto[805306368:939524095]	auto[1]	10	1			T130	1		T136	1		T393	1
auto[939524096:1073741823]	auto[0]	85	1			T40	1		T25	1		T131	1
auto[939524096:1073741823]	auto[1]	9	1			T4	2		T248	1		T107	1
auto[1073741824:1207959551]	auto[0]	80	1			T4	1		T39	1		T40	1
auto[1073741824:1207959551]	auto[1]	11	1			T247	1		T390	1		T240	2
auto[1207959552:1342177279]	auto[0]	79	1			T192	2		T25	2		T130	1
auto[1207959552:1342177279]	auto[1]	9	1			T134	1		T395	1		T438	1
auto[1342177280:1476395007]	auto[0]	90	1			T49	1		T192	1		T25	3
auto[1342177280:1476395007]	auto[1]	10	1			T239	1		T395	1		T300	1
auto[1476395008:1610612735]	auto[0]	87	1			T39	1		T25	1		T47	2
auto[1476395008:1610612735]	auto[1]	7	1			T247	1		T248	1		T239	1
auto[1610612736:1744830463]	auto[0]	87	1			T39	1		T43	1		T47	1
auto[1610612736:1744830463]	auto[1]	10	1			T247	1		T248	1		T393	2
auto[1744830464:1879048191]	auto[0]	99	1			T4	1		T23	1		T49	1
auto[1744830464:1879048191]	auto[1]	6	1			T148	1		T200	1		T305	1
auto[1879048192:2013265919]	auto[0]	77	1			T4	1		T25	2		T47	3
auto[1879048192:2013265919]	auto[1]	4	1			T272	2		T200	1		T248	1
auto[2013265920:2147483647]	auto[0]	89	1			T25	2		T131	1		T102	1
auto[2013265920:2147483647]	auto[1]	7	1			T148	1		T134	1		T305	1
auto[2147483648:2281701375]	auto[0]	91	1			T47	1		T21	1		T36	2
auto[2147483648:2281701375]	auto[1]	12	1			T135	1		T305	1		T377	1
auto[2281701376:2415919103]	auto[0]	91	1			T192	1		T43	1		T25	3
auto[2281701376:2415919103]	auto[1]	6	1			T148	1		T371	1		T429	1
auto[2415919104:2550136831]	auto[0]	89	1			T43	1		T25	1		T44	1
auto[2415919104:2550136831]	auto[1]	11	1			T147	1		T393	1		T330	1
auto[2550136832:2684354559]	auto[0]	80	1			T102	1		T47	1		T248	1
auto[2550136832:2684354559]	auto[1]	8	1			T130	2		T289	1		T427	1
auto[2684354560:2818572287]	auto[0]	95	1			T25	2		T130	2		T148	1
auto[2684354560:2818572287]	auto[1]	7	1			T134	1		T272	1		T334	1
auto[2818572288:2952790015]	auto[0]	86	1			T40	1		T43	2		T130	1
auto[2818572288:2952790015]	auto[1]	12	1			T148	2		T305	1		T425	3
auto[2952790016:3087007743]	auto[0]	86	1			T16	1		T40	1		T25	1
auto[2952790016:3087007743]	auto[1]	8	1			T4	1		T200	1		T248	1
auto[3087007744:3221225471]	auto[0]	94	1			T40	1		T101	1		T192	1
auto[3087007744:3221225471]	auto[1]	4	1			T135	1		T272	1		T333	1
auto[3221225472:3355443199]	auto[0]	91	1			T25	2		T195	1		T220	1
auto[3221225472:3355443199]	auto[1]	11	1			T147	1		T135	1		T200	1
auto[3355443200:3489660927]	auto[0]	84	1			T4	1		T43	1		T25	1
auto[3355443200:3489660927]	auto[1]	11	1			T277	1		T239	1		T395	1
auto[3489660928:3623878655]	auto[0]	85	1			T5	1		T25	1		T47	3
auto[3489660928:3623878655]	auto[1]	11	1			T148	1		T247	1		T135	1
auto[3623878656:3758096383]	auto[0]	91	1			T24	1		T43	1		T25	1
auto[3623878656:3758096383]	auto[1]	9	1			T239	1		T300	1		T359	1
auto[3758096384:3892314111]	auto[0]	95	1			T192	1		T43	1		T219	1
auto[3758096384:3892314111]	auto[1]	10	1			T4	1		T277	1		T248	1
auto[3892314112:4026531839]	auto[0]	82	1			T101	1		T130	1		T148	1
auto[3892314112:4026531839]	auto[1]	9	1			T4	1		T277	1		T107	1
auto[4026531840:4160749567]	auto[0]	76	1			T4	1		T25	1		T130	2
auto[4026531840:4160749567]	auto[1]	5	1			T247	1		T277	1		T428	1
auto[4160749568:4294967295]	auto[0]	71	1			T5	1		T16	1		T25	1
auto[4160749568:4294967295]	auto[1]	10	1			T239	1		T273	1		T425	1