Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6184

1

T4

11

T5

12

T16

3

auto[1]

286

1

T4

5

T147

6

T148

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2607	1			T4	5		T5	6		T16	1
auto[134217728:268435455]	173	1			T5	1		T23	1		T39	1
auto[268435456:402653183]	141	1			T5	1		T23	1		T40	1
auto[402653184:536870911]	132	1			T43	1		T25	3		T131	1
auto[536870912:671088639]	112	1			T4	1		T43	2		T25	1
auto[671088640:805306367]	139	1			T23	1		T40	1		T192	2
auto[805306368:939524095]	120	1			T101	1		T25	3		T44	1
auto[939524096:1073741823]	131	1			T5	1		T25	1		T148	1
auto[1073741824:1207959551]	113	1			T4	2		T192	1		T43	1
auto[1207959552:1342177279]	125	1			T16	1		T43	1		T130	3
auto[1342177280:1476395007]	124	1			T39	1		T43	1		T25	1
auto[1476395008:1610612735]	125	1			T4	1		T43	1		T130	2
auto[1610612736:1744830463]	122	1			T4	1		T192	1		T25	3
auto[1744830464:1879048191]	125	1			T5	1		T25	2		T44	1
auto[1879048192:2013265919]	121	1			T192	1		T43	1		T25	2
auto[2013265920:2147483647]	115	1			T25	3		T131	1		T44	1
auto[2147483648:2281701375]	138	1			T5	2		T23	1		T25	1
auto[2281701376:2415919103]	101	1			T4	1		T25	1		T131	1
auto[2415919104:2550136831]	138	1			T25	3		T147	1		T47	3
auto[2550136832:2684354559]	121	1			T4	1		T24	1		T130	1
auto[2684354560:2818572287]	119	1			T43	1		T25	3		T148	1
auto[2818572288:2952790015]	119	1			T43	1		T25	1		T102	1
auto[2952790016:3087007743]	105	1			T192	1		T43	1		T25	3
auto[3087007744:3221225471]	119	1			T201	3		T47	4		T134	2
auto[3221225472:3355443199]	125	1			T147	1		T148	3		T201	1
auto[3355443200:3489660927]	135	1			T4	1		T25	1		T147	1
auto[3489660928:3623878655]	132	1			T25	4		T147	1		T148	1
auto[3623878656:3758096383]	124	1			T4	3		T39	1		T43	2
auto[3758096384:3892314111]	121	1			T39	1		T101	1		T25	5
auto[3892314112:4026531839]	123	1			T40	1		T101	1		T192	1
auto[4026531840:4160749567]	111	1			T16	1		T25	1		T131	1
auto[4160749568:4294967295]	114	1			T40	1		T49	1		T25	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2596	1			T4	5		T5	6		T16	1
auto[0:134217727]	auto[1]	11	1			T134	1		T107	1		T305	1
auto[134217728:268435455]	auto[0]	162	1			T5	1		T23	1		T39	1
auto[134217728:268435455]	auto[1]	11	1			T147	1		T134	1		T247	1
auto[268435456:402653183]	auto[0]	132	1			T5	1		T23	1		T40	1
auto[268435456:402653183]	auto[1]	9	1			T272	1		T377	1		T426	1
auto[402653184:536870911]	auto[0]	117	1			T43	1		T25	3		T131	1
auto[402653184:536870911]	auto[1]	15	1			T136	1		T200	2		T248	1
auto[536870912:671088639]	auto[0]	110	1			T4	1		T43	2		T25	1
auto[536870912:671088639]	auto[1]	2	1			T248	1		T429	1		-	-
auto[671088640:805306367]	auto[0]	131	1			T23	1		T40	1		T192	2
auto[671088640:805306367]	auto[1]	8	1			T147	1		T148	1		T134	1
auto[805306368:939524095]	auto[0]	111	1			T101	1		T25	3		T44	1
auto[805306368:939524095]	auto[1]	9	1			T277	1		T393	1		T107	1
auto[939524096:1073741823]	auto[0]	123	1			T5	1		T25	1		T148	1
auto[939524096:1073741823]	auto[1]	8	1			T248	1		T359	1		T333	2
auto[1073741824:1207959551]	auto[0]	104	1			T4	1		T192	1		T43	1
auto[1073741824:1207959551]	auto[1]	9	1			T4	1		T134	1		T107	1
auto[1207959552:1342177279]	auto[0]	115	1			T16	1		T43	1		T130	3
auto[1207959552:1342177279]	auto[1]	10	1			T134	2		T135	1		T272	1
auto[1342177280:1476395007]	auto[0]	117	1			T39	1		T43	1		T25	1
auto[1342177280:1476395007]	auto[1]	7	1			T277	2		T248	1		T107	1
auto[1476395008:1610612735]	auto[0]	117	1			T4	1		T43	1		T130	2
auto[1476395008:1610612735]	auto[1]	8	1			T393	1		T305	1		T430	1
auto[1610612736:1744830463]	auto[0]	116	1			T4	1		T192	1		T25	3
auto[1610612736:1744830463]	auto[1]	6	1			T272	1		T200	1		T248	1
auto[1744830464:1879048191]	auto[0]	119	1			T5	1		T25	2		T44	1
auto[1744830464:1879048191]	auto[1]	6	1			T247	1		T429	1		T295	1
auto[1879048192:2013265919]	auto[0]	113	1			T192	1		T43	1		T25	2
auto[1879048192:2013265919]	auto[1]	8	1			T277	1		T425	1		T427	1
auto[2013265920:2147483647]	auto[0]	101	1			T25	3		T131	1		T44	1
auto[2013265920:2147483647]	auto[1]	14	1			T135	1		T272	1		T277	2
auto[2147483648:2281701375]	auto[0]	131	1			T5	2		T23	1		T25	1
auto[2147483648:2281701375]	auto[1]	7	1			T200	1		T377	1		T295	1
auto[2281701376:2415919103]	auto[0]	93	1			T25	1		T131	1		T47	3
auto[2281701376:2415919103]	auto[1]	8	1			T4	1		T272	1		T277	1
auto[2415919104:2550136831]	auto[0]	129	1			T25	3		T147	1		T47	3
auto[2415919104:2550136831]	auto[1]	9	1			T277	1		T248	2		T239	1
auto[2550136832:2684354559]	auto[0]	118	1			T4	1		T24	1		T130	1
auto[2550136832:2684354559]	auto[1]	3	1			T239	1		T266	1		T433	1
auto[2684354560:2818572287]	auto[0]	109	1			T43	1		T25	3		T47	4
auto[2684354560:2818572287]	auto[1]	10	1			T148	1		T272	2		T200	1
auto[2818572288:2952790015]	auto[0]	108	1			T43	1		T25	1		T102	1
auto[2818572288:2952790015]	auto[1]	11	1			T107	1		T371	1		T359	1
auto[2952790016:3087007743]	auto[0]	93	1			T192	1		T43	1		T25	3
auto[2952790016:3087007743]	auto[1]	12	1			T134	1		T135	1		T136	2
auto[3087007744:3221225471]	auto[0]	111	1			T201	3		T47	4		T134	1
auto[3087007744:3221225471]	auto[1]	8	1			T134	1		T247	2		T393	1
auto[3221225472:3355443199]	auto[0]	117	1			T148	1		T201	1		T47	6
auto[3221225472:3355443199]	auto[1]	8	1			T147	1		T148	2		T107	1
auto[3355443200:3489660927]	auto[0]	125	1			T25	1		T148	1		T47	4
auto[3355443200:3489660927]	auto[1]	10	1			T4	1		T147	1		T247	3
auto[3489660928:3623878655]	auto[0]	120	1			T25	4		T201	1		T47	3
auto[3489660928:3623878655]	auto[1]	12	1			T147	1		T148	1		T134	1
auto[3623878656:3758096383]	auto[0]	112	1			T4	1		T39	1		T43	2
auto[3623878656:3758096383]	auto[1]	12	1			T4	2		T147	1		T148	1
auto[3758096384:3892314111]	auto[0]	115	1			T39	1		T101	1		T25	5
auto[3758096384:3892314111]	auto[1]	6	1			T393	1		T334	1		T427	2
auto[3892314112:4026531839]	auto[0]	113	1			T40	1		T101	1		T192	1
auto[3892314112:4026531839]	auto[1]	10	1			T134	1		T200	1		T393	1
auto[4026531840:4160749567]	auto[0]	99	1			T16	1		T25	1		T131	1
auto[4026531840:4160749567]	auto[1]	12	1			T148	1		T247	1		T248	1
auto[4160749568:4294967295]	auto[0]	107	1			T40	1		T49	1		T25	2
auto[4160749568:4294967295]	auto[1]	7	1			T390	1		T429	1		T295	1