Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 99.10 97.95 98.37 100.00 99.11 98.41 91.63


Total test records in report: 1079
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T1010 /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.4211106958 Feb 08 01:07:12 PM PST 24 Feb 08 01:07:16 PM PST 24 353153996 ps
T1011 /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1481929215 Feb 08 01:07:10 PM PST 24 Feb 08 01:07:20 PM PST 24 295475149 ps
T1012 /workspace/coverage/default/18.keymgr_direct_to_disabled.919951343 Feb 08 01:06:54 PM PST 24 Feb 08 01:06:57 PM PST 24 123751568 ps
T1013 /workspace/coverage/default/13.keymgr_sideload_otbn.3820481459 Feb 08 01:05:51 PM PST 24 Feb 08 01:06:05 PM PST 24 55493979 ps
T1014 /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1714035958 Feb 08 01:05:15 PM PST 24 Feb 08 01:05:23 PM PST 24 559817585 ps
T1015 /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1058468921 Feb 08 01:05:32 PM PST 24 Feb 08 01:05:37 PM PST 24 120637039 ps
T1016 /workspace/coverage/default/47.keymgr_sideload_kmac.160741938 Feb 08 01:08:57 PM PST 24 Feb 08 01:09:12 PM PST 24 238007407 ps
T1017 /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.370167610 Feb 08 01:06:10 PM PST 24 Feb 08 01:06:20 PM PST 24 85019961 ps
T1018 /workspace/coverage/default/12.keymgr_sideload_protect.249249122 Feb 08 01:05:45 PM PST 24 Feb 08 01:06:09 PM PST 24 6151343299 ps
T1019 /workspace/coverage/default/0.keymgr_sw_invalid_input.2957541479 Feb 08 01:04:00 PM PST 24 Feb 08 01:04:08 PM PST 24 194189964 ps
T1020 /workspace/coverage/default/3.keymgr_sideload_protect.2291820483 Feb 08 01:04:12 PM PST 24 Feb 08 01:05:08 PM PST 24 5927879429 ps
T1021 /workspace/coverage/default/16.keymgr_lc_disable.1582751947 Feb 08 01:06:10 PM PST 24 Feb 08 01:06:18 PM PST 24 42329551 ps
T1022 /workspace/coverage/default/4.keymgr_sideload_otbn.2488453938 Feb 08 01:04:20 PM PST 24 Feb 08 01:04:23 PM PST 24 88232993 ps
T1023 /workspace/coverage/default/21.keymgr_sw_invalid_input.2767305501 Feb 08 01:06:56 PM PST 24 Feb 08 01:07:03 PM PST 24 399335588 ps
T1024 /workspace/coverage/default/5.keymgr_random.4123490986 Feb 08 01:04:47 PM PST 24 Feb 08 01:04:52 PM PST 24 269903989 ps
T1025 /workspace/coverage/default/44.keymgr_alert_test.2539472224 Feb 08 01:09:02 PM PST 24 Feb 08 01:09:08 PM PST 24 21223272 ps
T1026 /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3705022234 Feb 08 01:09:06 PM PST 24 Feb 08 01:09:17 PM PST 24 96343519 ps
T1027 /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2126046963 Feb 08 01:08:58 PM PST 24 Feb 08 01:09:09 PM PST 24 452463881 ps
T1028 /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2990854647 Feb 08 01:06:18 PM PST 24 Feb 08 01:06:24 PM PST 24 76198468 ps
T1029 /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1687253023 Feb 08 01:04:21 PM PST 24 Feb 08 01:04:25 PM PST 24 296059570 ps
T1030 /workspace/coverage/default/49.keymgr_kmac_rsp_err.3482730014 Feb 08 01:09:06 PM PST 24 Feb 08 01:09:17 PM PST 24 259475664 ps
T1031 /workspace/coverage/default/23.keymgr_kmac_rsp_err.190607224 Feb 08 01:07:13 PM PST 24 Feb 08 01:08:26 PM PST 24 4560492931 ps
T1032 /workspace/coverage/default/46.keymgr_smoke.374023468 Feb 08 01:08:51 PM PST 24 Feb 08 01:08:54 PM PST 24 537234268 ps
T1033 /workspace/coverage/default/5.keymgr_sw_invalid_input.4088356406 Feb 08 01:04:46 PM PST 24 Feb 08 01:04:52 PM PST 24 609240358 ps
T1034 /workspace/coverage/default/5.keymgr_sideload.4235019947 Feb 08 01:04:47 PM PST 24 Feb 08 01:04:52 PM PST 24 138006838 ps
T382 /workspace/coverage/default/25.keymgr_stress_all.4072966640 Feb 08 01:07:15 PM PST 24 Feb 08 01:07:55 PM PST 24 1649978902 ps
T1035 /workspace/coverage/default/26.keymgr_sideload_kmac.3366563555 Feb 08 01:07:14 PM PST 24 Feb 08 01:07:20 PM PST 24 442191475 ps
T402 /workspace/coverage/default/13.keymgr_kmac_rsp_err.3378789688 Feb 08 01:05:46 PM PST 24 Feb 08 01:05:59 PM PST 24 175799068 ps
T1036 /workspace/coverage/default/35.keymgr_sideload_protect.536436818 Feb 08 01:08:07 PM PST 24 Feb 08 01:08:26 PM PST 24 1867944644 ps
T1037 /workspace/coverage/default/6.keymgr_direct_to_disabled.3463374214 Feb 08 01:05:14 PM PST 24 Feb 08 01:05:18 PM PST 24 88493175 ps
T1038 /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2412799855 Feb 08 01:07:38 PM PST 24 Feb 08 01:08:01 PM PST 24 3552998844 ps
T1039 /workspace/coverage/default/12.keymgr_hwsw_invalid_input.783346986 Feb 08 01:05:45 PM PST 24 Feb 08 01:05:59 PM PST 24 287887269 ps
T1040 /workspace/coverage/default/17.keymgr_random.363732000 Feb 08 01:06:18 PM PST 24 Feb 08 01:06:25 PM PST 24 208349596 ps
T1041 /workspace/coverage/default/20.keymgr_custom_cm.1602488255 Feb 08 01:06:50 PM PST 24 Feb 08 01:06:58 PM PST 24 86948893 ps
T1042 /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2547259832 Feb 08 01:08:32 PM PST 24 Feb 08 01:08:37 PM PST 24 71178408 ps
T1043 /workspace/coverage/default/12.keymgr_lc_disable.1713451123 Feb 08 01:05:44 PM PST 24 Feb 08 01:05:58 PM PST 24 207215241 ps
T1044 /workspace/coverage/default/11.keymgr_sw_invalid_input.179384049 Feb 08 01:05:46 PM PST 24 Feb 08 01:06:31 PM PST 24 1174560294 ps
T1045 /workspace/coverage/default/13.keymgr_sideload_protect.1885093032 Feb 08 01:05:50 PM PST 24 Feb 08 01:06:03 PM PST 24 92783344 ps
T1046 /workspace/coverage/default/20.keymgr_lc_disable.1193702226 Feb 08 01:06:59 PM PST 24 Feb 08 01:07:07 PM PST 24 658525505 ps
T233 /workspace/coverage/default/19.keymgr_stress_all.4276524950 Feb 08 01:06:56 PM PST 24 Feb 08 01:14:08 PM PST 24 24215603847 ps
T1047 /workspace/coverage/default/39.keymgr_sideload_kmac.2370410708 Feb 08 01:08:30 PM PST 24 Feb 08 01:08:35 PM PST 24 127669249 ps
T1048 /workspace/coverage/default/24.keymgr_direct_to_disabled.1898933041 Feb 08 01:07:10 PM PST 24 Feb 08 01:07:12 PM PST 24 27582715 ps
T1049 /workspace/coverage/default/29.keymgr_sideload_protect.994988658 Feb 08 01:07:35 PM PST 24 Feb 08 01:07:40 PM PST 24 77440463 ps
T1050 /workspace/coverage/default/1.keymgr_stress_all.4153174441 Feb 08 01:03:54 PM PST 24 Feb 08 01:04:42 PM PST 24 1855031416 ps
T1051 /workspace/coverage/default/28.keymgr_random.1609472118 Feb 08 01:07:39 PM PST 24 Feb 08 01:07:45 PM PST 24 109368161 ps
T1052 /workspace/coverage/default/22.keymgr_smoke.3894861642 Feb 08 01:07:00 PM PST 24 Feb 08 01:07:42 PM PST 24 7677925201 ps
T1053 /workspace/coverage/default/12.keymgr_stress_all.856675878 Feb 08 01:05:51 PM PST 24 Feb 08 01:06:05 PM PST 24 250902643 ps
T1054 /workspace/coverage/default/21.keymgr_sideload_kmac.3638426120 Feb 08 01:06:58 PM PST 24 Feb 08 01:07:06 PM PST 24 154945275 ps
T1055 /workspace/coverage/default/28.keymgr_hwsw_invalid_input.4115259095 Feb 08 01:07:42 PM PST 24 Feb 08 01:07:50 PM PST 24 746985564 ps
T1056 /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3959032812 Feb 08 01:03:54 PM PST 24 Feb 08 01:03:57 PM PST 24 56809227 ps
T1057 /workspace/coverage/default/33.keymgr_kmac_rsp_err.3746771860 Feb 08 01:08:02 PM PST 24 Feb 08 01:08:07 PM PST 24 57410996 ps
T1058 /workspace/coverage/default/28.keymgr_custom_cm.2611108924 Feb 08 01:07:32 PM PST 24 Feb 08 01:07:40 PM PST 24 797489739 ps
T1059 /workspace/coverage/default/6.keymgr_hwsw_invalid_input.4233819799 Feb 08 01:05:17 PM PST 24 Feb 08 01:05:24 PM PST 24 203820004 ps
T320 /workspace/coverage/default/43.keymgr_kmac_rsp_err.813699621 Feb 08 01:08:35 PM PST 24 Feb 08 01:08:41 PM PST 24 479224488 ps
T1060 /workspace/coverage/default/48.keymgr_custom_cm.2227076287 Feb 08 01:09:02 PM PST 24 Feb 08 01:09:11 PM PST 24 569118756 ps
T46 /workspace/coverage/default/31.keymgr_stress_all.3193404481 Feb 08 01:07:47 PM PST 24 Feb 08 01:11:00 PM PST 24 38707039796 ps
T1061 /workspace/coverage/default/12.keymgr_kmac_rsp_err.3385301003 Feb 08 01:05:47 PM PST 24 Feb 08 01:05:59 PM PST 24 80802226 ps
T1062 /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.440926927 Feb 08 01:06:06 PM PST 24 Feb 08 01:06:13 PM PST 24 415166843 ps
T227 /workspace/coverage/default/11.keymgr_custom_cm.632585887 Feb 08 01:05:45 PM PST 24 Feb 08 01:06:01 PM PST 24 144813159 ps
T1063 /workspace/coverage/default/24.keymgr_sideload.806565038 Feb 08 01:07:14 PM PST 24 Feb 08 01:07:22 PM PST 24 1063543641 ps
T104 /workspace/coverage/default/4.keymgr_sec_cm.696522 Feb 08 01:04:47 PM PST 24 Feb 08 01:05:14 PM PST 24 3117545459 ps
T149 /workspace/coverage/default/13.keymgr_custom_cm.2230610828 Feb 08 01:05:50 PM PST 24 Feb 08 01:06:06 PM PST 24 109503794 ps
T1064 /workspace/coverage/default/32.keymgr_cfg_regwen.1486306785 Feb 08 01:07:48 PM PST 24 Feb 08 01:07:52 PM PST 24 36633462 ps
T1065 /workspace/coverage/default/21.keymgr_stress_all.118385818 Feb 08 01:07:02 PM PST 24 Feb 08 01:07:15 PM PST 24 1049221961 ps
T1066 /workspace/coverage/default/4.keymgr_sideload_protect.1696015420 Feb 08 01:04:48 PM PST 24 Feb 08 01:04:55 PM PST 24 289753044 ps
T1067 /workspace/coverage/default/10.keymgr_sideload.3396193451 Feb 08 01:05:31 PM PST 24 Feb 08 01:05:35 PM PST 24 64206932 ps
T321 /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3471909795 Feb 08 01:06:07 PM PST 24 Feb 08 01:06:18 PM PST 24 796528271 ps
T1068 /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1287862571 Feb 08 01:04:47 PM PST 24 Feb 08 01:04:50 PM PST 24 235773978 ps
T1069 /workspace/coverage/default/26.keymgr_sideload_protect.1590063723 Feb 08 01:07:19 PM PST 24 Feb 08 01:07:24 PM PST 24 245786212 ps
T1070 /workspace/coverage/default/13.keymgr_sideload_kmac.3645254991 Feb 08 01:05:47 PM PST 24 Feb 08 01:05:58 PM PST 24 352278246 ps
T1071 /workspace/coverage/default/0.keymgr_sideload_otbn.1122616511 Feb 08 01:03:54 PM PST 24 Feb 08 01:03:58 PM PST 24 155305697 ps
T1072 /workspace/coverage/default/24.keymgr_random.1591316838 Feb 08 01:07:10 PM PST 24 Feb 08 01:07:14 PM PST 24 69747024 ps
T1073 /workspace/coverage/default/6.keymgr_stress_all.1955632049 Feb 08 01:05:11 PM PST 24 Feb 08 01:05:44 PM PST 24 1289345067 ps
T1074 /workspace/coverage/default/47.keymgr_direct_to_disabled.1576248425 Feb 08 01:09:00 PM PST 24 Feb 08 01:09:11 PM PST 24 148293709 ps
T1075 /workspace/coverage/default/20.keymgr_sideload_otbn.2396213282 Feb 08 01:06:59 PM PST 24 Feb 08 01:07:06 PM PST 24 172334113 ps
T1076 /workspace/coverage/default/9.keymgr_sw_invalid_input.3153716259 Feb 08 01:05:27 PM PST 24 Feb 08 01:05:35 PM PST 24 160872741 ps
T1077 /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3422899261 Feb 08 01:08:55 PM PST 24 Feb 08 01:08:59 PM PST 24 96328536 ps
T1078 /workspace/coverage/default/9.keymgr_lc_disable.3357182818 Feb 08 01:05:19 PM PST 24 Feb 08 01:05:24 PM PST 24 182317072 ps
T1079 /workspace/coverage/default/44.keymgr_sideload_aes.500421376 Feb 08 01:08:36 PM PST 24 Feb 08 01:08:44 PM PST 24 228846179 ps

Test location /workspace/coverage/default/8.keymgr_custom_cm.3634345834
Short name T3
Test name
Test status
Simulation time 56640286 ps
CPU time 2.91 seconds
Started Feb 08 01:05:25 PM PST 24
Finished Feb 08 01:05:29 PM PST 24
Peak memory 221424 kb
Host smart-35e96563-e5d7-4580-89b6-2b900c930e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634345834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3634345834
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3300138094
Short name T25
Test name
Test status
Simulation time 9410171086 ps
CPU time 305.77 seconds
Started Feb 08 01:05:40 PM PST 24
Finished Feb 08 01:10:47 PM PST 24
Peak memory 222576 kb
Host smart-3c9d95f0-54cf-4854-8961-926da3d9dbb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300138094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3300138094
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1395446122
Short name T47
Test name
Test status
Simulation time 759027861 ps
CPU time 39.15 seconds
Started Feb 08 01:06:07 PM PST 24
Finished Feb 08 01:06:50 PM PST 24
Peak memory 222588 kb
Host smart-29e6e588-72bf-49c6-b9c7-e02784c8890b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395446122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1395446122
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2860193339
Short name T12
Test name
Test status
Simulation time 3531811484 ps
CPU time 39.44 seconds
Started Feb 08 01:06:07 PM PST 24
Finished Feb 08 01:06:51 PM PST 24
Peak memory 235784 kb
Host smart-aa4e51d1-3780-4e8c-ad5e-d3c68dcabaf6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860193339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2860193339
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2852589356
Short name T102
Test name
Test status
Simulation time 885107843 ps
CPU time 9.01 seconds
Started Feb 08 01:05:14 PM PST 24
Finished Feb 08 01:05:24 PM PST 24
Peak memory 222548 kb
Host smart-bedbd3b3-74c6-4124-9821-fbfcd3ff9704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852589356 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2852589356
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3519689888
Short name T4
Test name
Test status
Simulation time 830458989 ps
CPU time 45.87 seconds
Started Feb 08 01:07:32 PM PST 24
Finished Feb 08 01:08:19 PM PST 24
Peak memory 214744 kb
Host smart-357af994-e3f0-4c55-bd84-4af8e1acd66c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519689888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3519689888
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3920804929
Short name T50
Test name
Test status
Simulation time 3320591873 ps
CPU time 22.61 seconds
Started Feb 08 01:07:32 PM PST 24
Finished Feb 08 01:07:55 PM PST 24
Peak memory 221280 kb
Host smart-3b3ef5ec-f260-4a2a-9b7e-8f81afb85036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920804929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3920804929
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.7106781
Short name T67
Test name
Test status
Simulation time 825210493 ps
CPU time 30.46 seconds
Started Feb 08 01:04:46 PM PST 24
Finished Feb 08 01:05:17 PM PST 24
Peak memory 220420 kb
Host smart-08497cc8-018a-4417-9f14-32d83a362c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7106781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.7106781
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.311389813
Short name T112
Test name
Test status
Simulation time 651750631 ps
CPU time 7.5 seconds
Started Feb 08 12:28:19 PM PST 24
Finished Feb 08 12:28:55 PM PST 24
Peak memory 213552 kb
Host smart-a73a5e08-1de7-4721-a5bf-2fe5df90681e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311389813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.311389813
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2559699923
Short name T9
Test name
Test status
Simulation time 122832840 ps
CPU time 2.56 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:36 PM PST 24
Peak memory 208484 kb
Host smart-ae79d8a7-70de-4a23-93d0-3eca8e48e36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559699923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2559699923
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3193404481
Short name T46
Test name
Test status
Simulation time 38707039796 ps
CPU time 191.42 seconds
Started Feb 08 01:07:47 PM PST 24
Finished Feb 08 01:11:00 PM PST 24
Peak memory 217268 kb
Host smart-ccead114-2697-4b56-857b-9672e3c1fdc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193404481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3193404481
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1000248566
Short name T427
Test name
Test status
Simulation time 1719199364 ps
CPU time 45.45 seconds
Started Feb 08 01:05:23 PM PST 24
Finished Feb 08 01:06:09 PM PST 24
Peak memory 214316 kb
Host smart-da5b8e9d-22e8-462a-810d-8e77477b5937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1000248566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1000248566
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1793127227
Short name T43
Test name
Test status
Simulation time 187996489 ps
CPU time 13.97 seconds
Started Feb 08 01:04:20 PM PST 24
Finished Feb 08 01:04:34 PM PST 24
Peak memory 222684 kb
Host smart-e30181ad-8325-49f7-b154-e16c0e76cff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793127227 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1793127227
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3637556364
Short name T88
Test name
Test status
Simulation time 156273664 ps
CPU time 3.9 seconds
Started Feb 08 01:07:51 PM PST 24
Finished Feb 08 01:07:56 PM PST 24
Peak memory 220068 kb
Host smart-d17fa9b2-5e8d-4c06-a818-57303327eccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637556364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3637556364
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2527553637
Short name T30
Test name
Test status
Simulation time 213703056 ps
CPU time 2.87 seconds
Started Feb 08 01:08:33 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 209712 kb
Host smart-545d4c6d-bdc8-4cc6-9a6d-29da39976e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527553637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2527553637
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1234995673
Short name T247
Test name
Test status
Simulation time 709490607 ps
CPU time 10.01 seconds
Started Feb 08 01:07:09 PM PST 24
Finished Feb 08 01:07:20 PM PST 24
Peak memory 214392 kb
Host smart-32d6f414-9ef5-4368-bb62-0f3b16324db8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1234995673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1234995673
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.728284225
Short name T439
Test name
Test status
Simulation time 5229844200 ps
CPU time 74.35 seconds
Started Feb 08 01:07:39 PM PST 24
Finished Feb 08 01:08:55 PM PST 24
Peak memory 214828 kb
Host smart-9c05e5e4-b5d0-4238-a4b4-af2845b29b06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=728284225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.728284225
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3232693329
Short name T117
Test name
Test status
Simulation time 3537925723 ps
CPU time 19.93 seconds
Started Feb 08 12:28:43 PM PST 24
Finished Feb 08 12:29:37 PM PST 24
Peak memory 217440 kb
Host smart-7a803ebb-c4f4-4fe6-833d-d19eb34ca366
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232693329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3232693329
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1184713521
Short name T97
Test name
Test status
Simulation time 125826732 ps
CPU time 6.15 seconds
Started Feb 08 01:05:25 PM PST 24
Finished Feb 08 01:05:32 PM PST 24
Peak memory 214328 kb
Host smart-06994ce4-1e1a-448c-a983-1a5f7748201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184713521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1184713521
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2091215729
Short name T272
Test name
Test status
Simulation time 7027221944 ps
CPU time 26.15 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:30 PM PST 24
Peak memory 214612 kb
Host smart-8d360f66-659f-4822-914a-df2a412ff7ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091215729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2091215729
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3492525920
Short name T249
Test name
Test status
Simulation time 4324971619 ps
CPU time 38.71 seconds
Started Feb 08 01:08:30 PM PST 24
Finished Feb 08 01:09:10 PM PST 24
Peak memory 216444 kb
Host smart-31b3ef34-c3fc-443b-871f-850397ffa4a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492525920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3492525920
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2225177683
Short name T72
Test name
Test status
Simulation time 5148421410 ps
CPU time 38.68 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:09:09 PM PST 24
Peak memory 222552 kb
Host smart-6e816909-f9e8-478c-8423-d2cefa0c52ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225177683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2225177683
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2838977160
Short name T241
Test name
Test status
Simulation time 939193234 ps
CPU time 49.26 seconds
Started Feb 08 01:03:59 PM PST 24
Finished Feb 08 01:04:50 PM PST 24
Peak memory 214256 kb
Host smart-c651d99e-0cbf-41cc-b1ef-3b449f23929e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838977160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2838977160
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2836811834
Short name T16
Test name
Test status
Simulation time 513064737 ps
CPU time 4.81 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:07 PM PST 24
Peak memory 214364 kb
Host smart-88a40004-8535-423f-aeac-ce7f27d46cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836811834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2836811834
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1260113580
Short name T91
Test name
Test status
Simulation time 83642790 ps
CPU time 3.5 seconds
Started Feb 08 01:06:10 PM PST 24
Finished Feb 08 01:06:19 PM PST 24
Peak memory 219212 kb
Host smart-f9b4d3d3-e85f-4a3f-a666-44274db78139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260113580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1260113580
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1270091319
Short name T23
Test name
Test status
Simulation time 240868932 ps
CPU time 5.1 seconds
Started Feb 08 01:08:08 PM PST 24
Finished Feb 08 01:08:13 PM PST 24
Peak memory 218428 kb
Host smart-5d8f696c-b7bf-41b4-a3c6-87d110c397f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270091319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1270091319
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3918361600
Short name T147
Test name
Test status
Simulation time 2166525222 ps
CPU time 101.23 seconds
Started Feb 08 01:08:13 PM PST 24
Finished Feb 08 01:09:55 PM PST 24
Peak memory 222472 kb
Host smart-05cd35fd-2b66-47e4-8fe9-b00bbeb98d85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918361600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3918361600
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4262237757
Short name T33
Test name
Test status
Simulation time 233270911 ps
CPU time 1.99 seconds
Started Feb 08 01:07:53 PM PST 24
Finished Feb 08 01:07:56 PM PST 24
Peak memory 208424 kb
Host smart-c79bf0d2-245c-442b-ab72-7aeac3784aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262237757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4262237757
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3047208500
Short name T278
Test name
Test status
Simulation time 7011497605 ps
CPU time 70.92 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:09:16 PM PST 24
Peak memory 222420 kb
Host smart-3a2478a5-3e47-4dd7-9303-45076572c332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047208500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3047208500
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1527598664
Short name T266
Test name
Test status
Simulation time 1006787320 ps
CPU time 13.11 seconds
Started Feb 08 01:03:59 PM PST 24
Finished Feb 08 01:04:14 PM PST 24
Peak memory 214384 kb
Host smart-99f53380-d566-44cc-9675-4972ff7725cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1527598664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1527598664
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1097061587
Short name T55
Test name
Test status
Simulation time 762509946 ps
CPU time 2.4 seconds
Started Feb 08 01:07:11 PM PST 24
Finished Feb 08 01:07:15 PM PST 24
Peak memory 217084 kb
Host smart-c6adefe8-00db-4ebd-aebf-9c5e4607358b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097061587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1097061587
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2713730728
Short name T66
Test name
Test status
Simulation time 1080632845 ps
CPU time 23.33 seconds
Started Feb 08 01:07:44 PM PST 24
Finished Feb 08 01:08:08 PM PST 24
Peak memory 220140 kb
Host smart-b1a6ac1e-013d-4774-bf8c-160827d7378d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713730728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2713730728
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3451358490
Short name T124
Test name
Test status
Simulation time 2336057090 ps
CPU time 6.69 seconds
Started Feb 08 12:28:50 PM PST 24
Finished Feb 08 12:29:30 PM PST 24
Peak memory 213340 kb
Host smart-fe67c197-7138-498b-8bc6-477df96ef352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451358490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3451358490
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2330103121
Short name T90
Test name
Test status
Simulation time 646554098 ps
CPU time 5.01 seconds
Started Feb 08 01:07:43 PM PST 24
Finished Feb 08 01:07:49 PM PST 24
Peak memory 222500 kb
Host smart-e2b75013-52e6-4db7-b5e5-e0f7538791c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330103121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2330103121
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1473313834
Short name T377
Test name
Test status
Simulation time 296708790 ps
CPU time 5.33 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 215148 kb
Host smart-64e5dbbc-0458-4cfe-ae09-0c8945d71c9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1473313834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1473313834
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.966894793
Short name T130
Test name
Test status
Simulation time 113784933 ps
CPU time 3.92 seconds
Started Feb 08 01:06:43 PM PST 24
Finished Feb 08 01:06:51 PM PST 24
Peak memory 222476 kb
Host smart-891b87fc-e71d-44f5-b1ae-9118731cbb92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=966894793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.966894793
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.256613613
Short name T277
Test name
Test status
Simulation time 111057604 ps
CPU time 6.71 seconds
Started Feb 08 01:07:42 PM PST 24
Finished Feb 08 01:07:50 PM PST 24
Peak memory 214004 kb
Host smart-3ad39ddc-9c90-4382-8fd8-a4a253673806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256613613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.256613613
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3893639814
Short name T36
Test name
Test status
Simulation time 5077341322 ps
CPU time 32.93 seconds
Started Feb 08 01:05:18 PM PST 24
Finished Feb 08 01:05:52 PM PST 24
Peak memory 222436 kb
Host smart-aec76cf6-1c16-4023-9967-d83502d8ceda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893639814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3893639814
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3444957004
Short name T210
Test name
Test status
Simulation time 624384736 ps
CPU time 9.48 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:23 PM PST 24
Peak memory 208828 kb
Host smart-3515cfda-65a1-4a0b-bb73-c3af5e2c0cb4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444957004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3444957004
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.4013197532
Short name T167
Test name
Test status
Simulation time 347601211 ps
CPU time 8.64 seconds
Started Feb 08 12:28:42 PM PST 24
Finished Feb 08 12:29:25 PM PST 24
Peak memory 208896 kb
Host smart-9ac613ad-daca-4af7-9df7-ea86f36b74a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013197532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.4013197532
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.709368668
Short name T590
Test name
Test status
Simulation time 28405596 ps
CPU time 0.67 seconds
Started Feb 08 01:05:39 PM PST 24
Finished Feb 08 01:05:42 PM PST 24
Peak memory 205884 kb
Host smart-f3c2adf8-7fbf-4de6-bea4-f783a66f8f2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709368668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.709368668
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.813699621
Short name T320
Test name
Test status
Simulation time 479224488 ps
CPU time 5.44 seconds
Started Feb 08 01:08:35 PM PST 24
Finished Feb 08 01:08:41 PM PST 24
Peak memory 214336 kb
Host smart-e20790da-3bdf-4f7f-be6d-892726cde4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813699621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.813699621
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3042096836
Short name T305
Test name
Test status
Simulation time 155376149 ps
CPU time 8.77 seconds
Started Feb 08 01:08:59 PM PST 24
Finished Feb 08 01:09:16 PM PST 24
Peak memory 214316 kb
Host smart-05068335-ad82-4c46-a4de-33f56cadbdcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042096836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3042096836
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.612934362
Short name T368
Test name
Test status
Simulation time 196227503 ps
CPU time 3.25 seconds
Started Feb 08 01:07:00 PM PST 24
Finished Feb 08 01:07:06 PM PST 24
Peak memory 220432 kb
Host smart-9133d74e-5bd1-4ef1-8c2e-4c27a75721a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612934362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.612934362
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2927153280
Short name T359
Test name
Test status
Simulation time 238407855 ps
CPU time 4.55 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:08 PM PST 24
Peak memory 215284 kb
Host smart-16716798-49dc-4d1c-8aab-217221574830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927153280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2927153280
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1290937898
Short name T393
Test name
Test status
Simulation time 118260578 ps
CPU time 4.39 seconds
Started Feb 08 01:08:58 PM PST 24
Finished Feb 08 01:09:10 PM PST 24
Peak memory 214356 kb
Host smart-5e29817f-6759-4384-b5ec-b4478a37285d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290937898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1290937898
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1686379148
Short name T159
Test name
Test status
Simulation time 1075997970 ps
CPU time 13.47 seconds
Started Feb 08 12:28:42 PM PST 24
Finished Feb 08 12:29:29 PM PST 24
Peak memory 208644 kb
Host smart-b69ea8a8-d9d2-46cb-8a83-7d4f71503ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686379148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1686379148
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.811831388
Short name T158
Test name
Test status
Simulation time 215352338 ps
CPU time 4.82 seconds
Started Feb 08 12:28:11 PM PST 24
Finished Feb 08 12:28:41 PM PST 24
Peak memory 213488 kb
Host smart-35801ef2-1d80-485d-977e-72cdf8044dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811831388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
811831388
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2999910986
Short name T230
Test name
Test status
Simulation time 421390940 ps
CPU time 13.25 seconds
Started Feb 08 01:04:28 PM PST 24
Finished Feb 08 01:04:42 PM PST 24
Peak memory 222480 kb
Host smart-b218a53e-cfa1-45ca-b820-fbae62b42ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999910986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2999910986
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1558429184
Short name T350
Test name
Test status
Simulation time 114380909 ps
CPU time 4.8 seconds
Started Feb 08 01:06:47 PM PST 24
Finished Feb 08 01:06:57 PM PST 24
Peak memory 208812 kb
Host smart-d8f50f9e-973e-4fcc-acca-501ba81061b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558429184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1558429184
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2420772624
Short name T340
Test name
Test status
Simulation time 1128837849 ps
CPU time 27.77 seconds
Started Feb 08 01:06:07 PM PST 24
Finished Feb 08 01:06:39 PM PST 24
Peak memory 215664 kb
Host smart-55b9b529-ffc7-4b7d-a6cb-371426bc810a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420772624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2420772624
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.876597148
Short name T202
Test name
Test status
Simulation time 1134201740 ps
CPU time 9.1 seconds
Started Feb 08 01:07:42 PM PST 24
Finished Feb 08 01:07:52 PM PST 24
Peak memory 214820 kb
Host smart-8fb747a3-3a0d-4723-bb31-37f878f56698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876597148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.876597148
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3312519452
Short name T352
Test name
Test status
Simulation time 11718877982 ps
CPU time 246.93 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:12:09 PM PST 24
Peak memory 217724 kb
Host smart-dcd8892d-fbb6-4601-88ed-ce6da1a3f993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312519452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3312519452
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3679434863
Short name T314
Test name
Test status
Simulation time 63875953 ps
CPU time 2.63 seconds
Started Feb 08 01:08:08 PM PST 24
Finished Feb 08 01:08:12 PM PST 24
Peak memory 209440 kb
Host smart-998151ee-4e55-48d6-95c5-ef95b77c62b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679434863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3679434863
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1890827191
Short name T256
Test name
Test status
Simulation time 2820537250 ps
CPU time 7.3 seconds
Started Feb 08 01:04:50 PM PST 24
Finished Feb 08 01:04:58 PM PST 24
Peak memory 224168 kb
Host smart-3e89294d-b182-41b7-b229-448490339d94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890827191 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1890827191
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1435633660
Short name T101
Test name
Test status
Simulation time 98414412 ps
CPU time 4.09 seconds
Started Feb 08 01:05:40 PM PST 24
Finished Feb 08 01:05:46 PM PST 24
Peak memory 219144 kb
Host smart-94069b52-2295-44d6-8bbe-afcd91219c85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435633660 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1435633660
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1288020618
Short name T162
Test name
Test status
Simulation time 5737361444 ps
CPU time 33.97 seconds
Started Feb 08 12:28:39 PM PST 24
Finished Feb 08 12:29:46 PM PST 24
Peak memory 209168 kb
Host smart-ac15829e-d3e5-45e9-b868-a7990a447d28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288020618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1288020618
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2961675304
Short name T166
Test name
Test status
Simulation time 1016281552 ps
CPU time 21.53 seconds
Started Feb 08 12:28:35 PM PST 24
Finished Feb 08 12:29:28 PM PST 24
Peak memory 213292 kb
Host smart-cb529bf8-ea98-465b-9582-bd529060a8bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961675304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2961675304
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2150341090
Short name T150
Test name
Test status
Simulation time 268531551 ps
CPU time 2.74 seconds
Started Feb 08 01:07:52 PM PST 24
Finished Feb 08 01:07:56 PM PST 24
Peak memory 217796 kb
Host smart-579d0caa-f29c-4682-ba33-7ee95796326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150341090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2150341090
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.4276524950
Short name T233
Test name
Test status
Simulation time 24215603847 ps
CPU time 428.55 seconds
Started Feb 08 01:06:56 PM PST 24
Finished Feb 08 01:14:08 PM PST 24
Peak memory 222548 kb
Host smart-45a221cf-61ab-40d4-8202-e14752c67bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276524950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.4276524950
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2271227850
Short name T344
Test name
Test status
Simulation time 12423713305 ps
CPU time 100.88 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:08:56 PM PST 24
Peak memory 221220 kb
Host smart-805b9972-176b-4185-85ba-bd6c4163a517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271227850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2271227850
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2232580039
Short name T251
Test name
Test status
Simulation time 148218742 ps
CPU time 6.27 seconds
Started Feb 08 01:04:14 PM PST 24
Finished Feb 08 01:04:21 PM PST 24
Peak memory 210856 kb
Host smart-62257ec4-fb9b-4333-a7d0-bc6883077de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232580039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2232580039
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1285549680
Short name T264
Test name
Test status
Simulation time 36494663 ps
CPU time 2.4 seconds
Started Feb 08 01:04:28 PM PST 24
Finished Feb 08 01:04:31 PM PST 24
Peak memory 208508 kb
Host smart-622c5c43-551a-48bc-b2c7-a72c1036ef6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285549680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1285549680
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1712299524
Short name T107
Test name
Test status
Simulation time 294835024 ps
CPU time 15.09 seconds
Started Feb 08 01:04:46 PM PST 24
Finished Feb 08 01:05:02 PM PST 24
Peak memory 214136 kb
Host smart-df55f855-b3fd-4cc9-a4f9-f5261c080cc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712299524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1712299524
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3837514578
Short name T51
Test name
Test status
Simulation time 959191906 ps
CPU time 21.07 seconds
Started Feb 08 01:05:20 PM PST 24
Finished Feb 08 01:05:42 PM PST 24
Peak memory 220180 kb
Host smart-182272aa-f6bf-4603-b5d5-0579284f75f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837514578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3837514578
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2230610828
Short name T149
Test name
Test status
Simulation time 109503794 ps
CPU time 4.86 seconds
Started Feb 08 01:05:50 PM PST 24
Finished Feb 08 01:06:06 PM PST 24
Peak memory 222544 kb
Host smart-ecd28265-919f-422d-9efd-22a458a61ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230610828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2230610828
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.692820756
Short name T152
Test name
Test status
Simulation time 181300109 ps
CPU time 6.2 seconds
Started Feb 08 01:06:07 PM PST 24
Finished Feb 08 01:06:18 PM PST 24
Peak memory 218776 kb
Host smart-9306d5d4-fd2a-44e6-a780-d2708aa288ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692820756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.692820756
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3986073776
Short name T151
Test name
Test status
Simulation time 287074216 ps
CPU time 4.01 seconds
Started Feb 08 01:07:17 PM PST 24
Finished Feb 08 01:07:23 PM PST 24
Peak memory 218104 kb
Host smart-2de5804a-a33c-464c-804a-252fdded7aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986073776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3986073776
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3948294673
Short name T68
Test name
Test status
Simulation time 670260038 ps
CPU time 5.74 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:09 PM PST 24
Peak memory 215764 kb
Host smart-e51d1ae6-15e3-4333-b5a6-baa264473d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948294673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3948294673
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1779199193
Short name T263
Test name
Test status
Simulation time 544894306 ps
CPU time 6.24 seconds
Started Feb 08 01:05:44 PM PST 24
Finished Feb 08 01:06:01 PM PST 24
Peak memory 209920 kb
Host smart-0a212a52-331b-4ec9-9dad-834f1fd48b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779199193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1779199193
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1003592855
Short name T399
Test name
Test status
Simulation time 879561279 ps
CPU time 7.94 seconds
Started Feb 08 01:06:45 PM PST 24
Finished Feb 08 01:06:55 PM PST 24
Peak memory 210052 kb
Host smart-1b65b0df-f139-46a0-849d-a434c13dd378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003592855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1003592855
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.746862735
Short name T193
Test name
Test status
Simulation time 104797862 ps
CPU time 4.89 seconds
Started Feb 08 01:06:57 PM PST 24
Finished Feb 08 01:07:05 PM PST 24
Peak memory 210676 kb
Host smart-614964fb-f3fa-477f-ba76-cdb2e9f6ee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746862735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.746862735
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3915503593
Short name T342
Test name
Test status
Simulation time 2830192942 ps
CPU time 60.2 seconds
Started Feb 08 01:07:19 PM PST 24
Finished Feb 08 01:08:21 PM PST 24
Peak memory 222484 kb
Host smart-e64555ef-935e-40d7-8ad4-f02b0c81e96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915503593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3915503593
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2795732579
Short name T383
Test name
Test status
Simulation time 459379718 ps
CPU time 5.21 seconds
Started Feb 08 01:07:40 PM PST 24
Finished Feb 08 01:07:46 PM PST 24
Peak memory 222332 kb
Host smart-397b05b1-4116-42fc-89a8-9c5011c81c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795732579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2795732579
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.509994102
Short name T254
Test name
Test status
Simulation time 158695436 ps
CPU time 4.4 seconds
Started Feb 08 01:08:33 PM PST 24
Finished Feb 08 01:08:39 PM PST 24
Peak memory 215004 kb
Host smart-02b13f81-48d0-424f-981f-dd9c9969a912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=509994102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.509994102
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2756610416
Short name T99
Test name
Test status
Simulation time 112229063 ps
CPU time 2.29 seconds
Started Feb 08 01:04:46 PM PST 24
Finished Feb 08 01:04:49 PM PST 24
Peak memory 219144 kb
Host smart-d56182f0-06ce-4493-bbde-3f59605dfc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756610416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2756610416
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_random.3655512639
Short name T374
Test name
Test status
Simulation time 349195230 ps
CPU time 11.17 seconds
Started Feb 08 01:08:34 PM PST 24
Finished Feb 08 01:08:46 PM PST 24
Peak memory 208156 kb
Host smart-4761bcd1-ec29-4e81-8501-99e7ce1a0fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655512639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3655512639
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.207069677
Short name T236
Test name
Test status
Simulation time 242709840 ps
CPU time 11.92 seconds
Started Feb 08 01:08:57 PM PST 24
Finished Feb 08 01:09:17 PM PST 24
Peak memory 216760 kb
Host smart-2c91f144-9dd2-4c77-85b0-24e5b1df648d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207069677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.207069677
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.932347912
Short name T407
Test name
Test status
Simulation time 225211433 ps
CPU time 3.7 seconds
Started Feb 08 01:05:17 PM PST 24
Finished Feb 08 01:05:21 PM PST 24
Peak memory 208896 kb
Host smart-75f28ebc-9a68-4890-9c26-7b32b51303cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932347912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.932347912
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.143602821
Short name T165
Test name
Test status
Simulation time 1111281683 ps
CPU time 3.94 seconds
Started Feb 08 12:28:42 PM PST 24
Finished Feb 08 12:29:20 PM PST 24
Peak memory 208016 kb
Host smart-8fc86ec9-3fd9-4d6e-89a8-878476976ba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143602821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.143602821
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1620957150
Short name T156
Test name
Test status
Simulation time 450783975 ps
CPU time 4.08 seconds
Started Feb 08 12:28:40 PM PST 24
Finished Feb 08 12:29:17 PM PST 24
Peak memory 213484 kb
Host smart-3349e0b1-3bff-467d-a4c7-6eb3c2858466
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620957150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1620957150
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4058581246
Short name T164
Test name
Test status
Simulation time 560162917 ps
CPU time 5.03 seconds
Started Feb 08 12:28:16 PM PST 24
Finished Feb 08 12:28:47 PM PST 24
Peak memory 208376 kb
Host smart-cd5c246e-2e86-4aa4-8261-3d0e2b13dcd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058581246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4058581246
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3798989611
Short name T20
Test name
Test status
Simulation time 112938143 ps
CPU time 1.7 seconds
Started Feb 08 01:04:00 PM PST 24
Finished Feb 08 01:04:03 PM PST 24
Peak memory 222756 kb
Host smart-b294f86b-6fad-4960-9301-a520e8077f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798989611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3798989611
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3551343212
Short name T87
Test name
Test status
Simulation time 453040543 ps
CPU time 3.16 seconds
Started Feb 08 01:04:03 PM PST 24
Finished Feb 08 01:04:08 PM PST 24
Peak memory 209212 kb
Host smart-e16a7278-b6d2-473e-850d-aed85605fb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551343212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3551343212
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sideload.4293373878
Short name T325
Test name
Test status
Simulation time 93653069 ps
CPU time 3.16 seconds
Started Feb 08 01:03:52 PM PST 24
Finished Feb 08 01:03:56 PM PST 24
Peak memory 207824 kb
Host smart-f8f8f538-3031-401c-8178-c609b18e7d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293373878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.4293373878
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2355870183
Short name T8
Test name
Test status
Simulation time 682082063 ps
CPU time 3.54 seconds
Started Feb 08 01:03:51 PM PST 24
Finished Feb 08 01:03:55 PM PST 24
Peak memory 218792 kb
Host smart-2b91db1c-1f48-4b48-acaf-85c7c66b1e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355870183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2355870183
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3424253655
Short name T690
Test name
Test status
Simulation time 474350074 ps
CPU time 2.93 seconds
Started Feb 08 01:05:41 PM PST 24
Finished Feb 08 01:05:46 PM PST 24
Peak memory 210172 kb
Host smart-69024a11-ee14-4d40-974c-5fd306fe852c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424253655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3424253655
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2397092296
Short name T731
Test name
Test status
Simulation time 166664131 ps
CPU time 3.72 seconds
Started Feb 08 01:05:44 PM PST 24
Finished Feb 08 01:05:59 PM PST 24
Peak memory 217692 kb
Host smart-d69992e4-fef1-43cb-80c0-4713ef94e135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397092296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2397092296
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3922605410
Short name T397
Test name
Test status
Simulation time 537634834 ps
CPU time 15.83 seconds
Started Feb 08 01:05:45 PM PST 24
Finished Feb 08 01:06:11 PM PST 24
Peak memory 214320 kb
Host smart-e6ea4e1f-42ea-4d9d-97d2-ace35b30b46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922605410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3922605410
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3378789688
Short name T402
Test name
Test status
Simulation time 175799068 ps
CPU time 4.4 seconds
Started Feb 08 01:05:46 PM PST 24
Finished Feb 08 01:05:59 PM PST 24
Peak memory 222328 kb
Host smart-eef663d9-7d4d-4d43-860b-57bcbfc0ca6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378789688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3378789688
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2869386026
Short name T331
Test name
Test status
Simulation time 104490165 ps
CPU time 3.38 seconds
Started Feb 08 01:07:11 PM PST 24
Finished Feb 08 01:07:16 PM PST 24
Peak memory 209896 kb
Host smart-a1ec945f-d70c-4922-a550-9ed6a6cbee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869386026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2869386026
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1201897730
Short name T27
Test name
Test status
Simulation time 377921788 ps
CPU time 3.7 seconds
Started Feb 08 01:08:25 PM PST 24
Finished Feb 08 01:08:29 PM PST 24
Peak memory 218296 kb
Host smart-f95bb100-a184-49e0-9983-9e0a372b9d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201897730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1201897730
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2061409637
Short name T248
Test name
Test status
Simulation time 655566235 ps
CPU time 6.53 seconds
Started Feb 08 01:08:33 PM PST 24
Finished Feb 08 01:08:41 PM PST 24
Peak memory 215164 kb
Host smart-3c85edaf-8b00-40d2-8bf6-71d8c420d5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2061409637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2061409637
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3693572009
Short name T138
Test name
Test status
Simulation time 73049397 ps
CPU time 3.94 seconds
Started Feb 08 12:28:01 PM PST 24
Finished Feb 08 12:28:18 PM PST 24
Peak memory 205116 kb
Host smart-deb8b1e7-2c23-4b87-a338-e62a2bc45967
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693572009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
693572009
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2373297779
Short name T467
Test name
Test status
Simulation time 1009044532 ps
CPU time 14.81 seconds
Started Feb 08 12:27:57 PM PST 24
Finished Feb 08 12:28:23 PM PST 24
Peak memory 205112 kb
Host smart-35c20570-db12-4c44-81b2-29dc773b9a9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373297779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
373297779
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2082878723
Short name T446
Test name
Test status
Simulation time 41223974 ps
CPU time 0.89 seconds
Started Feb 08 12:27:58 PM PST 24
Finished Feb 08 12:28:10 PM PST 24
Peak memory 205016 kb
Host smart-1ea2b5c9-dd75-4c76-9a5c-b909a50bfcf9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082878723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
082878723
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.847931699
Short name T492
Test name
Test status
Simulation time 73020350 ps
CPU time 1.84 seconds
Started Feb 08 12:28:00 PM PST 24
Finished Feb 08 12:28:14 PM PST 24
Peak memory 213400 kb
Host smart-f932e436-df25-4f7b-abf5-b66876a02523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847931699 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.847931699
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1191373881
Short name T562
Test name
Test status
Simulation time 41192819 ps
CPU time 0.99 seconds
Started Feb 08 12:28:00 PM PST 24
Finished Feb 08 12:28:14 PM PST 24
Peak memory 205012 kb
Host smart-88405d80-6a60-4bf9-88d2-2a0e786c4f45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191373881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1191373881
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.657558870
Short name T530
Test name
Test status
Simulation time 22863822 ps
CPU time 0.69 seconds
Started Feb 08 12:28:06 PM PST 24
Finished Feb 08 12:28:27 PM PST 24
Peak memory 205012 kb
Host smart-230c2e12-5cb3-4030-afae-7e64234071c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657558870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.657558870
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3679910553
Short name T567
Test name
Test status
Simulation time 35640462 ps
CPU time 2.13 seconds
Started Feb 08 12:27:56 PM PST 24
Finished Feb 08 12:28:08 PM PST 24
Peak memory 205164 kb
Host smart-a26622d3-a610-4890-888e-956581e56d13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679910553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3679910553
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1320963699
Short name T120
Test name
Test status
Simulation time 786679249 ps
CPU time 8.02 seconds
Started Feb 08 12:27:55 PM PST 24
Finished Feb 08 12:28:14 PM PST 24
Peak memory 213548 kb
Host smart-37f6fd15-5bd1-4343-a3ad-ea18cf0ba80f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320963699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1320963699
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.289136727
Short name T534
Test name
Test status
Simulation time 457583031 ps
CPU time 9.49 seconds
Started Feb 08 12:28:07 PM PST 24
Finished Feb 08 12:28:37 PM PST 24
Peak memory 213500 kb
Host smart-8f12008d-fdf1-4e35-8cb0-f91f55431a1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289136727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.289136727
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2412180368
Short name T126
Test name
Test status
Simulation time 152480624 ps
CPU time 5.1 seconds
Started Feb 08 12:28:05 PM PST 24
Finished Feb 08 12:28:30 PM PST 24
Peak memory 213284 kb
Host smart-113cccf0-949a-419a-a5e2-80ae596cd539
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412180368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2412180368
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2113542187
Short name T153
Test name
Test status
Simulation time 879099002 ps
CPU time 24.5 seconds
Started Feb 08 12:28:06 PM PST 24
Finished Feb 08 12:28:51 PM PST 24
Peak memory 204988 kb
Host smart-66127ef9-bcca-4be4-8514-a5b257a31a5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113542187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
113542187
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3854623925
Short name T473
Test name
Test status
Simulation time 18832077 ps
CPU time 1.16 seconds
Started Feb 08 12:28:03 PM PST 24
Finished Feb 08 12:28:20 PM PST 24
Peak memory 205124 kb
Host smart-bc4e5570-ad78-4858-b5ce-301c06f8e5bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854623925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
854623925
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.557486474
Short name T527
Test name
Test status
Simulation time 33812175 ps
CPU time 1.82 seconds
Started Feb 08 12:28:01 PM PST 24
Finished Feb 08 12:28:15 PM PST 24
Peak memory 205148 kb
Host smart-c94cb5f2-5ed8-4e4d-9b98-09ef293f9633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557486474 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.557486474
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1256125050
Short name T499
Test name
Test status
Simulation time 51521331 ps
CPU time 1.43 seconds
Started Feb 08 12:28:03 PM PST 24
Finished Feb 08 12:28:21 PM PST 24
Peak memory 204944 kb
Host smart-f691ce3a-d4a1-4e81-a02e-90737e011eb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256125050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1256125050
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.509434730
Short name T563
Test name
Test status
Simulation time 37638062 ps
CPU time 0.82 seconds
Started Feb 08 12:28:03 PM PST 24
Finished Feb 08 12:28:20 PM PST 24
Peak memory 204864 kb
Host smart-0e633ca6-ae8d-403c-8fd8-ec4a8ebdb690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509434730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.509434730
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2704708548
Short name T146
Test name
Test status
Simulation time 201728934 ps
CPU time 2.35 seconds
Started Feb 08 12:28:01 PM PST 24
Finished Feb 08 12:28:16 PM PST 24
Peak memory 205112 kb
Host smart-8c9a81de-a895-4687-8d47-cbb5a063359b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704708548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2704708548
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.773419171
Short name T462
Test name
Test status
Simulation time 2520345751 ps
CPU time 16.78 seconds
Started Feb 08 12:28:02 PM PST 24
Finished Feb 08 12:28:32 PM PST 24
Peak memory 214700 kb
Host smart-c0af0637-08fd-43fb-b207-ee057b6bbe88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773419171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.773419171
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4027281929
Short name T487
Test name
Test status
Simulation time 374124711 ps
CPU time 2.6 seconds
Started Feb 08 12:27:57 PM PST 24
Finished Feb 08 12:28:11 PM PST 24
Peak memory 213372 kb
Host smart-35b1db2b-2c7c-4694-8c82-afe71d201437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027281929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4027281929
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1548189496
Short name T481
Test name
Test status
Simulation time 38711178 ps
CPU time 1.54 seconds
Started Feb 08 12:28:38 PM PST 24
Finished Feb 08 12:29:11 PM PST 24
Peak memory 213424 kb
Host smart-6a326089-c4a6-4e7f-820c-67da0e2bb699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548189496 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1548189496
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.427355653
Short name T575
Test name
Test status
Simulation time 17697599 ps
CPU time 1.2 seconds
Started Feb 08 12:28:35 PM PST 24
Finished Feb 08 12:29:08 PM PST 24
Peak memory 205376 kb
Host smart-c9c760a5-7f37-4581-aeb2-ca78e13f6274
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427355653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.427355653
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1617319197
Short name T529
Test name
Test status
Simulation time 10558338 ps
CPU time 0.68 seconds
Started Feb 08 12:28:33 PM PST 24
Finished Feb 08 12:29:05 PM PST 24
Peak memory 204984 kb
Host smart-98883c07-0aaf-41ad-8106-16178629bf02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617319197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1617319197
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.257425203
Short name T565
Test name
Test status
Simulation time 138412572 ps
CPU time 1.98 seconds
Started Feb 08 12:28:37 PM PST 24
Finished Feb 08 12:29:11 PM PST 24
Peak memory 213356 kb
Host smart-1a58e13b-bf39-47ae-93d4-9eef6418f798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257425203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.257425203
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4175208992
Short name T119
Test name
Test status
Simulation time 799113032 ps
CPU time 6 seconds
Started Feb 08 12:28:37 PM PST 24
Finished Feb 08 12:29:15 PM PST 24
Peak memory 213572 kb
Host smart-40fa8237-6a5e-4c07-b992-229b41adbb86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175208992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4175208992
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2659752747
Short name T460
Test name
Test status
Simulation time 446820692 ps
CPU time 15.22 seconds
Started Feb 08 12:28:39 PM PST 24
Finished Feb 08 12:29:26 PM PST 24
Peak memory 213568 kb
Host smart-6e2e91b7-61ba-45da-93cd-de728611a599
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659752747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2659752747
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2734897788
Short name T566
Test name
Test status
Simulation time 205939098 ps
CPU time 2.67 seconds
Started Feb 08 12:28:36 PM PST 24
Finished Feb 08 12:29:10 PM PST 24
Peak memory 213468 kb
Host smart-7f39f813-8d22-4722-8faf-e8e8f970b006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734897788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2734897788
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1703723477
Short name T168
Test name
Test status
Simulation time 242776814 ps
CPU time 3.41 seconds
Started Feb 08 12:28:39 PM PST 24
Finished Feb 08 12:29:15 PM PST 24
Peak memory 208616 kb
Host smart-169a5b7b-85c8-4648-8996-1138ddb310f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703723477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1703723477
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.4104134555
Short name T461
Test name
Test status
Simulation time 23398517 ps
CPU time 1.07 seconds
Started Feb 08 12:28:39 PM PST 24
Finished Feb 08 12:29:11 PM PST 24
Peak memory 204924 kb
Host smart-deb49f3a-a76c-4ae6-baee-d88f2f22b185
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104134555 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.4104134555
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3387802414
Short name T574
Test name
Test status
Simulation time 24916474 ps
CPU time 0.74 seconds
Started Feb 08 12:28:38 PM PST 24
Finished Feb 08 12:29:10 PM PST 24
Peak memory 204956 kb
Host smart-ad705fb6-1c1a-4399-a9c1-31f911a6b1fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387802414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3387802414
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3878143188
Short name T543
Test name
Test status
Simulation time 6193371717 ps
CPU time 20.44 seconds
Started Feb 08 12:28:44 PM PST 24
Finished Feb 08 12:29:38 PM PST 24
Peak memory 214704 kb
Host smart-af65678a-c647-48ef-ae4d-77b6afdde201
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878143188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3878143188
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.4256776805
Short name T479
Test name
Test status
Simulation time 392254453 ps
CPU time 8.07 seconds
Started Feb 08 12:28:40 PM PST 24
Finished Feb 08 12:29:21 PM PST 24
Peak memory 213688 kb
Host smart-d7e07ef9-6537-46da-ac52-209e09cfc5f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256776805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.4256776805
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4173076538
Short name T160
Test name
Test status
Simulation time 700563058 ps
CPU time 2.78 seconds
Started Feb 08 12:28:39 PM PST 24
Finished Feb 08 12:29:13 PM PST 24
Peak memory 213232 kb
Host smart-8ae7b13f-ee0e-4b2d-95be-324ca270c37f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173076538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.4173076538
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2726728033
Short name T176
Test name
Test status
Simulation time 33200025 ps
CPU time 1.55 seconds
Started Feb 08 12:28:43 PM PST 24
Finished Feb 08 12:29:18 PM PST 24
Peak memory 213432 kb
Host smart-3cf88cee-9750-4269-bb4c-a926f61cfedf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726728033 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2726728033
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4093279228
Short name T560
Test name
Test status
Simulation time 19885017 ps
CPU time 0.91 seconds
Started Feb 08 12:28:43 PM PST 24
Finished Feb 08 12:29:17 PM PST 24
Peak memory 204632 kb
Host smart-449293d0-e70e-482f-b86c-26b27cb02795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093279228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.4093279228
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2151720720
Short name T503
Test name
Test status
Simulation time 34415651 ps
CPU time 0.81 seconds
Started Feb 08 12:28:42 PM PST 24
Finished Feb 08 12:29:17 PM PST 24
Peak memory 204964 kb
Host smart-3602d69b-ff4c-4a77-94a1-f9d4fefd02de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151720720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2151720720
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1264041767
Short name T145
Test name
Test status
Simulation time 83791395 ps
CPU time 2.81 seconds
Started Feb 08 12:28:46 PM PST 24
Finished Feb 08 12:29:23 PM PST 24
Peak memory 205152 kb
Host smart-0404357e-c9f6-422f-8e6b-2c1402682d8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264041767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1264041767
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.591701185
Short name T468
Test name
Test status
Simulation time 157985191 ps
CPU time 4.06 seconds
Started Feb 08 12:28:42 PM PST 24
Finished Feb 08 12:29:20 PM PST 24
Peak memory 221712 kb
Host smart-2362bae3-a3f7-4096-9a66-8ff2da557338
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591701185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.591701185
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2842461188
Short name T161
Test name
Test status
Simulation time 116125758 ps
CPU time 2.64 seconds
Started Feb 08 12:28:39 PM PST 24
Finished Feb 08 12:29:14 PM PST 24
Peak memory 213444 kb
Host smart-01470c90-cb74-4ebb-b009-9836f5c687ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842461188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2842461188
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1060792967
Short name T537
Test name
Test status
Simulation time 55116601 ps
CPU time 1.07 seconds
Started Feb 08 12:28:43 PM PST 24
Finished Feb 08 12:29:17 PM PST 24
Peak memory 205192 kb
Host smart-19595cb3-388f-4402-bf82-5e132aa99f02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060792967 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1060792967
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.517866947
Short name T573
Test name
Test status
Simulation time 16754210 ps
CPU time 0.95 seconds
Started Feb 08 12:28:42 PM PST 24
Finished Feb 08 12:29:16 PM PST 24
Peak memory 204912 kb
Host smart-c159eb42-21fd-44f0-9425-3df3b24ca1ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517866947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.517866947
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.163924606
Short name T474
Test name
Test status
Simulation time 9720880 ps
CPU time 0.79 seconds
Started Feb 08 12:28:43 PM PST 24
Finished Feb 08 12:29:17 PM PST 24
Peak memory 204916 kb
Host smart-d1e7b2b8-ab22-454d-99b2-84166823f4dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163924606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.163924606
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.772130285
Short name T548
Test name
Test status
Simulation time 37096427 ps
CPU time 2.4 seconds
Started Feb 08 12:28:46 PM PST 24
Finished Feb 08 12:29:22 PM PST 24
Peak memory 205076 kb
Host smart-b12e068c-f1d7-435c-85bb-04b7c6e24e21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772130285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.772130285
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4228539367
Short name T173
Test name
Test status
Simulation time 138316030 ps
CPU time 2.72 seconds
Started Feb 08 12:28:50 PM PST 24
Finished Feb 08 12:29:26 PM PST 24
Peak memory 221708 kb
Host smart-5469b417-1093-4fd7-9364-dcfbcaa594ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228539367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.4228539367
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.4052059857
Short name T513
Test name
Test status
Simulation time 569330254 ps
CPU time 3.48 seconds
Started Feb 08 12:28:46 PM PST 24
Finished Feb 08 12:29:24 PM PST 24
Peak memory 213004 kb
Host smart-e77311a8-c5cb-4987-aed3-beb6a12f2e21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052059857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.4052059857
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1393728552
Short name T451
Test name
Test status
Simulation time 26865352 ps
CPU time 1.48 seconds
Started Feb 08 12:28:48 PM PST 24
Finished Feb 08 12:29:22 PM PST 24
Peak memory 213320 kb
Host smart-4015b261-10ad-4ef1-b999-f12c6209e8bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393728552 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1393728552
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2527565294
Short name T141
Test name
Test status
Simulation time 13473804 ps
CPU time 0.72 seconds
Started Feb 08 12:28:50 PM PST 24
Finished Feb 08 12:29:24 PM PST 24
Peak memory 204940 kb
Host smart-bac06906-6b5f-462d-bf81-76c6a1cbddff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527565294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2527565294
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.200804781
Short name T501
Test name
Test status
Simulation time 23506693 ps
CPU time 1.67 seconds
Started Feb 08 12:28:44 PM PST 24
Finished Feb 08 12:29:19 PM PST 24
Peak memory 205124 kb
Host smart-635e3bf8-6d17-4614-964d-4844d733a793
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200804781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.200804781
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1792351642
Short name T118
Test name
Test status
Simulation time 1155716580 ps
CPU time 2.76 seconds
Started Feb 08 12:28:40 PM PST 24
Finished Feb 08 12:29:16 PM PST 24
Peak memory 213596 kb
Host smart-f3f9afa2-c721-4d5f-99b3-1041ac45ceaa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792351642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1792351642
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1191173310
Short name T114
Test name
Test status
Simulation time 105520677 ps
CPU time 5.3 seconds
Started Feb 08 12:28:48 PM PST 24
Finished Feb 08 12:29:26 PM PST 24
Peak memory 213592 kb
Host smart-9dd6ad7f-d47c-46ec-9efd-2e0781330ee9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191173310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1191173310
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.129865906
Short name T521
Test name
Test status
Simulation time 1134857229 ps
CPU time 3.4 seconds
Started Feb 08 12:28:43 PM PST 24
Finished Feb 08 12:29:21 PM PST 24
Peak memory 216556 kb
Host smart-5ee7d584-a6cb-474c-b089-10453b008c59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129865906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.129865906
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2649750335
Short name T525
Test name
Test status
Simulation time 64072215 ps
CPU time 1.08 seconds
Started Feb 08 12:28:47 PM PST 24
Finished Feb 08 12:29:21 PM PST 24
Peak memory 205228 kb
Host smart-e3ae8777-4d29-4efe-a4ff-c2954335200e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649750335 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2649750335
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1348994455
Short name T469
Test name
Test status
Simulation time 92879335 ps
CPU time 1.07 seconds
Started Feb 08 12:28:44 PM PST 24
Finished Feb 08 12:29:19 PM PST 24
Peak memory 205120 kb
Host smart-f7d2817a-cd35-4cf8-96ca-d724354d6c54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348994455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1348994455
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3059450512
Short name T524
Test name
Test status
Simulation time 29642024 ps
CPU time 0.78 seconds
Started Feb 08 12:28:40 PM PST 24
Finished Feb 08 12:29:14 PM PST 24
Peak memory 204932 kb
Host smart-242d0469-0c5a-41f8-a84e-cc19144598f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059450512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3059450512
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1159112281
Short name T544
Test name
Test status
Simulation time 20968914 ps
CPU time 1.54 seconds
Started Feb 08 12:28:46 PM PST 24
Finished Feb 08 12:29:21 PM PST 24
Peak memory 205176 kb
Host smart-de00bd53-93ba-4a36-a73f-ee1d83cfbce3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159112281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1159112281
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2351178394
Short name T509
Test name
Test status
Simulation time 197581885 ps
CPU time 4.46 seconds
Started Feb 08 12:28:47 PM PST 24
Finished Feb 08 12:29:26 PM PST 24
Peak memory 213600 kb
Host smart-0d884527-4cba-403e-b117-b92dcdf61d08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351178394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2351178394
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1236107094
Short name T502
Test name
Test status
Simulation time 47528492 ps
CPU time 1.94 seconds
Started Feb 08 12:28:48 PM PST 24
Finished Feb 08 12:29:23 PM PST 24
Peak memory 213408 kb
Host smart-feb6345b-10da-45c9-b696-20158fa2b996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236107094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1236107094
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1500658151
Short name T177
Test name
Test status
Simulation time 27976603 ps
CPU time 0.92 seconds
Started Feb 08 12:28:44 PM PST 24
Finished Feb 08 12:29:19 PM PST 24
Peak memory 205132 kb
Host smart-f247ed3e-18af-40d2-ad44-34dd445ba8ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500658151 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1500658151
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3398867553
Short name T564
Test name
Test status
Simulation time 16904523 ps
CPU time 0.92 seconds
Started Feb 08 12:28:46 PM PST 24
Finished Feb 08 12:29:21 PM PST 24
Peak memory 205008 kb
Host smart-4f52f2df-8c36-48ee-8ad9-b349351860a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398867553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3398867553
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3811333467
Short name T536
Test name
Test status
Simulation time 9180710 ps
CPU time 0.66 seconds
Started Feb 08 12:28:46 PM PST 24
Finished Feb 08 12:29:21 PM PST 24
Peak memory 205024 kb
Host smart-55c8719a-e52f-4b88-ba65-31c922778b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811333467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3811333467
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.848625119
Short name T572
Test name
Test status
Simulation time 341632132 ps
CPU time 3.53 seconds
Started Feb 08 12:28:42 PM PST 24
Finished Feb 08 12:29:20 PM PST 24
Peak memory 205140 kb
Host smart-8469b909-7109-42df-bb18-b7c97a5d1a7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848625119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.848625119
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.673625447
Short name T472
Test name
Test status
Simulation time 660181491 ps
CPU time 9.25 seconds
Started Feb 08 12:28:44 PM PST 24
Finished Feb 08 12:29:27 PM PST 24
Peak memory 213688 kb
Host smart-4a21bab2-a595-4309-9f18-410585ff2137
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673625447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.673625447
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1464318475
Short name T539
Test name
Test status
Simulation time 165637599 ps
CPU time 2.88 seconds
Started Feb 08 12:28:46 PM PST 24
Finished Feb 08 12:29:23 PM PST 24
Peak memory 215648 kb
Host smart-73bb912d-b1d7-4779-b8f4-4b15e2462ff2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464318475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1464318475
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3446217887
Short name T519
Test name
Test status
Simulation time 11711618 ps
CPU time 0.96 seconds
Started Feb 08 12:28:42 PM PST 24
Finished Feb 08 12:29:17 PM PST 24
Peak memory 205068 kb
Host smart-0c176eea-755b-41f8-8ac7-c1122e6fc4ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446217887 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3446217887
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3690917152
Short name T449
Test name
Test status
Simulation time 23494219 ps
CPU time 1.31 seconds
Started Feb 08 12:28:46 PM PST 24
Finished Feb 08 12:29:22 PM PST 24
Peak memory 204488 kb
Host smart-25f5e0e1-6920-4675-9010-439c78bb28a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690917152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3690917152
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.91772715
Short name T140
Test name
Test status
Simulation time 10786934 ps
CPU time 0.81 seconds
Started Feb 08 12:28:43 PM PST 24
Finished Feb 08 12:29:17 PM PST 24
Peak memory 204692 kb
Host smart-ce66cbac-70c5-42f2-bde0-0436bd6e5297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91772715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.91772715
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1435086359
Short name T463
Test name
Test status
Simulation time 1019766549 ps
CPU time 6.05 seconds
Started Feb 08 12:28:40 PM PST 24
Finished Feb 08 12:29:19 PM PST 24
Peak memory 213356 kb
Host smart-7f98aa74-dae5-46aa-b00b-25e43fdd5823
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435086359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1435086359
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2641750831
Short name T113
Test name
Test status
Simulation time 109290037 ps
CPU time 5.39 seconds
Started Feb 08 12:28:44 PM PST 24
Finished Feb 08 12:29:23 PM PST 24
Peak memory 213632 kb
Host smart-868957b2-09f8-4ddf-90ad-48b566df3381
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641750831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2641750831
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2504165686
Short name T550
Test name
Test status
Simulation time 639245647 ps
CPU time 3.35 seconds
Started Feb 08 12:28:43 PM PST 24
Finished Feb 08 12:29:20 PM PST 24
Peak memory 213396 kb
Host smart-4cea0c86-4cd6-4339-8cea-5b5c11b6c016
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504165686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2504165686
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3027709304
Short name T526
Test name
Test status
Simulation time 103797738 ps
CPU time 1.5 seconds
Started Feb 08 12:28:42 PM PST 24
Finished Feb 08 12:29:17 PM PST 24
Peak memory 213360 kb
Host smart-c9334bac-a7aa-419c-aaf8-78f20623ecdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027709304 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3027709304
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.249464976
Short name T137
Test name
Test status
Simulation time 23180904 ps
CPU time 0.85 seconds
Started Feb 08 12:28:50 PM PST 24
Finished Feb 08 12:29:24 PM PST 24
Peak memory 204968 kb
Host smart-61263b2a-e65d-4857-91de-f78278dee9fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249464976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.249464976
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3453626816
Short name T485
Test name
Test status
Simulation time 45580034 ps
CPU time 0.82 seconds
Started Feb 08 12:28:50 PM PST 24
Finished Feb 08 12:29:24 PM PST 24
Peak memory 204980 kb
Host smart-be507aa6-9b64-4bb0-bdfe-aa37c6289f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453626816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3453626816
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.154203921
Short name T144
Test name
Test status
Simulation time 50973770 ps
CPU time 1.89 seconds
Started Feb 08 12:28:40 PM PST 24
Finished Feb 08 12:29:15 PM PST 24
Peak memory 205088 kb
Host smart-a1099554-3345-471c-bf20-006f4d282fea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154203921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.154203921
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3817458571
Short name T538
Test name
Test status
Simulation time 338300828 ps
CPU time 1.85 seconds
Started Feb 08 12:28:39 PM PST 24
Finished Feb 08 12:29:14 PM PST 24
Peak memory 213460 kb
Host smart-3a0c501f-fa14-4349-a183-5d92f025a26c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817458571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3817458571
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4214757286
Short name T121
Test name
Test status
Simulation time 1273943012 ps
CPU time 7.71 seconds
Started Feb 08 12:28:44 PM PST 24
Finished Feb 08 12:29:25 PM PST 24
Peak memory 219824 kb
Host smart-3c85904d-8153-4ef7-b012-c4050314f1a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214757286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4214757286
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.105139874
Short name T545
Test name
Test status
Simulation time 68911437 ps
CPU time 2.64 seconds
Started Feb 08 12:28:42 PM PST 24
Finished Feb 08 12:29:19 PM PST 24
Peak memory 213396 kb
Host smart-3f1199ab-d37c-40af-933c-2189f419c788
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105139874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.105139874
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2928416839
Short name T478
Test name
Test status
Simulation time 424965858 ps
CPU time 4.57 seconds
Started Feb 08 12:28:46 PM PST 24
Finished Feb 08 12:29:25 PM PST 24
Peak memory 208704 kb
Host smart-9a369ea4-e142-4f57-ae68-4e8cbbeaa2b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928416839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2928416839
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3058917791
Short name T484
Test name
Test status
Simulation time 11147570 ps
CPU time 0.81 seconds
Started Feb 08 12:28:41 PM PST 24
Finished Feb 08 12:29:16 PM PST 24
Peak memory 205128 kb
Host smart-ce19d2b3-5bb2-4ba3-ab23-15060959a18b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058917791 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3058917791
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2210324398
Short name T457
Test name
Test status
Simulation time 18557667 ps
CPU time 1 seconds
Started Feb 08 12:28:50 PM PST 24
Finished Feb 08 12:29:24 PM PST 24
Peak memory 205020 kb
Host smart-486ce735-63b2-49f3-a716-c9f03e5acb6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210324398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2210324398
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1910013224
Short name T496
Test name
Test status
Simulation time 93234520 ps
CPU time 0.79 seconds
Started Feb 08 12:28:46 PM PST 24
Finished Feb 08 12:29:21 PM PST 24
Peak memory 204944 kb
Host smart-47ad6308-57f0-4b61-a71c-db61597c990c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910013224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1910013224
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.457557915
Short name T510
Test name
Test status
Simulation time 643942824 ps
CPU time 4.88 seconds
Started Feb 08 12:28:42 PM PST 24
Finished Feb 08 12:29:21 PM PST 24
Peak memory 213664 kb
Host smart-f98d564d-2629-42aa-9453-93f6a20e207f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457557915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.457557915
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.277800790
Short name T542
Test name
Test status
Simulation time 1823678211 ps
CPU time 6.21 seconds
Started Feb 08 12:28:43 PM PST 24
Finished Feb 08 12:29:23 PM PST 24
Peak memory 213520 kb
Host smart-bdfc2d4c-2e7e-4e5e-85c2-446ec0e87893
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277800790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.277800790
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1754039533
Short name T155
Test name
Test status
Simulation time 62365992 ps
CPU time 3.24 seconds
Started Feb 08 12:28:43 PM PST 24
Finished Feb 08 12:29:21 PM PST 24
Peak memory 208712 kb
Host smart-fa83817e-b996-4589-b8ed-4e660bf3c71a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754039533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1754039533
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3812262579
Short name T143
Test name
Test status
Simulation time 69280496 ps
CPU time 4.4 seconds
Started Feb 08 12:28:00 PM PST 24
Finished Feb 08 12:28:17 PM PST 24
Peak memory 204996 kb
Host smart-f43fdbbb-a3c8-42a6-9f78-fa9c080b9385
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812262579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
812262579
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.4175674924
Short name T561
Test name
Test status
Simulation time 460217112 ps
CPU time 8.3 seconds
Started Feb 08 12:27:59 PM PST 24
Finished Feb 08 12:28:19 PM PST 24
Peak memory 205004 kb
Host smart-c33b7b40-42a7-40ed-8c31-9071634c7836
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175674924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.4
175674924
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.791933292
Short name T577
Test name
Test status
Simulation time 34656490 ps
CPU time 1.41 seconds
Started Feb 08 12:27:58 PM PST 24
Finished Feb 08 12:28:10 PM PST 24
Peak memory 204896 kb
Host smart-960c856d-2325-40d9-af09-47315ed7ac16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791933292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.791933292
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3554140985
Short name T184
Test name
Test status
Simulation time 30527166 ps
CPU time 1.23 seconds
Started Feb 08 12:28:12 PM PST 24
Finished Feb 08 12:28:39 PM PST 24
Peak memory 213416 kb
Host smart-06de1193-f299-458e-b9f9-5dd9efe4caab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554140985 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3554140985
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1728271284
Short name T569
Test name
Test status
Simulation time 26595641 ps
CPU time 0.91 seconds
Started Feb 08 12:27:59 PM PST 24
Finished Feb 08 12:28:11 PM PST 24
Peak memory 204936 kb
Host smart-1030c5a1-a3bf-4670-8041-e6e121c5acdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728271284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1728271284
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3645191191
Short name T456
Test name
Test status
Simulation time 17187367 ps
CPU time 0.7 seconds
Started Feb 08 12:28:00 PM PST 24
Finished Feb 08 12:28:13 PM PST 24
Peak memory 204992 kb
Host smart-e83ede41-cd16-4387-81ff-59de3e5713c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645191191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3645191191
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.271346911
Short name T551
Test name
Test status
Simulation time 146443846 ps
CPU time 2.02 seconds
Started Feb 08 12:28:00 PM PST 24
Finished Feb 08 12:28:13 PM PST 24
Peak memory 205156 kb
Host smart-6947a87e-0123-45d1-9fb7-4ad03ca0ba6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271346911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.271346911
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2293729808
Short name T541
Test name
Test status
Simulation time 2439695595 ps
CPU time 36.38 seconds
Started Feb 08 12:28:02 PM PST 24
Finished Feb 08 12:28:52 PM PST 24
Peak memory 213600 kb
Host smart-5b539455-43d3-49f4-9bc9-5fe66fe03dbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293729808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2293729808
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.752365738
Short name T517
Test name
Test status
Simulation time 501143393 ps
CPU time 3.53 seconds
Started Feb 08 12:28:00 PM PST 24
Finished Feb 08 12:28:16 PM PST 24
Peak memory 213352 kb
Host smart-11685f9b-963d-4906-8dad-52391c09dce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752365738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.752365738
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.59114063
Short name T157
Test name
Test status
Simulation time 231231045 ps
CPU time 3.38 seconds
Started Feb 08 12:27:58 PM PST 24
Finished Feb 08 12:28:12 PM PST 24
Peak memory 213220 kb
Host smart-a7795b16-6de3-4061-9c4c-e7165e2d2deb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59114063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.59114063
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.82375414
Short name T549
Test name
Test status
Simulation time 14664649 ps
CPU time 0.88 seconds
Started Feb 08 12:28:54 PM PST 24
Finished Feb 08 12:29:29 PM PST 24
Peak memory 205004 kb
Host smart-00561c20-2ed4-4936-af84-9c860c491ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82375414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.82375414
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2469307090
Short name T531
Test name
Test status
Simulation time 10669934 ps
CPU time 0.85 seconds
Started Feb 08 12:28:59 PM PST 24
Finished Feb 08 12:29:38 PM PST 24
Peak memory 204960 kb
Host smart-c7b37b4b-4526-4db2-92a5-abb5274dd1d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469307090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2469307090
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3464367271
Short name T547
Test name
Test status
Simulation time 7601053 ps
CPU time 0.75 seconds
Started Feb 08 12:28:58 PM PST 24
Finished Feb 08 12:29:36 PM PST 24
Peak memory 205016 kb
Host smart-e10dc6b3-27e6-4230-80ec-c698d19e11fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464367271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3464367271
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2396417729
Short name T443
Test name
Test status
Simulation time 46245095 ps
CPU time 0.83 seconds
Started Feb 08 12:29:01 PM PST 24
Finished Feb 08 12:29:41 PM PST 24
Peak memory 205024 kb
Host smart-5e36be55-7193-49be-8889-e83c11c016f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396417729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2396417729
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1955776342
Short name T445
Test name
Test status
Simulation time 19402410 ps
CPU time 0.71 seconds
Started Feb 08 12:28:52 PM PST 24
Finished Feb 08 12:29:26 PM PST 24
Peak memory 204960 kb
Host smart-7e451e10-6520-4cd2-aabf-f9cc72144ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955776342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1955776342
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.870030589
Short name T557
Test name
Test status
Simulation time 13152728 ps
CPU time 0.8 seconds
Started Feb 08 12:29:00 PM PST 24
Finished Feb 08 12:29:40 PM PST 24
Peak memory 204956 kb
Host smart-2b94cf9d-9d45-41c0-a216-f0ce546352a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870030589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.870030589
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.4126107566
Short name T494
Test name
Test status
Simulation time 42323218 ps
CPU time 0.74 seconds
Started Feb 08 12:28:54 PM PST 24
Finished Feb 08 12:29:28 PM PST 24
Peak memory 204924 kb
Host smart-f7ae0c31-1d77-4ec0-a44c-0a0f16156273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126107566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.4126107566
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.773628946
Short name T506
Test name
Test status
Simulation time 9533054 ps
CPU time 0.84 seconds
Started Feb 08 12:28:54 PM PST 24
Finished Feb 08 12:29:29 PM PST 24
Peak memory 205020 kb
Host smart-07c87cb4-574e-40d3-bb11-2765dbe434f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773628946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.773628946
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.967768509
Short name T493
Test name
Test status
Simulation time 16084051 ps
CPU time 0.74 seconds
Started Feb 08 12:29:04 PM PST 24
Finished Feb 08 12:29:49 PM PST 24
Peak memory 204172 kb
Host smart-e38d8bbc-0e15-4b2f-a536-a6d6ff5978f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967768509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.967768509
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1517879229
Short name T489
Test name
Test status
Simulation time 12046522 ps
CPU time 0.81 seconds
Started Feb 08 12:28:51 PM PST 24
Finished Feb 08 12:29:24 PM PST 24
Peak memory 205000 kb
Host smart-fb798191-d242-4dff-bd7f-d9597dc900e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517879229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1517879229
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.790215825
Short name T480
Test name
Test status
Simulation time 754818036 ps
CPU time 14.25 seconds
Started Feb 08 12:28:14 PM PST 24
Finished Feb 08 12:28:54 PM PST 24
Peak memory 205096 kb
Host smart-b904322a-447a-4fc7-98fc-19a82a9a59f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790215825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.790215825
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3892040406
Short name T450
Test name
Test status
Simulation time 1188856607 ps
CPU time 6.26 seconds
Started Feb 08 12:28:12 PM PST 24
Finished Feb 08 12:28:43 PM PST 24
Peak memory 205056 kb
Host smart-028ca705-7403-409e-8202-5edbba85a7a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892040406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
892040406
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.159365178
Short name T555
Test name
Test status
Simulation time 28783907 ps
CPU time 1.16 seconds
Started Feb 08 12:28:18 PM PST 24
Finished Feb 08 12:28:47 PM PST 24
Peak memory 205168 kb
Host smart-477297ed-d6cb-44a8-94cf-f7b7f7487bef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159365178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.159365178
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.130197327
Short name T180
Test name
Test status
Simulation time 113195301 ps
CPU time 1.67 seconds
Started Feb 08 12:28:18 PM PST 24
Finished Feb 08 12:28:47 PM PST 24
Peak memory 213768 kb
Host smart-810c8c01-ae99-4ff0-b424-528ca8fbb29e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130197327 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.130197327
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3537319226
Short name T505
Test name
Test status
Simulation time 13572824 ps
CPU time 0.93 seconds
Started Feb 08 12:28:11 PM PST 24
Finished Feb 08 12:28:38 PM PST 24
Peak memory 204996 kb
Host smart-0d448b47-5bbc-4cba-88aa-d25c445f63d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537319226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3537319226
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1472424078
Short name T482
Test name
Test status
Simulation time 54141538 ps
CPU time 0.69 seconds
Started Feb 08 12:28:17 PM PST 24
Finished Feb 08 12:28:44 PM PST 24
Peak memory 205380 kb
Host smart-3dbb6c3c-9243-47aa-b3ca-b4f9804ee5fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472424078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1472424078
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2589864559
Short name T504
Test name
Test status
Simulation time 250981016 ps
CPU time 1.81 seconds
Started Feb 08 12:28:22 PM PST 24
Finished Feb 08 12:28:55 PM PST 24
Peak memory 205040 kb
Host smart-83c93193-7b78-44a1-867d-b61aa58d7382
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589864559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2589864559
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.41643531
Short name T464
Test name
Test status
Simulation time 293314400 ps
CPU time 7.77 seconds
Started Feb 08 12:28:12 PM PST 24
Finished Feb 08 12:28:45 PM PST 24
Peak memory 213540 kb
Host smart-3edfbf69-da19-423d-86d4-30a6ee2cdf70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41643531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_
reg_errors.41643531
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3043037930
Short name T568
Test name
Test status
Simulation time 283616499 ps
CPU time 6.97 seconds
Started Feb 08 12:28:15 PM PST 24
Finished Feb 08 12:28:48 PM PST 24
Peak memory 219740 kb
Host smart-a9ce9841-20c4-4e66-989d-30d648ac6f79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043037930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3043037930
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.553507962
Short name T154
Test name
Test status
Simulation time 57692015 ps
CPU time 1.81 seconds
Started Feb 08 12:28:14 PM PST 24
Finished Feb 08 12:28:41 PM PST 24
Peak memory 213344 kb
Host smart-ba0bfa62-0525-4b4e-bd24-cb35444539e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553507962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.553507962
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.262757100
Short name T458
Test name
Test status
Simulation time 11481082 ps
CPU time 0.82 seconds
Started Feb 08 12:28:55 PM PST 24
Finished Feb 08 12:29:30 PM PST 24
Peak memory 204992 kb
Host smart-acf37cf1-ec08-4145-a085-04fa2dc93205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262757100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.262757100
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1382403365
Short name T483
Test name
Test status
Simulation time 15575786 ps
CPU time 0.71 seconds
Started Feb 08 12:28:57 PM PST 24
Finished Feb 08 12:29:34 PM PST 24
Peak memory 204860 kb
Host smart-8b367683-6377-413b-9159-2e42a160f7c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382403365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1382403365
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2841359991
Short name T142
Test name
Test status
Simulation time 39542338 ps
CPU time 0.71 seconds
Started Feb 08 12:28:50 PM PST 24
Finished Feb 08 12:29:24 PM PST 24
Peak memory 204924 kb
Host smart-390425f6-cbdc-4341-b7ee-fef6cb505137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841359991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2841359991
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2823057957
Short name T491
Test name
Test status
Simulation time 21565131 ps
CPU time 0.72 seconds
Started Feb 08 12:28:48 PM PST 24
Finished Feb 08 12:29:22 PM PST 24
Peak memory 204948 kb
Host smart-d1390e15-f789-4980-bb6a-1feb160c9249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823057957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2823057957
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1762633909
Short name T139
Test name
Test status
Simulation time 29614144 ps
CPU time 0.78 seconds
Started Feb 08 12:28:58 PM PST 24
Finished Feb 08 12:29:36 PM PST 24
Peak memory 205012 kb
Host smart-46479153-a555-42dd-87f3-b227ed9d17a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762633909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1762633909
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4018526705
Short name T187
Test name
Test status
Simulation time 24004961 ps
CPU time 0.81 seconds
Started Feb 08 12:29:01 PM PST 24
Finished Feb 08 12:29:42 PM PST 24
Peak memory 204936 kb
Host smart-2c8496b6-355f-440f-8c3c-26cac23c840d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018526705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4018526705
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2642371391
Short name T556
Test name
Test status
Simulation time 86855286 ps
CPU time 0.78 seconds
Started Feb 08 12:28:54 PM PST 24
Finished Feb 08 12:29:29 PM PST 24
Peak memory 204892 kb
Host smart-3e1cb2a1-a48e-46e2-ae79-c37ee84f2309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642371391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2642371391
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2852052013
Short name T444
Test name
Test status
Simulation time 20096687 ps
CPU time 0.71 seconds
Started Feb 08 12:28:56 PM PST 24
Finished Feb 08 12:29:33 PM PST 24
Peak memory 205000 kb
Host smart-b356bd83-bc6f-4fc8-b5e2-7978fde50b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852052013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2852052013
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2982708824
Short name T452
Test name
Test status
Simulation time 8465523 ps
CPU time 0.69 seconds
Started Feb 08 12:29:08 PM PST 24
Finished Feb 08 12:29:53 PM PST 24
Peak memory 205020 kb
Host smart-afa76172-5ca8-46fd-8912-579775ba9156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982708824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2982708824
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.920553830
Short name T471
Test name
Test status
Simulation time 15510398 ps
CPU time 0.81 seconds
Started Feb 08 12:28:55 PM PST 24
Finished Feb 08 12:29:30 PM PST 24
Peak memory 204968 kb
Host smart-69b35196-84bb-4238-8706-af2cf7f67bd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920553830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.920553830
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3992534449
Short name T476
Test name
Test status
Simulation time 512030300 ps
CPU time 7.17 seconds
Started Feb 08 12:28:17 PM PST 24
Finished Feb 08 12:28:51 PM PST 24
Peak memory 205164 kb
Host smart-55a294fe-6132-4861-87b4-9a5955cb5fc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992534449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
992534449
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2625194995
Short name T528
Test name
Test status
Simulation time 1613633369 ps
CPU time 14.09 seconds
Started Feb 08 12:28:18 PM PST 24
Finished Feb 08 12:29:00 PM PST 24
Peak memory 205180 kb
Host smart-71a2ab95-1a70-49ec-aee3-e103894b400f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625194995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
625194995
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1146258136
Short name T515
Test name
Test status
Simulation time 44374198 ps
CPU time 1.56 seconds
Started Feb 08 12:28:22 PM PST 24
Finished Feb 08 12:28:55 PM PST 24
Peak memory 204976 kb
Host smart-417b90a3-509e-4a6d-b590-1ec08fb354a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146258136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
146258136
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1627673857
Short name T453
Test name
Test status
Simulation time 16421198 ps
CPU time 1.41 seconds
Started Feb 08 12:28:12 PM PST 24
Finished Feb 08 12:28:39 PM PST 24
Peak memory 213400 kb
Host smart-4a02284a-9dde-4f34-bb01-117d39375fcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627673857 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1627673857
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.401369968
Short name T514
Test name
Test status
Simulation time 60998146 ps
CPU time 1.12 seconds
Started Feb 08 12:28:18 PM PST 24
Finished Feb 08 12:28:47 PM PST 24
Peak memory 205432 kb
Host smart-c3ab731d-7571-4d57-87a2-b5d0fd37c752
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401369968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.401369968
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.282450689
Short name T498
Test name
Test status
Simulation time 206523869 ps
CPU time 0.83 seconds
Started Feb 08 12:28:14 PM PST 24
Finished Feb 08 12:28:41 PM PST 24
Peak memory 205072 kb
Host smart-2e8971f8-a879-4baf-a532-4156f0ae908f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282450689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.282450689
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.298244774
Short name T576
Test name
Test status
Simulation time 656040030 ps
CPU time 3.6 seconds
Started Feb 08 12:28:14 PM PST 24
Finished Feb 08 12:28:44 PM PST 24
Peak memory 218448 kb
Host smart-aeb400c7-2597-42cd-a2bb-d99f271f66ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298244774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.298244774
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1354407936
Short name T465
Test name
Test status
Simulation time 205897170 ps
CPU time 4.65 seconds
Started Feb 08 12:28:13 PM PST 24
Finished Feb 08 12:28:43 PM PST 24
Peak memory 219640 kb
Host smart-a777859c-dcee-489a-970d-7d7dd8621bb4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354407936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1354407936
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3877026420
Short name T179
Test name
Test status
Simulation time 56471992 ps
CPU time 1.66 seconds
Started Feb 08 12:28:14 PM PST 24
Finished Feb 08 12:28:41 PM PST 24
Peak memory 215564 kb
Host smart-d5d3297d-40e9-4508-a85c-469f5203cfa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877026420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3877026420
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2751111950
Short name T409
Test name
Test status
Simulation time 504280438 ps
CPU time 11.94 seconds
Started Feb 08 12:28:17 PM PST 24
Finished Feb 08 12:28:56 PM PST 24
Peak memory 213372 kb
Host smart-a874d269-9e19-4473-9ab6-d14af51c5c13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751111950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2751111950
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2778118386
Short name T454
Test name
Test status
Simulation time 13339602 ps
CPU time 0.73 seconds
Started Feb 08 12:29:04 PM PST 24
Finished Feb 08 12:29:48 PM PST 24
Peak memory 204932 kb
Host smart-0c758f9f-ac54-466d-8224-e26eda38761c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778118386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2778118386
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.4259191286
Short name T486
Test name
Test status
Simulation time 14698748 ps
CPU time 0.89 seconds
Started Feb 08 12:29:04 PM PST 24
Finished Feb 08 12:29:49 PM PST 24
Peak memory 204472 kb
Host smart-24b4b5d4-a6a7-4c83-8fea-e0cc9c4b48a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259191286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.4259191286
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2223004606
Short name T188
Test name
Test status
Simulation time 106936120 ps
CPU time 0.77 seconds
Started Feb 08 12:28:57 PM PST 24
Finished Feb 08 12:29:35 PM PST 24
Peak memory 205000 kb
Host smart-e4f1e1d2-89b4-412e-b498-74585d68fed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223004606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2223004606
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2289938337
Short name T497
Test name
Test status
Simulation time 53814608 ps
CPU time 0.73 seconds
Started Feb 08 12:28:55 PM PST 24
Finished Feb 08 12:29:30 PM PST 24
Peak memory 205080 kb
Host smart-8e7d94de-e8b7-4bc4-b9be-9baf56f06131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289938337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2289938337
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2554680175
Short name T447
Test name
Test status
Simulation time 22165381 ps
CPU time 1.05 seconds
Started Feb 08 12:29:01 PM PST 24
Finished Feb 08 12:29:44 PM PST 24
Peak memory 205060 kb
Host smart-7883788c-7dcb-4b7d-93c5-5983fa793316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554680175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2554680175
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1075444068
Short name T448
Test name
Test status
Simulation time 103160742 ps
CPU time 0.84 seconds
Started Feb 08 12:29:01 PM PST 24
Finished Feb 08 12:29:42 PM PST 24
Peak memory 205032 kb
Host smart-75b8c71c-0585-4736-8b57-68892e77b812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075444068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1075444068
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1229882657
Short name T554
Test name
Test status
Simulation time 43903371 ps
CPU time 0.83 seconds
Started Feb 08 12:29:12 PM PST 24
Finished Feb 08 12:29:56 PM PST 24
Peak memory 205000 kb
Host smart-3e54c338-3b31-4b6a-9599-9a79d24c0acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229882657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1229882657
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1886621669
Short name T533
Test name
Test status
Simulation time 11889320 ps
CPU time 0.71 seconds
Started Feb 08 12:29:02 PM PST 24
Finished Feb 08 12:29:44 PM PST 24
Peak memory 204960 kb
Host smart-3d7b69c1-5306-4ed3-bde3-bce42e60d351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886621669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1886621669
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1117009607
Short name T455
Test name
Test status
Simulation time 12035750 ps
CPU time 0.74 seconds
Started Feb 08 12:28:57 PM PST 24
Finished Feb 08 12:29:34 PM PST 24
Peak memory 204968 kb
Host smart-8664dc6a-5443-402b-b751-04e6c4039efb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117009607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1117009607
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3027793292
Short name T507
Test name
Test status
Simulation time 8753766 ps
CPU time 0.73 seconds
Started Feb 08 12:29:01 PM PST 24
Finished Feb 08 12:29:42 PM PST 24
Peak memory 205024 kb
Host smart-1e866b50-c348-4df0-aadc-fdf53b74aee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027793292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3027793292
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3732054684
Short name T178
Test name
Test status
Simulation time 29840763 ps
CPU time 1.51 seconds
Started Feb 08 12:28:20 PM PST 24
Finished Feb 08 12:28:52 PM PST 24
Peak memory 213340 kb
Host smart-d655bd75-e356-48cc-9619-c1926b77266d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732054684 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3732054684
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3125596855
Short name T466
Test name
Test status
Simulation time 21088203 ps
CPU time 0.92 seconds
Started Feb 08 12:28:13 PM PST 24
Finished Feb 08 12:28:39 PM PST 24
Peak memory 204928 kb
Host smart-1a96e406-9fa2-48fb-b7ea-823fb62097f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125596855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3125596855
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.207913382
Short name T488
Test name
Test status
Simulation time 12512776 ps
CPU time 0.7 seconds
Started Feb 08 12:28:19 PM PST 24
Finished Feb 08 12:28:49 PM PST 24
Peak memory 204956 kb
Host smart-facb68ab-882a-4b67-a67f-0599971a63ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207913382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.207913382
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4258285120
Short name T520
Test name
Test status
Simulation time 25136818 ps
CPU time 1.39 seconds
Started Feb 08 12:28:20 PM PST 24
Finished Feb 08 12:28:52 PM PST 24
Peak memory 204940 kb
Host smart-7f50b803-d100-44a4-b880-e5846faef7e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258285120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4258285120
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3822043515
Short name T477
Test name
Test status
Simulation time 753251995 ps
CPU time 4.45 seconds
Started Feb 08 12:28:22 PM PST 24
Finished Feb 08 12:28:58 PM PST 24
Peak memory 213540 kb
Host smart-d50d972f-54f2-460d-a80e-32dca4bbfaaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822043515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3822043515
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3571250250
Short name T470
Test name
Test status
Simulation time 352217517 ps
CPU time 2.39 seconds
Started Feb 08 12:28:20 PM PST 24
Finished Feb 08 12:28:53 PM PST 24
Peak memory 215428 kb
Host smart-977c63b5-fad3-4279-91dc-4d5c0ddcad54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571250250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3571250250
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3374717307
Short name T174
Test name
Test status
Simulation time 193306891 ps
CPU time 5.15 seconds
Started Feb 08 12:28:16 PM PST 24
Finished Feb 08 12:28:48 PM PST 24
Peak memory 213372 kb
Host smart-db91a655-3893-4d7a-81c5-30770113c147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374717307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3374717307
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.596919641
Short name T189
Test name
Test status
Simulation time 34498239 ps
CPU time 1.23 seconds
Started Feb 08 12:28:14 PM PST 24
Finished Feb 08 12:28:40 PM PST 24
Peak memory 213420 kb
Host smart-2d465a4e-23f5-480e-aa6d-771e1c0bcef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596919641 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.596919641
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.474702831
Short name T508
Test name
Test status
Simulation time 99173295 ps
CPU time 1.06 seconds
Started Feb 08 12:28:16 PM PST 24
Finished Feb 08 12:28:43 PM PST 24
Peak memory 205040 kb
Host smart-e0b04474-f910-4962-a56b-77f2a419f603
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474702831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.474702831
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2634502627
Short name T512
Test name
Test status
Simulation time 36770120 ps
CPU time 0.73 seconds
Started Feb 08 12:28:16 PM PST 24
Finished Feb 08 12:28:43 PM PST 24
Peak memory 204976 kb
Host smart-7b6badcc-eb4d-4308-82de-1bdd2b6d39b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634502627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2634502627
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3481153013
Short name T475
Test name
Test status
Simulation time 33857413 ps
CPU time 2.03 seconds
Started Feb 08 12:28:22 PM PST 24
Finished Feb 08 12:28:55 PM PST 24
Peak memory 205080 kb
Host smart-09fff558-ef24-4620-95b1-69b3bc8168e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481153013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3481153013
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3907726423
Short name T500
Test name
Test status
Simulation time 333729087 ps
CPU time 4.74 seconds
Started Feb 08 12:28:12 PM PST 24
Finished Feb 08 12:28:43 PM PST 24
Peak memory 213544 kb
Host smart-d82bb5be-8bf9-41ff-b063-d6d960d366c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907726423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3907726423
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3897325208
Short name T546
Test name
Test status
Simulation time 87546606 ps
CPU time 1.5 seconds
Started Feb 08 12:28:13 PM PST 24
Finished Feb 08 12:28:40 PM PST 24
Peak memory 213424 kb
Host smart-f7eab855-9da2-4cf3-a2ed-a1905a8a4184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897325208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3897325208
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.4144584568
Short name T518
Test name
Test status
Simulation time 197636945 ps
CPU time 3.28 seconds
Started Feb 08 12:28:20 PM PST 24
Finished Feb 08 12:28:54 PM PST 24
Peak memory 208216 kb
Host smart-86260af2-d8ed-4400-a480-c994bfdf5dbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144584568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.4144584568
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1882236983
Short name T490
Test name
Test status
Simulation time 111620119 ps
CPU time 1.29 seconds
Started Feb 08 12:28:17 PM PST 24
Finished Feb 08 12:28:47 PM PST 24
Peak memory 213372 kb
Host smart-32efc673-5efa-4a38-988a-6dec9011b5e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882236983 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1882236983
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1195074305
Short name T540
Test name
Test status
Simulation time 202313074 ps
CPU time 1.11 seconds
Started Feb 08 12:28:15 PM PST 24
Finished Feb 08 12:28:42 PM PST 24
Peak memory 205140 kb
Host smart-88c7f030-e4ee-4a6f-8fba-477720b94de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195074305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1195074305
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.513564039
Short name T516
Test name
Test status
Simulation time 24458352 ps
CPU time 0.81 seconds
Started Feb 08 12:28:13 PM PST 24
Finished Feb 08 12:28:39 PM PST 24
Peak memory 204988 kb
Host smart-ee0bc436-4afb-45f9-8f2d-85bfdb093d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513564039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.513564039
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1574559069
Short name T558
Test name
Test status
Simulation time 710586435 ps
CPU time 1.48 seconds
Started Feb 08 12:28:21 PM PST 24
Finished Feb 08 12:28:52 PM PST 24
Peak memory 204976 kb
Host smart-e7971849-5ec8-4c42-b41b-e2f6c867e8ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574559069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1574559069
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4145289938
Short name T185
Test name
Test status
Simulation time 711255613 ps
CPU time 12.98 seconds
Started Feb 08 12:28:16 PM PST 24
Finished Feb 08 12:28:55 PM PST 24
Peak memory 213964 kb
Host smart-2a0f35c5-4549-4f87-9545-95b64d2065e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145289938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.4145289938
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1561905000
Short name T559
Test name
Test status
Simulation time 350136065 ps
CPU time 3.01 seconds
Started Feb 08 12:28:16 PM PST 24
Finished Feb 08 12:28:45 PM PST 24
Peak memory 214764 kb
Host smart-d3fd90c9-a5ce-4944-9510-c88d5ae86b56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561905000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1561905000
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3064691951
Short name T511
Test name
Test status
Simulation time 21526060 ps
CPU time 1.63 seconds
Started Feb 08 12:28:21 PM PST 24
Finished Feb 08 12:28:52 PM PST 24
Peak memory 213304 kb
Host smart-1954af3a-b198-4b59-9985-633d075376b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064691951 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3064691951
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.527640308
Short name T535
Test name
Test status
Simulation time 54127796 ps
CPU time 0.67 seconds
Started Feb 08 12:28:19 PM PST 24
Finished Feb 08 12:28:47 PM PST 24
Peak memory 205000 kb
Host smart-8717b4ce-f291-4a92-976f-5ff59acb7cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527640308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.527640308
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1695051440
Short name T532
Test name
Test status
Simulation time 327428477 ps
CPU time 2.33 seconds
Started Feb 08 12:28:20 PM PST 24
Finished Feb 08 12:28:52 PM PST 24
Peak memory 205104 kb
Host smart-a9a3275c-9ccd-48f9-89f8-e45659d02e9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695051440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1695051440
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3770098816
Short name T571
Test name
Test status
Simulation time 314102307 ps
CPU time 7.62 seconds
Started Feb 08 12:28:19 PM PST 24
Finished Feb 08 12:28:54 PM PST 24
Peak memory 213604 kb
Host smart-3be2de6d-1160-4e37-8a7a-2ffdc3e16cb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770098816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3770098816
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.846383459
Short name T495
Test name
Test status
Simulation time 1709234227 ps
CPU time 10.1 seconds
Started Feb 08 12:28:20 PM PST 24
Finished Feb 08 12:29:01 PM PST 24
Peak memory 213404 kb
Host smart-72649417-37c9-426d-a80b-47b8afadba6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846383459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.846383459
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3670830270
Short name T125
Test name
Test status
Simulation time 74715050 ps
CPU time 1.88 seconds
Started Feb 08 12:28:20 PM PST 24
Finished Feb 08 12:28:52 PM PST 24
Peak memory 213404 kb
Host smart-96040366-e4fd-4b88-ae57-16abdc1256d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670830270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3670830270
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3226127197
Short name T553
Test name
Test status
Simulation time 25206234 ps
CPU time 1.26 seconds
Started Feb 08 12:28:36 PM PST 24
Finished Feb 08 12:29:09 PM PST 24
Peak memory 213404 kb
Host smart-36dde63c-04ed-43cd-b3ca-e8357bc2645f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226127197 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3226127197
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2983346045
Short name T570
Test name
Test status
Simulation time 28797505 ps
CPU time 1.23 seconds
Started Feb 08 12:28:38 PM PST 24
Finished Feb 08 12:29:11 PM PST 24
Peak memory 204972 kb
Host smart-460a956f-1d50-4e13-b25d-39e9634be210
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983346045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2983346045
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2764505054
Short name T186
Test name
Test status
Simulation time 50030045 ps
CPU time 0.74 seconds
Started Feb 08 12:28:38 PM PST 24
Finished Feb 08 12:29:11 PM PST 24
Peak memory 204996 kb
Host smart-6017cd57-d262-49df-a0f9-388df85e154c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764505054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2764505054
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3159818514
Short name T459
Test name
Test status
Simulation time 207295649 ps
CPU time 1.65 seconds
Started Feb 08 12:28:39 PM PST 24
Finished Feb 08 12:29:12 PM PST 24
Peak memory 205156 kb
Host smart-04336264-db89-4527-9395-dc5cf467eae7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159818514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3159818514
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2453937631
Short name T523
Test name
Test status
Simulation time 1433713236 ps
CPU time 6.42 seconds
Started Feb 08 12:28:21 PM PST 24
Finished Feb 08 12:28:57 PM PST 24
Peak memory 213432 kb
Host smart-00f02f46-dd88-4f07-a321-8518a3e3e2bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453937631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2453937631
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3979683896
Short name T522
Test name
Test status
Simulation time 990108473 ps
CPU time 9.46 seconds
Started Feb 08 12:28:19 PM PST 24
Finished Feb 08 12:28:57 PM PST 24
Peak memory 213456 kb
Host smart-71055377-8e20-4490-8550-660db39453bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979683896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3979683896
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2474178647
Short name T552
Test name
Test status
Simulation time 358992978 ps
CPU time 2.38 seconds
Started Feb 08 12:28:39 PM PST 24
Finished Feb 08 12:29:14 PM PST 24
Peak memory 214416 kb
Host smart-cf6554ca-9e8e-4219-922e-052b1eab5d50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474178647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2474178647
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.660062422
Short name T616
Test name
Test status
Simulation time 24162368 ps
CPU time 0.69 seconds
Started Feb 08 01:03:59 PM PST 24
Finished Feb 08 01:04:01 PM PST 24
Peak memory 205764 kb
Host smart-62a1a050-da88-42b8-ba60-a06a39bb551f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660062422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.660062422
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2182309583
Short name T11
Test name
Test status
Simulation time 309106230 ps
CPU time 4.18 seconds
Started Feb 08 01:04:04 PM PST 24
Finished Feb 08 01:04:09 PM PST 24
Peak memory 218996 kb
Host smart-27975f25-3f64-4dbd-9607-bf91d6437a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182309583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2182309583
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2405996947
Short name T57
Test name
Test status
Simulation time 56362859 ps
CPU time 2.84 seconds
Started Feb 08 01:04:00 PM PST 24
Finished Feb 08 01:04:05 PM PST 24
Peak memory 218272 kb
Host smart-b51299f6-01c3-42ef-b44c-900865eae421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405996947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2405996947
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2977755002
Short name T772
Test name
Test status
Simulation time 293926176 ps
CPU time 4.37 seconds
Started Feb 08 01:03:56 PM PST 24
Finished Feb 08 01:04:02 PM PST 24
Peak memory 209972 kb
Host smart-02b5c14c-3fba-42f1-acee-973fa6e8dac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977755002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2977755002
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.392081213
Short name T936
Test name
Test status
Simulation time 96233218 ps
CPU time 4.84 seconds
Started Feb 08 01:03:58 PM PST 24
Finished Feb 08 01:04:04 PM PST 24
Peak memory 208972 kb
Host smart-86293088-19c1-4713-9f28-442c9b711e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392081213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.392081213
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2940820174
Short name T14
Test name
Test status
Simulation time 388904324 ps
CPU time 8.88 seconds
Started Feb 08 01:04:02 PM PST 24
Finished Feb 08 01:04:13 PM PST 24
Peak memory 237588 kb
Host smart-054cf960-9eca-4905-a7ba-b2eccdd6243b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940820174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2940820174
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.14904299
Short name T941
Test name
Test status
Simulation time 91783540 ps
CPU time 1.99 seconds
Started Feb 08 01:03:54 PM PST 24
Finished Feb 08 01:03:57 PM PST 24
Peak memory 208628 kb
Host smart-c2b197d3-5716-4140-898f-2e1f108846bc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14904299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.14904299
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2922900101
Short name T740
Test name
Test status
Simulation time 193560496 ps
CPU time 2.8 seconds
Started Feb 08 01:03:53 PM PST 24
Finished Feb 08 01:03:56 PM PST 24
Peak memory 208000 kb
Host smart-f3635105-f764-4f92-b21c-80d14ad9fc97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922900101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2922900101
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1122616511
Short name T1071
Test name
Test status
Simulation time 155305697 ps
CPU time 3.83 seconds
Started Feb 08 01:03:54 PM PST 24
Finished Feb 08 01:03:58 PM PST 24
Peak memory 207584 kb
Host smart-f33b281a-3ef2-48e1-a755-f509d8405f9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122616511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1122616511
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3078132209
Short name T199
Test name
Test status
Simulation time 445570824 ps
CPU time 3.79 seconds
Started Feb 08 01:03:55 PM PST 24
Finished Feb 08 01:03:59 PM PST 24
Peak memory 210140 kb
Host smart-272a1bc0-d2a9-4a7c-a18e-34abb50b0332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078132209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3078132209
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.862908339
Short name T881
Test name
Test status
Simulation time 716168849 ps
CPU time 3.26 seconds
Started Feb 08 01:04:00 PM PST 24
Finished Feb 08 01:04:05 PM PST 24
Peak memory 206700 kb
Host smart-dd3316af-0ead-4f91-820d-063a3c17cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862908339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.862908339
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3069372891
Short name T946
Test name
Test status
Simulation time 3965003413 ps
CPU time 84.65 seconds
Started Feb 08 01:04:08 PM PST 24
Finished Feb 08 01:05:34 PM PST 24
Peak memory 216372 kb
Host smart-956b62f9-a3d8-4f1b-a4e7-41fb0249b348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069372891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3069372891
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3070552439
Short name T222
Test name
Test status
Simulation time 1156089651 ps
CPU time 10.17 seconds
Started Feb 08 01:03:56 PM PST 24
Finished Feb 08 01:04:08 PM PST 24
Peak memory 222516 kb
Host smart-481a1fc3-2424-4b38-8ce2-1eedb70d23bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070552439 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3070552439
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2957541479
Short name T1019
Test name
Test status
Simulation time 194189964 ps
CPU time 5.65 seconds
Started Feb 08 01:04:00 PM PST 24
Finished Feb 08 01:04:08 PM PST 24
Peak memory 209148 kb
Host smart-17171b28-8743-4329-85ba-6a678129d7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957541479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2957541479
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.489983489
Short name T794
Test name
Test status
Simulation time 171893776 ps
CPU time 3.45 seconds
Started Feb 08 01:03:55 PM PST 24
Finished Feb 08 01:03:59 PM PST 24
Peak memory 210372 kb
Host smart-6c006fc9-04b2-48ba-a346-fad978a0a0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489983489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.489983489
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2962495296
Short name T106
Test name
Test status
Simulation time 41362056 ps
CPU time 0.72 seconds
Started Feb 08 01:03:59 PM PST 24
Finished Feb 08 01:04:01 PM PST 24
Peak memory 205880 kb
Host smart-d0b87b3c-9825-4b85-8554-a27612630c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962495296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2962495296
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.310352280
Short name T200
Test name
Test status
Simulation time 525270979 ps
CPU time 13.04 seconds
Started Feb 08 01:03:56 PM PST 24
Finished Feb 08 01:04:10 PM PST 24
Peak memory 214668 kb
Host smart-5579b332-9823-4a2b-bac2-6bf19c13e084
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=310352280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.310352280
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1666188114
Short name T796
Test name
Test status
Simulation time 162378069 ps
CPU time 3.39 seconds
Started Feb 08 01:04:01 PM PST 24
Finished Feb 08 01:04:06 PM PST 24
Peak memory 209712 kb
Host smart-24d332ab-cd58-487b-b560-0ca79cb63c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666188114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1666188114
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2591288171
Short name T92
Test name
Test status
Simulation time 164856638 ps
CPU time 4.42 seconds
Started Feb 08 01:04:01 PM PST 24
Finished Feb 08 01:04:07 PM PST 24
Peak memory 208616 kb
Host smart-f2593d29-9866-4a2d-ad41-86195c80aea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591288171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2591288171
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.848164926
Short name T316
Test name
Test status
Simulation time 2301659526 ps
CPU time 16.41 seconds
Started Feb 08 01:04:02 PM PST 24
Finished Feb 08 01:04:20 PM PST 24
Peak memory 222484 kb
Host smart-d98c9ba9-bd86-4100-aac0-a67b0d7478b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848164926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.848164926
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_random.3401486896
Short name T242
Test name
Test status
Simulation time 477388805 ps
CPU time 9.41 seconds
Started Feb 08 01:03:57 PM PST 24
Finished Feb 08 01:04:07 PM PST 24
Peak memory 207544 kb
Host smart-687dfbf6-18cf-4dab-baf6-649d71c15f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401486896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3401486896
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2623730884
Short name T103
Test name
Test status
Simulation time 4600649470 ps
CPU time 108.8 seconds
Started Feb 08 01:03:58 PM PST 24
Finished Feb 08 01:05:48 PM PST 24
Peak memory 262744 kb
Host smart-7545811a-de76-480b-b3c9-29d6d9d0813f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623730884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2623730884
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.740361932
Short name T708
Test name
Test status
Simulation time 437887034 ps
CPU time 3.9 seconds
Started Feb 08 01:03:56 PM PST 24
Finished Feb 08 01:04:01 PM PST 24
Peak memory 207320 kb
Host smart-fbadcc40-0de6-4499-9019-b72d65fab02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740361932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.740361932
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.396114816
Short name T654
Test name
Test status
Simulation time 50121259 ps
CPU time 2.72 seconds
Started Feb 08 01:04:01 PM PST 24
Finished Feb 08 01:04:05 PM PST 24
Peak memory 208476 kb
Host smart-b9ae37fe-02d7-452c-a152-24ed04bc9dbf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396114816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.396114816
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1889006658
Short name T214
Test name
Test status
Simulation time 274228442 ps
CPU time 7.97 seconds
Started Feb 08 01:04:01 PM PST 24
Finished Feb 08 01:04:11 PM PST 24
Peak memory 208672 kb
Host smart-c521a7c2-810e-428a-ac6e-291beffce22f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889006658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1889006658
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1451329930
Short name T629
Test name
Test status
Simulation time 54689893 ps
CPU time 2.9 seconds
Started Feb 08 01:03:52 PM PST 24
Finished Feb 08 01:03:56 PM PST 24
Peak memory 206916 kb
Host smart-9d3c3a74-64c6-4e41-bf28-83d9b31d9fa7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451329930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1451329930
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1273040686
Short name T206
Test name
Test status
Simulation time 80795765 ps
CPU time 2.15 seconds
Started Feb 08 01:03:58 PM PST 24
Finished Feb 08 01:04:01 PM PST 24
Peak memory 207352 kb
Host smart-31655ee8-d4a6-4cff-a453-781cc2caeca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273040686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1273040686
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3742097172
Short name T581
Test name
Test status
Simulation time 146362185 ps
CPU time 3.18 seconds
Started Feb 08 01:04:01 PM PST 24
Finished Feb 08 01:04:06 PM PST 24
Peak memory 206740 kb
Host smart-918b364e-3a11-48d3-a1b1-64c80a798875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742097172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3742097172
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.4153174441
Short name T1050
Test name
Test status
Simulation time 1855031416 ps
CPU time 47.02 seconds
Started Feb 08 01:03:54 PM PST 24
Finished Feb 08 01:04:42 PM PST 24
Peak memory 216092 kb
Host smart-e05053fc-dafc-45ba-86bc-f2688330098e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153174441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.4153174441
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.914142816
Short name T235
Test name
Test status
Simulation time 210810481 ps
CPU time 13.68 seconds
Started Feb 08 01:04:05 PM PST 24
Finished Feb 08 01:04:20 PM PST 24
Peak memory 223380 kb
Host smart-f80f1b86-0483-4cd0-9659-42cc231099d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914142816 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.914142816
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.295161008
Short name T738
Test name
Test status
Simulation time 12101246521 ps
CPU time 70.64 seconds
Started Feb 08 01:04:03 PM PST 24
Finished Feb 08 01:05:15 PM PST 24
Peak memory 218264 kb
Host smart-3d77a63f-2276-4371-8569-f89bf5f75d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295161008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.295161008
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3959032812
Short name T1056
Test name
Test status
Simulation time 56809227 ps
CPU time 1.54 seconds
Started Feb 08 01:03:54 PM PST 24
Finished Feb 08 01:03:57 PM PST 24
Peak memory 210116 kb
Host smart-93d5fb07-23bf-4805-a8b0-61045b44e2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959032812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3959032812
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.440801530
Short name T240
Test name
Test status
Simulation time 343906948 ps
CPU time 5.18 seconds
Started Feb 08 01:05:41 PM PST 24
Finished Feb 08 01:05:48 PM PST 24
Peak memory 215112 kb
Host smart-5e202ecb-dd64-49a3-a52d-1044d1919329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440801530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.440801530
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2698629787
Short name T994
Test name
Test status
Simulation time 1449593181 ps
CPU time 4.28 seconds
Started Feb 08 01:05:38 PM PST 24
Finished Feb 08 01:05:43 PM PST 24
Peak memory 214288 kb
Host smart-8c515147-fc03-40d1-8d6d-7e3e687be10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698629787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2698629787
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.4031711066
Short name T64
Test name
Test status
Simulation time 570287480 ps
CPU time 3.19 seconds
Started Feb 08 01:05:39 PM PST 24
Finished Feb 08 01:05:44 PM PST 24
Peak memory 208380 kb
Host smart-e5ba2d80-a5e5-4061-b101-ea90c13b0af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031711066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.4031711066
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3927382129
Short name T89
Test name
Test status
Simulation time 1872614539 ps
CPU time 18.23 seconds
Started Feb 08 01:05:40 PM PST 24
Finished Feb 08 01:06:01 PM PST 24
Peak memory 222440 kb
Host smart-ab712719-0c7a-475c-8f2c-c6fb5494a470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927382129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3927382129
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2166717460
Short name T216
Test name
Test status
Simulation time 1605648474 ps
CPU time 53 seconds
Started Feb 08 01:05:39 PM PST 24
Finished Feb 08 01:06:33 PM PST 24
Peak memory 217560 kb
Host smart-e825ac5a-e9dc-4ccb-b464-1e36c9ae2765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166717460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2166717460
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2065641931
Short name T901
Test name
Test status
Simulation time 53113802 ps
CPU time 3.77 seconds
Started Feb 08 01:05:42 PM PST 24
Finished Feb 08 01:05:53 PM PST 24
Peak memory 220248 kb
Host smart-5279249d-8e81-485c-aa0e-00e4da1b6d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065641931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2065641931
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1971187694
Short name T261
Test name
Test status
Simulation time 238678196 ps
CPU time 5.56 seconds
Started Feb 08 01:05:38 PM PST 24
Finished Feb 08 01:05:44 PM PST 24
Peak memory 214256 kb
Host smart-43ce916f-6881-400d-a4b3-49a00cb94f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971187694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1971187694
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3396193451
Short name T1067
Test name
Test status
Simulation time 64206932 ps
CPU time 3.38 seconds
Started Feb 08 01:05:31 PM PST 24
Finished Feb 08 01:05:35 PM PST 24
Peak memory 208844 kb
Host smart-88cd0edc-6100-4833-bc89-27724e34f729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396193451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3396193451
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.704644397
Short name T916
Test name
Test status
Simulation time 82415406 ps
CPU time 3.95 seconds
Started Feb 08 01:05:24 PM PST 24
Finished Feb 08 01:05:28 PM PST 24
Peak memory 207252 kb
Host smart-4998ef22-0493-4ec3-b47a-692754f32a95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704644397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.704644397
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2247154575
Short name T362
Test name
Test status
Simulation time 7578514419 ps
CPU time 53.5 seconds
Started Feb 08 01:05:25 PM PST 24
Finished Feb 08 01:06:19 PM PST 24
Peak memory 208752 kb
Host smart-1dc51aca-795e-4374-bd8c-defe5c680e22
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247154575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2247154575
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3415630833
Short name T432
Test name
Test status
Simulation time 109770472 ps
CPU time 2.88 seconds
Started Feb 08 01:05:39 PM PST 24
Finished Feb 08 01:05:44 PM PST 24
Peak memory 207732 kb
Host smart-7a418f04-bc53-47c7-901b-46d0157d0293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415630833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3415630833
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.851886549
Short name T626
Test name
Test status
Simulation time 1234609317 ps
CPU time 3.97 seconds
Started Feb 08 01:05:21 PM PST 24
Finished Feb 08 01:05:26 PM PST 24
Peak memory 208200 kb
Host smart-d0460213-8da2-4dbe-9d83-01e87606c7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851886549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.851886549
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2143420548
Short name T115
Test name
Test status
Simulation time 717723369 ps
CPU time 4.18 seconds
Started Feb 08 01:05:40 PM PST 24
Finished Feb 08 01:05:46 PM PST 24
Peak memory 222788 kb
Host smart-c90fb444-6f17-452e-9dec-9c9032c87788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143420548 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2143420548
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.4106329635
Short name T442
Test name
Test status
Simulation time 192724984 ps
CPU time 5.9 seconds
Started Feb 08 01:05:38 PM PST 24
Finished Feb 08 01:05:45 PM PST 24
Peak memory 209088 kb
Host smart-b0506d4f-cc59-4eba-bfe8-6f7435da7114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106329635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.4106329635
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3095388935
Short name T1001
Test name
Test status
Simulation time 61129724 ps
CPU time 0.78 seconds
Started Feb 08 01:05:44 PM PST 24
Finished Feb 08 01:05:56 PM PST 24
Peak memory 205304 kb
Host smart-74e92cb9-c6e5-48c7-af2f-862c604ea029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095388935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3095388935
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2727127945
Short name T440
Test name
Test status
Simulation time 1239950709 ps
CPU time 10.53 seconds
Started Feb 08 01:05:44 PM PST 24
Finished Feb 08 01:06:06 PM PST 24
Peak memory 214288 kb
Host smart-ffc9d2c9-df1a-472b-992e-b484bac20c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727127945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2727127945
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.632585887
Short name T227
Test name
Test status
Simulation time 144813159 ps
CPU time 6.13 seconds
Started Feb 08 01:05:45 PM PST 24
Finished Feb 08 01:06:01 PM PST 24
Peak memory 210192 kb
Host smart-fe7b05e9-7319-4041-9d96-d2de48dca0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632585887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.632585887
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3611942541
Short name T79
Test name
Test status
Simulation time 247587693 ps
CPU time 6.86 seconds
Started Feb 08 01:05:40 PM PST 24
Finished Feb 08 01:05:49 PM PST 24
Peak memory 209676 kb
Host smart-0f02c405-00e5-46a7-a512-21aba6057991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611942541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3611942541
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2132018735
Short name T408
Test name
Test status
Simulation time 282950598 ps
CPU time 6.6 seconds
Started Feb 08 01:05:46 PM PST 24
Finished Feb 08 01:06:02 PM PST 24
Peak memory 214388 kb
Host smart-6099b51a-ff82-4b9e-aa2e-7cfe06953490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132018735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2132018735
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1362326277
Short name T844
Test name
Test status
Simulation time 225462427 ps
CPU time 9.18 seconds
Started Feb 08 01:05:43 PM PST 24
Finished Feb 08 01:06:02 PM PST 24
Peak memory 214696 kb
Host smart-aa5f5ff4-5252-4dba-af22-bde3b3b10265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362326277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1362326277
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.662814809
Short name T434
Test name
Test status
Simulation time 396918450 ps
CPU time 3.72 seconds
Started Feb 08 01:05:41 PM PST 24
Finished Feb 08 01:05:47 PM PST 24
Peak memory 220384 kb
Host smart-2994cccb-c860-4c9a-961d-851d86c3c811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662814809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.662814809
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3169151883
Short name T245
Test name
Test status
Simulation time 70584006 ps
CPU time 3.57 seconds
Started Feb 08 01:05:41 PM PST 24
Finished Feb 08 01:05:47 PM PST 24
Peak memory 207220 kb
Host smart-834b1555-7530-46bb-b450-6f7e5c3a0758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169151883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3169151883
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.350581548
Short name T111
Test name
Test status
Simulation time 86309532 ps
CPU time 1.87 seconds
Started Feb 08 01:05:42 PM PST 24
Finished Feb 08 01:05:52 PM PST 24
Peak memory 206736 kb
Host smart-9c3d6d26-c4dc-428b-9b9d-63dc8a8e8b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350581548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.350581548
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3860851563
Short name T989
Test name
Test status
Simulation time 673411267 ps
CPU time 5.03 seconds
Started Feb 08 01:05:46 PM PST 24
Finished Feb 08 01:06:00 PM PST 24
Peak memory 209204 kb
Host smart-3d5a8898-4cf6-4086-acc3-15024d34c38f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860851563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3860851563
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.4093922693
Short name T827
Test name
Test status
Simulation time 44171968 ps
CPU time 1.89 seconds
Started Feb 08 01:05:46 PM PST 24
Finished Feb 08 01:05:57 PM PST 24
Peak memory 207324 kb
Host smart-1b8f4d4c-a7c5-4664-84d2-00d55d733b3d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093922693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4093922693
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.4239368080
Short name T715
Test name
Test status
Simulation time 207476199 ps
CPU time 2.94 seconds
Started Feb 08 01:05:41 PM PST 24
Finished Feb 08 01:05:46 PM PST 24
Peak memory 206764 kb
Host smart-95ad891f-c14e-42ad-a39a-ecf20bf4f86a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239368080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.4239368080
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3546810176
Short name T630
Test name
Test status
Simulation time 248676235 ps
CPU time 3.26 seconds
Started Feb 08 01:05:45 PM PST 24
Finished Feb 08 01:05:58 PM PST 24
Peak memory 208672 kb
Host smart-c4e34418-5fd3-4bdc-af8a-9785dfd9b6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546810176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3546810176
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3149023716
Short name T820
Test name
Test status
Simulation time 199896086 ps
CPU time 2.64 seconds
Started Feb 08 01:05:39 PM PST 24
Finished Feb 08 01:05:44 PM PST 24
Peak memory 207208 kb
Host smart-b96f36b0-2305-4f2f-9039-cf591b204827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149023716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3149023716
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2727649081
Short name T714
Test name
Test status
Simulation time 581619552 ps
CPU time 4.88 seconds
Started Feb 08 01:05:44 PM PST 24
Finished Feb 08 01:06:00 PM PST 24
Peak memory 206864 kb
Host smart-6eb0e00c-7cab-41a4-ab1c-0f0dbe1a5e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727649081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2727649081
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3768433009
Short name T435
Test name
Test status
Simulation time 82746387 ps
CPU time 2.7 seconds
Started Feb 08 01:05:44 PM PST 24
Finished Feb 08 01:05:58 PM PST 24
Peak memory 214352 kb
Host smart-3058210f-9743-4c31-9366-2221f47d075f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768433009 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3768433009
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.179384049
Short name T1044
Test name
Test status
Simulation time 1174560294 ps
CPU time 35.89 seconds
Started Feb 08 01:05:46 PM PST 24
Finished Feb 08 01:06:31 PM PST 24
Peak memory 208232 kb
Host smart-6501852c-c01d-44d6-a864-83bfef70d398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179384049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.179384049
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1072101957
Short name T54
Test name
Test status
Simulation time 74832696 ps
CPU time 2.22 seconds
Started Feb 08 01:05:43 PM PST 24
Finished Feb 08 01:05:55 PM PST 24
Peak memory 210096 kb
Host smart-6151f5cb-74ac-43e2-9f5d-045ac78baa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072101957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1072101957
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.4061027272
Short name T848
Test name
Test status
Simulation time 54402791 ps
CPU time 0.83 seconds
Started Feb 08 01:05:51 PM PST 24
Finished Feb 08 01:06:03 PM PST 24
Peak memory 205740 kb
Host smart-b7a8aaec-5a3b-4ba9-8668-af5e40f0cb9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061027272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.4061027272
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1901198008
Short name T425
Test name
Test status
Simulation time 256146799 ps
CPU time 4.28 seconds
Started Feb 08 01:05:47 PM PST 24
Finished Feb 08 01:06:00 PM PST 24
Peak memory 215372 kb
Host smart-1d13d799-3d5b-4391-a0dc-27d3edf22979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901198008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1901198008
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1221627126
Short name T929
Test name
Test status
Simulation time 380943522 ps
CPU time 3.52 seconds
Started Feb 08 01:05:47 PM PST 24
Finished Feb 08 01:05:59 PM PST 24
Peak memory 221296 kb
Host smart-535a02fd-6f9d-40d8-a7fa-4dd894b2d243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221627126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1221627126
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.783346986
Short name T1039
Test name
Test status
Simulation time 287887269 ps
CPU time 4.13 seconds
Started Feb 08 01:05:45 PM PST 24
Finished Feb 08 01:05:59 PM PST 24
Peak memory 219476 kb
Host smart-015179f5-c8b7-4f75-9684-c9a6c26a06e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783346986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.783346986
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3385301003
Short name T1061
Test name
Test status
Simulation time 80802226 ps
CPU time 4.31 seconds
Started Feb 08 01:05:47 PM PST 24
Finished Feb 08 01:05:59 PM PST 24
Peak memory 210536 kb
Host smart-1e1212aa-ba6d-47d6-8bde-0b60fdc2d210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385301003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3385301003
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1713451123
Short name T1043
Test name
Test status
Simulation time 207215241 ps
CPU time 2.79 seconds
Started Feb 08 01:05:44 PM PST 24
Finished Feb 08 01:05:58 PM PST 24
Peak memory 210012 kb
Host smart-d46a294f-1ccf-4130-96a9-be58e52742bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713451123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1713451123
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.454631900
Short name T855
Test name
Test status
Simulation time 280702816 ps
CPU time 9.13 seconds
Started Feb 08 01:05:40 PM PST 24
Finished Feb 08 01:05:52 PM PST 24
Peak memory 214300 kb
Host smart-8daf7d7e-4105-44bb-a38b-418807831b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454631900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.454631900
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.467541351
Short name T622
Test name
Test status
Simulation time 285620789 ps
CPU time 3.49 seconds
Started Feb 08 01:05:47 PM PST 24
Finished Feb 08 01:05:59 PM PST 24
Peak memory 208736 kb
Host smart-48649c0d-52e6-4946-ba96-309224e734c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467541351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.467541351
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3450027059
Short name T977
Test name
Test status
Simulation time 431224541 ps
CPU time 4.14 seconds
Started Feb 08 01:05:44 PM PST 24
Finished Feb 08 01:05:59 PM PST 24
Peak memory 208504 kb
Host smart-12f5cd27-1224-4f99-b287-8b13849c2f89
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450027059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3450027059
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3691275057
Short name T722
Test name
Test status
Simulation time 327597010 ps
CPU time 4.96 seconds
Started Feb 08 01:05:46 PM PST 24
Finished Feb 08 01:06:00 PM PST 24
Peak memory 208580 kb
Host smart-310956c5-4674-436b-96c3-8889972b329d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691275057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3691275057
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1616608498
Short name T732
Test name
Test status
Simulation time 223179217 ps
CPU time 3.04 seconds
Started Feb 08 01:05:46 PM PST 24
Finished Feb 08 01:05:58 PM PST 24
Peak memory 206844 kb
Host smart-ddd53fb9-7dcf-4fbe-be15-84109133a249
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616608498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1616608498
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.249249122
Short name T1018
Test name
Test status
Simulation time 6151343299 ps
CPU time 14.26 seconds
Started Feb 08 01:05:45 PM PST 24
Finished Feb 08 01:06:09 PM PST 24
Peak memory 209196 kb
Host smart-25da7947-9c29-4a38-83bf-800adb08b14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249249122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.249249122
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3407168506
Short name T836
Test name
Test status
Simulation time 391412589 ps
CPU time 5.45 seconds
Started Feb 08 01:05:42 PM PST 24
Finished Feb 08 01:05:54 PM PST 24
Peak memory 208528 kb
Host smart-1b4234ec-a3aa-4dac-abb3-ec1d99d069d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407168506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3407168506
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.856675878
Short name T1053
Test name
Test status
Simulation time 250902643 ps
CPU time 2.97 seconds
Started Feb 08 01:05:51 PM PST 24
Finished Feb 08 01:06:05 PM PST 24
Peak memory 206820 kb
Host smart-62087699-4a9e-4583-b550-ef69df722eca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856675878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.856675878
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2971354348
Short name T621
Test name
Test status
Simulation time 727463619 ps
CPU time 5.71 seconds
Started Feb 08 01:05:48 PM PST 24
Finished Feb 08 01:06:02 PM PST 24
Peak memory 219952 kb
Host smart-836cb27b-ee7d-485c-a156-47dc63ab8ad2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971354348 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2971354348
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.524795202
Short name T959
Test name
Test status
Simulation time 118145241 ps
CPU time 3.64 seconds
Started Feb 08 01:05:47 PM PST 24
Finished Feb 08 01:05:59 PM PST 24
Peak memory 208056 kb
Host smart-0ec3dcc9-cd8b-4fe3-8ab2-e2398cbcc903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524795202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.524795202
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3305907096
Short name T914
Test name
Test status
Simulation time 487232139 ps
CPU time 2.86 seconds
Started Feb 08 01:05:43 PM PST 24
Finished Feb 08 01:05:55 PM PST 24
Peak memory 210192 kb
Host smart-82f6694b-c005-42d2-a173-4a4287ba234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305907096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3305907096
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2783754022
Short name T797
Test name
Test status
Simulation time 14162370 ps
CPU time 0.73 seconds
Started Feb 08 01:05:40 PM PST 24
Finished Feb 08 01:05:43 PM PST 24
Peak memory 205724 kb
Host smart-e9b1cd8e-c460-4350-8037-9dce13cd9802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783754022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2783754022
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.485576575
Short name T371
Test name
Test status
Simulation time 152768288 ps
CPU time 3.11 seconds
Started Feb 08 01:05:44 PM PST 24
Finished Feb 08 01:05:58 PM PST 24
Peak memory 214912 kb
Host smart-1246648e-7818-4194-9d77-1c7da7918b49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485576575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.485576575
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1405640995
Short name T110
Test name
Test status
Simulation time 562278197 ps
CPU time 5.17 seconds
Started Feb 08 01:05:47 PM PST 24
Finished Feb 08 01:06:00 PM PST 24
Peak memory 219608 kb
Host smart-6ff11afd-eec2-4bbe-8e28-d1e3b4a9ade0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405640995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1405640995
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2041809036
Short name T971
Test name
Test status
Simulation time 1270802378 ps
CPU time 3.79 seconds
Started Feb 08 01:05:44 PM PST 24
Finished Feb 08 01:05:59 PM PST 24
Peak memory 209524 kb
Host smart-b68363b7-b7ea-43bf-8743-30b881d595d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041809036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2041809036
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.870033746
Short name T675
Test name
Test status
Simulation time 1253453587 ps
CPU time 7.14 seconds
Started Feb 08 01:05:45 PM PST 24
Finished Feb 08 01:06:02 PM PST 24
Peak memory 207428 kb
Host smart-e9756fa5-096b-4d39-a03f-6d4dd9c538e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870033746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.870033746
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1262176092
Short name T791
Test name
Test status
Simulation time 219067393 ps
CPU time 3.81 seconds
Started Feb 08 01:05:48 PM PST 24
Finished Feb 08 01:06:00 PM PST 24
Peak memory 206800 kb
Host smart-4fb3b7c6-fdf1-46fa-a10e-4dd552d8dccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262176092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1262176092
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.4205683451
Short name T862
Test name
Test status
Simulation time 3822630668 ps
CPU time 34.38 seconds
Started Feb 08 01:05:51 PM PST 24
Finished Feb 08 01:06:36 PM PST 24
Peak memory 208672 kb
Host smart-faa2e274-ee02-41b5-be2a-6f507f887725
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205683451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.4205683451
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3645254991
Short name T1070
Test name
Test status
Simulation time 352278246 ps
CPU time 3.15 seconds
Started Feb 08 01:05:47 PM PST 24
Finished Feb 08 01:05:58 PM PST 24
Peak memory 206892 kb
Host smart-d3aaae8a-a348-4b53-b169-b8f40bc6cd6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645254991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3645254991
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3820481459
Short name T1013
Test name
Test status
Simulation time 55493979 ps
CPU time 2.74 seconds
Started Feb 08 01:05:51 PM PST 24
Finished Feb 08 01:06:05 PM PST 24
Peak memory 206788 kb
Host smart-005b9cb5-2100-49e9-9f00-8a8617b3edc5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820481459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3820481459
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1885093032
Short name T1045
Test name
Test status
Simulation time 92783344 ps
CPU time 2.08 seconds
Started Feb 08 01:05:50 PM PST 24
Finished Feb 08 01:06:03 PM PST 24
Peak memory 208460 kb
Host smart-b858a04e-af5d-42d0-9a2b-ae0dec7b08e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885093032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1885093032
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.265756226
Short name T879
Test name
Test status
Simulation time 8658093777 ps
CPU time 49.91 seconds
Started Feb 08 01:05:48 PM PST 24
Finished Feb 08 01:06:46 PM PST 24
Peak memory 208892 kb
Host smart-0e353349-aa09-4581-b6f3-47fb1a7817ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265756226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.265756226
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3166517613
Short name T800
Test name
Test status
Simulation time 1616127664 ps
CPU time 12.67 seconds
Started Feb 08 01:05:47 PM PST 24
Finished Feb 08 01:06:08 PM PST 24
Peak memory 217052 kb
Host smart-e4bf1730-98fb-4187-ba9b-dc47f44c46b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166517613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3166517613
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4092165239
Short name T766
Test name
Test status
Simulation time 17131161 ps
CPU time 1.35 seconds
Started Feb 08 01:05:46 PM PST 24
Finished Feb 08 01:05:56 PM PST 24
Peak memory 208404 kb
Host smart-f92b97c8-910e-4545-a92d-4bffeabb6257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092165239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4092165239
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1950475960
Short name T803
Test name
Test status
Simulation time 66841735 ps
CPU time 0.75 seconds
Started Feb 08 01:06:08 PM PST 24
Finished Feb 08 01:06:14 PM PST 24
Peak memory 205884 kb
Host smart-d0525c15-6bcf-4398-b18d-2b29c0d688b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950475960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1950475960
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2178891503
Short name T330
Test name
Test status
Simulation time 166318935 ps
CPU time 3.23 seconds
Started Feb 08 01:06:03 PM PST 24
Finished Feb 08 01:06:09 PM PST 24
Peak memory 214256 kb
Host smart-22ebc613-e3c6-4506-8e8b-51d020445e62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178891503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2178891503
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1528585055
Short name T228
Test name
Test status
Simulation time 74958562 ps
CPU time 2.69 seconds
Started Feb 08 01:06:11 PM PST 24
Finished Feb 08 01:06:19 PM PST 24
Peak memory 219496 kb
Host smart-2a8ca867-b23f-49e4-8876-a95233fa773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528585055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1528585055
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1548142746
Short name T659
Test name
Test status
Simulation time 315529455 ps
CPU time 2.74 seconds
Started Feb 08 01:06:06 PM PST 24
Finished Feb 08 01:06:11 PM PST 24
Peak memory 218240 kb
Host smart-f5eae964-7d6f-498b-b349-17a03fb36c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548142746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1548142746
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4166676536
Short name T315
Test name
Test status
Simulation time 91580595 ps
CPU time 4.29 seconds
Started Feb 08 01:06:04 PM PST 24
Finished Feb 08 01:06:11 PM PST 24
Peak memory 211880 kb
Host smart-5f1df8a8-1114-451d-9eea-b1c3424900a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166676536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4166676536
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1117195021
Short name T231
Test name
Test status
Simulation time 153174572 ps
CPU time 5.34 seconds
Started Feb 08 01:06:08 PM PST 24
Finished Feb 08 01:06:18 PM PST 24
Peak memory 214332 kb
Host smart-612c47a9-0a12-4e24-a358-151b5f967e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117195021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1117195021
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.838798080
Short name T632
Test name
Test status
Simulation time 96406140 ps
CPU time 4.08 seconds
Started Feb 08 01:06:05 PM PST 24
Finished Feb 08 01:06:11 PM PST 24
Peak memory 209100 kb
Host smart-fe57ad46-ab4e-49ad-ab31-b371bee2b3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838798080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.838798080
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.248038699
Short name T329
Test name
Test status
Simulation time 157704968 ps
CPU time 2.49 seconds
Started Feb 08 01:06:10 PM PST 24
Finished Feb 08 01:06:18 PM PST 24
Peak memory 206844 kb
Host smart-3a7748df-5121-43d4-8a20-7ec38e17da41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248038699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.248038699
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.4221918650
Short name T591
Test name
Test status
Simulation time 417221768 ps
CPU time 8.38 seconds
Started Feb 08 01:06:05 PM PST 24
Finished Feb 08 01:06:16 PM PST 24
Peak memory 208716 kb
Host smart-17bdcb7d-1699-4433-9fe3-e8496c1cc4ee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221918650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.4221918650
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2576570236
Short name T213
Test name
Test status
Simulation time 274689831 ps
CPU time 2.97 seconds
Started Feb 08 01:06:12 PM PST 24
Finished Feb 08 01:06:20 PM PST 24
Peak memory 206728 kb
Host smart-59af57df-314c-48f4-96c6-7429c59ca744
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576570236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2576570236
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1541046321
Short name T268
Test name
Test status
Simulation time 538877358 ps
CPU time 6.29 seconds
Started Feb 08 01:06:05 PM PST 24
Finished Feb 08 01:06:14 PM PST 24
Peak memory 208280 kb
Host smart-2217d9fe-0795-4c79-a46f-d3796dd1977b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541046321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1541046321
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2425203769
Short name T419
Test name
Test status
Simulation time 388819518 ps
CPU time 2.2 seconds
Started Feb 08 01:06:12 PM PST 24
Finished Feb 08 01:06:19 PM PST 24
Peak memory 209196 kb
Host smart-db3fb1e6-3835-45e4-88fc-2f99e1ea14f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425203769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2425203769
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.983282688
Short name T203
Test name
Test status
Simulation time 41077232 ps
CPU time 2.28 seconds
Started Feb 08 01:06:10 PM PST 24
Finished Feb 08 01:06:18 PM PST 24
Peak memory 207988 kb
Host smart-e79b8869-5b77-47bb-8dab-b4efc6735992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983282688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.983282688
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.187944387
Short name T972
Test name
Test status
Simulation time 295486671 ps
CPU time 7.76 seconds
Started Feb 08 01:06:07 PM PST 24
Finished Feb 08 01:06:17 PM PST 24
Peak memory 208388 kb
Host smart-0a84362c-7954-456d-af02-c020a8290321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187944387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.187944387
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.440926927
Short name T1062
Test name
Test status
Simulation time 415166843 ps
CPU time 4.39 seconds
Started Feb 08 01:06:06 PM PST 24
Finished Feb 08 01:06:13 PM PST 24
Peak memory 219152 kb
Host smart-50a5c793-c36b-40a0-ad6d-deea59cd7ee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440926927 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.440926927
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2904845484
Short name T932
Test name
Test status
Simulation time 272641025 ps
CPU time 8.02 seconds
Started Feb 08 01:06:04 PM PST 24
Finished Feb 08 01:06:15 PM PST 24
Peak memory 218388 kb
Host smart-17f24efd-adde-4a60-9a1c-7cd2a0498d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904845484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2904845484
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.342578655
Short name T887
Test name
Test status
Simulation time 350545536 ps
CPU time 2.63 seconds
Started Feb 08 01:06:04 PM PST 24
Finished Feb 08 01:06:10 PM PST 24
Peak memory 210120 kb
Host smart-5df54037-e8ec-4e95-9928-dadc2c317c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342578655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.342578655
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1942837604
Short name T905
Test name
Test status
Simulation time 14900006 ps
CPU time 0.77 seconds
Started Feb 08 01:06:08 PM PST 24
Finished Feb 08 01:06:13 PM PST 24
Peak memory 205892 kb
Host smart-7c7bc9d8-211c-4d45-885d-8e502ee769d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942837604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1942837604
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1510354819
Short name T334
Test name
Test status
Simulation time 359248570 ps
CPU time 4.16 seconds
Started Feb 08 01:06:05 PM PST 24
Finished Feb 08 01:06:12 PM PST 24
Peak memory 214312 kb
Host smart-0e63194a-01a6-42c8-b171-8ea32985d11b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510354819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1510354819
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.38409285
Short name T299
Test name
Test status
Simulation time 93490621 ps
CPU time 2.29 seconds
Started Feb 08 01:06:07 PM PST 24
Finished Feb 08 01:06:14 PM PST 24
Peak memory 209092 kb
Host smart-10a7faf5-0f23-4abb-a065-6405826fd5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38409285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.38409285
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3471909795
Short name T321
Test name
Test status
Simulation time 796528271 ps
CPU time 6.44 seconds
Started Feb 08 01:06:07 PM PST 24
Finished Feb 08 01:06:18 PM PST 24
Peak memory 219816 kb
Host smart-4930a832-1fa9-41f7-811a-c780da9a209f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471909795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3471909795
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2175690686
Short name T252
Test name
Test status
Simulation time 525450147 ps
CPU time 5.67 seconds
Started Feb 08 01:06:06 PM PST 24
Finished Feb 08 01:06:14 PM PST 24
Peak memory 222332 kb
Host smart-453a0df4-dba7-46a6-9525-6a866772bf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175690686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2175690686
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.607571051
Short name T835
Test name
Test status
Simulation time 59092427 ps
CPU time 2.22 seconds
Started Feb 08 01:06:05 PM PST 24
Finished Feb 08 01:06:10 PM PST 24
Peak memory 207504 kb
Host smart-09a9f7bc-3cd2-4356-b02e-94dddcde015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607571051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.607571051
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2165342605
Short name T641
Test name
Test status
Simulation time 1614819719 ps
CPU time 4.9 seconds
Started Feb 08 01:06:04 PM PST 24
Finished Feb 08 01:06:12 PM PST 24
Peak memory 208092 kb
Host smart-1a4010cc-c1d1-4e77-b4d7-60933c5979a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165342605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2165342605
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.490547004
Short name T1002
Test name
Test status
Simulation time 36752414 ps
CPU time 2.46 seconds
Started Feb 08 01:06:03 PM PST 24
Finished Feb 08 01:06:09 PM PST 24
Peak memory 208396 kb
Host smart-d508f46a-1c2e-4917-b9f3-c414ec1aa3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490547004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.490547004
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3651304
Short name T417
Test name
Test status
Simulation time 410065615 ps
CPU time 2.93 seconds
Started Feb 08 01:06:02 PM PST 24
Finished Feb 08 01:06:09 PM PST 24
Peak memory 208764 kb
Host smart-5b5d99d4-5800-4181-82b2-0f78c46bd2fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3651304
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.895533241
Short name T699
Test name
Test status
Simulation time 1615461604 ps
CPU time 9.1 seconds
Started Feb 08 01:06:06 PM PST 24
Finished Feb 08 01:06:17 PM PST 24
Peak memory 208700 kb
Host smart-64088712-a6d0-4eb9-9c80-6808f43e389b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895533241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.895533241
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.324860342
Short name T872
Test name
Test status
Simulation time 54827008 ps
CPU time 2.9 seconds
Started Feb 08 01:06:11 PM PST 24
Finished Feb 08 01:06:19 PM PST 24
Peak memory 207252 kb
Host smart-f9c4499b-a82c-47e5-8df0-44fde9c47e57
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324860342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.324860342
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3822892251
Short name T947
Test name
Test status
Simulation time 126528050 ps
CPU time 1.89 seconds
Started Feb 08 01:06:06 PM PST 24
Finished Feb 08 01:06:10 PM PST 24
Peak memory 207808 kb
Host smart-a401d839-3424-4978-8489-ae6de5b9916d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822892251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3822892251
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3964264373
Short name T909
Test name
Test status
Simulation time 158500828 ps
CPU time 5.35 seconds
Started Feb 08 01:06:06 PM PST 24
Finished Feb 08 01:06:14 PM PST 24
Peak memory 206564 kb
Host smart-db922c10-151d-4ea0-a809-18af76ff2bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964264373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3964264373
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.370167610
Short name T1017
Test name
Test status
Simulation time 85019961 ps
CPU time 3.97 seconds
Started Feb 08 01:06:10 PM PST 24
Finished Feb 08 01:06:20 PM PST 24
Peak memory 217016 kb
Host smart-dd06cb7f-cbe9-4a48-8201-a24df4df446a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370167610 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.370167610
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3391137658
Short name T825
Test name
Test status
Simulation time 195662728 ps
CPU time 3.93 seconds
Started Feb 08 01:06:05 PM PST 24
Finished Feb 08 01:06:12 PM PST 24
Peak memory 209780 kb
Host smart-1745d00b-db4e-4392-8073-0682c53599eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391137658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3391137658
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.215547272
Short name T108
Test name
Test status
Simulation time 1218000391 ps
CPU time 10.32 seconds
Started Feb 08 01:06:06 PM PST 24
Finished Feb 08 01:06:19 PM PST 24
Peak memory 210168 kb
Host smart-7cb370b8-6cb0-44ae-b7a2-72257c61d0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215547272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.215547272
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.63410568
Short name T78
Test name
Test status
Simulation time 48246364 ps
CPU time 0.9 seconds
Started Feb 08 01:06:08 PM PST 24
Finished Feb 08 01:06:15 PM PST 24
Peak memory 205820 kb
Host smart-7536b025-3caa-4c6b-b9ce-5d855adf6d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63410568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.63410568
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3448400527
Short name T296
Test name
Test status
Simulation time 6182845906 ps
CPU time 54.95 seconds
Started Feb 08 01:06:09 PM PST 24
Finished Feb 08 01:07:10 PM PST 24
Peak memory 215612 kb
Host smart-e6692790-0e19-4396-b931-7e7b744f1b5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448400527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3448400527
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3440341306
Short name T59
Test name
Test status
Simulation time 463472994 ps
CPU time 3.83 seconds
Started Feb 08 01:06:12 PM PST 24
Finished Feb 08 01:06:21 PM PST 24
Peak memory 214516 kb
Host smart-40d280b6-cbb3-4412-9010-ea7831d67bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440341306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3440341306
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3844105067
Short name T749
Test name
Test status
Simulation time 20689732 ps
CPU time 1.35 seconds
Started Feb 08 01:06:04 PM PST 24
Finished Feb 08 01:06:08 PM PST 24
Peak memory 207104 kb
Host smart-bffc0987-bc94-4f54-bb4d-4599011adece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844105067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3844105067
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1773305447
Short name T951
Test name
Test status
Simulation time 258801434 ps
CPU time 3.57 seconds
Started Feb 08 01:06:14 PM PST 24
Finished Feb 08 01:06:21 PM PST 24
Peak memory 221452 kb
Host smart-e3de51c1-67f8-4300-85f1-8755dbad4b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773305447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1773305447
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1569316052
Short name T253
Test name
Test status
Simulation time 690825064 ps
CPU time 6.35 seconds
Started Feb 08 01:06:08 PM PST 24
Finished Feb 08 01:06:19 PM PST 24
Peak memory 222444 kb
Host smart-2311fdc5-55aa-4861-b4cb-b8de3c9a5acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569316052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1569316052
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1582751947
Short name T1021
Test name
Test status
Simulation time 42329551 ps
CPU time 2.36 seconds
Started Feb 08 01:06:10 PM PST 24
Finished Feb 08 01:06:18 PM PST 24
Peak memory 208396 kb
Host smart-a4f9eddc-c8f3-48c9-bc2a-5f8608cf23b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582751947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1582751947
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2263455504
Short name T308
Test name
Test status
Simulation time 124465622 ps
CPU time 5.16 seconds
Started Feb 08 01:06:04 PM PST 24
Finished Feb 08 01:06:12 PM PST 24
Peak memory 207520 kb
Host smart-87cdfbd0-abf3-4d52-947d-937766223344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263455504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2263455504
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3532848428
Short name T267
Test name
Test status
Simulation time 122036111 ps
CPU time 2.93 seconds
Started Feb 08 01:06:09 PM PST 24
Finished Feb 08 01:06:17 PM PST 24
Peak memory 208544 kb
Host smart-24a6d15d-cf27-427c-86ec-e4bcacd2bcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532848428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3532848428
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.958345205
Short name T867
Test name
Test status
Simulation time 189869838 ps
CPU time 2.77 seconds
Started Feb 08 01:06:05 PM PST 24
Finished Feb 08 01:06:10 PM PST 24
Peak memory 206756 kb
Host smart-0f3a3a14-b4a9-4bbd-8626-369ed3f58b57
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958345205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.958345205
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3027720115
Short name T627
Test name
Test status
Simulation time 54780261 ps
CPU time 2.7 seconds
Started Feb 08 01:06:08 PM PST 24
Finished Feb 08 01:06:15 PM PST 24
Peak memory 208164 kb
Host smart-490bc237-e00c-4ecf-b25b-4b94160b9169
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027720115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3027720115
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3983219101
Short name T911
Test name
Test status
Simulation time 109148054 ps
CPU time 2.48 seconds
Started Feb 08 01:06:13 PM PST 24
Finished Feb 08 01:06:19 PM PST 24
Peak memory 206816 kb
Host smart-d5eacae1-09d1-4593-8c91-5f864539598c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983219101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3983219101
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2099882699
Short name T351
Test name
Test status
Simulation time 61485257 ps
CPU time 2.56 seconds
Started Feb 08 01:06:12 PM PST 24
Finished Feb 08 01:06:19 PM PST 24
Peak memory 209908 kb
Host smart-c43617d3-9de6-4670-8437-c157cb032049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099882699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2099882699
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.498459854
Short name T883
Test name
Test status
Simulation time 388251277 ps
CPU time 6.84 seconds
Started Feb 08 01:06:04 PM PST 24
Finished Feb 08 01:06:14 PM PST 24
Peak memory 208636 kb
Host smart-d5daf024-e6b7-4757-b054-22556a9e73b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498459854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.498459854
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1852436883
Short name T229
Test name
Test status
Simulation time 4290105956 ps
CPU time 17.28 seconds
Started Feb 08 01:06:08 PM PST 24
Finished Feb 08 01:06:29 PM PST 24
Peak memory 215016 kb
Host smart-1a800c14-2dc4-461e-95a8-7cef39cd97e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852436883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1852436883
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.4289727470
Short name T221
Test name
Test status
Simulation time 1011757738 ps
CPU time 6.79 seconds
Started Feb 08 01:06:06 PM PST 24
Finished Feb 08 01:06:15 PM PST 24
Peak memory 222620 kb
Host smart-e42775d8-6bd5-4b9c-974c-b9d3dc507ba7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289727470 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.4289727470
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4098605006
Short name T378
Test name
Test status
Simulation time 248392868 ps
CPU time 4.44 seconds
Started Feb 08 01:06:06 PM PST 24
Finished Feb 08 01:06:13 PM PST 24
Peak memory 222584 kb
Host smart-10343e90-b674-434e-8f7d-db52820c3e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098605006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4098605006
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2779096043
Short name T628
Test name
Test status
Simulation time 171288164 ps
CPU time 3.82 seconds
Started Feb 08 01:06:03 PM PST 24
Finished Feb 08 01:06:10 PM PST 24
Peak memory 210420 kb
Host smart-eafc201c-62b1-4380-bd57-36e6f5f03ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779096043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2779096043
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.4116111711
Short name T631
Test name
Test status
Simulation time 40348482 ps
CPU time 0.86 seconds
Started Feb 08 01:06:18 PM PST 24
Finished Feb 08 01:06:21 PM PST 24
Peak memory 205884 kb
Host smart-799d9c8b-184d-4c56-9a0b-e0eeae09b189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116111711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.4116111711
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.4062017691
Short name T430
Test name
Test status
Simulation time 393324004 ps
CPU time 2.32 seconds
Started Feb 08 01:06:13 PM PST 24
Finished Feb 08 01:06:19 PM PST 24
Peak memory 214328 kb
Host smart-a6cebb78-9bb5-4b23-b0b8-a5b868b7852c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062017691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.4062017691
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2047506678
Short name T624
Test name
Test status
Simulation time 31966053 ps
CPU time 1.9 seconds
Started Feb 08 01:06:14 PM PST 24
Finished Feb 08 01:06:20 PM PST 24
Peak memory 214560 kb
Host smart-3f388ec8-f892-4b4e-be3b-95ce7e20a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047506678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2047506678
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1355556826
Short name T866
Test name
Test status
Simulation time 266843140 ps
CPU time 1.45 seconds
Started Feb 08 01:06:17 PM PST 24
Finished Feb 08 01:06:20 PM PST 24
Peak memory 208224 kb
Host smart-66962454-4bf9-4266-ada9-05c8ada9dac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355556826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1355556826
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.524272010
Short name T5
Test name
Test status
Simulation time 121274268 ps
CPU time 4.52 seconds
Started Feb 08 01:06:09 PM PST 24
Finished Feb 08 01:06:20 PM PST 24
Peak memory 209400 kb
Host smart-61e4e348-0fc3-417d-bac0-66275ac26a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524272010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.524272010
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2027913496
Short name T190
Test name
Test status
Simulation time 211684107 ps
CPU time 8.8 seconds
Started Feb 08 01:06:11 PM PST 24
Finished Feb 08 01:06:25 PM PST 24
Peak memory 211700 kb
Host smart-a5dd7d8d-888d-4902-8605-f91c95787919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027913496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2027913496
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1664238748
Short name T707
Test name
Test status
Simulation time 580846812 ps
CPU time 5.63 seconds
Started Feb 08 01:06:14 PM PST 24
Finished Feb 08 01:06:24 PM PST 24
Peak memory 209476 kb
Host smart-cd103442-e2d9-45d9-a3a3-98e12bd47506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664238748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1664238748
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.363732000
Short name T1040
Test name
Test status
Simulation time 208349596 ps
CPU time 4.77 seconds
Started Feb 08 01:06:18 PM PST 24
Finished Feb 08 01:06:25 PM PST 24
Peak memory 209812 kb
Host smart-b4cd567a-6ffc-453d-bf28-8f62aaec1282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363732000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.363732000
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1483073572
Short name T752
Test name
Test status
Simulation time 45554109 ps
CPU time 2.56 seconds
Started Feb 08 01:06:08 PM PST 24
Finished Feb 08 01:06:16 PM PST 24
Peak memory 208268 kb
Host smart-ed552f3f-e34d-48be-b0a6-3a359adef36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483073572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1483073572
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.769320000
Short name T595
Test name
Test status
Simulation time 196867216 ps
CPU time 4.82 seconds
Started Feb 08 01:06:05 PM PST 24
Finished Feb 08 01:06:13 PM PST 24
Peak memory 208792 kb
Host smart-7d8605d4-3906-4fb1-bfc8-2aa641aaddb1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769320000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.769320000
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.569590437
Short name T637
Test name
Test status
Simulation time 51679353 ps
CPU time 2.11 seconds
Started Feb 08 01:06:09 PM PST 24
Finished Feb 08 01:06:18 PM PST 24
Peak memory 208772 kb
Host smart-e9ecfc18-1427-456c-af5b-58531169e5d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569590437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.569590437
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1590649305
Short name T990
Test name
Test status
Simulation time 62483290 ps
CPU time 2.3 seconds
Started Feb 08 01:06:09 PM PST 24
Finished Feb 08 01:06:18 PM PST 24
Peak memory 208428 kb
Host smart-958f2673-a0b4-4134-89bd-6d1f454b34bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590649305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1590649305
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2356128475
Short name T288
Test name
Test status
Simulation time 209849395 ps
CPU time 2.89 seconds
Started Feb 08 01:06:16 PM PST 24
Finished Feb 08 01:06:21 PM PST 24
Peak memory 220400 kb
Host smart-947ee6ac-9a7c-4245-9b5f-65e7fb70f928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356128475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2356128475
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3737664135
Short name T411
Test name
Test status
Simulation time 83496601 ps
CPU time 1.82 seconds
Started Feb 08 01:06:18 PM PST 24
Finished Feb 08 01:06:22 PM PST 24
Peak memory 206944 kb
Host smart-7f142d6c-71bf-4c48-9fbe-76b9e3c39444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737664135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3737664135
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1815101985
Short name T834
Test name
Test status
Simulation time 1841412800 ps
CPU time 17.76 seconds
Started Feb 08 01:06:17 PM PST 24
Finished Feb 08 01:06:37 PM PST 24
Peak memory 219296 kb
Host smart-b7b1f55a-3b9a-49c6-b8d4-307a980f3924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815101985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1815101985
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2990854647
Short name T1028
Test name
Test status
Simulation time 76198468 ps
CPU time 3.54 seconds
Started Feb 08 01:06:18 PM PST 24
Finished Feb 08 01:06:24 PM PST 24
Peak memory 222568 kb
Host smart-2442b56c-6848-4a5a-b84a-fb5086de17f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990854647 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2990854647
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2514586770
Short name T353
Test name
Test status
Simulation time 315443488 ps
CPU time 4.15 seconds
Started Feb 08 01:06:19 PM PST 24
Finished Feb 08 01:06:25 PM PST 24
Peak memory 218408 kb
Host smart-23bb22d6-98c3-405a-bd2f-b428fbe0b716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514586770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2514586770
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2720243023
Short name T35
Test name
Test status
Simulation time 167784365 ps
CPU time 2.99 seconds
Started Feb 08 01:06:16 PM PST 24
Finished Feb 08 01:06:22 PM PST 24
Peak memory 210132 kb
Host smart-827a71b8-212b-4741-ab65-7a94055af5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720243023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2720243023
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1347644640
Short name T593
Test name
Test status
Simulation time 44363941 ps
CPU time 0.81 seconds
Started Feb 08 01:06:53 PM PST 24
Finished Feb 08 01:06:55 PM PST 24
Peak memory 205724 kb
Host smart-aac332f3-7d52-4130-9f21-99e818eec4fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347644640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1347644640
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1761046650
Short name T295
Test name
Test status
Simulation time 2000216305 ps
CPU time 56.03 seconds
Started Feb 08 01:06:40 PM PST 24
Finished Feb 08 01:07:43 PM PST 24
Peak memory 215512 kb
Host smart-5b7a32ea-387e-4273-969e-6bb236503ff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761046650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1761046650
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2023665584
Short name T655
Test name
Test status
Simulation time 113439635 ps
CPU time 2.64 seconds
Started Feb 08 01:06:46 PM PST 24
Finished Feb 08 01:06:55 PM PST 24
Peak memory 209552 kb
Host smart-d4d37d2e-4aa0-44aa-b1fa-f9738d7938d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023665584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2023665584
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.919951343
Short name T1012
Test name
Test status
Simulation time 123751568 ps
CPU time 1.47 seconds
Started Feb 08 01:06:54 PM PST 24
Finished Feb 08 01:06:57 PM PST 24
Peak memory 207188 kb
Host smart-aeedacf2-3b0d-42c5-9087-0273bd7098e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919951343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.919951343
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1489444495
Short name T86
Test name
Test status
Simulation time 41340725 ps
CPU time 2.9 seconds
Started Feb 08 01:06:53 PM PST 24
Finished Feb 08 01:06:58 PM PST 24
Peak memory 208500 kb
Host smart-f26cd1cb-bde5-4c3a-ae90-8c7474b25291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489444495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1489444495
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.236497952
Short name T926
Test name
Test status
Simulation time 3736647298 ps
CPU time 28.71 seconds
Started Feb 08 01:06:38 PM PST 24
Finished Feb 08 01:07:15 PM PST 24
Peak memory 222484 kb
Host smart-409a78ab-a49b-40ef-b9e8-0a7e34858649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236497952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.236497952
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1307453897
Short name T604
Test name
Test status
Simulation time 965435386 ps
CPU time 3.25 seconds
Started Feb 08 01:06:56 PM PST 24
Finished Feb 08 01:07:02 PM PST 24
Peak memory 214552 kb
Host smart-7a6d13c5-1884-4354-a817-35dc852871a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307453897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1307453897
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1251307358
Short name T312
Test name
Test status
Simulation time 96911994 ps
CPU time 4.31 seconds
Started Feb 08 01:06:48 PM PST 24
Finished Feb 08 01:06:57 PM PST 24
Peak memory 218528 kb
Host smart-18195466-4843-4dc0-af7f-7c9fbd164858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251307358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1251307358
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.4233906294
Short name T756
Test name
Test status
Simulation time 373720333 ps
CPU time 2.52 seconds
Started Feb 08 01:06:41 PM PST 24
Finished Feb 08 01:06:49 PM PST 24
Peak memory 208552 kb
Host smart-12b62241-ce77-4606-a677-3a114a536e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233906294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.4233906294
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2451615689
Short name T684
Test name
Test status
Simulation time 47087066 ps
CPU time 2.59 seconds
Started Feb 08 01:06:43 PM PST 24
Finished Feb 08 01:06:50 PM PST 24
Peak memory 208080 kb
Host smart-6a5cc64a-f87b-44d4-8a2e-a16fc74b7248
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451615689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2451615689
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1720515580
Short name T767
Test name
Test status
Simulation time 1792073154 ps
CPU time 8.63 seconds
Started Feb 08 01:06:52 PM PST 24
Finished Feb 08 01:07:03 PM PST 24
Peak memory 208024 kb
Host smart-c045ff34-1445-4d63-b0a8-0f9cb1bd2838
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720515580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1720515580
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3284215653
Short name T269
Test name
Test status
Simulation time 646883595 ps
CPU time 4.3 seconds
Started Feb 08 01:06:37 PM PST 24
Finished Feb 08 01:06:51 PM PST 24
Peak memory 208392 kb
Host smart-a55c8ac5-2396-4456-b28e-0d9f50fdd861
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284215653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3284215653
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1276090309
Short name T865
Test name
Test status
Simulation time 1519379219 ps
CPU time 6.41 seconds
Started Feb 08 01:06:44 PM PST 24
Finished Feb 08 01:06:54 PM PST 24
Peak memory 220540 kb
Host smart-d5089c2e-7931-4091-b65f-0bda26bb7cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276090309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1276090309
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3386328523
Short name T861
Test name
Test status
Simulation time 68518822 ps
CPU time 1.78 seconds
Started Feb 08 01:06:50 PM PST 24
Finished Feb 08 01:06:56 PM PST 24
Peak memory 206592 kb
Host smart-ef3f808f-a141-415f-9c41-9219cc7dbbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386328523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3386328523
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.353947902
Short name T928
Test name
Test status
Simulation time 5197473569 ps
CPU time 115.76 seconds
Started Feb 08 01:06:36 PM PST 24
Finished Feb 08 01:08:41 PM PST 24
Peak memory 222568 kb
Host smart-b7d8179b-7c86-4606-be56-3450adee702e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353947902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.353947902
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3037529666
Short name T823
Test name
Test status
Simulation time 174778954 ps
CPU time 2.76 seconds
Started Feb 08 01:06:39 PM PST 24
Finished Feb 08 01:06:49 PM PST 24
Peak memory 222616 kb
Host smart-bb684484-6162-4825-a009-758c0576655d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037529666 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3037529666
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.57976923
Short name T376
Test name
Test status
Simulation time 657669835 ps
CPU time 3.05 seconds
Started Feb 08 01:06:50 PM PST 24
Finished Feb 08 01:06:57 PM PST 24
Peak memory 209316 kb
Host smart-fea94837-b268-4428-90c4-c4ec4ea51a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57976923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.57976923
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3218677351
Short name T704
Test name
Test status
Simulation time 43439769 ps
CPU time 1.81 seconds
Started Feb 08 01:06:43 PM PST 24
Finished Feb 08 01:06:49 PM PST 24
Peak memory 209768 kb
Host smart-8e73efd0-2fd9-4823-963d-7e5d228f31e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218677351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3218677351
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3559245090
Short name T583
Test name
Test status
Simulation time 18496759 ps
CPU time 0.78 seconds
Started Feb 08 01:06:36 PM PST 24
Finished Feb 08 01:06:38 PM PST 24
Peak memory 205872 kb
Host smart-314d70ca-f7a1-42b6-bdfe-12f699fdec27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559245090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3559245090
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1115133856
Short name T970
Test name
Test status
Simulation time 70228183 ps
CPU time 1.45 seconds
Started Feb 08 01:06:50 PM PST 24
Finished Feb 08 01:06:55 PM PST 24
Peak memory 208284 kb
Host smart-def7dee5-db77-41c1-a4f6-e66ace810569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115133856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1115133856
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2952074751
Short name T921
Test name
Test status
Simulation time 69475886 ps
CPU time 2.65 seconds
Started Feb 08 01:06:42 PM PST 24
Finished Feb 08 01:06:50 PM PST 24
Peak memory 209572 kb
Host smart-c0eb463b-31a5-417d-bc2b-4768ea576a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952074751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2952074751
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.278574643
Short name T22
Test name
Test status
Simulation time 628461128 ps
CPU time 8.52 seconds
Started Feb 08 01:06:55 PM PST 24
Finished Feb 08 01:07:05 PM PST 24
Peak memory 218344 kb
Host smart-726413d8-428f-4796-8691-614f4938760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278574643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.278574643
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1468530979
Short name T343
Test name
Test status
Simulation time 123215895 ps
CPU time 5.45 seconds
Started Feb 08 01:06:49 PM PST 24
Finished Feb 08 01:06:59 PM PST 24
Peak memory 210888 kb
Host smart-e34b24ef-72b2-4f3b-9dcd-f8989defd8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468530979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1468530979
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2727313444
Short name T751
Test name
Test status
Simulation time 181867374 ps
CPU time 7.4 seconds
Started Feb 08 01:06:37 PM PST 24
Finished Feb 08 01:06:54 PM PST 24
Peak memory 210012 kb
Host smart-4a253507-d3a5-49b6-8c4c-f81436b6f280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727313444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2727313444
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1461506042
Short name T902
Test name
Test status
Simulation time 228743338 ps
CPU time 5.13 seconds
Started Feb 08 01:06:35 PM PST 24
Finished Feb 08 01:06:41 PM PST 24
Peak memory 209268 kb
Host smart-52c7d671-1375-40ea-b3c9-2632bbd54e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461506042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1461506042
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1668036658
Short name T784
Test name
Test status
Simulation time 2874616347 ps
CPU time 45.63 seconds
Started Feb 08 01:06:49 PM PST 24
Finished Feb 08 01:07:39 PM PST 24
Peak memory 207940 kb
Host smart-3e0e4383-77c6-422b-95d4-671d0ac44a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668036658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1668036658
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2875543701
Short name T754
Test name
Test status
Simulation time 1889389773 ps
CPU time 7.99 seconds
Started Feb 08 01:06:50 PM PST 24
Finished Feb 08 01:07:02 PM PST 24
Peak memory 208720 kb
Host smart-bd76b7e9-b09c-469c-8f45-5ce4666fd37f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875543701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2875543701
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.736491783
Short name T212
Test name
Test status
Simulation time 262298947 ps
CPU time 4.07 seconds
Started Feb 08 01:06:43 PM PST 24
Finished Feb 08 01:06:51 PM PST 24
Peak memory 206828 kb
Host smart-68c1c4c3-0cbc-4c65-9568-3a5491ec8655
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736491783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.736491783
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.4078432585
Short name T18
Test name
Test status
Simulation time 42936669 ps
CPU time 2.02 seconds
Started Feb 08 01:06:38 PM PST 24
Finished Feb 08 01:06:49 PM PST 24
Peak memory 206740 kb
Host smart-f112a69e-805d-43db-8c4a-f7eba33a86ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078432585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.4078432585
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1747137920
Short name T360
Test name
Test status
Simulation time 321269623 ps
CPU time 2.41 seconds
Started Feb 08 01:06:49 PM PST 24
Finished Feb 08 01:06:56 PM PST 24
Peak memory 218228 kb
Host smart-6dc8112b-7f98-46b8-ab68-35fff9db9f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747137920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1747137920
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3836481011
Short name T422
Test name
Test status
Simulation time 534449877 ps
CPU time 2.76 seconds
Started Feb 08 01:07:00 PM PST 24
Finished Feb 08 01:07:05 PM PST 24
Peak memory 206888 kb
Host smart-3431f6d9-fb40-4996-9b5f-d2fd62a2d716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836481011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3836481011
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.4026244033
Short name T217
Test name
Test status
Simulation time 236966947 ps
CPU time 2.46 seconds
Started Feb 08 01:06:41 PM PST 24
Finished Feb 08 01:06:50 PM PST 24
Peak memory 222648 kb
Host smart-59551aa1-b16b-4cac-9208-476cfd05b8de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026244033 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.4026244033
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1351145620
Short name T271
Test name
Test status
Simulation time 926122341 ps
CPU time 4.1 seconds
Started Feb 08 01:06:48 PM PST 24
Finished Feb 08 01:06:57 PM PST 24
Peak memory 218132 kb
Host smart-0a7cd262-4f47-46d3-916f-2d4900da9199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351145620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1351145620
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.207779459
Short name T821
Test name
Test status
Simulation time 136828909 ps
CPU time 1.82 seconds
Started Feb 08 01:06:57 PM PST 24
Finished Feb 08 01:07:02 PM PST 24
Peak memory 210032 kb
Host smart-e924641c-8791-4729-9727-59c0df871758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207779459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.207779459
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.836220833
Short name T776
Test name
Test status
Simulation time 43147261 ps
CPU time 0.88 seconds
Started Feb 08 01:04:12 PM PST 24
Finished Feb 08 01:04:14 PM PST 24
Peak memory 206076 kb
Host smart-967ed39d-c9a4-43b9-9565-2e923f2f46f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836220833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.836220833
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.4233547899
Short name T34
Test name
Test status
Simulation time 392165947 ps
CPU time 4.41 seconds
Started Feb 08 01:05:58 PM PST 24
Finished Feb 08 01:06:10 PM PST 24
Peak memory 213208 kb
Host smart-0a0e79e5-5f1b-4ee9-8ca7-a2007150b2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233547899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.4233547899
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.327452997
Short name T381
Test name
Test status
Simulation time 1776638769 ps
CPU time 13.4 seconds
Started Feb 08 01:03:54 PM PST 24
Finished Feb 08 01:04:08 PM PST 24
Peak memory 218180 kb
Host smart-59024111-237a-49f8-b6c6-955b40ca1f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327452997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.327452997
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.887517165
Short name T96
Test name
Test status
Simulation time 277565482 ps
CPU time 3.36 seconds
Started Feb 08 01:04:13 PM PST 24
Finished Feb 08 01:04:17 PM PST 24
Peak memory 208384 kb
Host smart-f31dd48c-3919-4395-bbab-dcf92c7e9a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887517165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.887517165
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3261046359
Short name T283
Test name
Test status
Simulation time 79546958 ps
CPU time 3.63 seconds
Started Feb 08 01:05:58 PM PST 24
Finished Feb 08 01:06:09 PM PST 24
Peak memory 212540 kb
Host smart-db8f06d0-b980-47f2-98ad-94796495bc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261046359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3261046359
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2508993544
Short name T975
Test name
Test status
Simulation time 76135008 ps
CPU time 3.53 seconds
Started Feb 08 01:04:12 PM PST 24
Finished Feb 08 01:04:17 PM PST 24
Peak memory 206132 kb
Host smart-d811005e-da7a-40ec-8b9d-7772f68af682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508993544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2508993544
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.407904148
Short name T665
Test name
Test status
Simulation time 65737085 ps
CPU time 3.43 seconds
Started Feb 08 01:04:04 PM PST 24
Finished Feb 08 01:04:08 PM PST 24
Peak memory 209228 kb
Host smart-32593b32-a2ad-4e0a-b745-ab712a0cadcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407904148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.407904148
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.4000446679
Short name T13
Test name
Test status
Simulation time 1125414639 ps
CPU time 16.69 seconds
Started Feb 08 01:04:28 PM PST 24
Finished Feb 08 01:04:46 PM PST 24
Peak memory 237244 kb
Host smart-da1511a6-0765-4f27-af0b-c6a7c8795437
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000446679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.4000446679
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3861358176
Short name T649
Test name
Test status
Simulation time 213907826 ps
CPU time 2.48 seconds
Started Feb 08 01:04:00 PM PST 24
Finished Feb 08 01:04:04 PM PST 24
Peak memory 208352 kb
Host smart-c961fcb9-a57b-400f-bcec-6e09d0e348a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861358176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3861358176
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3784150887
Short name T211
Test name
Test status
Simulation time 428927139 ps
CPU time 3.58 seconds
Started Feb 08 01:04:01 PM PST 24
Finished Feb 08 01:04:06 PM PST 24
Peak memory 208612 kb
Host smart-ce55235a-625e-4125-ac32-1894b2b264fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784150887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3784150887
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1999568541
Short name T692
Test name
Test status
Simulation time 2800386103 ps
CPU time 33.89 seconds
Started Feb 08 01:03:55 PM PST 24
Finished Feb 08 01:04:30 PM PST 24
Peak memory 208108 kb
Host smart-efda8c03-47c3-4ae4-82a7-3beee3aedbd0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999568541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1999568541
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2351555493
Short name T851
Test name
Test status
Simulation time 1601234768 ps
CPU time 42 seconds
Started Feb 08 01:04:00 PM PST 24
Finished Feb 08 01:04:44 PM PST 24
Peak memory 208096 kb
Host smart-ca8db451-9282-4647-9452-db4dc8b42f2a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351555493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2351555493
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1953641255
Short name T323
Test name
Test status
Simulation time 171256557 ps
CPU time 2.34 seconds
Started Feb 08 01:06:07 PM PST 24
Finished Feb 08 01:06:14 PM PST 24
Peak memory 218036 kb
Host smart-91e25209-a91c-4b2a-9587-c243a81bb0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953641255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1953641255
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2941821773
Short name T739
Test name
Test status
Simulation time 688633055 ps
CPU time 5.42 seconds
Started Feb 08 01:03:59 PM PST 24
Finished Feb 08 01:04:05 PM PST 24
Peak memory 208348 kb
Host smart-5395cc3b-490e-4cf9-9b7f-d60d00f9f5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941821773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2941821773
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.432877377
Short name T405
Test name
Test status
Simulation time 419637203 ps
CPU time 5.12 seconds
Started Feb 08 01:04:21 PM PST 24
Finished Feb 08 01:04:27 PM PST 24
Peak memory 209088 kb
Host smart-26942152-0b9d-4155-aa54-5ab834bfa208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432877377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.432877377
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.775481542
Short name T934
Test name
Test status
Simulation time 296980008 ps
CPU time 3.17 seconds
Started Feb 08 01:04:12 PM PST 24
Finished Feb 08 01:04:16 PM PST 24
Peak memory 210168 kb
Host smart-e126bfac-e639-4148-9aa6-b0c59af13a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775481542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.775481542
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.4044168769
Short name T768
Test name
Test status
Simulation time 28312834 ps
CPU time 0.78 seconds
Started Feb 08 01:06:46 PM PST 24
Finished Feb 08 01:06:53 PM PST 24
Peak memory 205824 kb
Host smart-09b0a7fb-ad4a-432d-9a1c-c78be93b8024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044168769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.4044168769
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2829857189
Short name T437
Test name
Test status
Simulation time 722891579 ps
CPU time 4.46 seconds
Started Feb 08 01:06:49 PM PST 24
Finished Feb 08 01:06:58 PM PST 24
Peak memory 215324 kb
Host smart-444ab1b0-e29f-4474-ba28-3959eb2dce91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2829857189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2829857189
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1602488255
Short name T1041
Test name
Test status
Simulation time 86948893 ps
CPU time 4.25 seconds
Started Feb 08 01:06:50 PM PST 24
Finished Feb 08 01:06:58 PM PST 24
Peak memory 210276 kb
Host smart-21666ac5-54e1-416c-9c4d-7480689db6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602488255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1602488255
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2920447957
Short name T58
Test name
Test status
Simulation time 1272323616 ps
CPU time 16.83 seconds
Started Feb 08 01:06:42 PM PST 24
Finished Feb 08 01:07:04 PM PST 24
Peak memory 209284 kb
Host smart-ee6ce82d-af7b-411a-a224-b006b114e55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920447957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2920447957
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3318715262
Short name T366
Test name
Test status
Simulation time 409008332 ps
CPU time 4.28 seconds
Started Feb 08 01:06:56 PM PST 24
Finished Feb 08 01:07:02 PM PST 24
Peak memory 219828 kb
Host smart-6c7a9a1f-bab1-4d0f-987d-d33fe6b93481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318715262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3318715262
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1193702226
Short name T1046
Test name
Test status
Simulation time 658525505 ps
CPU time 5.33 seconds
Started Feb 08 01:06:59 PM PST 24
Finished Feb 08 01:07:07 PM PST 24
Peak memory 215904 kb
Host smart-2d9619d2-e67a-4a3b-b1d1-78c5af005731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193702226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1193702226
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.971726504
Short name T40
Test name
Test status
Simulation time 1149574040 ps
CPU time 28.06 seconds
Started Feb 08 01:06:57 PM PST 24
Finished Feb 08 01:07:29 PM PST 24
Peak memory 217968 kb
Host smart-4c5dbf72-9d96-4f33-a4c2-853cc3a40f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971726504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.971726504
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3497186006
Short name T357
Test name
Test status
Simulation time 37597797 ps
CPU time 2.31 seconds
Started Feb 08 01:06:36 PM PST 24
Finished Feb 08 01:06:46 PM PST 24
Peak memory 206760 kb
Host smart-9cc6d823-12a4-49de-8f09-ddab3e127f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497186006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3497186006
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.4208557166
Short name T795
Test name
Test status
Simulation time 243591062 ps
CPU time 3.08 seconds
Started Feb 08 01:06:48 PM PST 24
Finished Feb 08 01:06:56 PM PST 24
Peak memory 206888 kb
Host smart-d66cfce7-3600-499d-a4a4-618fe2fee9e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208557166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4208557166
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2266938052
Short name T610
Test name
Test status
Simulation time 168389394 ps
CPU time 3.99 seconds
Started Feb 08 01:06:49 PM PST 24
Finished Feb 08 01:06:57 PM PST 24
Peak memory 206880 kb
Host smart-b3708cec-51a2-4253-8347-1ad097c8d7a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266938052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2266938052
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2396213282
Short name T1075
Test name
Test status
Simulation time 172334113 ps
CPU time 3.34 seconds
Started Feb 08 01:06:59 PM PST 24
Finished Feb 08 01:07:06 PM PST 24
Peak memory 208472 kb
Host smart-0629a04b-12c0-4e1d-ade0-af1a0222e2bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396213282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2396213282
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1268833820
Short name T853
Test name
Test status
Simulation time 666807876 ps
CPU time 11.44 seconds
Started Feb 08 01:07:00 PM PST 24
Finished Feb 08 01:07:14 PM PST 24
Peak memory 209068 kb
Host smart-64b9965f-2d74-4424-b86f-94f768e531ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268833820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1268833820
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3174268129
Short name T85
Test name
Test status
Simulation time 55040460 ps
CPU time 2.86 seconds
Started Feb 08 01:07:00 PM PST 24
Finished Feb 08 01:07:06 PM PST 24
Peak memory 206772 kb
Host smart-8f811e42-fe3c-4159-8274-afdc912a43c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174268129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3174268129
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3006224925
Short name T201
Test name
Test status
Simulation time 581741682 ps
CPU time 5.86 seconds
Started Feb 08 01:06:54 PM PST 24
Finished Feb 08 01:07:01 PM PST 24
Peak memory 209904 kb
Host smart-2c56d53a-f794-4586-b593-828587cbb80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006224925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3006224925
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1798674723
Short name T725
Test name
Test status
Simulation time 245608028 ps
CPU time 3.3 seconds
Started Feb 08 01:06:37 PM PST 24
Finished Feb 08 01:06:50 PM PST 24
Peak memory 210424 kb
Host smart-12803b24-6f6e-4bf1-9657-5d4fa6d7f5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798674723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1798674723
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2825199974
Short name T789
Test name
Test status
Simulation time 53252706 ps
CPU time 0.94 seconds
Started Feb 08 01:06:55 PM PST 24
Finished Feb 08 01:06:58 PM PST 24
Peak memory 206068 kb
Host smart-e572eae3-d7b1-48b1-b8ac-2b7617d553c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825199974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2825199974
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.301045521
Short name T387
Test name
Test status
Simulation time 244257598 ps
CPU time 4.7 seconds
Started Feb 08 01:07:02 PM PST 24
Finished Feb 08 01:07:08 PM PST 24
Peak memory 215168 kb
Host smart-b82c54c7-14f8-4a33-80f2-1af202ac694b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301045521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.301045521
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1778379103
Short name T944
Test name
Test status
Simulation time 152525373 ps
CPU time 4.86 seconds
Started Feb 08 01:06:52 PM PST 24
Finished Feb 08 01:06:59 PM PST 24
Peak memory 208956 kb
Host smart-e0e645e7-f212-4524-82b6-b66764768a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778379103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1778379103
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2015141905
Short name T389
Test name
Test status
Simulation time 54070596 ps
CPU time 2.71 seconds
Started Feb 08 01:06:54 PM PST 24
Finished Feb 08 01:06:59 PM PST 24
Peak memory 214320 kb
Host smart-3cbb8e72-c088-492d-83e9-804b6fe683d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015141905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2015141905
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1503484093
Short name T49
Test name
Test status
Simulation time 77056640 ps
CPU time 3.05 seconds
Started Feb 08 01:06:55 PM PST 24
Finished Feb 08 01:07:00 PM PST 24
Peak memory 209692 kb
Host smart-3bdf51f9-f8e0-4a67-8ff2-a1f2a142e190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503484093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1503484093
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.4170145823
Short name T1005
Test name
Test status
Simulation time 706590092 ps
CPU time 10.39 seconds
Started Feb 08 01:06:55 PM PST 24
Finished Feb 08 01:07:07 PM PST 24
Peak memory 218240 kb
Host smart-fbdce22b-d478-45cf-ac55-a132ae377625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170145823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.4170145823
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.4136310372
Short name T884
Test name
Test status
Simulation time 492244858 ps
CPU time 4.24 seconds
Started Feb 08 01:06:56 PM PST 24
Finished Feb 08 01:07:02 PM PST 24
Peak memory 206868 kb
Host smart-a7e4eafd-85b9-4b56-9de0-2bd48d9d7265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136310372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.4136310372
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.307950723
Short name T674
Test name
Test status
Simulation time 114135643 ps
CPU time 3.17 seconds
Started Feb 08 01:06:40 PM PST 24
Finished Feb 08 01:06:50 PM PST 24
Peak memory 208456 kb
Host smart-358a0619-4b67-4843-813d-8e554e25ab20
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307950723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.307950723
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3638426120
Short name T1054
Test name
Test status
Simulation time 154945275 ps
CPU time 4.92 seconds
Started Feb 08 01:06:58 PM PST 24
Finished Feb 08 01:07:06 PM PST 24
Peak memory 206872 kb
Host smart-395bcfbb-1100-4ef7-9b0a-c16878d7817a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638426120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3638426120
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1742931395
Short name T904
Test name
Test status
Simulation time 226493650 ps
CPU time 3.88 seconds
Started Feb 08 01:06:46 PM PST 24
Finished Feb 08 01:06:56 PM PST 24
Peak memory 208616 kb
Host smart-f3740c56-8fb5-436b-9a24-a9fb53373056
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742931395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1742931395
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1320361327
Short name T642
Test name
Test status
Simulation time 129887076 ps
CPU time 2.24 seconds
Started Feb 08 01:06:40 PM PST 24
Finished Feb 08 01:06:49 PM PST 24
Peak memory 215388 kb
Host smart-022b96f3-1f4b-4833-8316-3fdf3503c5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320361327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1320361327
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3655545189
Short name T657
Test name
Test status
Simulation time 537058098 ps
CPU time 3.23 seconds
Started Feb 08 01:06:49 PM PST 24
Finished Feb 08 01:06:57 PM PST 24
Peak memory 206608 kb
Host smart-5b143d18-d61f-46d2-881a-b05db5883d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655545189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3655545189
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.118385818
Short name T1065
Test name
Test status
Simulation time 1049221961 ps
CPU time 11.18 seconds
Started Feb 08 01:07:02 PM PST 24
Finished Feb 08 01:07:15 PM PST 24
Peak memory 219772 kb
Host smart-1a273c20-a68d-4542-9119-e779f2757bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118385818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.118385818
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.648531156
Short name T845
Test name
Test status
Simulation time 204426027 ps
CPU time 4.77 seconds
Started Feb 08 01:07:04 PM PST 24
Finished Feb 08 01:07:10 PM PST 24
Peak memory 217940 kb
Host smart-9976c0ab-bea2-4db4-96d3-ff5aba590c5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648531156 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.648531156
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2767305501
Short name T1023
Test name
Test status
Simulation time 399335588 ps
CPU time 4.44 seconds
Started Feb 08 01:06:56 PM PST 24
Finished Feb 08 01:07:03 PM PST 24
Peak memory 209368 kb
Host smart-42247a2f-3391-411a-9df9-aeb4fb73bccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767305501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2767305501
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1664952306
Short name T424
Test name
Test status
Simulation time 143264262 ps
CPU time 5.39 seconds
Started Feb 08 01:06:57 PM PST 24
Finished Feb 08 01:07:06 PM PST 24
Peak memory 210644 kb
Host smart-9e161f77-b468-4acf-ab95-9a97fee103d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664952306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1664952306
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.4071275379
Short name T737
Test name
Test status
Simulation time 33348934 ps
CPU time 0.72 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:14 PM PST 24
Peak memory 205624 kb
Host smart-55867ed2-8e17-4f1a-b769-5f89b764063a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071275379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.4071275379
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.944170235
Short name T759
Test name
Test status
Simulation time 68594685 ps
CPU time 1.48 seconds
Started Feb 08 01:07:08 PM PST 24
Finished Feb 08 01:07:10 PM PST 24
Peak memory 207624 kb
Host smart-b25da8e5-cb25-4c2b-aa1e-b7493e70d12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944170235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.944170235
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1481929215
Short name T1011
Test name
Test status
Simulation time 295475149 ps
CPU time 9.53 seconds
Started Feb 08 01:07:10 PM PST 24
Finished Feb 08 01:07:20 PM PST 24
Peak memory 209376 kb
Host smart-8cc2c613-e191-4c70-bc78-2d4d31238512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481929215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1481929215
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.353913618
Short name T341
Test name
Test status
Simulation time 281418291 ps
CPU time 4.08 seconds
Started Feb 08 01:07:09 PM PST 24
Finished Feb 08 01:07:14 PM PST 24
Peak memory 220864 kb
Host smart-d2a5ecf1-7ff4-425f-a795-2b5a17998001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353913618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.353913618
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1163337374
Short name T324
Test name
Test status
Simulation time 212618921 ps
CPU time 5.06 seconds
Started Feb 08 01:07:11 PM PST 24
Finished Feb 08 01:07:17 PM PST 24
Peak memory 220212 kb
Host smart-d5a07adc-342d-4824-8c8c-e34d53d50cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163337374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1163337374
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3175392543
Short name T192
Test name
Test status
Simulation time 2051109918 ps
CPU time 8.13 seconds
Started Feb 08 01:07:10 PM PST 24
Finished Feb 08 01:07:19 PM PST 24
Peak memory 209796 kb
Host smart-3c586d12-6ebc-4b3e-af30-a0b8275fce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175392543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3175392543
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2602508520
Short name T133
Test name
Test status
Simulation time 845594476 ps
CPU time 7.36 seconds
Started Feb 08 01:06:48 PM PST 24
Finished Feb 08 01:07:01 PM PST 24
Peak memory 206796 kb
Host smart-e2be7d0a-04ee-4085-bb3b-26291591688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602508520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2602508520
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1380815957
Short name T812
Test name
Test status
Simulation time 111759413 ps
CPU time 3.82 seconds
Started Feb 08 01:06:58 PM PST 24
Finished Feb 08 01:07:05 PM PST 24
Peak memory 206764 kb
Host smart-c3616b74-9cc2-4750-b322-b520f684341a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380815957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1380815957
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.158986076
Short name T786
Test name
Test status
Simulation time 132584779 ps
CPU time 4.22 seconds
Started Feb 08 01:06:53 PM PST 24
Finished Feb 08 01:06:59 PM PST 24
Peak memory 206948 kb
Host smart-719eaa50-54d1-47c5-8a53-8bff358e15e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158986076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.158986076
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1355125952
Short name T830
Test name
Test status
Simulation time 170494189 ps
CPU time 6.46 seconds
Started Feb 08 01:07:16 PM PST 24
Finished Feb 08 01:07:24 PM PST 24
Peak memory 208640 kb
Host smart-69aa26d2-0c3d-4170-9457-0ae88b7ea907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355125952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1355125952
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3894861642
Short name T1052
Test name
Test status
Simulation time 7677925201 ps
CPU time 39.74 seconds
Started Feb 08 01:07:00 PM PST 24
Finished Feb 08 01:07:42 PM PST 24
Peak memory 208220 kb
Host smart-617bd3dc-d82f-4762-9107-e010efb35ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894861642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3894861642
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2188503114
Short name T656
Test name
Test status
Simulation time 451892328 ps
CPU time 6.06 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:07:22 PM PST 24
Peak memory 222632 kb
Host smart-88e935ee-45b3-4466-b3d9-72a4f06a6c86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188503114 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2188503114
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1758890988
Short name T623
Test name
Test status
Simulation time 121626121 ps
CPU time 4.61 seconds
Started Feb 08 01:07:18 PM PST 24
Finished Feb 08 01:07:25 PM PST 24
Peak memory 208108 kb
Host smart-02c015b1-6b45-49ec-8068-5a428261adfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758890988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1758890988
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.18219485
Short name T712
Test name
Test status
Simulation time 68487611 ps
CPU time 1.95 seconds
Started Feb 08 01:07:09 PM PST 24
Finished Feb 08 01:07:12 PM PST 24
Peak memory 209920 kb
Host smart-2e89e33c-ae6e-4dda-ac58-8aa1d86e0186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18219485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.18219485
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2430172064
Short name T730
Test name
Test status
Simulation time 26234688 ps
CPU time 0.9 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:15 PM PST 24
Peak memory 205780 kb
Host smart-1eed16b9-e6d8-4662-b3da-ab1ece1cdd6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430172064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2430172064
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1485399076
Short name T239
Test name
Test status
Simulation time 188497633 ps
CPU time 4.12 seconds
Started Feb 08 01:07:15 PM PST 24
Finished Feb 08 01:07:20 PM PST 24
Peak memory 214388 kb
Host smart-5baedefb-d138-4599-862d-66093ac12661
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485399076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1485399076
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2836981169
Short name T965
Test name
Test status
Simulation time 184656400 ps
CPU time 4.48 seconds
Started Feb 08 01:07:15 PM PST 24
Finished Feb 08 01:07:21 PM PST 24
Peak memory 210224 kb
Host smart-46f24ce1-1c0c-4dab-a3e6-15aafb179f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836981169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2836981169
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.4072642376
Short name T65
Test name
Test status
Simulation time 328696059 ps
CPU time 2.63 seconds
Started Feb 08 01:07:13 PM PST 24
Finished Feb 08 01:07:17 PM PST 24
Peak memory 214384 kb
Host smart-c7e15bf6-8544-4c5c-bce3-7a5fe3378fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072642376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.4072642376
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2001690492
Short name T850
Test name
Test status
Simulation time 337099799 ps
CPU time 8.73 seconds
Started Feb 08 01:07:13 PM PST 24
Finished Feb 08 01:07:23 PM PST 24
Peak memory 214404 kb
Host smart-336eeba2-74d7-4f3f-bd2d-8aea5f41a267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001690492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2001690492
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.190607224
Short name T1031
Test name
Test status
Simulation time 4560492931 ps
CPU time 70.41 seconds
Started Feb 08 01:07:13 PM PST 24
Finished Feb 08 01:08:26 PM PST 24
Peak memory 229644 kb
Host smart-54d3f40f-c4e7-407e-bd7b-2d079e00e382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190607224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.190607224
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.640107021
Short name T833
Test name
Test status
Simulation time 135638543 ps
CPU time 4.3 seconds
Started Feb 08 01:07:13 PM PST 24
Finished Feb 08 01:07:19 PM PST 24
Peak memory 214328 kb
Host smart-0e9592ab-ff4e-44bc-8e76-da4c3187f015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640107021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.640107021
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.453354964
Short name T781
Test name
Test status
Simulation time 171662010 ps
CPU time 3.21 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:17 PM PST 24
Peak memory 207692 kb
Host smart-a35b74c5-f12a-4444-b18c-0c501403716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453354964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.453354964
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1562494714
Short name T336
Test name
Test status
Simulation time 230117702 ps
CPU time 3.23 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:07:19 PM PST 24
Peak memory 206924 kb
Host smart-06b69b8c-44f4-4519-ab43-2e9828e6d51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562494714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1562494714
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1746391030
Short name T311
Test name
Test status
Simulation time 334063520 ps
CPU time 5.51 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:19 PM PST 24
Peak memory 206864 kb
Host smart-d30281c6-7a7b-4159-bb1e-6fe914d53854
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746391030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1746391030
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1880116293
Short name T964
Test name
Test status
Simulation time 43543143 ps
CPU time 1.97 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:07:17 PM PST 24
Peak memory 208680 kb
Host smart-e81d3b15-8c0d-4303-b3a9-ccebc1a15009
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880116293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1880116293
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.463195288
Short name T270
Test name
Test status
Simulation time 171191068 ps
CPU time 3.93 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:18 PM PST 24
Peak memory 207400 kb
Host smart-9b64aec5-dd1e-44e8-be39-2f044ac89145
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463195288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.463195288
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3964456100
Short name T915
Test name
Test status
Simulation time 647344774 ps
CPU time 2.66 seconds
Started Feb 08 01:07:08 PM PST 24
Finished Feb 08 01:07:12 PM PST 24
Peak memory 206728 kb
Host smart-c8a17008-fc4d-4732-b5d2-155bcacf395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964456100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3964456100
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4116743678
Short name T918
Test name
Test status
Simulation time 577035190 ps
CPU time 12.84 seconds
Started Feb 08 01:07:11 PM PST 24
Finished Feb 08 01:07:25 PM PST 24
Peak memory 208508 kb
Host smart-37bfd870-2a81-4552-b1f3-0bdc5f0f9246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116743678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4116743678
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.4079065724
Short name T798
Test name
Test status
Simulation time 343388339 ps
CPU time 3.98 seconds
Started Feb 08 01:07:13 PM PST 24
Finished Feb 08 01:07:19 PM PST 24
Peak memory 222612 kb
Host smart-de834807-234c-43d6-8396-cbe17436fa3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079065724 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.4079065724
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3165112989
Short name T898
Test name
Test status
Simulation time 41710489 ps
CPU time 2.76 seconds
Started Feb 08 01:07:13 PM PST 24
Finished Feb 08 01:07:18 PM PST 24
Peak memory 207804 kb
Host smart-bfa500a6-bfea-493e-be1e-a3bf1d968e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165112989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3165112989
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2645759966
Short name T172
Test name
Test status
Simulation time 38798794 ps
CPU time 1.42 seconds
Started Feb 08 01:07:16 PM PST 24
Finished Feb 08 01:07:18 PM PST 24
Peak memory 209768 kb
Host smart-7f8ee2be-3e3e-4bb1-97d5-fc7ee803bb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645759966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2645759966
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2492931543
Short name T847
Test name
Test status
Simulation time 56477234 ps
CPU time 0.75 seconds
Started Feb 08 01:07:11 PM PST 24
Finished Feb 08 01:07:13 PM PST 24
Peak memory 205868 kb
Host smart-854cef95-a009-4f6b-b8df-9de06d046633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492931543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2492931543
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.291803009
Short name T426
Test name
Test status
Simulation time 2908757802 ps
CPU time 18.82 seconds
Started Feb 08 01:07:11 PM PST 24
Finished Feb 08 01:07:31 PM PST 24
Peak memory 214396 kb
Host smart-53dc5f83-cd51-47d1-976f-affbc6a07f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291803009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.291803009
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4089007632
Short name T61
Test name
Test status
Simulation time 69948720 ps
CPU time 2.78 seconds
Started Feb 08 01:07:16 PM PST 24
Finished Feb 08 01:07:20 PM PST 24
Peak memory 208636 kb
Host smart-e53f028c-df33-4dd8-8136-8b267a8fb726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089007632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4089007632
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1898933041
Short name T1048
Test name
Test status
Simulation time 27582715 ps
CPU time 1.48 seconds
Started Feb 08 01:07:10 PM PST 24
Finished Feb 08 01:07:12 PM PST 24
Peak memory 207148 kb
Host smart-32d7537b-c7db-4fa7-9b7e-2c1c8249bc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898933041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1898933041
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2664449145
Short name T259
Test name
Test status
Simulation time 55709680 ps
CPU time 3.34 seconds
Started Feb 08 01:07:13 PM PST 24
Finished Feb 08 01:07:18 PM PST 24
Peak memory 219204 kb
Host smart-02216bfd-d4ca-4578-947b-7db729be5d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664449145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2664449145
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1947566293
Short name T945
Test name
Test status
Simulation time 492190974 ps
CPU time 7.71 seconds
Started Feb 08 01:07:16 PM PST 24
Finished Feb 08 01:07:24 PM PST 24
Peak memory 211324 kb
Host smart-39e7e62f-401e-44bb-9218-7827cd6db683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947566293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1947566293
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.263843482
Short name T774
Test name
Test status
Simulation time 80175352 ps
CPU time 2.59 seconds
Started Feb 08 01:07:11 PM PST 24
Finished Feb 08 01:07:15 PM PST 24
Peak memory 206696 kb
Host smart-d1aa4591-2ce1-4ae9-a708-3b8477cfbdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263843482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.263843482
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1591316838
Short name T1072
Test name
Test status
Simulation time 69747024 ps
CPU time 3.52 seconds
Started Feb 08 01:07:10 PM PST 24
Finished Feb 08 01:07:14 PM PST 24
Peak memory 214356 kb
Host smart-ba1a42e1-e658-4a34-b017-6a1307eaf93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591316838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1591316838
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.806565038
Short name T1063
Test name
Test status
Simulation time 1063543641 ps
CPU time 7.09 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:07:22 PM PST 24
Peak memory 208652 kb
Host smart-e32898f0-6383-4a1c-b997-9e65218eeeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806565038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.806565038
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1612914065
Short name T724
Test name
Test status
Simulation time 122577964 ps
CPU time 4 seconds
Started Feb 08 01:07:10 PM PST 24
Finished Feb 08 01:07:15 PM PST 24
Peak memory 206924 kb
Host smart-21b396c3-57d5-4b86-8d2a-6963a7c087cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612914065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1612914065
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.280076690
Short name T682
Test name
Test status
Simulation time 1837418521 ps
CPU time 12.89 seconds
Started Feb 08 01:07:15 PM PST 24
Finished Feb 08 01:07:29 PM PST 24
Peak memory 208568 kb
Host smart-b75713da-9eb9-4d5a-beab-df1e1aee128b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280076690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.280076690
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1535103926
Short name T765
Test name
Test status
Simulation time 2263248221 ps
CPU time 60.55 seconds
Started Feb 08 01:07:11 PM PST 24
Finished Feb 08 01:08:13 PM PST 24
Peak memory 208224 kb
Host smart-4348d2c0-af3e-4c73-b25e-aa46af0140e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535103926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1535103926
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3828904707
Short name T838
Test name
Test status
Simulation time 368299359 ps
CPU time 4.27 seconds
Started Feb 08 01:07:13 PM PST 24
Finished Feb 08 01:07:18 PM PST 24
Peak memory 218308 kb
Host smart-db7db48d-3642-4fd7-b6b8-01d205e9a61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828904707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3828904707
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1399767412
Short name T598
Test name
Test status
Simulation time 389571038 ps
CPU time 2.61 seconds
Started Feb 08 01:07:13 PM PST 24
Finished Feb 08 01:07:17 PM PST 24
Peak memory 207348 kb
Host smart-3f520d31-f586-40c4-894e-3be5201235b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399767412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1399767412
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2318212528
Short name T310
Test name
Test status
Simulation time 5490425773 ps
CPU time 69.44 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:08:25 PM PST 24
Peak memory 222548 kb
Host smart-f643d2b7-f19e-44be-93f1-18d69aa9390b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318212528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2318212528
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.4211106958
Short name T1010
Test name
Test status
Simulation time 353153996 ps
CPU time 2.54 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:16 PM PST 24
Peak memory 222628 kb
Host smart-9a567f7d-9d17-4d35-bf57-d2f32e7d762d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211106958 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.4211106958
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2796980591
Short name T688
Test name
Test status
Simulation time 219861881 ps
CPU time 6.65 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:20 PM PST 24
Peak memory 208872 kb
Host smart-0d562534-8514-4b7f-8ae0-55546737759d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796980591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2796980591
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3822493029
Short name T805
Test name
Test status
Simulation time 1131617205 ps
CPU time 24.22 seconds
Started Feb 08 01:07:11 PM PST 24
Finished Feb 08 01:07:36 PM PST 24
Peak memory 210572 kb
Host smart-ae76ad81-1784-4854-ac54-34cca2a06cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822493029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3822493029
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.91240085
Short name T804
Test name
Test status
Simulation time 68445075 ps
CPU time 0.93 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:15 PM PST 24
Peak memory 205848 kb
Host smart-188676f1-412e-4d18-8ecb-32fc52899cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91240085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.91240085
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2362638836
Short name T274
Test name
Test status
Simulation time 222916376 ps
CPU time 3.83 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:18 PM PST 24
Peak memory 214272 kb
Host smart-cc1e4fc2-984f-4d83-9a7b-147fe6cda42f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2362638836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2362638836
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1562892879
Short name T29
Test name
Test status
Simulation time 160464549 ps
CPU time 2.01 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:07:18 PM PST 24
Peak memory 222416 kb
Host smart-479acff4-ae65-42ca-8110-048be085ee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562892879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1562892879
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.387415803
Short name T981
Test name
Test status
Simulation time 171892954 ps
CPU time 3.56 seconds
Started Feb 08 01:07:08 PM PST 24
Finished Feb 08 01:07:13 PM PST 24
Peak memory 219544 kb
Host smart-743c8a8d-a080-472b-8c76-1a7c224d9716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387415803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.387415803
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.345368897
Short name T94
Test name
Test status
Simulation time 10158230920 ps
CPU time 74.6 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:08:28 PM PST 24
Peak memory 214264 kb
Host smart-4ef37016-42d7-4208-acb0-92547ec0424f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345368897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.345368897
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3445160796
Short name T279
Test name
Test status
Simulation time 3922083865 ps
CPU time 8.06 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:21 PM PST 24
Peak memory 214280 kb
Host smart-14f37ea2-7de9-45d5-9148-944a7a617527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445160796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3445160796
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1671280151
Short name T367
Test name
Test status
Simulation time 182576866 ps
CPU time 3.39 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:07:19 PM PST 24
Peak memory 222336 kb
Host smart-153f8f84-38e6-45be-8111-828ba219cfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671280151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1671280151
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.121132497
Short name T957
Test name
Test status
Simulation time 164271867 ps
CPU time 4.06 seconds
Started Feb 08 01:07:11 PM PST 24
Finished Feb 08 01:07:15 PM PST 24
Peak memory 208984 kb
Host smart-405593e0-ad61-4d60-99a1-9dbbbb01d109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121132497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.121132497
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1501735894
Short name T1009
Test name
Test status
Simulation time 67427678 ps
CPU time 3.2 seconds
Started Feb 08 01:07:08 PM PST 24
Finished Feb 08 01:07:13 PM PST 24
Peak memory 206640 kb
Host smart-daeb1d3b-bca1-4da8-ad77-88980bff3350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501735894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1501735894
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3070835357
Short name T782
Test name
Test status
Simulation time 2246365143 ps
CPU time 40.76 seconds
Started Feb 08 01:07:10 PM PST 24
Finished Feb 08 01:07:52 PM PST 24
Peak memory 208656 kb
Host smart-cbb2177a-7327-4b2a-975a-31b7e5e38145
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070835357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3070835357
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2456119825
Short name T783
Test name
Test status
Simulation time 103516515 ps
CPU time 2.76 seconds
Started Feb 08 01:07:15 PM PST 24
Finished Feb 08 01:07:19 PM PST 24
Peak memory 206768 kb
Host smart-01a2369f-1666-467a-9bb6-bbeb5e962d4c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456119825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2456119825
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3517172551
Short name T734
Test name
Test status
Simulation time 176734350 ps
CPU time 4.77 seconds
Started Feb 08 01:07:15 PM PST 24
Finished Feb 08 01:07:21 PM PST 24
Peak memory 208248 kb
Host smart-29ad35d0-be12-4db8-864e-56fbbdf1111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517172551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3517172551
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.717161768
Short name T900
Test name
Test status
Simulation time 130745340 ps
CPU time 3.45 seconds
Started Feb 08 01:07:12 PM PST 24
Finished Feb 08 01:07:17 PM PST 24
Peak memory 208008 kb
Host smart-b2c25e98-709d-472a-b840-4727ac2f2d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717161768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.717161768
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.4072966640
Short name T382
Test name
Test status
Simulation time 1649978902 ps
CPU time 39.62 seconds
Started Feb 08 01:07:15 PM PST 24
Finished Feb 08 01:07:55 PM PST 24
Peak memory 216360 kb
Host smart-2518a1e0-43db-44f6-b554-cd2f6481fb36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072966640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4072966640
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2753202889
Short name T220
Test name
Test status
Simulation time 638490704 ps
CPU time 13.31 seconds
Started Feb 08 01:07:19 PM PST 24
Finished Feb 08 01:07:34 PM PST 24
Peak memory 224128 kb
Host smart-66c30530-8494-46a1-9dd9-073acafb135c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753202889 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2753202889
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.377586783
Short name T335
Test name
Test status
Simulation time 647842637 ps
CPU time 7.52 seconds
Started Feb 08 01:07:10 PM PST 24
Finished Feb 08 01:07:19 PM PST 24
Peak memory 209452 kb
Host smart-4a375b81-328b-4626-8a95-7037edf3005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377586783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.377586783
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3183717918
Short name T163
Test name
Test status
Simulation time 143231026 ps
CPU time 3.13 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:07:18 PM PST 24
Peak memory 210368 kb
Host smart-b42ac5ed-36b3-4fa3-b65e-81ccde175435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183717918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3183717918
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.599921906
Short name T891
Test name
Test status
Simulation time 9695277 ps
CPU time 0.81 seconds
Started Feb 08 01:07:17 PM PST 24
Finished Feb 08 01:07:20 PM PST 24
Peak memory 205876 kb
Host smart-39123f75-a592-40a6-b72f-6615ed9460b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599921906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.599921906
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2040519302
Short name T395
Test name
Test status
Simulation time 196955536 ps
CPU time 3.79 seconds
Started Feb 08 01:07:18 PM PST 24
Finished Feb 08 01:07:24 PM PST 24
Peak memory 214304 kb
Host smart-2ace7206-9bf6-4fd6-aca5-63998649be83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040519302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2040519302
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1351408282
Short name T403
Test name
Test status
Simulation time 324329733 ps
CPU time 3.46 seconds
Started Feb 08 01:07:19 PM PST 24
Finished Feb 08 01:07:24 PM PST 24
Peak memory 207268 kb
Host smart-add97904-8038-4b8e-a039-f0c4e7f6a6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351408282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1351408282
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.539388944
Short name T258
Test name
Test status
Simulation time 715929517 ps
CPU time 5.85 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:07:22 PM PST 24
Peak memory 219208 kb
Host smart-b0b68060-9c8c-4bf3-ad72-57a677f10d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539388944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.539388944
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3509500775
Short name T980
Test name
Test status
Simulation time 46296613 ps
CPU time 2.13 seconds
Started Feb 08 01:07:15 PM PST 24
Finished Feb 08 01:07:18 PM PST 24
Peak memory 222468 kb
Host smart-34f3c3d0-fcab-4f86-8e7f-b16813906cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509500775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3509500775
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3327202311
Short name T697
Test name
Test status
Simulation time 2083511802 ps
CPU time 7.79 seconds
Started Feb 08 01:07:17 PM PST 24
Finished Feb 08 01:07:27 PM PST 24
Peak memory 217876 kb
Host smart-75fa4be6-bb7a-4b1f-84cd-aaddd02002b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327202311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3327202311
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1929993434
Short name T600
Test name
Test status
Simulation time 602987748 ps
CPU time 10.97 seconds
Started Feb 08 01:07:15 PM PST 24
Finished Feb 08 01:07:27 PM PST 24
Peak memory 206636 kb
Host smart-535d8252-0dc2-48da-bf93-ecab71f5a409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929993434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1929993434
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1169540411
Short name T831
Test name
Test status
Simulation time 4110069540 ps
CPU time 54.09 seconds
Started Feb 08 01:07:16 PM PST 24
Finished Feb 08 01:08:11 PM PST 24
Peak memory 208240 kb
Host smart-b5982e73-e084-475a-8bfd-9304a669ff77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169540411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1169540411
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3366563555
Short name T1035
Test name
Test status
Simulation time 442191475 ps
CPU time 4.13 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:07:20 PM PST 24
Peak memory 206916 kb
Host smart-2a12d3b9-7abe-4c94-b9d0-a1b44a0d1292
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366563555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3366563555
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2523331653
Short name T680
Test name
Test status
Simulation time 318266734 ps
CPU time 6.7 seconds
Started Feb 08 01:07:15 PM PST 24
Finished Feb 08 01:07:23 PM PST 24
Peak memory 206972 kb
Host smart-cab85276-5d9f-4842-8413-28ed78cb8778
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523331653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2523331653
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1590063723
Short name T1069
Test name
Test status
Simulation time 245786212 ps
CPU time 3.38 seconds
Started Feb 08 01:07:19 PM PST 24
Finished Feb 08 01:07:24 PM PST 24
Peak memory 209084 kb
Host smart-9c3c6fc2-ef85-4e2b-a954-fbc33e9f6a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590063723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1590063723
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.522954814
Short name T819
Test name
Test status
Simulation time 1947447020 ps
CPU time 12.83 seconds
Started Feb 08 01:07:13 PM PST 24
Finished Feb 08 01:07:27 PM PST 24
Peak memory 206880 kb
Host smart-6462a0b8-1465-42f7-9ebc-00efcc78b918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522954814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.522954814
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4032349807
Short name T327
Test name
Test status
Simulation time 26419006565 ps
CPU time 355.14 seconds
Started Feb 08 01:07:19 PM PST 24
Finished Feb 08 01:13:16 PM PST 24
Peak memory 222540 kb
Host smart-42daf426-1008-4350-a450-b920dc039cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032349807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4032349807
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.659952425
Short name T969
Test name
Test status
Simulation time 481044783 ps
CPU time 4.83 seconds
Started Feb 08 01:07:20 PM PST 24
Finished Feb 08 01:07:27 PM PST 24
Peak memory 222872 kb
Host smart-d0adc44a-ad2a-4aba-8408-c5d927874605
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659952425 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.659952425
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.164149254
Short name T779
Test name
Test status
Simulation time 567626223 ps
CPU time 7.21 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:07:23 PM PST 24
Peak memory 210324 kb
Host smart-9a4f862b-71ce-4e44-bcb3-1a362ba6bbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164149254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.164149254
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2956779071
Short name T955
Test name
Test status
Simulation time 65163350 ps
CPU time 2.73 seconds
Started Feb 08 01:07:14 PM PST 24
Finished Feb 08 01:07:18 PM PST 24
Peak memory 209916 kb
Host smart-7387acc1-6db4-4a56-9fae-d90eae301add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956779071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2956779071
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1299236310
Short name T997
Test name
Test status
Simulation time 42969033 ps
CPU time 0.82 seconds
Started Feb 08 01:07:37 PM PST 24
Finished Feb 08 01:07:39 PM PST 24
Peak memory 205808 kb
Host smart-cbd9b6fd-371c-4db6-afee-13b62fa8b6b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299236310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1299236310
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2196703458
Short name T441
Test name
Test status
Simulation time 231304333 ps
CPU time 11.77 seconds
Started Feb 08 01:07:17 PM PST 24
Finished Feb 08 01:07:31 PM PST 24
Peak memory 214320 kb
Host smart-988ddd45-dcf0-4a39-9448-9ed7bb7216b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196703458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2196703458
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1883282588
Short name T620
Test name
Test status
Simulation time 513118590 ps
CPU time 2.73 seconds
Started Feb 08 01:07:33 PM PST 24
Finished Feb 08 01:07:36 PM PST 24
Peak memory 216964 kb
Host smart-45391ecf-807e-471e-ae91-892c6ad671c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883282588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1883282588
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1433574045
Short name T339
Test name
Test status
Simulation time 441037724 ps
CPU time 3.68 seconds
Started Feb 08 01:07:19 PM PST 24
Finished Feb 08 01:07:24 PM PST 24
Peak memory 214256 kb
Host smart-ce2f3772-9299-46f4-8f9e-de341cf1dd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433574045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1433574045
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4280755799
Short name T611
Test name
Test status
Simulation time 93490719 ps
CPU time 2.49 seconds
Started Feb 08 01:07:40 PM PST 24
Finished Feb 08 01:07:44 PM PST 24
Peak memory 208644 kb
Host smart-4bb2760e-8cb2-49a7-8a00-aa2259d122f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280755799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4280755799
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3530080965
Short name T394
Test name
Test status
Simulation time 173821298 ps
CPU time 4.41 seconds
Started Feb 08 01:07:18 PM PST 24
Finished Feb 08 01:07:25 PM PST 24
Peak memory 209888 kb
Host smart-ecf0ec02-a7c5-4c52-bb5c-301d755aafaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530080965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3530080965
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.663091788
Short name T667
Test name
Test status
Simulation time 98794889 ps
CPU time 4.74 seconds
Started Feb 08 01:07:17 PM PST 24
Finished Feb 08 01:07:24 PM PST 24
Peak memory 218376 kb
Host smart-07cf7bfb-b774-4509-8204-e2f45cb92e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663091788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.663091788
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2354971367
Short name T693
Test name
Test status
Simulation time 443347921 ps
CPU time 3.94 seconds
Started Feb 08 01:07:20 PM PST 24
Finished Feb 08 01:07:26 PM PST 24
Peak memory 208580 kb
Host smart-b3aed84e-bf4e-4ba5-b48a-b94ff5232be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354971367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2354971367
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1055565723
Short name T578
Test name
Test status
Simulation time 110954687 ps
CPU time 2.84 seconds
Started Feb 08 01:07:20 PM PST 24
Finished Feb 08 01:07:25 PM PST 24
Peak memory 206728 kb
Host smart-e24caec4-6214-4308-9e85-8739076ab979
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055565723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1055565723
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3999530504
Short name T802
Test name
Test status
Simulation time 217219217 ps
CPU time 6.01 seconds
Started Feb 08 01:07:17 PM PST 24
Finished Feb 08 01:07:24 PM PST 24
Peak memory 208728 kb
Host smart-10d7388a-d096-454a-8ec9-184707c9bd12
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999530504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3999530504
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2421764800
Short name T420
Test name
Test status
Simulation time 1064163776 ps
CPU time 25.79 seconds
Started Feb 08 01:07:19 PM PST 24
Finished Feb 08 01:07:46 PM PST 24
Peak memory 207956 kb
Host smart-ee24af50-9a0d-478b-b009-b190ec9cc26d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421764800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2421764800
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3196889096
Short name T979
Test name
Test status
Simulation time 297397154 ps
CPU time 3.69 seconds
Started Feb 08 01:07:32 PM PST 24
Finished Feb 08 01:07:37 PM PST 24
Peak memory 214304 kb
Host smart-f7fc8dc4-83b0-4fc6-b633-a38731c4f448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196889096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3196889096
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3065154152
Short name T585
Test name
Test status
Simulation time 169764646 ps
CPU time 2.27 seconds
Started Feb 08 01:07:20 PM PST 24
Finished Feb 08 01:07:24 PM PST 24
Peak memory 206376 kb
Host smart-dc4e0b55-e0b4-41f0-a58c-afec0f1e352d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065154152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3065154152
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2636543477
Short name T857
Test name
Test status
Simulation time 221391916 ps
CPU time 5.77 seconds
Started Feb 08 01:07:37 PM PST 24
Finished Feb 08 01:07:44 PM PST 24
Peak memory 208956 kb
Host smart-e72403b6-833a-44a1-a9f8-760cebdfba05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636543477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2636543477
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1137256490
Short name T698
Test name
Test status
Simulation time 1263178464 ps
CPU time 7.41 seconds
Started Feb 08 01:07:38 PM PST 24
Finished Feb 08 01:07:47 PM PST 24
Peak memory 218612 kb
Host smart-95bb0a19-e69a-4a79-b687-990ae47778cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137256490 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1137256490
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3319613431
Short name T396
Test name
Test status
Simulation time 39199092 ps
CPU time 3.11 seconds
Started Feb 08 01:07:19 PM PST 24
Finished Feb 08 01:07:23 PM PST 24
Peak memory 214316 kb
Host smart-d4437217-4a2f-47ca-8199-baa845c50ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319613431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3319613431
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1192074287
Short name T423
Test name
Test status
Simulation time 114507596 ps
CPU time 1.78 seconds
Started Feb 08 01:07:44 PM PST 24
Finished Feb 08 01:07:46 PM PST 24
Peak memory 209876 kb
Host smart-3bda3574-0bbc-4dca-8663-17faaa2bdc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192074287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1192074287
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3082907469
Short name T777
Test name
Test status
Simulation time 7859371 ps
CPU time 0.69 seconds
Started Feb 08 01:07:31 PM PST 24
Finished Feb 08 01:07:33 PM PST 24
Peak memory 205888 kb
Host smart-a700e270-03fc-4846-86ea-e255aac415e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082907469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3082907469
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2611108924
Short name T1058
Test name
Test status
Simulation time 797489739 ps
CPU time 6.75 seconds
Started Feb 08 01:07:32 PM PST 24
Finished Feb 08 01:07:40 PM PST 24
Peak memory 209104 kb
Host smart-460d7bd1-9f15-43f4-8d5f-21fed90093a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611108924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2611108924
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3765163359
Short name T978
Test name
Test status
Simulation time 2829821121 ps
CPU time 14.35 seconds
Started Feb 08 01:07:37 PM PST 24
Finished Feb 08 01:07:53 PM PST 24
Peak memory 208500 kb
Host smart-c4c6b790-1c86-4584-acfe-915645a3b34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765163359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3765163359
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.4115259095
Short name T1055
Test name
Test status
Simulation time 746985564 ps
CPU time 7.24 seconds
Started Feb 08 01:07:42 PM PST 24
Finished Feb 08 01:07:50 PM PST 24
Peak memory 219148 kb
Host smart-f113d2cb-733c-4cfa-81ac-1f52a06c7289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115259095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.4115259095
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.4261944214
Short name T400
Test name
Test status
Simulation time 163009228 ps
CPU time 6.45 seconds
Started Feb 08 01:07:32 PM PST 24
Finished Feb 08 01:07:39 PM PST 24
Peak memory 222420 kb
Host smart-d7822348-9ded-4343-b74c-d9f4fa738651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261944214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4261944214
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3651445529
Short name T370
Test name
Test status
Simulation time 40582991 ps
CPU time 2.81 seconds
Started Feb 08 01:07:39 PM PST 24
Finished Feb 08 01:07:43 PM PST 24
Peak memory 209308 kb
Host smart-c900b8a4-0f5e-4192-be15-253a06058b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651445529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3651445529
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1609472118
Short name T1051
Test name
Test status
Simulation time 109368161 ps
CPU time 5.3 seconds
Started Feb 08 01:07:39 PM PST 24
Finished Feb 08 01:07:45 PM PST 24
Peak memory 209280 kb
Host smart-0678a514-ae84-438c-a8c9-880c7ba904cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609472118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1609472118
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3430851373
Short name T109
Test name
Test status
Simulation time 28990171 ps
CPU time 2.08 seconds
Started Feb 08 01:07:37 PM PST 24
Finished Feb 08 01:07:40 PM PST 24
Peak memory 208440 kb
Host smart-195511a1-fcc3-479d-a7e0-3756e374413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430851373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3430851373
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3834625390
Short name T760
Test name
Test status
Simulation time 346854681 ps
CPU time 7.2 seconds
Started Feb 08 01:07:39 PM PST 24
Finished Feb 08 01:07:48 PM PST 24
Peak memory 208288 kb
Host smart-5593bb9c-c423-4cc5-ab81-19bf16b61104
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834625390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3834625390
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.4026086498
Short name T703
Test name
Test status
Simulation time 236206955 ps
CPU time 3.34 seconds
Started Feb 08 01:07:32 PM PST 24
Finished Feb 08 01:07:36 PM PST 24
Peak memory 208652 kb
Host smart-5fc7abda-eb63-4136-bde9-13dba7c79745
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026086498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.4026086498
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1999773339
Short name T1
Test name
Test status
Simulation time 603874082 ps
CPU time 21.62 seconds
Started Feb 08 01:07:34 PM PST 24
Finished Feb 08 01:07:57 PM PST 24
Peak memory 208452 kb
Host smart-7db2218e-5b28-4445-a78a-7ae04d0659c6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999773339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1999773339
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3910203136
Short name T601
Test name
Test status
Simulation time 510431900 ps
CPU time 4.59 seconds
Started Feb 08 01:07:36 PM PST 24
Finished Feb 08 01:07:42 PM PST 24
Peak memory 208916 kb
Host smart-999e7315-7c17-42fa-9e96-3bf83a76d8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910203136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3910203136
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1904434980
Short name T421
Test name
Test status
Simulation time 460753149 ps
CPU time 3.79 seconds
Started Feb 08 01:07:37 PM PST 24
Finished Feb 08 01:07:42 PM PST 24
Peak memory 208356 kb
Host smart-81ae9895-06d2-428f-94b3-f44e77426ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904434980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1904434980
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3526855422
Short name T854
Test name
Test status
Simulation time 76806451 ps
CPU time 3.69 seconds
Started Feb 08 01:07:38 PM PST 24
Finished Feb 08 01:07:43 PM PST 24
Peak memory 208588 kb
Host smart-a7d7c859-fc01-4fcc-bdac-25059065b7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526855422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3526855422
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3925212317
Short name T706
Test name
Test status
Simulation time 41626028 ps
CPU time 1.6 seconds
Started Feb 08 01:07:33 PM PST 24
Finished Feb 08 01:07:35 PM PST 24
Peak memory 209988 kb
Host smart-04a33c31-2b2c-4492-b80a-ffbdddba4215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925212317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3925212317
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2589079154
Short name T82
Test name
Test status
Simulation time 15205988 ps
CPU time 0.74 seconds
Started Feb 08 01:07:39 PM PST 24
Finished Feb 08 01:07:41 PM PST 24
Peak memory 205880 kb
Host smart-9dec668a-16a4-43dc-9a57-03798df91c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589079154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2589079154
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3160814408
Short name T26
Test name
Test status
Simulation time 41257252 ps
CPU time 1.35 seconds
Started Feb 08 01:07:37 PM PST 24
Finished Feb 08 01:07:39 PM PST 24
Peak memory 208744 kb
Host smart-163a8788-8cc3-4707-8350-11a00a08deb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160814408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3160814408
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1226433582
Short name T689
Test name
Test status
Simulation time 73856834 ps
CPU time 3.34 seconds
Started Feb 08 01:07:32 PM PST 24
Finished Feb 08 01:07:36 PM PST 24
Peak memory 214308 kb
Host smart-3e9d1ab0-0a21-4f80-8d57-1c72dcbb8619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226433582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1226433582
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2412799855
Short name T1038
Test name
Test status
Simulation time 3552998844 ps
CPU time 21.53 seconds
Started Feb 08 01:07:38 PM PST 24
Finished Feb 08 01:08:01 PM PST 24
Peak memory 214376 kb
Host smart-3e754aaa-a05d-484e-90d4-1f6b86dfe4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412799855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2412799855
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.761891776
Short name T317
Test name
Test status
Simulation time 264968953 ps
CPU time 4.1 seconds
Started Feb 08 01:07:34 PM PST 24
Finished Feb 08 01:07:39 PM PST 24
Peak memory 209740 kb
Host smart-0c742658-989b-41a1-ae9a-8000e7f35c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761891776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.761891776
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2127740983
Short name T660
Test name
Test status
Simulation time 1849620220 ps
CPU time 12.65 seconds
Started Feb 08 01:07:34 PM PST 24
Finished Feb 08 01:07:48 PM PST 24
Peak memory 207928 kb
Host smart-adaa6bdb-3381-40d8-97c0-5a4158862741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127740983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2127740983
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1362592048
Short name T666
Test name
Test status
Simulation time 115193781 ps
CPU time 3.96 seconds
Started Feb 08 01:07:39 PM PST 24
Finished Feb 08 01:07:44 PM PST 24
Peak memory 208560 kb
Host smart-7974b955-ed04-49a1-a41d-7430ceb3300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362592048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1362592048
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3352067041
Short name T773
Test name
Test status
Simulation time 52054815 ps
CPU time 2.74 seconds
Started Feb 08 01:07:37 PM PST 24
Finished Feb 08 01:07:41 PM PST 24
Peak memory 206972 kb
Host smart-677ef947-945e-4786-84f3-8bdb7a5c338c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352067041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3352067041
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3966347040
Short name T596
Test name
Test status
Simulation time 819605777 ps
CPU time 3.02 seconds
Started Feb 08 01:07:38 PM PST 24
Finished Feb 08 01:07:42 PM PST 24
Peak memory 208740 kb
Host smart-3c7dda27-92c2-41ec-9210-769b7cdb9606
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966347040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3966347040
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2899549500
Short name T636
Test name
Test status
Simulation time 47299391 ps
CPU time 2.93 seconds
Started Feb 08 01:07:34 PM PST 24
Finished Feb 08 01:07:38 PM PST 24
Peak memory 208920 kb
Host smart-e01e9181-688c-4153-ab7c-00ffb38e7d30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899549500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2899549500
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.994988658
Short name T1049
Test name
Test status
Simulation time 77440463 ps
CPU time 3.65 seconds
Started Feb 08 01:07:35 PM PST 24
Finished Feb 08 01:07:40 PM PST 24
Peak memory 218148 kb
Host smart-16ff8ac7-dc32-4580-b3fc-b79b760a0f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994988658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.994988658
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2880832360
Short name T711
Test name
Test status
Simulation time 3216309813 ps
CPU time 17.59 seconds
Started Feb 08 01:07:39 PM PST 24
Finished Feb 08 01:07:58 PM PST 24
Peak memory 208076 kb
Host smart-3ecbb072-bea7-42e1-b413-6c93a6a37091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880832360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2880832360
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.4261286466
Short name T237
Test name
Test status
Simulation time 242810860 ps
CPU time 5.93 seconds
Started Feb 08 01:07:40 PM PST 24
Finished Feb 08 01:07:47 PM PST 24
Peak memory 215592 kb
Host smart-75bfb5e6-9124-4a14-b02c-d4bae7cbe01c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261286466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4261286466
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2546648876
Short name T647
Test name
Test status
Simulation time 232623038 ps
CPU time 10.97 seconds
Started Feb 08 01:07:39 PM PST 24
Finished Feb 08 01:07:51 PM PST 24
Peak memory 219908 kb
Host smart-d422b017-9e7c-4cb2-aebf-5b12bfb1b3e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546648876 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2546648876
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1548064432
Short name T984
Test name
Test status
Simulation time 626045788 ps
CPU time 16.97 seconds
Started Feb 08 01:07:38 PM PST 24
Finished Feb 08 01:07:56 PM PST 24
Peak memory 208872 kb
Host smart-1a93d1fe-b9d1-4970-9073-1d3655c6bc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548064432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1548064432
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.564687875
Short name T721
Test name
Test status
Simulation time 62667170 ps
CPU time 3.24 seconds
Started Feb 08 01:07:35 PM PST 24
Finished Feb 08 01:07:39 PM PST 24
Peak memory 210416 kb
Host smart-e05af8b2-f318-427a-b066-bc98c0215c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564687875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.564687875
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2260229466
Short name T602
Test name
Test status
Simulation time 43264365 ps
CPU time 0.71 seconds
Started Feb 08 01:04:14 PM PST 24
Finished Feb 08 01:04:15 PM PST 24
Peak memory 205796 kb
Host smart-91e55262-5085-4e19-b405-fbdf4903c633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260229466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2260229466
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3646636469
Short name T289
Test name
Test status
Simulation time 46810188 ps
CPU time 3.25 seconds
Started Feb 08 01:06:07 PM PST 24
Finished Feb 08 01:06:14 PM PST 24
Peak memory 214024 kb
Host smart-0d0690e0-0260-4768-9790-bc6c94938a38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646636469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3646636469
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3243735695
Short name T986
Test name
Test status
Simulation time 281363030 ps
CPU time 6.38 seconds
Started Feb 08 01:04:19 PM PST 24
Finished Feb 08 01:04:26 PM PST 24
Peak memory 208824 kb
Host smart-817f552b-8192-44e2-92d1-b37c482a5041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243735695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3243735695
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.172637357
Short name T679
Test name
Test status
Simulation time 405598140 ps
CPU time 7.52 seconds
Started Feb 08 01:04:13 PM PST 24
Finished Feb 08 01:04:21 PM PST 24
Peak memory 218616 kb
Host smart-c5e2a17c-eb39-4e15-9ba3-addcb429f223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172637357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.172637357
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1048459505
Short name T930
Test name
Test status
Simulation time 123814758 ps
CPU time 2.71 seconds
Started Feb 08 01:04:18 PM PST 24
Finished Feb 08 01:04:21 PM PST 24
Peak memory 214432 kb
Host smart-6a19a087-303f-4fd4-90b6-514a79dc25c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048459505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1048459505
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1313879930
Short name T856
Test name
Test status
Simulation time 1433016926 ps
CPU time 11.41 seconds
Started Feb 08 01:04:12 PM PST 24
Finished Feb 08 01:04:24 PM PST 24
Peak memory 209648 kb
Host smart-5b4c91e7-cdaa-422e-9443-eefee44abdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313879930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1313879930
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3423907087
Short name T204
Test name
Test status
Simulation time 252653195 ps
CPU time 3.33 seconds
Started Feb 08 01:04:28 PM PST 24
Finished Feb 08 01:04:32 PM PST 24
Peak memory 207456 kb
Host smart-896f96d3-dc49-4483-a385-3de0df28d213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423907087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3423907087
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2059991948
Short name T967
Test name
Test status
Simulation time 2132602311 ps
CPU time 14.85 seconds
Started Feb 08 01:06:07 PM PST 24
Finished Feb 08 01:06:25 PM PST 24
Peak memory 208736 kb
Host smart-206831c2-d962-4672-a4b7-38899817f6a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059991948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2059991948
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1440535878
Short name T635
Test name
Test status
Simulation time 199825085 ps
CPU time 7.61 seconds
Started Feb 08 01:04:14 PM PST 24
Finished Feb 08 01:04:23 PM PST 24
Peak memory 207848 kb
Host smart-d0ad2805-fb83-4d15-9c1c-0720e2b3a8db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440535878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1440535878
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.685884453
Short name T413
Test name
Test status
Simulation time 20693688 ps
CPU time 1.62 seconds
Started Feb 08 01:05:58 PM PST 24
Finished Feb 08 01:06:07 PM PST 24
Peak memory 205080 kb
Host smart-f5e8b321-d2d9-45aa-9a35-ca3963fc6193
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685884453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.685884453
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2291820483
Short name T1020
Test name
Test status
Simulation time 5927879429 ps
CPU time 55.13 seconds
Started Feb 08 01:04:12 PM PST 24
Finished Feb 08 01:05:08 PM PST 24
Peak memory 209092 kb
Host smart-10a5b0e4-b5f6-4f9e-add2-1f7bcc429c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291820483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2291820483
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.413472435
Short name T933
Test name
Test status
Simulation time 382596903 ps
CPU time 9.05 seconds
Started Feb 08 01:04:13 PM PST 24
Finished Feb 08 01:04:23 PM PST 24
Peak memory 208244 kb
Host smart-b9052f6a-ad57-4e08-a804-83b3a4c46001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413472435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.413472435
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1687253023
Short name T1029
Test name
Test status
Simulation time 296059570 ps
CPU time 3.49 seconds
Started Feb 08 01:04:21 PM PST 24
Finished Feb 08 01:04:25 PM PST 24
Peak memory 214368 kb
Host smart-cbe5c339-b426-430b-a08a-c77f418f3ce4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687253023 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.1687253023
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.829039190
Short name T392
Test name
Test status
Simulation time 1446952866 ps
CPU time 11.73 seconds
Started Feb 08 01:04:18 PM PST 24
Finished Feb 08 01:04:30 PM PST 24
Peak memory 219744 kb
Host smart-2f33f0fa-3e9f-4f62-8fd3-68b649c18044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829039190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.829039190
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.237413769
Short name T785
Test name
Test status
Simulation time 323326766 ps
CPU time 3.87 seconds
Started Feb 08 01:04:13 PM PST 24
Finished Feb 08 01:04:18 PM PST 24
Peak memory 210020 kb
Host smart-f1b34f2a-3a3a-4ffc-ba97-519c40082a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237413769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.237413769
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2532247556
Short name T735
Test name
Test status
Simulation time 33053709 ps
CPU time 0.86 seconds
Started Feb 08 01:07:33 PM PST 24
Finished Feb 08 01:07:35 PM PST 24
Peak memory 205708 kb
Host smart-bf3c13c3-fa0f-4e8d-9624-d32ea8eca71d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532247556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2532247556
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.501946756
Short name T839
Test name
Test status
Simulation time 114309728 ps
CPU time 5.14 seconds
Started Feb 08 01:07:52 PM PST 24
Finished Feb 08 01:07:58 PM PST 24
Peak memory 208508 kb
Host smart-a08498a2-118d-4103-96f6-02f4c6d5d0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501946756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.501946756
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1344077194
Short name T923
Test name
Test status
Simulation time 284627217 ps
CPU time 3.6 seconds
Started Feb 08 01:07:41 PM PST 24
Finished Feb 08 01:07:45 PM PST 24
Peak memory 210284 kb
Host smart-4465263a-fde9-4c29-bf41-32d9c4f1352e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344077194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1344077194
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.4289269330
Short name T262
Test name
Test status
Simulation time 98087812 ps
CPU time 4.17 seconds
Started Feb 08 01:07:41 PM PST 24
Finished Feb 08 01:07:46 PM PST 24
Peak memory 214500 kb
Host smart-9a5be2a5-a8d7-42ea-9312-5885d6170497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289269330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4289269330
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1219014035
Short name T250
Test name
Test status
Simulation time 56655334 ps
CPU time 3.43 seconds
Started Feb 08 01:07:42 PM PST 24
Finished Feb 08 01:07:46 PM PST 24
Peak memory 222532 kb
Host smart-59ff8749-fc10-4a16-b7dd-6f3a685e9246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219014035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1219014035
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.234609021
Short name T48
Test name
Test status
Simulation time 111763255 ps
CPU time 3.5 seconds
Started Feb 08 01:07:52 PM PST 24
Finished Feb 08 01:07:57 PM PST 24
Peak memory 221904 kb
Host smart-a632bd08-1645-427f-9bc4-a4ac5746bc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234609021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.234609021
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2510424391
Short name T793
Test name
Test status
Simulation time 226610784 ps
CPU time 4.14 seconds
Started Feb 08 01:07:42 PM PST 24
Finished Feb 08 01:07:47 PM PST 24
Peak memory 214136 kb
Host smart-bfd5a820-beea-4401-8d21-37a798273984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510424391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2510424391
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.489630896
Short name T747
Test name
Test status
Simulation time 6400080298 ps
CPU time 49.33 seconds
Started Feb 08 01:07:32 PM PST 24
Finished Feb 08 01:08:22 PM PST 24
Peak memory 208840 kb
Host smart-9bd8558b-e36d-4e96-9c9f-ea54b32e7d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489630896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.489630896
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3668686270
Short name T386
Test name
Test status
Simulation time 862638241 ps
CPU time 4.01 seconds
Started Feb 08 01:07:34 PM PST 24
Finished Feb 08 01:07:39 PM PST 24
Peak memory 208936 kb
Host smart-daeed7dd-5844-4594-851a-78a2fc57b51f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668686270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3668686270
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.16909815
Short name T899
Test name
Test status
Simulation time 47636858 ps
CPU time 2.55 seconds
Started Feb 08 01:07:32 PM PST 24
Finished Feb 08 01:07:35 PM PST 24
Peak memory 207976 kb
Host smart-e4664c3a-2dc9-4ad6-81ef-873a8d451140
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16909815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.16909815
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2752013553
Short name T672
Test name
Test status
Simulation time 2981981967 ps
CPU time 17.09 seconds
Started Feb 08 01:07:38 PM PST 24
Finished Feb 08 01:07:56 PM PST 24
Peak memory 208036 kb
Host smart-561b915f-6bda-416a-92a2-7ce69481caf4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752013553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2752013553
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.95918376
Short name T663
Test name
Test status
Simulation time 39025873 ps
CPU time 1.9 seconds
Started Feb 08 01:07:44 PM PST 24
Finished Feb 08 01:07:46 PM PST 24
Peak memory 206768 kb
Host smart-0dda02cf-e65e-4ee8-9f45-77bf8727a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95918376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.95918376
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2612394750
Short name T678
Test name
Test status
Simulation time 44217098 ps
CPU time 2.7 seconds
Started Feb 08 01:07:34 PM PST 24
Finished Feb 08 01:07:38 PM PST 24
Peak memory 208392 kb
Host smart-3df98114-0b5b-46ff-92af-8905e087d0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612394750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2612394750
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2293209500
Short name T76
Test name
Test status
Simulation time 3307286224 ps
CPU time 43.08 seconds
Started Feb 08 01:07:43 PM PST 24
Finished Feb 08 01:08:27 PM PST 24
Peak memory 215412 kb
Host smart-13551f14-38f2-4db5-8600-0722804d181f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293209500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2293209500
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.517919351
Short name T741
Test name
Test status
Simulation time 166804029 ps
CPU time 7.36 seconds
Started Feb 08 01:07:53 PM PST 24
Finished Feb 08 01:08:01 PM PST 24
Peak memory 219940 kb
Host smart-19a82480-3954-4e0b-b3e3-a954b624b713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517919351 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.517919351
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1842595819
Short name T298
Test name
Test status
Simulation time 43761753 ps
CPU time 3.07 seconds
Started Feb 08 01:07:44 PM PST 24
Finished Feb 08 01:07:48 PM PST 24
Peak memory 214436 kb
Host smart-dd2ef468-280a-40f6-a804-4f26255db600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842595819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1842595819
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1558462156
Short name T171
Test name
Test status
Simulation time 369719848 ps
CPU time 2.15 seconds
Started Feb 08 01:07:45 PM PST 24
Finished Feb 08 01:07:48 PM PST 24
Peak memory 209696 kb
Host smart-38c75e2f-df36-4266-9b0a-9e86cf88653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558462156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1558462156
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3276579490
Short name T893
Test name
Test status
Simulation time 34925229 ps
CPU time 1.02 seconds
Started Feb 08 01:07:51 PM PST 24
Finished Feb 08 01:07:53 PM PST 24
Peak memory 205996 kb
Host smart-91460e30-ab98-4537-96fe-c469090e718f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276579490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3276579490
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3003250652
Short name T136
Test name
Test status
Simulation time 204241898 ps
CPU time 3.9 seconds
Started Feb 08 01:07:48 PM PST 24
Finished Feb 08 01:07:53 PM PST 24
Peak memory 214324 kb
Host smart-2785cf72-720a-4235-aaac-e590a14ef99f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003250652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3003250652
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.74049485
Short name T870
Test name
Test status
Simulation time 39533336 ps
CPU time 2.15 seconds
Started Feb 08 01:07:35 PM PST 24
Finished Feb 08 01:07:38 PM PST 24
Peak memory 208212 kb
Host smart-92d6d894-bab7-486a-b073-9dd083f309d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74049485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.74049485
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.4250447619
Short name T286
Test name
Test status
Simulation time 546326121 ps
CPU time 4.56 seconds
Started Feb 08 01:07:53 PM PST 24
Finished Feb 08 01:07:59 PM PST 24
Peak memory 208788 kb
Host smart-716a9dc4-8df5-444d-a167-87f374481aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250447619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.4250447619
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.4043204140
Short name T45
Test name
Test status
Simulation time 49941128 ps
CPU time 1.77 seconds
Started Feb 08 01:07:42 PM PST 24
Finished Feb 08 01:07:45 PM PST 24
Peak memory 214336 kb
Host smart-94d6e0fc-744a-4174-9094-52b286aec8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043204140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.4043204140
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1252689646
Short name T896
Test name
Test status
Simulation time 86338144 ps
CPU time 4.09 seconds
Started Feb 08 01:07:50 PM PST 24
Finished Feb 08 01:07:56 PM PST 24
Peak memory 208800 kb
Host smart-82c124a1-0f30-41ce-a122-b9da2aa3c01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252689646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1252689646
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2735860064
Short name T380
Test name
Test status
Simulation time 101863842 ps
CPU time 3.42 seconds
Started Feb 08 01:07:42 PM PST 24
Finished Feb 08 01:07:47 PM PST 24
Peak memory 206788 kb
Host smart-01aa90c7-35e8-4f79-8ca4-b63a8abb7c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735860064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2735860064
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.511341251
Short name T182
Test name
Test status
Simulation time 316934092 ps
CPU time 4.12 seconds
Started Feb 08 01:07:53 PM PST 24
Finished Feb 08 01:07:58 PM PST 24
Peak memory 206948 kb
Host smart-2d2f5ef7-3513-4752-93b5-7ad10269e30d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511341251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.511341251
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1371184862
Short name T807
Test name
Test status
Simulation time 940561236 ps
CPU time 24.85 seconds
Started Feb 08 01:07:52 PM PST 24
Finished Feb 08 01:08:18 PM PST 24
Peak memory 207944 kb
Host smart-8f832f86-3f07-4d59-8382-be5665a6d6b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371184862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1371184862
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3774101685
Short name T287
Test name
Test status
Simulation time 370704396 ps
CPU time 3.58 seconds
Started Feb 08 01:07:53 PM PST 24
Finished Feb 08 01:07:57 PM PST 24
Peak memory 208616 kb
Host smart-b66aad5a-7291-47a8-a374-874e8bbd5f31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774101685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3774101685
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1544246644
Short name T987
Test name
Test status
Simulation time 464407180 ps
CPU time 4.03 seconds
Started Feb 08 01:07:47 PM PST 24
Finished Feb 08 01:07:52 PM PST 24
Peak memory 207860 kb
Host smart-c02ce07a-b488-4d78-ae96-092034b32607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544246644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1544246644
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1723706851
Short name T129
Test name
Test status
Simulation time 57646821 ps
CPU time 1.8 seconds
Started Feb 08 01:07:34 PM PST 24
Finished Feb 08 01:07:36 PM PST 24
Peak memory 206868 kb
Host smart-44834d52-949a-4ad1-8e36-bc7556b3f2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723706851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1723706851
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2434867089
Short name T123
Test name
Test status
Simulation time 185240400 ps
CPU time 5.55 seconds
Started Feb 08 01:07:43 PM PST 24
Finished Feb 08 01:07:49 PM PST 24
Peak memory 222364 kb
Host smart-44063c68-7c87-474e-a506-59367a9b35f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434867089 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2434867089
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.643624986
Short name T733
Test name
Test status
Simulation time 347492489 ps
CPU time 5.23 seconds
Started Feb 08 01:07:52 PM PST 24
Finished Feb 08 01:07:59 PM PST 24
Peak memory 208952 kb
Host smart-0dedc31e-69b7-4497-975c-f1e4b7ad0d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643624986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.643624986
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2189006805
Short name T410
Test name
Test status
Simulation time 56789304 ps
CPU time 2.09 seconds
Started Feb 08 01:07:43 PM PST 24
Finished Feb 08 01:07:46 PM PST 24
Peak memory 210096 kb
Host smart-cfc26dd6-8d10-4601-85bf-801e4ab5092e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189006805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2189006805
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.423044331
Short name T787
Test name
Test status
Simulation time 10800599 ps
CPU time 0.72 seconds
Started Feb 08 01:07:51 PM PST 24
Finished Feb 08 01:07:53 PM PST 24
Peak memory 205828 kb
Host smart-4170f80e-e9ad-4940-a14d-0dae209d439e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423044331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.423044331
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1486306785
Short name T1064
Test name
Test status
Simulation time 36633462 ps
CPU time 2.76 seconds
Started Feb 08 01:07:48 PM PST 24
Finished Feb 08 01:07:52 PM PST 24
Peak memory 214804 kb
Host smart-2c405e67-dcfd-4c6f-af8a-de06335786d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486306785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1486306785
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1790440316
Short name T71
Test name
Test status
Simulation time 272761872 ps
CPU time 5.5 seconds
Started Feb 08 01:07:40 PM PST 24
Finished Feb 08 01:07:47 PM PST 24
Peak memory 209192 kb
Host smart-bb8d0452-487c-4e2a-a24b-f8b777a36994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790440316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1790440316
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3306571244
Short name T924
Test name
Test status
Simulation time 238128224 ps
CPU time 6.58 seconds
Started Feb 08 01:07:44 PM PST 24
Finished Feb 08 01:07:51 PM PST 24
Peak memory 210296 kb
Host smart-309bd9b1-4ae7-4ab0-8741-f0b228cbd21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306571244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3306571244
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1774730897
Short name T917
Test name
Test status
Simulation time 415280686 ps
CPU time 6.22 seconds
Started Feb 08 01:07:42 PM PST 24
Finished Feb 08 01:07:50 PM PST 24
Peak memory 209732 kb
Host smart-41b5e4bd-b5c8-42dc-8cfa-e6e98bd1a043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774730897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1774730897
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.234156152
Short name T859
Test name
Test status
Simulation time 128585917 ps
CPU time 3.52 seconds
Started Feb 08 01:07:38 PM PST 24
Finished Feb 08 01:07:43 PM PST 24
Peak memory 208228 kb
Host smart-f1bc037b-6963-41a6-b040-5c4670df70f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234156152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.234156152
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.4025673680
Short name T840
Test name
Test status
Simulation time 331389507 ps
CPU time 3.27 seconds
Started Feb 08 01:07:48 PM PST 24
Finished Feb 08 01:07:52 PM PST 24
Peak memory 206788 kb
Host smart-ae3c54ba-e968-4113-8279-2ffd4d3940c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025673680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4025673680
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3297788363
Short name T664
Test name
Test status
Simulation time 182750408 ps
CPU time 5.62 seconds
Started Feb 08 01:07:48 PM PST 24
Finished Feb 08 01:07:54 PM PST 24
Peak memory 208004 kb
Host smart-1bc9d07a-bb86-4ed3-b017-eab94365deb3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297788363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3297788363
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2214881041
Short name T895
Test name
Test status
Simulation time 310395645 ps
CPU time 6.84 seconds
Started Feb 08 01:07:48 PM PST 24
Finished Feb 08 01:07:56 PM PST 24
Peak memory 209048 kb
Host smart-e1799f0a-e5ce-4640-bd04-91ebab8c40c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214881041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2214881041
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1423868134
Short name T431
Test name
Test status
Simulation time 69809258 ps
CPU time 2.54 seconds
Started Feb 08 01:07:41 PM PST 24
Finished Feb 08 01:07:44 PM PST 24
Peak memory 208408 kb
Host smart-383ac4fa-c980-4e75-aeee-fcc4dc5528af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423868134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1423868134
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.4263643024
Short name T603
Test name
Test status
Simulation time 356162895 ps
CPU time 3.72 seconds
Started Feb 08 01:07:42 PM PST 24
Finished Feb 08 01:07:47 PM PST 24
Peak memory 208404 kb
Host smart-3208ad7b-02f1-4089-ac6f-7a6ca4fbdb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263643024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4263643024
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.463922571
Short name T864
Test name
Test status
Simulation time 213313203 ps
CPU time 7.38 seconds
Started Feb 08 01:07:51 PM PST 24
Finished Feb 08 01:08:00 PM PST 24
Peak memory 219940 kb
Host smart-4b7ed4d6-5879-460e-8f32-0c9c5c07febc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463922571 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.463922571
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2530767689
Short name T373
Test name
Test status
Simulation time 144746783 ps
CPU time 5.72 seconds
Started Feb 08 01:07:41 PM PST 24
Finished Feb 08 01:07:48 PM PST 24
Peak memory 208684 kb
Host smart-cc5ce6c0-c454-491a-bf4b-664bc1aa5dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530767689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2530767689
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2916887434
Short name T713
Test name
Test status
Simulation time 66288279 ps
CPU time 2.78 seconds
Started Feb 08 01:07:51 PM PST 24
Finished Feb 08 01:07:55 PM PST 24
Peak memory 210352 kb
Host smart-1f9be402-ea94-4442-8648-36f0bb3979ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916887434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2916887434
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1328290395
Short name T100
Test name
Test status
Simulation time 289480399 ps
CPU time 1.01 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:04 PM PST 24
Peak memory 206048 kb
Host smart-e91e3915-79b8-48cc-b6d5-9ce8cb375907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328290395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1328290395
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.4220602540
Short name T284
Test name
Test status
Simulation time 209987664 ps
CPU time 4.22 seconds
Started Feb 08 01:07:45 PM PST 24
Finished Feb 08 01:07:51 PM PST 24
Peak memory 218840 kb
Host smart-0451879f-6612-4aaf-8227-5ed26e1bfda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220602540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.4220602540
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2044912612
Short name T633
Test name
Test status
Simulation time 359313680 ps
CPU time 4.66 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:07 PM PST 24
Peak memory 214232 kb
Host smart-c5a2e211-1173-46cd-8758-0e61c16927a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044912612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2044912612
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3746771860
Short name T1057
Test name
Test status
Simulation time 57410996 ps
CPU time 3.53 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:07 PM PST 24
Peak memory 214236 kb
Host smart-9071fd60-9ea7-4466-b230-1aa24818ded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746771860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3746771860
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2482416329
Short name T1008
Test name
Test status
Simulation time 78228173 ps
CPU time 3.96 seconds
Started Feb 08 01:07:44 PM PST 24
Finished Feb 08 01:07:49 PM PST 24
Peak memory 209148 kb
Host smart-6e2bbd08-77c7-49a3-8176-a1ce0acb3bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482416329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2482416329
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1495478450
Short name T639
Test name
Test status
Simulation time 99002830 ps
CPU time 3.69 seconds
Started Feb 08 01:07:43 PM PST 24
Finished Feb 08 01:07:48 PM PST 24
Peak memory 207512 kb
Host smart-960c794e-afcf-46c5-b3b2-25242b2683a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495478450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1495478450
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.203798633
Short name T332
Test name
Test status
Simulation time 287514618 ps
CPU time 3.57 seconds
Started Feb 08 01:07:39 PM PST 24
Finished Feb 08 01:07:43 PM PST 24
Peak memory 208696 kb
Host smart-f2e26f98-8916-4293-b389-35ebf423e136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203798633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.203798633
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.108693330
Short name T38
Test name
Test status
Simulation time 85376524 ps
CPU time 1.72 seconds
Started Feb 08 01:07:45 PM PST 24
Finished Feb 08 01:07:47 PM PST 24
Peak memory 206728 kb
Host smart-54d046b1-61f8-47df-b5ee-3e20a76e66a4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108693330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.108693330
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3520047727
Short name T580
Test name
Test status
Simulation time 64892911 ps
CPU time 2.29 seconds
Started Feb 08 01:07:42 PM PST 24
Finished Feb 08 01:07:46 PM PST 24
Peak memory 206992 kb
Host smart-e3782763-144c-44f8-8656-93601ecf87ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520047727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3520047727
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2871916465
Short name T643
Test name
Test status
Simulation time 2041606483 ps
CPU time 15.96 seconds
Started Feb 08 01:07:52 PM PST 24
Finished Feb 08 01:08:09 PM PST 24
Peak memory 208900 kb
Host smart-3049405d-2215-4ce0-86cd-2c157b7347bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871916465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2871916465
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3245691357
Short name T651
Test name
Test status
Simulation time 90182934 ps
CPU time 4.04 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:07 PM PST 24
Peak memory 214324 kb
Host smart-2423496f-d879-4b2d-88f3-86570a77027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245691357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3245691357
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2866787149
Short name T696
Test name
Test status
Simulation time 85519540 ps
CPU time 1.71 seconds
Started Feb 08 01:07:44 PM PST 24
Finished Feb 08 01:07:46 PM PST 24
Peak memory 206828 kb
Host smart-cde7ef30-f6c4-42d8-99af-64cf79c88771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866787149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2866787149
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.118966147
Short name T589
Test name
Test status
Simulation time 738983318 ps
CPU time 4.11 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:07 PM PST 24
Peak memory 222644 kb
Host smart-6dfeb034-684c-4b24-9e28-94203baa283e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118966147 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.118966147
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.262555344
Short name T436
Test name
Test status
Simulation time 96547363 ps
CPU time 4.59 seconds
Started Feb 08 01:08:00 PM PST 24
Finished Feb 08 01:08:06 PM PST 24
Peak memory 208984 kb
Host smart-8e1fe549-0a7e-49f0-a23e-3afcfa6376a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262555344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.262555344
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2851897927
Short name T17
Test name
Test status
Simulation time 47734336 ps
CPU time 2.37 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:05 PM PST 24
Peak memory 210044 kb
Host smart-2aff7c51-4d96-46d9-a85f-d3856f144a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851897927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2851897927
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2821763566
Short name T719
Test name
Test status
Simulation time 20866039 ps
CPU time 0.89 seconds
Started Feb 08 01:08:00 PM PST 24
Finished Feb 08 01:08:02 PM PST 24
Peak memory 205888 kb
Host smart-43f7baf3-88ed-4b16-9dfa-019589899c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821763566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2821763566
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2915860805
Short name T974
Test name
Test status
Simulation time 267876193 ps
CPU time 10.18 seconds
Started Feb 08 01:08:06 PM PST 24
Finished Feb 08 01:08:17 PM PST 24
Peak memory 210124 kb
Host smart-8c09e905-2e64-445e-8127-e71280ca3147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915860805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2915860805
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.254345684
Short name T1000
Test name
Test status
Simulation time 174316144 ps
CPU time 2.67 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:05 PM PST 24
Peak memory 207212 kb
Host smart-7f1971a1-f0f8-4b68-88dc-639f6cee48f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254345684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.254345684
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2270267063
Short name T348
Test name
Test status
Simulation time 207871499 ps
CPU time 6.45 seconds
Started Feb 08 01:08:00 PM PST 24
Finished Feb 08 01:08:08 PM PST 24
Peak memory 219384 kb
Host smart-8d877290-5d38-46de-969e-1b8f99405a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270267063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2270267063
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1271652882
Short name T718
Test name
Test status
Simulation time 167492945 ps
CPU time 6.25 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:10 PM PST 24
Peak memory 210112 kb
Host smart-cb694f41-f7e0-4af0-8dae-0a5914b07066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271652882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1271652882
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3314202204
Short name T225
Test name
Test status
Simulation time 76825327 ps
CPU time 3.28 seconds
Started Feb 08 01:08:09 PM PST 24
Finished Feb 08 01:08:13 PM PST 24
Peak memory 220076 kb
Host smart-268087ad-d5ec-4e74-b6e5-43ab22cdcdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314202204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3314202204
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1805413587
Short name T303
Test name
Test status
Simulation time 196677690 ps
CPU time 4.1 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:09 PM PST 24
Peak memory 207884 kb
Host smart-a5d42644-3c5b-4d65-b779-9a171e17e618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805413587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1805413587
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3354584948
Short name T743
Test name
Test status
Simulation time 511433330 ps
CPU time 5.86 seconds
Started Feb 08 01:08:07 PM PST 24
Finished Feb 08 01:08:14 PM PST 24
Peak memory 206852 kb
Host smart-e4e90e3a-a3fb-4926-9689-6b8dc62a493f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354584948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3354584948
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3214574345
Short name T648
Test name
Test status
Simulation time 213444763 ps
CPU time 5.89 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:11 PM PST 24
Peak memory 207952 kb
Host smart-0005592d-8c14-42fd-9c72-ebe460e88661
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214574345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3214574345
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2716689970
Short name T950
Test name
Test status
Simulation time 994146744 ps
CPU time 7.85 seconds
Started Feb 08 01:08:05 PM PST 24
Finished Feb 08 01:08:14 PM PST 24
Peak memory 208504 kb
Host smart-acbe79ae-15fa-4e8a-918d-d34c8d1a154e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716689970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2716689970
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1034437246
Short name T810
Test name
Test status
Simulation time 240169227 ps
CPU time 3.32 seconds
Started Feb 08 01:08:05 PM PST 24
Finished Feb 08 01:08:09 PM PST 24
Peak memory 206872 kb
Host smart-ba58dd6c-316c-4610-a3c8-739f1c6dfa54
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034437246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1034437246
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2226453600
Short name T617
Test name
Test status
Simulation time 451779045 ps
CPU time 5.27 seconds
Started Feb 08 01:08:09 PM PST 24
Finished Feb 08 01:08:15 PM PST 24
Peak memory 208672 kb
Host smart-d9300de1-e439-486c-84c6-faa87115a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226453600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2226453600
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.4271765611
Short name T998
Test name
Test status
Simulation time 149161179 ps
CPU time 4.1 seconds
Started Feb 08 01:08:07 PM PST 24
Finished Feb 08 01:08:12 PM PST 24
Peak memory 206780 kb
Host smart-33be7127-01e5-4acf-8091-76c2fb4b6dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271765611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.4271765611
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1786789533
Short name T244
Test name
Test status
Simulation time 15241930279 ps
CPU time 255.96 seconds
Started Feb 08 01:08:09 PM PST 24
Finished Feb 08 01:12:26 PM PST 24
Peak memory 217860 kb
Host smart-d565f65e-1307-41af-8fd1-ac4f0c5bd131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786789533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1786789533
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3612202538
Short name T638
Test name
Test status
Simulation time 443078397 ps
CPU time 3.62 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:07 PM PST 24
Peak memory 222540 kb
Host smart-afb6b247-22ab-48dd-85d0-2e61d9ab1221
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612202538 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3612202538
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1594349667
Short name T717
Test name
Test status
Simulation time 133488027 ps
CPU time 3.16 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:05 PM PST 24
Peak memory 207988 kb
Host smart-a2d6bc1d-8aea-45be-a8f7-93b1a73ce477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594349667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1594349667
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1839125008
Short name T837
Test name
Test status
Simulation time 476883106 ps
CPU time 2.9 seconds
Started Feb 08 01:08:12 PM PST 24
Finished Feb 08 01:08:16 PM PST 24
Peak memory 210064 kb
Host smart-0feda674-b772-4f81-9df0-c2b199ff6619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839125008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1839125008
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.720161203
Short name T625
Test name
Test status
Simulation time 16863790 ps
CPU time 0.79 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:02 PM PST 24
Peak memory 205872 kb
Host smart-0f336b4b-a5e1-4954-809b-5c76cfea56da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720161203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.720161203
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2836054378
Short name T148
Test name
Test status
Simulation time 3069351201 ps
CPU time 39.81 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:42 PM PST 24
Peak memory 214396 kb
Host smart-3e52b34b-c7be-4e09-8e19-1dcebcb13795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2836054378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2836054378
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2487662673
Short name T962
Test name
Test status
Simulation time 752010532 ps
CPU time 4.87 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:08 PM PST 24
Peak memory 207664 kb
Host smart-3e08bfc6-a834-4d05-8fab-d9a57651bff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487662673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2487662673
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1650961270
Short name T885
Test name
Test status
Simulation time 189640139 ps
CPU time 3.08 seconds
Started Feb 08 01:08:08 PM PST 24
Finished Feb 08 01:08:13 PM PST 24
Peak memory 208596 kb
Host smart-bc5c83fe-519b-413a-86cf-49665ed4bb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650961270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1650961270
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.315294234
Short name T280
Test name
Test status
Simulation time 52953717 ps
CPU time 3.47 seconds
Started Feb 08 01:08:03 PM PST 24
Finished Feb 08 01:08:07 PM PST 24
Peak memory 210568 kb
Host smart-614de00d-261d-45e7-b700-d4c5b1162994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315294234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.315294234
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3778461731
Short name T6
Test name
Test status
Simulation time 1581609915 ps
CPU time 3.44 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:09 PM PST 24
Peak memory 214324 kb
Host smart-e11d3f50-c960-4262-b6b0-ef06a40c5f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778461731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3778461731
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2322534679
Short name T877
Test name
Test status
Simulation time 270246069 ps
CPU time 4.66 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:08 PM PST 24
Peak memory 209804 kb
Host smart-89ccd07f-ec3e-48d2-b5c5-b99eed0e4a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322534679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2322534679
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.590939454
Short name T207
Test name
Test status
Simulation time 477454042 ps
CPU time 6.91 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:12 PM PST 24
Peak memory 207872 kb
Host smart-2d242a0e-7d0e-4fd2-b6e4-b16207c54f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590939454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.590939454
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4183407756
Short name T889
Test name
Test status
Simulation time 222165938 ps
CPU time 3.13 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:08 PM PST 24
Peak memory 206912 kb
Host smart-7d46ac6d-9fc2-4537-ad1a-95ff7c2e3d62
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183407756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4183407756
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.705663487
Short name T922
Test name
Test status
Simulation time 658601679 ps
CPU time 5.18 seconds
Started Feb 08 01:08:00 PM PST 24
Finished Feb 08 01:08:06 PM PST 24
Peak memory 208504 kb
Host smart-eb9fd840-7c08-4097-892c-455781126af9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705663487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.705663487
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.506798682
Short name T618
Test name
Test status
Simulation time 196918783 ps
CPU time 6.03 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:11 PM PST 24
Peak memory 206928 kb
Host smart-8eca1f1c-9c81-4e24-878a-fee19f0ffd9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506798682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.506798682
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.536436818
Short name T1036
Test name
Test status
Simulation time 1867944644 ps
CPU time 18.77 seconds
Started Feb 08 01:08:07 PM PST 24
Finished Feb 08 01:08:26 PM PST 24
Peak memory 214352 kb
Host smart-183159d1-1720-4aee-8e07-5459669ad09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536436818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.536436818
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2292077192
Short name T897
Test name
Test status
Simulation time 173093767 ps
CPU time 4.66 seconds
Started Feb 08 01:08:06 PM PST 24
Finished Feb 08 01:08:12 PM PST 24
Peak memory 208204 kb
Host smart-c739dfc6-2660-4aa6-b595-41457f2794c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292077192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2292077192
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2082149689
Short name T122
Test name
Test status
Simulation time 210252489 ps
CPU time 3.81 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:07 PM PST 24
Peak memory 222608 kb
Host smart-c09aace5-ac12-42c2-ab2e-1d5755e4586c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082149689 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2082149689
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3758284390
Short name T304
Test name
Test status
Simulation time 2373575512 ps
CPU time 10.74 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:15 PM PST 24
Peak memory 209768 kb
Host smart-a5300205-2d93-4961-be08-96c992bfc2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758284390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3758284390
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2324466007
Short name T37
Test name
Test status
Simulation time 444034950 ps
CPU time 2.63 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:05 PM PST 24
Peak memory 210160 kb
Host smart-124fbd6b-1f01-4b71-8747-ad5bd9546847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324466007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2324466007
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3405846162
Short name T582
Test name
Test status
Simulation time 45997768 ps
CPU time 0.85 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:04 PM PST 24
Peak memory 205892 kb
Host smart-4fdd9ee2-eb7f-460f-9309-ed802972cdea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405846162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3405846162
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1728596357
Short name T868
Test name
Test status
Simulation time 101652004 ps
CPU time 1.53 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:07 PM PST 24
Peak memory 207964 kb
Host smart-4798e812-37c3-43ac-bd90-a1971617c491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728596357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1728596357
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1889302405
Short name T21
Test name
Test status
Simulation time 467983119 ps
CPU time 8.16 seconds
Started Feb 08 01:08:05 PM PST 24
Finished Feb 08 01:08:14 PM PST 24
Peak memory 218960 kb
Host smart-3292a9b2-bb4a-43e4-92b1-a9f6785a47f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889302405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1889302405
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1196550529
Short name T976
Test name
Test status
Simulation time 1179860682 ps
CPU time 5.81 seconds
Started Feb 08 01:08:11 PM PST 24
Finished Feb 08 01:08:18 PM PST 24
Peak memory 214340 kb
Host smart-ff2f8e1e-7b75-46a9-855b-849804064b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196550529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1196550529
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1805552639
Short name T662
Test name
Test status
Simulation time 454086858 ps
CPU time 5.22 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:10 PM PST 24
Peak memory 214300 kb
Host smart-63d5753f-39aa-429c-b5fe-a2341e6df7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805552639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1805552639
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.827524387
Short name T127
Test name
Test status
Simulation time 32013530 ps
CPU time 2.41 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:06 PM PST 24
Peak memory 206744 kb
Host smart-94426f9a-32d2-4fe6-818e-79ca02044ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827524387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.827524387
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.533421515
Short name T181
Test name
Test status
Simulation time 167920713 ps
CPU time 5.13 seconds
Started Feb 08 01:08:05 PM PST 24
Finished Feb 08 01:08:11 PM PST 24
Peak memory 207556 kb
Host smart-a037d6d9-e406-4b30-ab3d-3755d54550da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533421515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.533421515
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.525432270
Short name T952
Test name
Test status
Simulation time 920800573 ps
CPU time 23.64 seconds
Started Feb 08 01:08:05 PM PST 24
Finished Feb 08 01:08:30 PM PST 24
Peak memory 208900 kb
Host smart-3600ae45-6636-4825-b656-0c88b723629b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525432270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.525432270
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1871121677
Short name T81
Test name
Test status
Simulation time 311457647 ps
CPU time 7.84 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:12 PM PST 24
Peak memory 209072 kb
Host smart-52a55e8f-fdb4-4388-9f5d-cc544baca649
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871121677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1871121677
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3256344920
Short name T770
Test name
Test status
Simulation time 1080948037 ps
CPU time 11.03 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:14 PM PST 24
Peak memory 207824 kb
Host smart-c64ed8de-005f-4c34-8f02-5d30de6d3200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256344920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3256344920
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.14095573
Short name T726
Test name
Test status
Simulation time 1829168643 ps
CPU time 12.49 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:14 PM PST 24
Peak memory 208876 kb
Host smart-b609eb89-b68a-4f6e-9267-d241b2c8fcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14095573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.14095573
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2339534635
Short name T940
Test name
Test status
Simulation time 2940799690 ps
CPU time 28.47 seconds
Started Feb 08 01:08:08 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 217252 kb
Host smart-b28c9a27-d453-4bad-8bd0-a5b43ce97750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339534635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2339534635
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.4054015372
Short name T801
Test name
Test status
Simulation time 154258207 ps
CPU time 5.01 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:10 PM PST 24
Peak memory 222572 kb
Host smart-3dfdbf3a-d0d7-40d0-af5d-55691f94b299
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054015372 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.4054015372
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1796845017
Short name T83
Test name
Test status
Simulation time 818030517 ps
CPU time 3.65 seconds
Started Feb 08 01:08:01 PM PST 24
Finished Feb 08 01:08:06 PM PST 24
Peak memory 209168 kb
Host smart-2731a787-f513-4e83-8ce3-905a3bca307b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796845017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1796845017
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.351900581
Short name T763
Test name
Test status
Simulation time 139858129 ps
CPU time 3.39 seconds
Started Feb 08 01:08:02 PM PST 24
Finished Feb 08 01:08:07 PM PST 24
Peak memory 209808 kb
Host smart-6fc4ae92-ea72-4141-8c9b-551f58d385f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351900581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.351900581
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.247940445
Short name T894
Test name
Test status
Simulation time 9448547 ps
CPU time 0.72 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:32 PM PST 24
Peak memory 205872 kb
Host smart-b6cc50d4-ebd5-4b74-a001-1c31b579899f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247940445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.247940445
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3112826301
Short name T925
Test name
Test status
Simulation time 322823892 ps
CPU time 2.08 seconds
Started Feb 08 01:08:26 PM PST 24
Finished Feb 08 01:08:29 PM PST 24
Peak memory 208128 kb
Host smart-cd275810-168d-453b-a4eb-cb69304495ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112826301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3112826301
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1791212557
Short name T369
Test name
Test status
Simulation time 167925821 ps
CPU time 4.45 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:09 PM PST 24
Peak memory 209700 kb
Host smart-fa2b8e10-5dd3-4844-985e-ca5c9dc14157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791212557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1791212557
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3458863023
Short name T888
Test name
Test status
Simulation time 111371919 ps
CPU time 4.28 seconds
Started Feb 08 01:08:14 PM PST 24
Finished Feb 08 01:08:19 PM PST 24
Peak memory 218080 kb
Host smart-8c28a395-03fd-4a2a-a57e-221dea1fbcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458863023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3458863023
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.318144483
Short name T364
Test name
Test status
Simulation time 1096454415 ps
CPU time 6.34 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 210400 kb
Host smart-92d569b9-dcce-4901-aa74-800d674d85b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318144483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.318144483
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1009680969
Short name T232
Test name
Test status
Simulation time 253780875 ps
CPU time 6.95 seconds
Started Feb 08 01:08:11 PM PST 24
Finished Feb 08 01:08:19 PM PST 24
Peak memory 214084 kb
Host smart-62f9d6e5-97cd-4a2e-8550-e3a97af73444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009680969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1009680969
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.389555636
Short name T39
Test name
Test status
Simulation time 93052394 ps
CPU time 4.19 seconds
Started Feb 08 01:08:16 PM PST 24
Finished Feb 08 01:08:21 PM PST 24
Peak memory 208804 kb
Host smart-1ac1d78d-a670-4999-a97f-ae7e45fd046b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389555636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.389555636
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3895710557
Short name T132
Test name
Test status
Simulation time 2378471370 ps
CPU time 16.59 seconds
Started Feb 08 01:08:12 PM PST 24
Finished Feb 08 01:08:29 PM PST 24
Peak memory 207868 kb
Host smart-b51fa9d6-c6ec-4c69-81fe-eff4d6250900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895710557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3895710557
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1579291104
Short name T919
Test name
Test status
Simulation time 1947587432 ps
CPU time 37.61 seconds
Started Feb 08 01:08:06 PM PST 24
Finished Feb 08 01:08:45 PM PST 24
Peak memory 207796 kb
Host smart-3c2a793d-a69d-42c9-82ea-1b220238a625
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579291104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1579291104
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.4012097910
Short name T586
Test name
Test status
Simulation time 121466582 ps
CPU time 4.78 seconds
Started Feb 08 01:08:04 PM PST 24
Finished Feb 08 01:08:10 PM PST 24
Peak memory 208344 kb
Host smart-e6ffd584-5c2a-4cb3-ad51-69e876f150b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012097910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.4012097910
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3627470139
Short name T813
Test name
Test status
Simulation time 56774426 ps
CPU time 2.96 seconds
Started Feb 08 01:08:06 PM PST 24
Finished Feb 08 01:08:10 PM PST 24
Peak memory 206348 kb
Host smart-ac248443-8128-48c5-bab9-16c59f0f1c76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627470139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3627470139
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1545995871
Short name T293
Test name
Test status
Simulation time 137277314 ps
CPU time 3.26 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:31 PM PST 24
Peak memory 209120 kb
Host smart-65122210-5425-4be6-a9ff-1984488a2475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545995871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1545995871
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.644019274
Short name T744
Test name
Test status
Simulation time 78742212 ps
CPU time 3.39 seconds
Started Feb 08 01:08:12 PM PST 24
Finished Feb 08 01:08:16 PM PST 24
Peak memory 208500 kb
Host smart-e67e42b3-f156-4b8d-b321-c803dac1b9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644019274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.644019274
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2972475446
Short name T388
Test name
Test status
Simulation time 19890870225 ps
CPU time 272.75 seconds
Started Feb 08 01:08:35 PM PST 24
Finished Feb 08 01:13:09 PM PST 24
Peak memory 220496 kb
Host smart-322cfe2f-8441-423d-8d08-1d592f696596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972475446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2972475446
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2070047647
Short name T702
Test name
Test status
Simulation time 298242268 ps
CPU time 8.42 seconds
Started Feb 08 01:08:31 PM PST 24
Finished Feb 08 01:08:41 PM PST 24
Peak memory 222592 kb
Host smart-cf082252-a7b3-4a3b-8912-d578da715572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070047647 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2070047647
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.122626917
Short name T313
Test name
Test status
Simulation time 258068005 ps
CPU time 7.32 seconds
Started Feb 08 01:08:13 PM PST 24
Finished Feb 08 01:08:21 PM PST 24
Peak memory 207124 kb
Host smart-c970c2c5-9975-44bb-aaec-a72f75abbd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122626917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.122626917
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1531627690
Short name T640
Test name
Test status
Simulation time 55451314 ps
CPU time 2.36 seconds
Started Feb 08 01:08:28 PM PST 24
Finished Feb 08 01:08:32 PM PST 24
Peak memory 210336 kb
Host smart-6bf0e474-5ea2-4bca-9088-3718b7e1a9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531627690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1531627690
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3843882582
Short name T920
Test name
Test status
Simulation time 44918904 ps
CPU time 0.78 seconds
Started Feb 08 01:08:34 PM PST 24
Finished Feb 08 01:08:35 PM PST 24
Peak memory 205872 kb
Host smart-af663ad2-bd41-451c-a3ba-7d7085240c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843882582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3843882582
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1620713566
Short name T428
Test name
Test status
Simulation time 64751012 ps
CPU time 3.58 seconds
Started Feb 08 01:08:25 PM PST 24
Finished Feb 08 01:08:29 PM PST 24
Peak memory 214296 kb
Host smart-0220dd36-5df6-40e2-ab34-3aa7d8216b18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620713566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1620713566
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3076770491
Short name T931
Test name
Test status
Simulation time 129180952 ps
CPU time 5.7 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 219032 kb
Host smart-a1ae957c-1694-4bcb-9703-d931ecb9ea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076770491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3076770491
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3342944146
Short name T828
Test name
Test status
Simulation time 353792409 ps
CPU time 3.86 seconds
Started Feb 08 01:08:30 PM PST 24
Finished Feb 08 01:08:35 PM PST 24
Peak memory 209988 kb
Host smart-74662b03-cf9d-40c4-9e35-2ffcd700596c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342944146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3342944146
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3223505745
Short name T873
Test name
Test status
Simulation time 80220604 ps
CPU time 3.52 seconds
Started Feb 08 01:08:34 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 214356 kb
Host smart-753fb487-a0d0-494b-a9b6-74a61a93b542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223505745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3223505745
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2326383834
Short name T968
Test name
Test status
Simulation time 2898957881 ps
CPU time 11.82 seconds
Started Feb 08 01:08:45 PM PST 24
Finished Feb 08 01:08:57 PM PST 24
Peak memory 222508 kb
Host smart-5e93be78-5145-454c-8928-38168fafbb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326383834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2326383834
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2417444316
Short name T52
Test name
Test status
Simulation time 84779335 ps
CPU time 3.73 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:31 PM PST 24
Peak memory 209344 kb
Host smart-5fc580c4-fcf9-4caf-aa10-c4a816adeaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417444316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2417444316
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.521466347
Short name T255
Test name
Test status
Simulation time 114532131 ps
CPU time 4.71 seconds
Started Feb 08 01:08:34 PM PST 24
Finished Feb 08 01:08:39 PM PST 24
Peak memory 214328 kb
Host smart-784b4a83-9ad4-42e5-8e7c-4a699aeb2825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521466347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.521466347
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3578476669
Short name T1007
Test name
Test status
Simulation time 21120365511 ps
CPU time 63.76 seconds
Started Feb 08 01:08:28 PM PST 24
Finished Feb 08 01:09:32 PM PST 24
Peak memory 208828 kb
Host smart-81c27186-a77b-4459-84f7-ab5e67b8479e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578476669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3578476669
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2878241679
Short name T705
Test name
Test status
Simulation time 70053457 ps
CPU time 3.37 seconds
Started Feb 08 01:08:33 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 208076 kb
Host smart-3021e8d2-524d-4cca-97e8-64600775959b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878241679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2878241679
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4154655876
Short name T742
Test name
Test status
Simulation time 976837121 ps
CPU time 8.72 seconds
Started Feb 08 01:08:31 PM PST 24
Finished Feb 08 01:08:41 PM PST 24
Peak memory 208800 kb
Host smart-75a19989-4c4d-43f7-a434-6dfdca7b5d4f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154655876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4154655876
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1514329653
Short name T687
Test name
Test status
Simulation time 412174959 ps
CPU time 6.15 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:34 PM PST 24
Peak memory 208028 kb
Host smart-0a8e6f53-953b-4de9-8238-f611aa0787d5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514329653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1514329653
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.4193020822
Short name T191
Test name
Test status
Simulation time 183746107 ps
CPU time 2.83 seconds
Started Feb 08 01:08:34 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 215476 kb
Host smart-6d525cbe-3515-4860-92da-c99ffa89ab2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193020822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4193020822
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1441914037
Short name T841
Test name
Test status
Simulation time 163585637 ps
CPU time 4.35 seconds
Started Feb 08 01:08:33 PM PST 24
Finished Feb 08 01:08:39 PM PST 24
Peak memory 206668 kb
Host smart-ff662754-3c84-482e-80a9-338dd78241ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441914037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1441914037
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.4038039648
Short name T875
Test name
Test status
Simulation time 350292946 ps
CPU time 4.25 seconds
Started Feb 08 01:08:26 PM PST 24
Finished Feb 08 01:08:31 PM PST 24
Peak memory 222736 kb
Host smart-5f51cd59-592f-46c3-b035-2fef9c19e621
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038039648 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.4038039648
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2111365039
Short name T958
Test name
Test status
Simulation time 970651584 ps
CPU time 5.55 seconds
Started Feb 08 01:08:31 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 218240 kb
Host smart-bfeaaedd-f724-4d07-b383-7c5f03398f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111365039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2111365039
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3736998133
Short name T169
Test name
Test status
Simulation time 67779409 ps
CPU time 2.01 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:30 PM PST 24
Peak memory 209776 kb
Host smart-098a9889-347d-4bf5-93d4-4119d99934f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736998133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3736998133
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3792783765
Short name T907
Test name
Test status
Simulation time 11611977 ps
CPU time 0.9 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:28 PM PST 24
Peak memory 205820 kb
Host smart-ac689601-c323-4479-af5d-b90280f1f4c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792783765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3792783765
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1269305171
Short name T44
Test name
Test status
Simulation time 256703788 ps
CPU time 3.95 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:35 PM PST 24
Peak memory 218308 kb
Host smart-98791c66-ab15-4107-9184-9c15c77eeb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269305171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1269305171
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2979257893
Short name T816
Test name
Test status
Simulation time 3802110825 ps
CPU time 27.71 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:55 PM PST 24
Peak memory 220884 kb
Host smart-abd5bd73-2d6f-4d6d-9c32-9b64660b7948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979257893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2979257893
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.602208053
Short name T301
Test name
Test status
Simulation time 1325132476 ps
CPU time 5.59 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:33 PM PST 24
Peak memory 214204 kb
Host smart-b2f0f295-ed1c-4f03-bde4-efe4462061f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602208053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.602208053
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3429862604
Short name T7
Test name
Test status
Simulation time 462869907 ps
CPU time 2.32 seconds
Started Feb 08 01:08:24 PM PST 24
Finished Feb 08 01:08:27 PM PST 24
Peak memory 209708 kb
Host smart-292e5db2-aca3-45df-a535-12155b0d5ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429862604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3429862604
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3676924766
Short name T700
Test name
Test status
Simulation time 141268612 ps
CPU time 4.39 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:32 PM PST 24
Peak memory 206888 kb
Host smart-2e10bc14-6293-4a95-8269-74f12c63041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676924766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3676924766
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3691152616
Short name T391
Test name
Test status
Simulation time 202615737 ps
CPU time 3.12 seconds
Started Feb 08 01:08:26 PM PST 24
Finished Feb 08 01:08:30 PM PST 24
Peak memory 206928 kb
Host smart-145d93b3-4105-4fff-a21b-c074702b0f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691152616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3691152616
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3227618575
Short name T609
Test name
Test status
Simulation time 2944730479 ps
CPU time 19.65 seconds
Started Feb 08 01:08:28 PM PST 24
Finished Feb 08 01:08:48 PM PST 24
Peak memory 208208 kb
Host smart-9bf794ac-436f-40ce-b4ba-896968f6c51b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227618575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3227618575
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2370410708
Short name T1047
Test name
Test status
Simulation time 127669249 ps
CPU time 4.18 seconds
Started Feb 08 01:08:30 PM PST 24
Finished Feb 08 01:08:35 PM PST 24
Peak memory 208652 kb
Host smart-e9311e80-c29f-4be4-ad14-435dea5ebd58
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370410708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2370410708
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1060242411
Short name T843
Test name
Test status
Simulation time 191835348 ps
CPU time 3.12 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 208484 kb
Host smart-6427a40f-989c-4cf4-a424-16dcf561d64c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060242411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1060242411
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.378321908
Short name T961
Test name
Test status
Simulation time 152552276 ps
CPU time 3.56 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:34 PM PST 24
Peak memory 218476 kb
Host smart-56ad2916-394b-4126-bea2-8f268dd62b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378321908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.378321908
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3146848529
Short name T198
Test name
Test status
Simulation time 77007277 ps
CPU time 3.62 seconds
Started Feb 08 01:08:31 PM PST 24
Finished Feb 08 01:08:35 PM PST 24
Peak memory 206684 kb
Host smart-17bed7da-9293-43ef-b070-1964ae71a2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146848529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3146848529
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2249452204
Short name T116
Test name
Test status
Simulation time 83823692 ps
CPU time 6.18 seconds
Started Feb 08 01:08:24 PM PST 24
Finished Feb 08 01:08:31 PM PST 24
Peak memory 221060 kb
Host smart-164c66a3-73a8-474e-a87b-0ea92a3f486b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249452204 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2249452204
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2776305012
Short name T963
Test name
Test status
Simulation time 203439767 ps
CPU time 4.82 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:33 PM PST 24
Peak memory 214156 kb
Host smart-95270297-ac91-44de-8d46-4e828b56623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776305012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2776305012
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3623326437
Short name T988
Test name
Test status
Simulation time 456364492 ps
CPU time 4.04 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 209972 kb
Host smart-89783a9e-3efb-4bb6-95ef-f0bee36abf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623326437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3623326437
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2011541469
Short name T592
Test name
Test status
Simulation time 18080593 ps
CPU time 0.8 seconds
Started Feb 08 01:04:46 PM PST 24
Finished Feb 08 01:04:47 PM PST 24
Peak memory 205888 kb
Host smart-165769c6-fe36-4eb7-9a0d-e37694f4ac24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011541469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2011541469
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.4222413596
Short name T135
Test name
Test status
Simulation time 262803389 ps
CPU time 8.19 seconds
Started Feb 08 01:04:14 PM PST 24
Finished Feb 08 01:04:23 PM PST 24
Peak memory 214556 kb
Host smart-93d37279-5ca6-4274-85a6-a49cfed9f831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222413596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.4222413596
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.775550747
Short name T910
Test name
Test status
Simulation time 345270792 ps
CPU time 3.64 seconds
Started Feb 08 01:04:47 PM PST 24
Finished Feb 08 01:04:51 PM PST 24
Peak memory 209596 kb
Host smart-5f042026-ca87-4ad8-af16-a4e07a0f50f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775550747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.775550747
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3842259772
Short name T63
Test name
Test status
Simulation time 139701216 ps
CPU time 2.23 seconds
Started Feb 08 01:04:18 PM PST 24
Finished Feb 08 01:04:21 PM PST 24
Peak memory 208068 kb
Host smart-df14e506-d8a4-4de9-87c3-04c43ada20cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842259772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3842259772
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1305246653
Short name T282
Test name
Test status
Simulation time 1198290297 ps
CPU time 5.29 seconds
Started Feb 08 01:04:46 PM PST 24
Finished Feb 08 01:04:52 PM PST 24
Peak memory 210556 kb
Host smart-ced01e3e-d599-4715-b51f-07aa316f861f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305246653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1305246653
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1597064092
Short name T238
Test name
Test status
Simulation time 45797351 ps
CPU time 2.83 seconds
Started Feb 08 01:04:14 PM PST 24
Finished Feb 08 01:04:17 PM PST 24
Peak memory 207908 kb
Host smart-84c8b35a-bde4-4fcb-880b-1ab4851f3b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597064092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1597064092
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1433323088
Short name T892
Test name
Test status
Simulation time 668066767 ps
CPU time 7.18 seconds
Started Feb 08 01:04:13 PM PST 24
Finished Feb 08 01:04:21 PM PST 24
Peak memory 218400 kb
Host smart-85a487c5-31e8-499f-b917-0a745bce52c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433323088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1433323088
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.696522
Short name T104
Test name
Test status
Simulation time 3117545459 ps
CPU time 26.45 seconds
Started Feb 08 01:04:47 PM PST 24
Finished Feb 08 01:05:14 PM PST 24
Peak memory 234140 kb
Host smart-6316140a-59de-4f89-bf2f-86fd7a483128
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.696522
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.4273386001
Short name T863
Test name
Test status
Simulation time 199527498 ps
CPU time 4.32 seconds
Started Feb 08 01:04:17 PM PST 24
Finished Feb 08 01:04:22 PM PST 24
Peak memory 206760 kb
Host smart-b393c2f9-ed5c-45e6-939f-45a30a2e77e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273386001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.4273386001
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2865915316
Short name T354
Test name
Test status
Simulation time 102960502 ps
CPU time 2.78 seconds
Started Feb 08 01:04:28 PM PST 24
Finished Feb 08 01:04:32 PM PST 24
Peak memory 206832 kb
Host smart-ad4ea8e3-1372-4b97-96f8-26f00818497c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865915316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2865915316
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2488453938
Short name T1022
Test name
Test status
Simulation time 88232993 ps
CPU time 3.22 seconds
Started Feb 08 01:04:20 PM PST 24
Finished Feb 08 01:04:23 PM PST 24
Peak memory 208340 kb
Host smart-645bdd64-d1e9-4da5-9af8-672562909b29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488453938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2488453938
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1696015420
Short name T1066
Test name
Test status
Simulation time 289753044 ps
CPU time 6.49 seconds
Started Feb 08 01:04:48 PM PST 24
Finished Feb 08 01:04:55 PM PST 24
Peak memory 209632 kb
Host smart-3d1e677c-cb09-4393-ab29-b6c3274a391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696015420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1696015420
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2354310868
Short name T876
Test name
Test status
Simulation time 226314007 ps
CPU time 6.48 seconds
Started Feb 08 01:04:21 PM PST 24
Finished Feb 08 01:04:28 PM PST 24
Peak memory 207808 kb
Host smart-cf2ee7b6-e05b-43fd-9573-ffd831c1f005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354310868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2354310868
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.808758001
Short name T832
Test name
Test status
Simulation time 989262911 ps
CPU time 7.46 seconds
Started Feb 08 01:04:21 PM PST 24
Finished Feb 08 01:04:29 PM PST 24
Peak memory 208752 kb
Host smart-38965429-ac99-4636-9fa9-54a4a0b36e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808758001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.808758001
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1287862571
Short name T1068
Test name
Test status
Simulation time 235773978 ps
CPU time 2.23 seconds
Started Feb 08 01:04:47 PM PST 24
Finished Feb 08 01:04:50 PM PST 24
Peak memory 210348 kb
Host smart-227aedd5-e37e-49d9-9006-031c0350e371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287862571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1287862571
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3575618123
Short name T842
Test name
Test status
Simulation time 160483953 ps
CPU time 0.75 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:34 PM PST 24
Peak memory 205892 kb
Host smart-f295bb43-8434-40c9-be44-117e72e8a117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575618123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3575618123
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1532968612
Short name T10
Test name
Test status
Simulation time 46665513 ps
CPU time 2.98 seconds
Started Feb 08 01:08:28 PM PST 24
Finished Feb 08 01:08:33 PM PST 24
Peak memory 214728 kb
Host smart-b038d352-6091-48bf-a27c-e44ec7821fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532968612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1532968612
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.689565573
Short name T788
Test name
Test status
Simulation time 60292678 ps
CPU time 3.16 seconds
Started Feb 08 01:08:33 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 218048 kb
Host smart-6a205674-0182-4e9d-b94f-88166ad1e63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689565573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.689565573
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3847188633
Short name T93
Test name
Test status
Simulation time 618849629 ps
CPU time 5.47 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:33 PM PST 24
Peak memory 208276 kb
Host smart-fc0a6378-a83d-44c5-a1e5-9061c11762e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847188633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3847188633
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2358246454
Short name T98
Test name
Test status
Simulation time 1928909987 ps
CPU time 6.53 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 222328 kb
Host smart-b8b593e4-886f-40a9-a465-84980eec5f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358246454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2358246454
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1790822199
Short name T60
Test name
Test status
Simulation time 91093473 ps
CPU time 4.51 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:35 PM PST 24
Peak memory 209132 kb
Host smart-f944b460-553e-40d4-b3c7-d279437e0b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790822199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1790822199
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1448780248
Short name T948
Test name
Test status
Simulation time 786278446 ps
CPU time 8.17 seconds
Started Feb 08 01:08:25 PM PST 24
Finished Feb 08 01:08:34 PM PST 24
Peak memory 218220 kb
Host smart-f3e18a0d-50e4-4636-8fdd-7016ce1909a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448780248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1448780248
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3771155733
Short name T128
Test name
Test status
Simulation time 236328561 ps
CPU time 3.07 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:36 PM PST 24
Peak memory 208572 kb
Host smart-ca161992-dc48-47d9-ae49-2182102bbcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771155733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3771155733
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2354600140
Short name T294
Test name
Test status
Simulation time 740118241 ps
CPU time 20.8 seconds
Started Feb 08 01:08:30 PM PST 24
Finished Feb 08 01:08:52 PM PST 24
Peak memory 208620 kb
Host smart-5e857705-39d6-462e-b594-5781d8043d48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354600140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2354600140
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3845530253
Short name T218
Test name
Test status
Simulation time 122450268 ps
CPU time 3.74 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:31 PM PST 24
Peak memory 206816 kb
Host smart-6ffe30b1-f4f9-42cd-80d1-6a4d0da44022
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845530253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3845530253
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4052959443
Short name T599
Test name
Test status
Simulation time 231492817 ps
CPU time 7.54 seconds
Started Feb 08 01:08:25 PM PST 24
Finished Feb 08 01:08:33 PM PST 24
Peak memory 208028 kb
Host smart-ff6b9e1b-895f-4a4c-8a04-22c891781a63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052959443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4052959443
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.4086189486
Short name T219
Test name
Test status
Simulation time 113766952 ps
CPU time 1.82 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:33 PM PST 24
Peak memory 208124 kb
Host smart-356c0cac-eaff-438b-8e45-5132148a2f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086189486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4086189486
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2516942548
Short name T943
Test name
Test status
Simulation time 60311744 ps
CPU time 2.91 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:30 PM PST 24
Peak memory 206100 kb
Host smart-71bf1920-bec6-4387-b42f-308bf6706916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516942548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2516942548
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.880687205
Short name T746
Test name
Test status
Simulation time 99324074691 ps
CPU time 230.26 seconds
Started Feb 08 01:08:33 PM PST 24
Finished Feb 08 01:12:24 PM PST 24
Peak memory 222504 kb
Host smart-48029861-19a8-4863-9f57-633733a2f323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880687205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.880687205
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2547259832
Short name T1042
Test name
Test status
Simulation time 71178408 ps
CPU time 3.55 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 219996 kb
Host smart-b6e5d65f-440f-470c-998a-f68ff9f7ca03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547259832 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2547259832
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.614970491
Short name T276
Test name
Test status
Simulation time 621684509 ps
CPU time 13.85 seconds
Started Feb 08 01:08:25 PM PST 24
Finished Feb 08 01:08:39 PM PST 24
Peak memory 218268 kb
Host smart-606b5ad7-dcf7-460a-b009-90e78aa57d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614970491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.614970491
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3717198750
Short name T31
Test name
Test status
Simulation time 178086061 ps
CPU time 2.47 seconds
Started Feb 08 01:08:33 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 210152 kb
Host smart-86776967-04db-4ef6-8275-d5fa1129c43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717198750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3717198750
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.525283312
Short name T723
Test name
Test status
Simulation time 17188048 ps
CPU time 0.75 seconds
Started Feb 08 01:08:43 PM PST 24
Finished Feb 08 01:08:44 PM PST 24
Peak memory 206004 kb
Host smart-1383bc63-2e1d-4f8a-ba77-ade1bc3212aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525283312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.525283312
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1160451702
Short name T134
Test name
Test status
Simulation time 230878789 ps
CPU time 12.13 seconds
Started Feb 08 01:08:33 PM PST 24
Finished Feb 08 01:08:46 PM PST 24
Peak memory 214356 kb
Host smart-18148c8f-fff5-4904-9998-73016955e355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1160451702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1160451702
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1533306230
Short name T775
Test name
Test status
Simulation time 155137853 ps
CPU time 2.21 seconds
Started Feb 08 01:08:31 PM PST 24
Finished Feb 08 01:08:34 PM PST 24
Peak memory 207736 kb
Host smart-0d58360c-147d-4534-8e61-5242b460033c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533306230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1533306230
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.451166368
Short name T406
Test name
Test status
Simulation time 2101512912 ps
CPU time 13.13 seconds
Started Feb 08 01:08:30 PM PST 24
Finished Feb 08 01:08:44 PM PST 24
Peak memory 214324 kb
Host smart-df0a3edf-bb56-438b-92f3-034a084e165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451166368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.451166368
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1772479477
Short name T95
Test name
Test status
Simulation time 6044266472 ps
CPU time 56.77 seconds
Started Feb 08 01:08:28 PM PST 24
Finished Feb 08 01:09:26 PM PST 24
Peak memory 220632 kb
Host smart-15f51cb8-ff3a-431f-93d2-9bbc95cdd04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772479477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1772479477
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.947427146
Short name T681
Test name
Test status
Simulation time 351352424 ps
CPU time 3.29 seconds
Started Feb 08 01:08:37 PM PST 24
Finished Feb 08 01:08:41 PM PST 24
Peak memory 214264 kb
Host smart-f12d219d-475c-4550-91dd-77eb46320fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947427146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.947427146
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3255047253
Short name T736
Test name
Test status
Simulation time 373613281 ps
CPU time 4.03 seconds
Started Feb 08 01:08:43 PM PST 24
Finished Feb 08 01:08:47 PM PST 24
Peak memory 207372 kb
Host smart-95ab6a6d-44f1-4a10-ae49-ef41ca4513c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255047253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3255047253
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3556385689
Short name T644
Test name
Test status
Simulation time 399201518 ps
CPU time 13.75 seconds
Started Feb 08 01:08:31 PM PST 24
Finished Feb 08 01:08:46 PM PST 24
Peak memory 208436 kb
Host smart-05837990-dd3c-4ebd-98c2-18ba4e1b60b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556385689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3556385689
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3403304880
Short name T860
Test name
Test status
Simulation time 2697299789 ps
CPU time 21.98 seconds
Started Feb 08 01:08:31 PM PST 24
Finished Feb 08 01:08:54 PM PST 24
Peak memory 209016 kb
Host smart-4fe8829e-6aeb-4808-8e97-dbd7c8abc3e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403304880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3403304880
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.442354371
Short name T361
Test name
Test status
Simulation time 275844484 ps
CPU time 4.24 seconds
Started Feb 08 01:08:35 PM PST 24
Finished Feb 08 01:08:40 PM PST 24
Peak memory 208660 kb
Host smart-62ef1260-3475-4e51-8d8d-413af3f8692e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442354371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.442354371
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1351394195
Short name T15
Test name
Test status
Simulation time 75846469 ps
CPU time 2.65 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:35 PM PST 24
Peak memory 208736 kb
Host smart-7f73fa4c-0b95-44ce-b424-c8bffaad805f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351394195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1351394195
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1879709719
Short name T80
Test name
Test status
Simulation time 299923732 ps
CPU time 6.17 seconds
Started Feb 08 01:08:34 PM PST 24
Finished Feb 08 01:08:41 PM PST 24
Peak memory 218008 kb
Host smart-9e691042-4b00-4b75-bfbe-aa12e9bd023d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879709719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1879709719
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3640198940
Short name T614
Test name
Test status
Simulation time 82331074 ps
CPU time 3.31 seconds
Started Feb 08 01:08:27 PM PST 24
Finished Feb 08 01:08:31 PM PST 24
Peak memory 208572 kb
Host smart-a70190e9-45db-4f00-a3c1-d4c09a37bbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640198940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3640198940
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1484287440
Short name T356
Test name
Test status
Simulation time 238456563 ps
CPU time 9.97 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:40 PM PST 24
Peak memory 220780 kb
Host smart-02ec3758-ff1a-4728-a0a2-fa5c9246e1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484287440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1484287440
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.609115976
Short name T745
Test name
Test status
Simulation time 509349255 ps
CPU time 7.29 seconds
Started Feb 08 01:08:35 PM PST 24
Finished Feb 08 01:08:43 PM PST 24
Peak memory 222528 kb
Host smart-a5b90245-2742-4314-8923-643280fd671e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609115976 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.609115976
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3660440393
Short name T347
Test name
Test status
Simulation time 32891040099 ps
CPU time 87.37 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:10:01 PM PST 24
Peak memory 214448 kb
Host smart-c545e87a-8845-4621-888b-3eccbeae31a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660440393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3660440393
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3002728942
Short name T846
Test name
Test status
Simulation time 25584179 ps
CPU time 0.77 seconds
Started Feb 08 01:08:35 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 205880 kb
Host smart-ab8c4c84-e0a0-423a-aad0-8574a1705a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002728942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3002728942
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3050650284
Short name T438
Test name
Test status
Simulation time 43324550 ps
CPU time 3.25 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 215344 kb
Host smart-75a3e19e-b84f-425d-91ba-f9acbd5bfb10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3050650284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3050650284
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2126717427
Short name T817
Test name
Test status
Simulation time 50620448 ps
CPU time 1.93 seconds
Started Feb 08 01:08:36 PM PST 24
Finished Feb 08 01:08:40 PM PST 24
Peak memory 214484 kb
Host smart-2d2091cf-a854-4745-9d81-482d626d7f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126717427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2126717427
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1247703166
Short name T416
Test name
Test status
Simulation time 66234599 ps
CPU time 2.45 seconds
Started Feb 08 01:08:36 PM PST 24
Finished Feb 08 01:08:40 PM PST 24
Peak memory 207188 kb
Host smart-0c99fdc9-6e1f-4a5a-9df1-e93a635a4162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247703166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1247703166
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1269040330
Short name T375
Test name
Test status
Simulation time 106849899 ps
CPU time 4.58 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 209864 kb
Host smart-5e8a40b3-9e4c-41df-96ba-4ebd9d3e52dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269040330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1269040330
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2126988617
Short name T194
Test name
Test status
Simulation time 1616129251 ps
CPU time 10.96 seconds
Started Feb 08 01:08:37 PM PST 24
Finished Feb 08 01:08:50 PM PST 24
Peak memory 222204 kb
Host smart-19344170-99da-4c35-bdbd-2b7d48ba952d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126988617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2126988617
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3975915881
Short name T365
Test name
Test status
Simulation time 788178385 ps
CPU time 5.51 seconds
Started Feb 08 01:08:37 PM PST 24
Finished Feb 08 01:08:44 PM PST 24
Peak memory 220124 kb
Host smart-77a68d67-d236-42b2-9db1-cf1340361286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975915881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3975915881
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3638864773
Short name T275
Test name
Test status
Simulation time 54712778 ps
CPU time 3.55 seconds
Started Feb 08 01:08:37 PM PST 24
Finished Feb 08 01:08:42 PM PST 24
Peak memory 207772 kb
Host smart-c5599255-93b2-4f13-8fce-f614f85adfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638864773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3638864773
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.521272089
Short name T935
Test name
Test status
Simulation time 253792931 ps
CPU time 7.56 seconds
Started Feb 08 01:08:43 PM PST 24
Finished Feb 08 01:08:51 PM PST 24
Peak memory 206996 kb
Host smart-a530adb7-6d25-4f4d-a7b5-c4fe8c81bce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521272089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.521272089
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4194230000
Short name T874
Test name
Test status
Simulation time 83592913 ps
CPU time 2.8 seconds
Started Feb 08 01:08:35 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 208696 kb
Host smart-f80862b2-9ab8-4529-9a82-3ea563a2cccb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194230000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4194230000
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3563368552
Short name T939
Test name
Test status
Simulation time 1130350788 ps
CPU time 30.76 seconds
Started Feb 08 01:08:35 PM PST 24
Finished Feb 08 01:09:07 PM PST 24
Peak memory 208968 kb
Host smart-a69ef0d6-773e-4bf7-9c8b-dc492807b677
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563368552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3563368552
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2230961349
Short name T973
Test name
Test status
Simulation time 970645187 ps
CPU time 5.61 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:36 PM PST 24
Peak memory 208760 kb
Host smart-53cfc133-6977-4a61-9339-7236ab7acbbb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230961349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2230961349
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2233559495
Short name T938
Test name
Test status
Simulation time 123861095 ps
CPU time 1.69 seconds
Started Feb 08 01:08:36 PM PST 24
Finished Feb 08 01:08:39 PM PST 24
Peak memory 207796 kb
Host smart-f172b100-72bf-41f1-8051-c3a124e8990f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233559495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2233559495
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3391330402
Short name T808
Test name
Test status
Simulation time 33844015 ps
CPU time 2.34 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:33 PM PST 24
Peak memory 208220 kb
Host smart-830ccad6-bf4c-4a5c-a8b5-bc33b30109ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391330402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3391330402
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3541032752
Short name T42
Test name
Test status
Simulation time 199805419 ps
CPU time 11.15 seconds
Started Feb 08 01:08:28 PM PST 24
Finished Feb 08 01:08:41 PM PST 24
Peak memory 216084 kb
Host smart-3d055714-0076-4eb4-b148-a1ddf66a846c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541032752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3541032752
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.826481360
Short name T669
Test name
Test status
Simulation time 706147633 ps
CPU time 6.34 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:08:37 PM PST 24
Peak memory 222632 kb
Host smart-a1383ba4-408a-42dc-8a7d-8db2f7d9dda0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826481360 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.826481360
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.996827439
Short name T379
Test name
Test status
Simulation time 985020866 ps
CPU time 13.54 seconds
Started Feb 08 01:08:35 PM PST 24
Finished Feb 08 01:08:50 PM PST 24
Peak memory 209304 kb
Host smart-1b9d6f48-9095-4b34-86c6-cbca13e0beaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996827439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.996827439
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2907619123
Short name T170
Test name
Test status
Simulation time 11645660600 ps
CPU time 23.89 seconds
Started Feb 08 01:08:37 PM PST 24
Finished Feb 08 01:09:02 PM PST 24
Peak memory 211356 kb
Host smart-18553241-32ad-47db-9801-3e3a91ad4156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907619123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2907619123
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1319968465
Short name T716
Test name
Test status
Simulation time 26824413 ps
CPU time 0.87 seconds
Started Feb 08 01:08:38 PM PST 24
Finished Feb 08 01:08:40 PM PST 24
Peak memory 205880 kb
Host smart-6d27840f-c926-47db-bc66-f58d07c61505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319968465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1319968465
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1635127189
Short name T28
Test name
Test status
Simulation time 316622547 ps
CPU time 2.41 seconds
Started Feb 08 01:08:34 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 222812 kb
Host smart-5b2a8b07-cb94-4f73-bfd2-e05c333d3433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635127189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1635127189
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.4124990171
Short name T75
Test name
Test status
Simulation time 173293947 ps
CPU time 5.14 seconds
Started Feb 08 01:08:33 PM PST 24
Finished Feb 08 01:08:40 PM PST 24
Peak memory 207904 kb
Host smart-f56f3fcc-d863-451b-ab72-54e916ed3f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124990171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.4124990171
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.213256955
Short name T960
Test name
Test status
Simulation time 112775288 ps
CPU time 4.86 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 214224 kb
Host smart-f58731f9-9f7f-4fa9-aa0f-6415696ac249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213256955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.213256955
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2309070153
Short name T290
Test name
Test status
Simulation time 96960106 ps
CPU time 3.69 seconds
Started Feb 08 01:08:33 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 222492 kb
Host smart-f19f1f81-484b-4f99-864a-d28c0502802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309070153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2309070153
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3799286197
Short name T404
Test name
Test status
Simulation time 939609949 ps
CPU time 4.07 seconds
Started Feb 08 01:08:34 PM PST 24
Finished Feb 08 01:08:39 PM PST 24
Peak memory 222468 kb
Host smart-940c405a-9fd8-4d5d-b425-e8e38934f227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799286197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3799286197
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1268115252
Short name T799
Test name
Test status
Simulation time 1899854030 ps
CPU time 25.97 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:59 PM PST 24
Peak memory 207996 kb
Host smart-5feb769f-8a7f-42dc-8dd4-8b0c32b8d8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268115252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1268115252
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3507489354
Short name T942
Test name
Test status
Simulation time 83240489 ps
CPU time 3.95 seconds
Started Feb 08 01:08:36 PM PST 24
Finished Feb 08 01:08:42 PM PST 24
Peak memory 208824 kb
Host smart-54ce96bb-3886-4141-ae0a-3f716aeee636
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507489354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3507489354
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.722407744
Short name T983
Test name
Test status
Simulation time 417265247 ps
CPU time 6.67 seconds
Started Feb 08 01:08:37 PM PST 24
Finished Feb 08 01:08:45 PM PST 24
Peak memory 208688 kb
Host smart-0403d619-27b7-4100-b3e9-6aa868c1f615
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722407744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.722407744
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1790882369
Short name T588
Test name
Test status
Simulation time 434067987 ps
CPU time 2.53 seconds
Started Feb 08 01:08:35 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 206772 kb
Host smart-9feb86e4-9207-4f53-ab35-bacf76010bae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790882369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1790882369
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2377835095
Short name T608
Test name
Test status
Simulation time 352497585 ps
CPU time 7.86 seconds
Started Feb 08 01:08:31 PM PST 24
Finished Feb 08 01:08:40 PM PST 24
Peak memory 210040 kb
Host smart-1f4fb4f4-1a0e-4722-944a-f521f52c1ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377835095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2377835095
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1231632357
Short name T993
Test name
Test status
Simulation time 297716255 ps
CPU time 6.72 seconds
Started Feb 08 01:08:30 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 207900 kb
Host smart-ff68504c-9a10-41b9-bfee-4f604610ebca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231632357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1231632357
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.4190199978
Short name T73
Test name
Test status
Simulation time 4410719287 ps
CPU time 45.12 seconds
Started Feb 08 01:08:38 PM PST 24
Finished Feb 08 01:09:25 PM PST 24
Peak memory 216204 kb
Host smart-ae50e9b9-1fd3-4e30-8c23-1aea5f270d12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190199978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4190199978
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1921745552
Short name T209
Test name
Test status
Simulation time 350156447 ps
CPU time 10.82 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:44 PM PST 24
Peak memory 220532 kb
Host smart-d28bd96c-34a6-425b-9a7a-29b4363d5541
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921745552 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1921745552
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3064524523
Short name T260
Test name
Test status
Simulation time 443061416 ps
CPU time 5.85 seconds
Started Feb 08 01:08:25 PM PST 24
Finished Feb 08 01:08:32 PM PST 24
Peak memory 209052 kb
Host smart-f697de8b-43d3-4ae7-b1fc-7bfed32f41f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064524523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3064524523
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1255103481
Short name T890
Test name
Test status
Simulation time 1189773014 ps
CPU time 3.07 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:08:36 PM PST 24
Peak memory 210280 kb
Host smart-161624d0-f7e3-4030-9401-0355af91d48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255103481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1255103481
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2539472224
Short name T1025
Test name
Test status
Simulation time 21223272 ps
CPU time 0.69 seconds
Started Feb 08 01:09:02 PM PST 24
Finished Feb 08 01:09:08 PM PST 24
Peak memory 205828 kb
Host smart-2a3eb402-3cae-452f-9703-8fe067b7a199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539472224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2539472224
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3905629445
Short name T429
Test name
Test status
Simulation time 3064643570 ps
CPU time 76.71 seconds
Started Feb 08 01:08:29 PM PST 24
Finished Feb 08 01:09:48 PM PST 24
Peak memory 217516 kb
Host smart-2287d2aa-a32f-4e1f-9aff-697650a50e1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905629445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3905629445
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3159790987
Short name T24
Test name
Test status
Simulation time 102858469 ps
CPU time 3.24 seconds
Started Feb 08 01:08:54 PM PST 24
Finished Feb 08 01:08:59 PM PST 24
Peak memory 210076 kb
Host smart-f48d8f81-2856-41e9-937f-84d73370c411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159790987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3159790987
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2014508064
Short name T398
Test name
Test status
Simulation time 210535363 ps
CPU time 2.46 seconds
Started Feb 08 01:08:35 PM PST 24
Finished Feb 08 01:08:38 PM PST 24
Peak memory 214212 kb
Host smart-d278378c-9681-4f06-80c8-f0e43d051d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014508064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2014508064
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3063300985
Short name T886
Test name
Test status
Simulation time 115470881 ps
CPU time 4.97 seconds
Started Feb 08 01:08:34 PM PST 24
Finished Feb 08 01:08:40 PM PST 24
Peak memory 219932 kb
Host smart-7efa3864-6a2e-4591-aaef-439dc6b113ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063300985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3063300985
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1048272340
Short name T205
Test name
Test status
Simulation time 64210462 ps
CPU time 3.92 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:09:02 PM PST 24
Peak memory 222428 kb
Host smart-306a8009-b1c2-4b3b-a775-67be2b132b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048272340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1048272340
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3487109014
Short name T224
Test name
Test status
Simulation time 500261657 ps
CPU time 11.56 seconds
Started Feb 08 01:08:42 PM PST 24
Finished Feb 08 01:08:55 PM PST 24
Peak memory 208836 kb
Host smart-55ad9a85-7a5f-4061-804f-b2b6bd42ca49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487109014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3487109014
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2273845704
Short name T658
Test name
Test status
Simulation time 417545291 ps
CPU time 3.94 seconds
Started Feb 08 01:08:40 PM PST 24
Finished Feb 08 01:08:45 PM PST 24
Peak memory 206832 kb
Host smart-f22a1013-6a06-4612-ab92-a95601eb145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273845704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2273845704
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.500421376
Short name T1079
Test name
Test status
Simulation time 228846179 ps
CPU time 6.3 seconds
Started Feb 08 01:08:36 PM PST 24
Finished Feb 08 01:08:44 PM PST 24
Peak memory 207916 kb
Host smart-0d2989ec-dec8-4e2f-9eb3-7038e3b9c0fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500421376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.500421376
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.81469546
Short name T676
Test name
Test status
Simulation time 766311339 ps
CPU time 3.77 seconds
Started Feb 08 01:08:43 PM PST 24
Finished Feb 08 01:08:47 PM PST 24
Peak memory 208472 kb
Host smart-9ece5cd0-4cf9-4371-b086-ab491f6033d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81469546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.81469546
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2996946798
Short name T338
Test name
Test status
Simulation time 7017307302 ps
CPU time 45.33 seconds
Started Feb 08 01:08:32 PM PST 24
Finished Feb 08 01:09:18 PM PST 24
Peak memory 208988 kb
Host smart-93566551-de2f-4fe2-b209-d19e98b2c30b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996946798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2996946798
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.492784350
Short name T880
Test name
Test status
Simulation time 127619091 ps
CPU time 2.1 seconds
Started Feb 08 01:08:53 PM PST 24
Finished Feb 08 01:08:57 PM PST 24
Peak memory 218196 kb
Host smart-131b7ba4-66ac-48a9-9b5b-e6e14b2e042e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492784350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.492784350
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1476191694
Short name T668
Test name
Test status
Simulation time 184886843 ps
CPU time 3.34 seconds
Started Feb 08 01:08:36 PM PST 24
Finished Feb 08 01:08:41 PM PST 24
Peak memory 206752 kb
Host smart-744ec2c2-e53f-4da8-8e6c-c56395fa2249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476191694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1476191694
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3210210736
Short name T291
Test name
Test status
Simulation time 26731759783 ps
CPU time 157.28 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:11:35 PM PST 24
Peak memory 216188 kb
Host smart-9050f0a9-b377-48a0-b1d4-4a656758eba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210210736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3210210736
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.565844366
Short name T729
Test name
Test status
Simulation time 339888157 ps
CPU time 7.14 seconds
Started Feb 08 01:08:58 PM PST 24
Finished Feb 08 01:09:15 PM PST 24
Peak memory 220520 kb
Host smart-dfa3a4b6-e35d-4580-b1ab-08075f8dd2ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565844366 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.565844366
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1669568044
Short name T646
Test name
Test status
Simulation time 1150649005 ps
CPU time 11.78 seconds
Started Feb 08 01:08:34 PM PST 24
Finished Feb 08 01:08:47 PM PST 24
Peak memory 208848 kb
Host smart-1f731cf6-b21f-47b6-a8f1-84d8754be7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669568044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1669568044
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2393504633
Short name T780
Test name
Test status
Simulation time 238048271 ps
CPU time 3.3 seconds
Started Feb 08 01:08:54 PM PST 24
Finished Feb 08 01:08:59 PM PST 24
Peak memory 210460 kb
Host smart-9d80879c-f367-462e-86d0-65548b68654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393504633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2393504633
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3438921350
Short name T753
Test name
Test status
Simulation time 15076203 ps
CPU time 0.75 seconds
Started Feb 08 01:08:57 PM PST 24
Finished Feb 08 01:09:06 PM PST 24
Peak memory 205880 kb
Host smart-65c51096-528b-43d2-a90c-1daf8dccb37c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438921350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3438921350
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.955890964
Short name T390
Test name
Test status
Simulation time 238286931 ps
CPU time 13.24 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:21 PM PST 24
Peak memory 215188 kb
Host smart-dd4d1dff-313e-4363-ae44-95cdee6282f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955890964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.955890964
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3062022202
Short name T771
Test name
Test status
Simulation time 383596669 ps
CPU time 8.28 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:09:06 PM PST 24
Peak memory 220500 kb
Host smart-716babfe-6884-47f6-a938-e854564b8971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062022202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3062022202
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2769720368
Short name T358
Test name
Test status
Simulation time 6599697941 ps
CPU time 27.57 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:09:25 PM PST 24
Peak memory 217656 kb
Host smart-02b8d2b7-ca61-4565-b3ae-ad18a839f11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769720368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2769720368
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3040752877
Short name T966
Test name
Test status
Simulation time 56988848 ps
CPU time 2.33 seconds
Started Feb 08 01:08:56 PM PST 24
Finished Feb 08 01:09:00 PM PST 24
Peak memory 209112 kb
Host smart-9000e411-0406-4031-95d7-496e91bec1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040752877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3040752877
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1705418718
Short name T824
Test name
Test status
Simulation time 2238994463 ps
CPU time 16.99 seconds
Started Feb 08 01:08:53 PM PST 24
Finished Feb 08 01:09:12 PM PST 24
Peak memory 222492 kb
Host smart-6f29df41-ea1c-45af-8429-8fc6ead87e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705418718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1705418718
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2479091432
Short name T912
Test name
Test status
Simulation time 88527143 ps
CPU time 4.04 seconds
Started Feb 08 01:08:54 PM PST 24
Finished Feb 08 01:08:59 PM PST 24
Peak memory 214224 kb
Host smart-682cdd88-afe2-4b03-914c-7ef90f29d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479091432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2479091432
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.4293180744
Short name T720
Test name
Test status
Simulation time 151577822 ps
CPU time 5.43 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:09:02 PM PST 24
Peak memory 207044 kb
Host smart-854f9d9e-891f-49c4-a019-8d3356eff5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293180744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.4293180744
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2897761179
Short name T653
Test name
Test status
Simulation time 346148376 ps
CPU time 6.83 seconds
Started Feb 08 01:09:01 PM PST 24
Finished Feb 08 01:09:14 PM PST 24
Peak memory 207224 kb
Host smart-c99daaa1-1adc-4172-8282-a0ce3a46282f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897761179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2897761179
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.560650226
Short name T927
Test name
Test status
Simulation time 211482955 ps
CPU time 3.2 seconds
Started Feb 08 01:08:54 PM PST 24
Finished Feb 08 01:09:00 PM PST 24
Peak memory 208436 kb
Host smart-3450c782-2f7a-441c-b210-2cee08a43c74
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560650226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.560650226
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.725158925
Short name T858
Test name
Test status
Simulation time 71192096 ps
CPU time 2.84 seconds
Started Feb 08 01:08:56 PM PST 24
Finished Feb 08 01:09:07 PM PST 24
Peak memory 208128 kb
Host smart-e76e046c-9bd2-4808-b648-6eafa8ad32a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725158925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.725158925
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3542418669
Short name T215
Test name
Test status
Simulation time 475513129 ps
CPU time 7.02 seconds
Started Feb 08 01:08:54 PM PST 24
Finished Feb 08 01:09:04 PM PST 24
Peak memory 208100 kb
Host smart-7f1b9eee-b76d-4645-be43-53152168d782
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542418669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3542418669
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.4038454069
Short name T418
Test name
Test status
Simulation time 3397870155 ps
CPU time 29.77 seconds
Started Feb 08 01:09:05 PM PST 24
Finished Feb 08 01:09:41 PM PST 24
Peak memory 208272 kb
Host smart-16a126c0-ce5c-4e1c-a04c-009eaae5ba5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038454069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.4038454069
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.855155995
Short name T650
Test name
Test status
Simulation time 125202932 ps
CPU time 3.79 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:09:01 PM PST 24
Peak memory 206644 kb
Host smart-4ababa9b-c350-4c47-b2c7-42543ce3f39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855155995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.855155995
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3704029195
Short name T41
Test name
Test status
Simulation time 1690063709 ps
CPU time 11.43 seconds
Started Feb 08 01:08:53 PM PST 24
Finished Feb 08 01:09:05 PM PST 24
Peak memory 219172 kb
Host smart-946b2def-0e25-40b9-a3c8-84c4a7bcecc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704029195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3704029195
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3545248578
Short name T226
Test name
Test status
Simulation time 444877154 ps
CPU time 7.31 seconds
Started Feb 08 01:08:57 PM PST 24
Finished Feb 08 01:09:13 PM PST 24
Peak memory 222568 kb
Host smart-cb9ba849-0cb5-4be7-9828-9e038ef20337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545248578 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3545248578
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1959668335
Short name T372
Test name
Test status
Simulation time 1216699407 ps
CPU time 5.25 seconds
Started Feb 08 01:09:02 PM PST 24
Finished Feb 08 01:09:13 PM PST 24
Peak memory 208640 kb
Host smart-f08be8f3-e436-4453-b5cd-c419277e8912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959668335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1959668335
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2126046963
Short name T1027
Test name
Test status
Simulation time 452463881 ps
CPU time 2.69 seconds
Started Feb 08 01:08:58 PM PST 24
Finished Feb 08 01:09:09 PM PST 24
Peak memory 209960 kb
Host smart-82b19b8b-197f-44af-8e07-4e7e6d9274d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126046963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2126046963
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4256362874
Short name T750
Test name
Test status
Simulation time 62110864 ps
CPU time 0.86 seconds
Started Feb 08 01:08:56 PM PST 24
Finished Feb 08 01:09:05 PM PST 24
Peak memory 205868 kb
Host smart-7fa42ab2-9067-44b9-9bec-a458a8a03de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256362874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4256362874
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1129180741
Short name T433
Test name
Test status
Simulation time 1370764718 ps
CPU time 31.07 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:39 PM PST 24
Peak memory 215244 kb
Host smart-6a0c7a61-3496-4653-b2f1-7d67cef1c9aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129180741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1129180741
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1399545615
Short name T871
Test name
Test status
Simulation time 214454280 ps
CPU time 2.75 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:10 PM PST 24
Peak memory 214564 kb
Host smart-8d0090ad-6763-47c6-aa81-d3009be40abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399545615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1399545615
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.713046442
Short name T70
Test name
Test status
Simulation time 141345932 ps
CPU time 1.98 seconds
Started Feb 08 01:08:56 PM PST 24
Finished Feb 08 01:09:00 PM PST 24
Peak memory 208076 kb
Host smart-75f3c7f5-95e7-4de4-9206-99ef41f2a2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713046442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.713046442
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1190086708
Short name T728
Test name
Test status
Simulation time 115432137 ps
CPU time 4.98 seconds
Started Feb 08 01:08:57 PM PST 24
Finished Feb 08 01:09:09 PM PST 24
Peak memory 222464 kb
Host smart-c3bd0675-084b-43f5-83bf-9baf87aa78ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190086708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1190086708
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.309619051
Short name T401
Test name
Test status
Simulation time 84070329 ps
CPU time 3.3 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:09:01 PM PST 24
Peak memory 222416 kb
Host smart-fcbf13b5-d103-4f99-a00c-4a3172ac947a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309619051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.309619051
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1242405519
Short name T597
Test name
Test status
Simulation time 134729114 ps
CPU time 4.07 seconds
Started Feb 08 01:08:56 PM PST 24
Finished Feb 08 01:09:08 PM PST 24
Peak memory 222564 kb
Host smart-4da890e6-7622-456d-8c89-e9f8358cb2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242405519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1242405519
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2906215985
Short name T778
Test name
Test status
Simulation time 265186758 ps
CPU time 6.42 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:09:04 PM PST 24
Peak memory 207716 kb
Host smart-0d0cbfe5-54ae-40e4-85ca-fb1e2d08d279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906215985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2906215985
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1538861984
Short name T587
Test name
Test status
Simulation time 64661002 ps
CPU time 3.06 seconds
Started Feb 08 01:08:54 PM PST 24
Finished Feb 08 01:09:00 PM PST 24
Peak memory 208236 kb
Host smart-8eb134fc-5700-47b3-b323-2872ad2d861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538861984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1538861984
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.835435260
Short name T594
Test name
Test status
Simulation time 281360699 ps
CPU time 3.04 seconds
Started Feb 08 01:08:54 PM PST 24
Finished Feb 08 01:09:00 PM PST 24
Peak memory 206916 kb
Host smart-565b9209-7941-4585-9487-8f302081588e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835435260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.835435260
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1545207821
Short name T1004
Test name
Test status
Simulation time 36326123 ps
CPU time 2.33 seconds
Started Feb 08 01:08:57 PM PST 24
Finished Feb 08 01:09:07 PM PST 24
Peak memory 206844 kb
Host smart-1ac5e975-8c58-431c-a2fa-55fdae1cb61d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545207821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1545207821
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.806360669
Short name T982
Test name
Test status
Simulation time 143780139 ps
CPU time 2.58 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:09:00 PM PST 24
Peak memory 207532 kb
Host smart-359760bf-6f6d-4ce9-87d7-67a7ee76175f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806360669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.806360669
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3872105492
Short name T309
Test name
Test status
Simulation time 237023565 ps
CPU time 2.11 seconds
Started Feb 08 01:08:59 PM PST 24
Finished Feb 08 01:09:10 PM PST 24
Peak memory 218332 kb
Host smart-50667fe4-b322-4126-af9e-b1d03485f2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872105492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3872105492
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.374023468
Short name T1032
Test name
Test status
Simulation time 537234268 ps
CPU time 2.61 seconds
Started Feb 08 01:08:51 PM PST 24
Finished Feb 08 01:08:54 PM PST 24
Peak memory 206736 kb
Host smart-da0748fd-4827-4d6c-b7d8-9881b0136c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374023468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.374023468
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1808969791
Short name T223
Test name
Test status
Simulation time 196316344 ps
CPU time 5.29 seconds
Started Feb 08 01:08:54 PM PST 24
Finished Feb 08 01:09:01 PM PST 24
Peak memory 222620 kb
Host smart-47533d56-bbeb-4a9d-8a6a-dbd4e45ef2e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808969791 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1808969791
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4262506418
Short name T345
Test name
Test status
Simulation time 153699019 ps
CPU time 6 seconds
Started Feb 08 01:08:56 PM PST 24
Finished Feb 08 01:09:10 PM PST 24
Peak memory 218072 kb
Host smart-d057c9c4-9031-42db-8c89-24831bf6a571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262506418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4262506418
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3422899261
Short name T1077
Test name
Test status
Simulation time 96328536 ps
CPU time 2.43 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:08:59 PM PST 24
Peak memory 210128 kb
Host smart-08812eee-c653-4193-87ea-584035a04467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422899261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3422899261
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.4098016440
Short name T579
Test name
Test status
Simulation time 37880839 ps
CPU time 0.71 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:08:58 PM PST 24
Peak memory 205844 kb
Host smart-1db6d7d1-fc93-4131-a986-02ef5058396b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098016440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4098016440
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3872894320
Short name T175
Test name
Test status
Simulation time 56281365 ps
CPU time 2.77 seconds
Started Feb 08 01:08:58 PM PST 24
Finished Feb 08 01:09:09 PM PST 24
Peak memory 214320 kb
Host smart-c95467dc-c3ff-4b99-80b8-00d1315b85d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872894320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3872894320
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1576248425
Short name T1074
Test name
Test status
Simulation time 148293709 ps
CPU time 3.57 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:11 PM PST 24
Peak memory 209708 kb
Host smart-72d8fa40-43f8-4a2d-9330-94707be8b48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576248425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1576248425
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1203243046
Short name T322
Test name
Test status
Simulation time 119003444 ps
CPU time 4.94 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:12 PM PST 24
Peak memory 220652 kb
Host smart-de367d75-2d36-4756-8fd7-f89502f19469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203243046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1203243046
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1857901117
Short name T208
Test name
Test status
Simulation time 359151800 ps
CPU time 4.57 seconds
Started Feb 08 01:08:56 PM PST 24
Finished Feb 08 01:09:07 PM PST 24
Peak memory 222408 kb
Host smart-a3e950e9-bc14-4eee-9b09-b819b0f215ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857901117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1857901117
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3474165291
Short name T661
Test name
Test status
Simulation time 185923489 ps
CPU time 4.36 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:12 PM PST 24
Peak memory 220608 kb
Host smart-c6235b03-fc8a-47fc-bef7-b280ebca2b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474165291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3474165291
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1785734680
Short name T84
Test name
Test status
Simulation time 106233239 ps
CPU time 2.08 seconds
Started Feb 08 01:08:58 PM PST 24
Finished Feb 08 01:09:10 PM PST 24
Peak memory 208004 kb
Host smart-e7942f87-c8d4-4440-99c5-823cfbe3e17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785734680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1785734680
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.501525799
Short name T764
Test name
Test status
Simulation time 195091452 ps
CPU time 2.7 seconds
Started Feb 08 01:08:54 PM PST 24
Finished Feb 08 01:08:59 PM PST 24
Peak memory 206904 kb
Host smart-9e82ebc0-a027-4642-8e0c-d0064538aef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501525799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.501525799
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.71474274
Short name T183
Test name
Test status
Simulation time 53177145 ps
CPU time 2.02 seconds
Started Feb 08 01:08:54 PM PST 24
Finished Feb 08 01:08:58 PM PST 24
Peak memory 208304 kb
Host smart-606707dc-ea19-4558-99b9-3a357f3acfa4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71474274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.71474274
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.160741938
Short name T1016
Test name
Test status
Simulation time 238007407 ps
CPU time 6.4 seconds
Started Feb 08 01:08:57 PM PST 24
Finished Feb 08 01:09:12 PM PST 24
Peak memory 208144 kb
Host smart-ec12d78c-b71e-45ad-9f6b-7ba50321fae2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160741938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.160741938
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2172573544
Short name T337
Test name
Test status
Simulation time 264305667 ps
CPU time 3.18 seconds
Started Feb 08 01:08:57 PM PST 24
Finished Feb 08 01:09:08 PM PST 24
Peak memory 208768 kb
Host smart-70b3fe19-f4a9-4602-a0d8-439a7cde1b56
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172573544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2172573544
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2010963956
Short name T257
Test name
Test status
Simulation time 1544915646 ps
CPU time 3.4 seconds
Started Feb 08 01:08:57 PM PST 24
Finished Feb 08 01:09:09 PM PST 24
Peak memory 209516 kb
Host smart-228264f2-9d77-4d42-8e49-b1ca5f43cab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010963956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2010963956
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3085081555
Short name T792
Test name
Test status
Simulation time 77762756 ps
CPU time 3.47 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:09:01 PM PST 24
Peak memory 208692 kb
Host smart-5ddb9fee-37d4-4721-8878-e79ad156546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085081555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3085081555
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2019838710
Short name T195
Test name
Test status
Simulation time 27447638240 ps
CPU time 205.29 seconds
Started Feb 08 01:08:53 PM PST 24
Finished Feb 08 01:12:20 PM PST 24
Peak memory 222572 kb
Host smart-5ef072e3-bca2-46b0-9513-1192be14d2b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019838710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2019838710
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3447085886
Short name T131
Test name
Test status
Simulation time 365892226 ps
CPU time 7.68 seconds
Started Feb 08 01:08:57 PM PST 24
Finished Feb 08 01:09:12 PM PST 24
Peak memory 208868 kb
Host smart-8ca716d8-6a9a-4f38-a949-b4376da8fe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447085886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3447085886
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1314773900
Short name T415
Test name
Test status
Simulation time 43389241 ps
CPU time 2.38 seconds
Started Feb 08 01:08:56 PM PST 24
Finished Feb 08 01:09:00 PM PST 24
Peak memory 209716 kb
Host smart-c86f9cc8-a34b-43c3-bf23-4a23f96c1b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314773900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1314773900
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1136305878
Short name T954
Test name
Test status
Simulation time 27378619 ps
CPU time 0.73 seconds
Started Feb 08 01:09:02 PM PST 24
Finished Feb 08 01:09:08 PM PST 24
Peak memory 205880 kb
Host smart-52688278-df58-4369-b70f-77f6be5b587d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136305878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1136305878
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2227076287
Short name T1060
Test name
Test status
Simulation time 569118756 ps
CPU time 3.85 seconds
Started Feb 08 01:09:02 PM PST 24
Finished Feb 08 01:09:11 PM PST 24
Peak memory 210616 kb
Host smart-082b335f-f42a-4887-a1e6-ce59d7e498c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227076287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2227076287
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2395319866
Short name T677
Test name
Test status
Simulation time 96500967 ps
CPU time 3.14 seconds
Started Feb 08 01:08:59 PM PST 24
Finished Feb 08 01:09:11 PM PST 24
Peak memory 208040 kb
Host smart-4d184a03-42cf-4cf3-bbf4-5fbca6621282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395319866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2395319866
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3945469193
Short name T809
Test name
Test status
Simulation time 102731556 ps
CPU time 3.36 seconds
Started Feb 08 01:08:59 PM PST 24
Finished Feb 08 01:09:11 PM PST 24
Peak memory 222484 kb
Host smart-187f778c-01d3-40f2-bb26-48e40201cf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945469193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3945469193
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3785721275
Short name T937
Test name
Test status
Simulation time 81198644 ps
CPU time 3.72 seconds
Started Feb 08 01:08:55 PM PST 24
Finished Feb 08 01:09:01 PM PST 24
Peak memory 208468 kb
Host smart-852fe00e-b98f-4c4b-802b-bb18adff52d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785721275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3785721275
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2448275982
Short name T849
Test name
Test status
Simulation time 324929971 ps
CPU time 9.21 seconds
Started Feb 08 01:09:02 PM PST 24
Finished Feb 08 01:09:17 PM PST 24
Peak memory 214328 kb
Host smart-76ccea57-bdf5-482e-ab27-a80c9a982341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448275982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2448275982
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3043646506
Short name T652
Test name
Test status
Simulation time 177301165 ps
CPU time 5.85 seconds
Started Feb 08 01:09:02 PM PST 24
Finished Feb 08 01:09:13 PM PST 24
Peak memory 208064 kb
Host smart-7aa3c822-48fd-41d6-8587-ef789996e5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043646506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3043646506
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1316982513
Short name T683
Test name
Test status
Simulation time 106967892 ps
CPU time 2.34 seconds
Started Feb 08 01:09:05 PM PST 24
Finished Feb 08 01:09:12 PM PST 24
Peak memory 206952 kb
Host smart-a56f5f53-7a6e-4fa6-99b0-9a8c748c473c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316982513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1316982513
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1638932070
Short name T878
Test name
Test status
Simulation time 277125870 ps
CPU time 2.98 seconds
Started Feb 08 01:09:04 PM PST 24
Finished Feb 08 01:09:11 PM PST 24
Peak memory 209048 kb
Host smart-24f54ae3-57bb-4aed-9f7d-577873df5763
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638932070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1638932070
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.194252589
Short name T852
Test name
Test status
Simulation time 302522171 ps
CPU time 6.9 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:14 PM PST 24
Peak memory 208032 kb
Host smart-20a8f972-aec4-4a92-be59-8c2c02797054
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194252589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.194252589
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.870821251
Short name T349
Test name
Test status
Simulation time 116421752 ps
CPU time 2.98 seconds
Started Feb 08 01:08:59 PM PST 24
Finished Feb 08 01:09:10 PM PST 24
Peak memory 218116 kb
Host smart-4f4d8ec4-0b49-4642-8b07-5bc50941b8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870821251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.870821251
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2569429134
Short name T913
Test name
Test status
Simulation time 52623257 ps
CPU time 2.68 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:10 PM PST 24
Peak memory 207984 kb
Host smart-ea9e440e-1456-4ab4-87cf-9cdbc012a30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569429134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2569429134
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1000290892
Short name T319
Test name
Test status
Simulation time 141951557 ps
CPU time 4.17 seconds
Started Feb 08 01:09:04 PM PST 24
Finished Feb 08 01:09:12 PM PST 24
Peak memory 208800 kb
Host smart-3b8ceb41-0082-48c8-bca9-0306241f75e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000290892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1000290892
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2407039731
Short name T906
Test name
Test status
Simulation time 323786067 ps
CPU time 4.1 seconds
Started Feb 08 01:08:48 PM PST 24
Finished Feb 08 01:08:53 PM PST 24
Peak memory 219056 kb
Host smart-5c14b6fa-6522-4997-8925-96afe80f9ee2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407039731 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2407039731
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1939978669
Short name T1006
Test name
Test status
Simulation time 106198131 ps
CPU time 4.81 seconds
Started Feb 08 01:08:58 PM PST 24
Finished Feb 08 01:09:12 PM PST 24
Peak memory 209276 kb
Host smart-76b6e86a-af3e-4059-9051-3aed8119410a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939978669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1939978669
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.784763759
Short name T761
Test name
Test status
Simulation time 144895711 ps
CPU time 2.08 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:10 PM PST 24
Peak memory 210776 kb
Host smart-5317adba-ceeb-4722-a0d5-b32f284b1d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784763759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.784763759
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1805532244
Short name T949
Test name
Test status
Simulation time 36036322 ps
CPU time 0.74 seconds
Started Feb 08 01:09:05 PM PST 24
Finished Feb 08 01:09:13 PM PST 24
Peak memory 205888 kb
Host smart-90675f57-3ec0-4bfc-9b30-a4ea6179eed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805532244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1805532244
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2046571278
Short name T300
Test name
Test status
Simulation time 107537312 ps
CPU time 2.48 seconds
Started Feb 08 01:09:03 PM PST 24
Finished Feb 08 01:09:11 PM PST 24
Peak memory 214236 kb
Host smart-7507368f-5847-4d84-a13c-59d8797a2d10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046571278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2046571278
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.961915748
Short name T234
Test name
Test status
Simulation time 1836056171 ps
CPU time 55.01 seconds
Started Feb 08 01:09:05 PM PST 24
Finished Feb 08 01:10:05 PM PST 24
Peak memory 209660 kb
Host smart-8c4f92d3-27e2-467d-88d2-5340aab7fdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961915748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.961915748
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1261435034
Short name T384
Test name
Test status
Simulation time 363326981 ps
CPU time 2.26 seconds
Started Feb 08 01:09:01 PM PST 24
Finished Feb 08 01:09:10 PM PST 24
Peak memory 218572 kb
Host smart-5c45b387-4ae4-4266-a976-744911b2fb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261435034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1261435034
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3705022234
Short name T1026
Test name
Test status
Simulation time 96343519 ps
CPU time 4.49 seconds
Started Feb 08 01:09:06 PM PST 24
Finished Feb 08 01:09:17 PM PST 24
Peak memory 221196 kb
Host smart-19cc8cf9-9241-4fb5-926d-86c67c3095e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705022234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3705022234
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3482730014
Short name T1030
Test name
Test status
Simulation time 259475664 ps
CPU time 4.48 seconds
Started Feb 08 01:09:06 PM PST 24
Finished Feb 08 01:09:17 PM PST 24
Peak memory 222408 kb
Host smart-5ff9eabb-2787-4b4f-bf62-0a9e6869b731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482730014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3482730014
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.87686744
Short name T748
Test name
Test status
Simulation time 126921106 ps
CPU time 3.42 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:11 PM PST 24
Peak memory 216852 kb
Host smart-75293395-231e-42c0-9b90-8897eadedc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87686744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.87686744
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1088584834
Short name T996
Test name
Test status
Simulation time 1085850383 ps
CPU time 37.31 seconds
Started Feb 08 01:09:04 PM PST 24
Finished Feb 08 01:09:45 PM PST 24
Peak memory 218420 kb
Host smart-5a21fb40-2a60-4478-85f7-0f028e4e7106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088584834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1088584834
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.455329875
Short name T246
Test name
Test status
Simulation time 399893291 ps
CPU time 3.36 seconds
Started Feb 08 01:09:02 PM PST 24
Finished Feb 08 01:09:11 PM PST 24
Peak memory 208672 kb
Host smart-2b6ced0b-eca4-4daf-a79f-d8828aebbe6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455329875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.455329875
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.782046711
Short name T709
Test name
Test status
Simulation time 1020282675 ps
CPU time 3.18 seconds
Started Feb 08 01:09:05 PM PST 24
Finished Feb 08 01:09:14 PM PST 24
Peak memory 206912 kb
Host smart-71e3d296-cc86-4245-8816-fddef98be8cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782046711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.782046711
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.317234138
Short name T882
Test name
Test status
Simulation time 80989835 ps
CPU time 2.01 seconds
Started Feb 08 01:09:05 PM PST 24
Finished Feb 08 01:09:13 PM PST 24
Peak memory 207392 kb
Host smart-a828be7b-7d17-4b56-b83f-b447a04e4441
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317234138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.317234138
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3604804584
Short name T265
Test name
Test status
Simulation time 136273885 ps
CPU time 2.68 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:10 PM PST 24
Peak memory 208476 kb
Host smart-b236a419-6b90-47bc-9861-8254d012efe7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604804584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3604804584
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3293447366
Short name T328
Test name
Test status
Simulation time 158852529 ps
CPU time 4.04 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:12 PM PST 24
Peak memory 209176 kb
Host smart-fc981f64-0543-4827-9ebd-d93b076f44b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293447366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3293447366
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.209780722
Short name T686
Test name
Test status
Simulation time 1066532371 ps
CPU time 6.89 seconds
Started Feb 08 01:09:00 PM PST 24
Finished Feb 08 01:09:14 PM PST 24
Peak memory 206628 kb
Host smart-71a0b96f-483f-4b85-9668-70e2c59c09bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209780722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.209780722
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.783792722
Short name T74
Test name
Test status
Simulation time 2146443060 ps
CPU time 53.34 seconds
Started Feb 08 01:09:05 PM PST 24
Finished Feb 08 01:10:04 PM PST 24
Peak memory 215596 kb
Host smart-326cae69-59c6-4668-8753-b0a80495e1be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783792722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.783792722
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1296046972
Short name T1003
Test name
Test status
Simulation time 173605853 ps
CPU time 8.15 seconds
Started Feb 08 01:09:06 PM PST 24
Finished Feb 08 01:09:20 PM PST 24
Peak memory 222632 kb
Host smart-3c47c07f-8ea0-4c1e-a5ce-97a4710046c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296046972 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1296046972
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2583599127
Short name T727
Test name
Test status
Simulation time 106671970 ps
CPU time 4.51 seconds
Started Feb 08 01:08:59 PM PST 24
Finished Feb 08 01:09:12 PM PST 24
Peak memory 207764 kb
Host smart-6eed1615-f6eb-4492-a26f-628a5cf6a7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583599127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2583599127
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.513633056
Short name T605
Test name
Test status
Simulation time 880380018 ps
CPU time 5.08 seconds
Started Feb 08 01:09:03 PM PST 24
Finished Feb 08 01:09:13 PM PST 24
Peak memory 210636 kb
Host smart-82da6c5d-85bc-4dd4-b9de-0d3212be1d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513633056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.513633056
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.519757885
Short name T826
Test name
Test status
Simulation time 31607865 ps
CPU time 0.77 seconds
Started Feb 08 01:04:49 PM PST 24
Finished Feb 08 01:04:50 PM PST 24
Peak memory 205816 kb
Host smart-4836dbab-ebc4-4f9c-9a4e-44594fdd6451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519757885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.519757885
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1314852674
Short name T32
Test name
Test status
Simulation time 500565330 ps
CPU time 4.62 seconds
Started Feb 08 01:04:46 PM PST 24
Finished Feb 08 01:04:51 PM PST 24
Peak memory 209744 kb
Host smart-b01afba3-ff36-4494-a5e9-4cf7cbc27c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314852674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1314852674
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1706424350
Short name T769
Test name
Test status
Simulation time 159722154 ps
CPU time 3.43 seconds
Started Feb 08 01:04:50 PM PST 24
Finished Feb 08 01:04:54 PM PST 24
Peak memory 209684 kb
Host smart-f11203f5-65c6-4a68-95a7-2ce5304db969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706424350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1706424350
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.818608996
Short name T995
Test name
Test status
Simulation time 726355954 ps
CPU time 9.49 seconds
Started Feb 08 01:04:50 PM PST 24
Finished Feb 08 01:05:01 PM PST 24
Peak memory 214396 kb
Host smart-23e003b8-cdf0-4b87-98ad-bf8a928ea433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818608996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.818608996
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3220862047
Short name T281
Test name
Test status
Simulation time 104015021 ps
CPU time 3.85 seconds
Started Feb 08 01:04:52 PM PST 24
Finished Feb 08 01:04:57 PM PST 24
Peak memory 209352 kb
Host smart-d71afb68-d996-430f-9974-773b1318e2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220862047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3220862047
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2265050961
Short name T326
Test name
Test status
Simulation time 371566671 ps
CPU time 11.03 seconds
Started Feb 08 01:04:47 PM PST 24
Finished Feb 08 01:04:58 PM PST 24
Peak memory 209364 kb
Host smart-27e542c4-e546-4621-91a2-2dd65a7e8b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265050961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2265050961
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.4123490986
Short name T1024
Test name
Test status
Simulation time 269903989 ps
CPU time 3.62 seconds
Started Feb 08 01:04:47 PM PST 24
Finished Feb 08 01:04:52 PM PST 24
Peak memory 208140 kb
Host smart-20a01ff3-8d9e-4c9c-8397-ad4e40c4e73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123490986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4123490986
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4235019947
Short name T1034
Test name
Test status
Simulation time 138006838 ps
CPU time 3.53 seconds
Started Feb 08 01:04:47 PM PST 24
Finished Feb 08 01:04:52 PM PST 24
Peak memory 207412 kb
Host smart-b910bb68-139d-4626-bfa0-a0eb7baa0f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235019947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4235019947
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1672031768
Short name T811
Test name
Test status
Simulation time 73229238 ps
CPU time 2.82 seconds
Started Feb 08 01:04:48 PM PST 24
Finished Feb 08 01:04:51 PM PST 24
Peak memory 208372 kb
Host smart-2942070d-f125-45e2-a9d5-0aba9b9f7b24
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672031768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1672031768
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.111051784
Short name T985
Test name
Test status
Simulation time 2495600465 ps
CPU time 13.01 seconds
Started Feb 08 01:04:50 PM PST 24
Finished Feb 08 01:05:05 PM PST 24
Peak memory 208888 kb
Host smart-0c0d0c66-6441-44e9-8998-4394de26b46d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111051784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.111051784
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.4268897757
Short name T757
Test name
Test status
Simulation time 267070634 ps
CPU time 3.57 seconds
Started Feb 08 01:04:51 PM PST 24
Finished Feb 08 01:04:55 PM PST 24
Peak memory 207068 kb
Host smart-a9838db0-934e-4d50-8968-fdcc9b07aad2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268897757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.4268897757
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.279731230
Short name T762
Test name
Test status
Simulation time 700800102 ps
CPU time 5.35 seconds
Started Feb 08 01:04:50 PM PST 24
Finished Feb 08 01:04:56 PM PST 24
Peak memory 209232 kb
Host smart-21cfa4aa-437a-4869-84a2-aec63afdd9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279731230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.279731230
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1182758988
Short name T615
Test name
Test status
Simulation time 40322350 ps
CPU time 2.34 seconds
Started Feb 08 01:04:46 PM PST 24
Finished Feb 08 01:04:49 PM PST 24
Peak memory 206744 kb
Host smart-ba5e3187-8633-431f-a7e9-f24707192bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182758988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1182758988
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.376489902
Short name T77
Test name
Test status
Simulation time 6238159762 ps
CPU time 127.09 seconds
Started Feb 08 01:04:50 PM PST 24
Finished Feb 08 01:06:58 PM PST 24
Peak memory 222800 kb
Host smart-add715b8-d183-4b1c-8f38-0f49604f61a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376489902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.376489902
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3443683410
Short name T619
Test name
Test status
Simulation time 82109427 ps
CPU time 5.1 seconds
Started Feb 08 01:04:48 PM PST 24
Finished Feb 08 01:04:54 PM PST 24
Peak memory 222548 kb
Host smart-731f99ef-87a9-4c43-af87-c55020898f95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443683410 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3443683410
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.4088356406
Short name T1033
Test name
Test status
Simulation time 609240358 ps
CPU time 5.26 seconds
Started Feb 08 01:04:46 PM PST 24
Finished Feb 08 01:04:52 PM PST 24
Peak memory 209244 kb
Host smart-4883b16f-f12a-4b4e-8d0f-37cbb0320283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088356406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.4088356406
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2079111242
Short name T956
Test name
Test status
Simulation time 150388906 ps
CPU time 2.56 seconds
Started Feb 08 01:04:50 PM PST 24
Finished Feb 08 01:04:54 PM PST 24
Peak memory 210204 kb
Host smart-835a496c-61fb-4446-9c5e-29bfcebdd5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079111242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2079111242
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3661903870
Short name T670
Test name
Test status
Simulation time 30118888 ps
CPU time 0.73 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:16 PM PST 24
Peak memory 205720 kb
Host smart-39605b6f-42c2-4050-a1f4-71b4a33e127c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661903870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3661903870
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3203458788
Short name T273
Test name
Test status
Simulation time 157695481 ps
CPU time 3.27 seconds
Started Feb 08 01:05:12 PM PST 24
Finished Feb 08 01:05:16 PM PST 24
Peak memory 215232 kb
Host smart-eb8b01c0-7b6e-4125-a103-d608f1e68ace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203458788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3203458788
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2337605977
Short name T19
Test name
Test status
Simulation time 111498179 ps
CPU time 1.83 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:18 PM PST 24
Peak memory 221588 kb
Host smart-a3bdf200-a1d8-4bd7-948d-d11885263a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337605977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2337605977
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3463374214
Short name T1037
Test name
Test status
Simulation time 88493175 ps
CPU time 2.59 seconds
Started Feb 08 01:05:14 PM PST 24
Finished Feb 08 01:05:18 PM PST 24
Peak memory 208060 kb
Host smart-3c28b3bc-6f67-47ac-897e-47631e00631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463374214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3463374214
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.4233819799
Short name T1059
Test name
Test status
Simulation time 203820004 ps
CPU time 6.05 seconds
Started Feb 08 01:05:17 PM PST 24
Finished Feb 08 01:05:24 PM PST 24
Peak memory 208580 kb
Host smart-ff73d09b-316d-4dc2-9959-dc4576e0c39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233819799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.4233819799
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2086943857
Short name T53
Test name
Test status
Simulation time 520874470 ps
CPU time 5.42 seconds
Started Feb 08 01:05:17 PM PST 24
Finished Feb 08 01:05:23 PM PST 24
Peak memory 214148 kb
Host smart-5ced0e1d-e172-4586-90d3-2904e289b0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086943857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2086943857
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3070330987
Short name T908
Test name
Test status
Simulation time 1140703553 ps
CPU time 4.64 seconds
Started Feb 08 01:05:12 PM PST 24
Finished Feb 08 01:05:18 PM PST 24
Peak memory 208768 kb
Host smart-95aedd59-ae8a-4257-ba62-faec176fd023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070330987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3070330987
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3621834206
Short name T306
Test name
Test status
Simulation time 3291240644 ps
CPU time 22.57 seconds
Started Feb 08 01:04:45 PM PST 24
Finished Feb 08 01:05:08 PM PST 24
Peak memory 208180 kb
Host smart-c884bae3-1d72-4a16-9b19-8968e5b439dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621834206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3621834206
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1956602845
Short name T685
Test name
Test status
Simulation time 128858705 ps
CPU time 3.4 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:19 PM PST 24
Peak memory 208896 kb
Host smart-cb233c50-a7d2-4be5-a62e-380432e8b12c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956602845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1956602845
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3120835323
Short name T412
Test name
Test status
Simulation time 67275977 ps
CPU time 3.53 seconds
Started Feb 08 01:04:48 PM PST 24
Finished Feb 08 01:04:53 PM PST 24
Peak memory 207140 kb
Host smart-6e4b3570-a1d6-4476-a959-b2761636c45f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120835323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3120835323
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.903595269
Short name T992
Test name
Test status
Simulation time 705851706 ps
CPU time 8.14 seconds
Started Feb 08 01:05:12 PM PST 24
Finished Feb 08 01:05:21 PM PST 24
Peak memory 208424 kb
Host smart-333f209c-2114-472b-8095-f74fdd912a0d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903595269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.903595269
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2941243005
Short name T953
Test name
Test status
Simulation time 77319928 ps
CPU time 1.77 seconds
Started Feb 08 01:05:17 PM PST 24
Finished Feb 08 01:05:20 PM PST 24
Peak memory 208084 kb
Host smart-30cfb09a-d98e-40f2-8ba4-74dc27833793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941243005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2941243005
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2089697238
Short name T694
Test name
Test status
Simulation time 176671436 ps
CPU time 2.49 seconds
Started Feb 08 01:04:49 PM PST 24
Finished Feb 08 01:04:52 PM PST 24
Peak memory 207044 kb
Host smart-a49f33f5-3b79-4307-aa92-64a8b311348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089697238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2089697238
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1955632049
Short name T1073
Test name
Test status
Simulation time 1289345067 ps
CPU time 32.42 seconds
Started Feb 08 01:05:11 PM PST 24
Finished Feb 08 01:05:44 PM PST 24
Peak memory 216632 kb
Host smart-c782b53b-40c4-4a74-bbe4-c20cb7a8c67a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955632049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1955632049
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2893396357
Short name T758
Test name
Test status
Simulation time 101659237 ps
CPU time 4.98 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:21 PM PST 24
Peak memory 210380 kb
Host smart-033487d8-6aa7-4abb-832b-f74204e4d3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893396357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2893396357
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2229465184
Short name T999
Test name
Test status
Simulation time 98202963 ps
CPU time 1.57 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:17 PM PST 24
Peak memory 208596 kb
Host smart-23eb4e4e-efc9-453e-ba71-b53576ff0b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229465184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2229465184
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3047021440
Short name T701
Test name
Test status
Simulation time 32690132 ps
CPU time 0.78 seconds
Started Feb 08 01:05:24 PM PST 24
Finished Feb 08 01:05:25 PM PST 24
Peak memory 205864 kb
Host smart-a7a3694c-e74b-458f-a995-2fae963d9358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047021440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3047021440
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.901479050
Short name T346
Test name
Test status
Simulation time 121496413 ps
CPU time 4.43 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:20 PM PST 24
Peak memory 215252 kb
Host smart-e39d1944-a5e9-4ba8-9a35-fd37703f9ca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901479050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.901479050
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.870200211
Short name T818
Test name
Test status
Simulation time 517342079 ps
CPU time 2.19 seconds
Started Feb 08 01:05:12 PM PST 24
Finished Feb 08 01:05:14 PM PST 24
Peak memory 210132 kb
Host smart-b5c80b09-b423-4e36-b5ac-e896cd600969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870200211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.870200211
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3449444224
Short name T755
Test name
Test status
Simulation time 141561097 ps
CPU time 2.59 seconds
Started Feb 08 01:05:16 PM PST 24
Finished Feb 08 01:05:19 PM PST 24
Peak memory 207700 kb
Host smart-d03b1cec-5375-4216-b5f8-bb5da5b2549b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449444224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3449444224
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1714035958
Short name T1014
Test name
Test status
Simulation time 559817585 ps
CPU time 7.34 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:23 PM PST 24
Peak memory 214328 kb
Host smart-b33e693a-7c4f-42db-97b0-41fa21c9c1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714035958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1714035958
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1838234214
Short name T197
Test name
Test status
Simulation time 1291096681 ps
CPU time 5.75 seconds
Started Feb 08 01:05:12 PM PST 24
Finished Feb 08 01:05:19 PM PST 24
Peak memory 214252 kb
Host smart-4b6d7fa7-1139-4da9-9aae-aca6b448433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838234214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1838234214
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.160291793
Short name T869
Test name
Test status
Simulation time 1083330494 ps
CPU time 3.06 seconds
Started Feb 08 01:05:18 PM PST 24
Finished Feb 08 01:05:22 PM PST 24
Peak memory 214244 kb
Host smart-d4765e21-3fcb-4a6a-91c3-69206cada828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160291793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.160291793
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1938892550
Short name T814
Test name
Test status
Simulation time 90869390 ps
CPU time 2.23 seconds
Started Feb 08 01:05:11 PM PST 24
Finished Feb 08 01:05:14 PM PST 24
Peak memory 208276 kb
Host smart-24585c78-49e0-4e74-9925-a9ce78f0e7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938892550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1938892550
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.341024775
Short name T414
Test name
Test status
Simulation time 142564114 ps
CPU time 5.72 seconds
Started Feb 08 01:05:14 PM PST 24
Finished Feb 08 01:05:20 PM PST 24
Peak memory 208084 kb
Host smart-d4afb132-3e3b-4699-b7d8-1f2e225dfdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341024775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.341024775
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3136857924
Short name T671
Test name
Test status
Simulation time 82820436 ps
CPU time 1.97 seconds
Started Feb 08 01:05:12 PM PST 24
Finished Feb 08 01:05:14 PM PST 24
Peak memory 206932 kb
Host smart-151c1180-0cf3-4671-9d7e-6a9286c0f4c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136857924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3136857924
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1381429505
Short name T634
Test name
Test status
Simulation time 38172893 ps
CPU time 2.47 seconds
Started Feb 08 01:05:14 PM PST 24
Finished Feb 08 01:05:17 PM PST 24
Peak memory 208680 kb
Host smart-20634b17-23ca-4497-afee-2f1243a69972
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381429505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1381429505
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1998027143
Short name T355
Test name
Test status
Simulation time 407473372 ps
CPU time 8.88 seconds
Started Feb 08 01:05:14 PM PST 24
Finished Feb 08 01:05:24 PM PST 24
Peak memory 208172 kb
Host smart-e919797e-59b0-4376-83d4-ef8353e5f162
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998027143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1998027143
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1647019302
Short name T243
Test name
Test status
Simulation time 48375990 ps
CPU time 2.84 seconds
Started Feb 08 01:05:18 PM PST 24
Finished Feb 08 01:05:21 PM PST 24
Peak memory 218108 kb
Host smart-1b963e06-2110-47d8-b859-f14f40bec390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647019302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1647019302
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2249908775
Short name T695
Test name
Test status
Simulation time 1018703046 ps
CPU time 4.43 seconds
Started Feb 08 01:05:17 PM PST 24
Finished Feb 08 01:05:23 PM PST 24
Peak memory 208664 kb
Host smart-10c1856c-bc8e-4f09-b88b-2378ab949511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249908775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2249908775
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3670689063
Short name T297
Test name
Test status
Simulation time 412788389 ps
CPU time 12.09 seconds
Started Feb 08 01:05:16 PM PST 24
Finished Feb 08 01:05:29 PM PST 24
Peak memory 215076 kb
Host smart-ab367b4b-d5e4-423f-b9ea-b414ae34e1d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670689063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3670689063
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2278253301
Short name T196
Test name
Test status
Simulation time 1049236583 ps
CPU time 7.34 seconds
Started Feb 08 01:05:20 PM PST 24
Finished Feb 08 01:05:28 PM PST 24
Peak memory 207480 kb
Host smart-f9d80041-d9f7-4468-90d6-42ed36989d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278253301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2278253301
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3718946993
Short name T56
Test name
Test status
Simulation time 104818006 ps
CPU time 2.75 seconds
Started Feb 08 01:05:18 PM PST 24
Finished Feb 08 01:05:22 PM PST 24
Peak memory 210188 kb
Host smart-8cf5c70d-411e-4f5b-b4da-345defba7d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718946993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3718946993
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1082193637
Short name T105
Test name
Test status
Simulation time 17735846 ps
CPU time 0.71 seconds
Started Feb 08 01:05:17 PM PST 24
Finished Feb 08 01:05:19 PM PST 24
Peak memory 205884 kb
Host smart-de71e5c7-e173-4fe7-a5ef-a50084e9dc14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082193637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1082193637
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2427930436
Short name T333
Test name
Test status
Simulation time 673933503 ps
CPU time 6.55 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:23 PM PST 24
Peak memory 215164 kb
Host smart-f3132aaf-a576-47c1-98de-0939df6476ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427930436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2427930436
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2308542406
Short name T285
Test name
Test status
Simulation time 564088322 ps
CPU time 3.78 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:19 PM PST 24
Peak memory 214424 kb
Host smart-861b5db5-60c2-486d-a41d-917c731d5af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308542406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2308542406
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3380017520
Short name T363
Test name
Test status
Simulation time 46582141 ps
CPU time 3.15 seconds
Started Feb 08 01:05:14 PM PST 24
Finished Feb 08 01:05:18 PM PST 24
Peak memory 211036 kb
Host smart-0dee7df2-91fb-47df-a5e7-b11cf6a07b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380017520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3380017520
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1309023059
Short name T710
Test name
Test status
Simulation time 171741590 ps
CPU time 3.59 seconds
Started Feb 08 01:05:33 PM PST 24
Finished Feb 08 01:05:38 PM PST 24
Peak memory 214376 kb
Host smart-4d16b79e-3f0b-4acd-abc9-de748dad4c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309023059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1309023059
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3726495819
Short name T292
Test name
Test status
Simulation time 222563050 ps
CPU time 4.83 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:21 PM PST 24
Peak memory 207048 kb
Host smart-9c805d6a-7de1-4078-843d-b5625dec600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726495819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3726495819
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.369444372
Short name T307
Test name
Test status
Simulation time 55155649 ps
CPU time 2.82 seconds
Started Feb 08 01:05:13 PM PST 24
Finished Feb 08 01:05:16 PM PST 24
Peak memory 208620 kb
Host smart-1e62491a-bbfc-45fa-abb6-fc9579d34f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369444372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.369444372
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3689888093
Short name T815
Test name
Test status
Simulation time 1856429500 ps
CPU time 9.57 seconds
Started Feb 08 01:05:12 PM PST 24
Finished Feb 08 01:05:22 PM PST 24
Peak memory 208108 kb
Host smart-832b8a0e-fe76-4af4-a69d-258c4ca7e02b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689888093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3689888093
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.4186004386
Short name T991
Test name
Test status
Simulation time 24364095 ps
CPU time 1.89 seconds
Started Feb 08 01:05:14 PM PST 24
Finished Feb 08 01:05:16 PM PST 24
Peak memory 206904 kb
Host smart-0a26b1f2-87f0-4973-a150-c4981bf3b8fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186004386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.4186004386
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1953094403
Short name T612
Test name
Test status
Simulation time 54004017 ps
CPU time 2.9 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:18 PM PST 24
Peak memory 206976 kb
Host smart-2c240a54-93fa-4627-ba88-ecd3d8a8c6f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953094403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1953094403
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4265628692
Short name T673
Test name
Test status
Simulation time 177837298 ps
CPU time 1.77 seconds
Started Feb 08 01:05:29 PM PST 24
Finished Feb 08 01:05:33 PM PST 24
Peak memory 206784 kb
Host smart-1d14f6e2-bf82-4ae1-aeff-1e6c44d6417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265628692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4265628692
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.943791949
Short name T606
Test name
Test status
Simulation time 2005837571 ps
CPU time 56.61 seconds
Started Feb 08 01:05:14 PM PST 24
Finished Feb 08 01:06:12 PM PST 24
Peak memory 208252 kb
Host smart-870a027b-0e63-499e-8ac0-7c8a2faaa5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943791949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.943791949
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.4218415993
Short name T318
Test name
Test status
Simulation time 19965119859 ps
CPU time 488.34 seconds
Started Feb 08 01:05:18 PM PST 24
Finished Feb 08 01:13:27 PM PST 24
Peak memory 223848 kb
Host smart-d14f3cb7-0c63-4e26-9834-79ccec49e4ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218415993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.4218415993
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1103570703
Short name T613
Test name
Test status
Simulation time 130500152 ps
CPU time 4.43 seconds
Started Feb 08 01:05:34 PM PST 24
Finished Feb 08 01:05:39 PM PST 24
Peak memory 218592 kb
Host smart-73d67a77-b302-459a-971b-c2e33e459942
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103570703 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1103570703
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2386032800
Short name T302
Test name
Test status
Simulation time 58648044 ps
CPU time 3.95 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:19 PM PST 24
Peak memory 218316 kb
Host smart-be14bc57-fa98-420d-95be-2bed875aee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386032800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2386032800
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1224085832
Short name T790
Test name
Test status
Simulation time 86238771 ps
CPU time 3.63 seconds
Started Feb 08 01:05:18 PM PST 24
Finished Feb 08 01:05:22 PM PST 24
Peak memory 209848 kb
Host smart-ec82caea-1a0a-40de-b5e8-ec4b4e4b65a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224085832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1224085832
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.333578697
Short name T691
Test name
Test status
Simulation time 69086641 ps
CPU time 0.74 seconds
Started Feb 08 01:05:27 PM PST 24
Finished Feb 08 01:05:29 PM PST 24
Peak memory 205888 kb
Host smart-a78de2f7-d585-4520-a3d8-be80a372a082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333578697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.333578697
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2089140970
Short name T62
Test name
Test status
Simulation time 174991660 ps
CPU time 3.07 seconds
Started Feb 08 01:05:17 PM PST 24
Finished Feb 08 01:05:21 PM PST 24
Peak memory 210092 kb
Host smart-6ba7717e-feb7-4551-a241-00140ea99633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089140970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2089140970
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.972914905
Short name T69
Test name
Test status
Simulation time 538594908 ps
CPU time 5.46 seconds
Started Feb 08 01:05:17 PM PST 24
Finished Feb 08 01:05:23 PM PST 24
Peak memory 206972 kb
Host smart-bf9c0058-d291-4151-844a-17247659e031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972914905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.972914905
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1235078387
Short name T385
Test name
Test status
Simulation time 312469396 ps
CPU time 2.49 seconds
Started Feb 08 01:05:25 PM PST 24
Finished Feb 08 01:05:28 PM PST 24
Peak memory 214268 kb
Host smart-421358ce-0394-4e53-92fb-1b8f28599fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235078387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1235078387
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3357182818
Short name T1078
Test name
Test status
Simulation time 182317072 ps
CPU time 4.18 seconds
Started Feb 08 01:05:19 PM PST 24
Finished Feb 08 01:05:24 PM PST 24
Peak memory 222404 kb
Host smart-ac310426-a305-4977-bb89-7e9405ddc01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357182818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3357182818
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2595062601
Short name T645
Test name
Test status
Simulation time 650663506 ps
CPU time 8.57 seconds
Started Feb 08 01:05:20 PM PST 24
Finished Feb 08 01:05:29 PM PST 24
Peak memory 207244 kb
Host smart-500d9dab-67ce-4c8b-969d-05b8495c2dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595062601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2595062601
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4282170052
Short name T584
Test name
Test status
Simulation time 541545068 ps
CPU time 3.4 seconds
Started Feb 08 01:05:15 PM PST 24
Finished Feb 08 01:05:19 PM PST 24
Peak memory 206812 kb
Host smart-787f5aec-9979-476a-9cea-fc9e66ca5dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282170052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4282170052
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2019237494
Short name T829
Test name
Test status
Simulation time 53455207 ps
CPU time 1.9 seconds
Started Feb 08 01:05:12 PM PST 24
Finished Feb 08 01:05:15 PM PST 24
Peak memory 206920 kb
Host smart-490ab4db-242e-41eb-bc99-f3735b4f5df7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019237494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2019237494
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2911367094
Short name T822
Test name
Test status
Simulation time 326274542 ps
CPU time 3.84 seconds
Started Feb 08 01:05:25 PM PST 24
Finished Feb 08 01:05:30 PM PST 24
Peak memory 208988 kb
Host smart-29550598-91f9-46ac-a4e6-8fb7592e0bad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911367094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2911367094
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2505435578
Short name T2
Test name
Test status
Simulation time 150100787 ps
CPU time 3 seconds
Started Feb 08 01:05:21 PM PST 24
Finished Feb 08 01:05:25 PM PST 24
Peak memory 208892 kb
Host smart-505dce73-4d0f-433f-b155-333022e778d5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505435578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2505435578
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3435525608
Short name T903
Test name
Test status
Simulation time 61537650 ps
CPU time 2.7 seconds
Started Feb 08 01:05:18 PM PST 24
Finished Feb 08 01:05:21 PM PST 24
Peak memory 218236 kb
Host smart-d7d38649-0ceb-431c-8a0a-bcdc53af74e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435525608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3435525608
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2118872050
Short name T607
Test name
Test status
Simulation time 176805746 ps
CPU time 2.63 seconds
Started Feb 08 01:05:19 PM PST 24
Finished Feb 08 01:05:22 PM PST 24
Peak memory 206908 kb
Host smart-f4ba838f-c72c-4504-b8a6-29c1e5254b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118872050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2118872050
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1058468921
Short name T1015
Test name
Test status
Simulation time 120637039 ps
CPU time 4.16 seconds
Started Feb 08 01:05:32 PM PST 24
Finished Feb 08 01:05:37 PM PST 24
Peak memory 220008 kb
Host smart-27380efa-8f6e-4092-8fc3-06e00ed84ea2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058468921 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1058468921
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3153716259
Short name T1076
Test name
Test status
Simulation time 160872741 ps
CPU time 6.67 seconds
Started Feb 08 01:05:27 PM PST 24
Finished Feb 08 01:05:35 PM PST 24
Peak memory 214324 kb
Host smart-098f829c-1341-48ed-9a13-f7f0933bb750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153716259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3153716259
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.221346177
Short name T806
Test name
Test status
Simulation time 658098786 ps
CPU time 17.56 seconds
Started Feb 08 01:05:16 PM PST 24
Finished Feb 08 01:05:34 PM PST 24
Peak memory 210708 kb
Host smart-421c788e-1e75-4275-a46c-99eb96844fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221346177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.221346177
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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