| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 8 | 0 | 8 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| invalid_hw_input_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 8 | 0 | 8 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[OtpRootKeyInvalid] | 739 | 1 | T23 | 10 | T91 | 2 | T24 | 10 | ||||
| auto[OtpRootKeyValidLow] | 145 | 1 | T23 | 3 | T24 | 1 | T156 | 1 | ||||
| auto[LcStateInvalid] | 156 | 1 | T77 | 48 | T85 | 36 | T372 | 12 | ||||
| auto[OtpDevIdInvalid] | 60 | 1 | T78 | 24 | T373 | 36 | - | - | ||||
| auto[RomDigestInvalid] | 180 | 1 | T78 | 36 | T250 | 12 | T357 | 72 | ||||
| auto[RomDigestValidLow] | 24 | 1 | T374 | 12 | T375 | 12 | - | - | ||||
| auto[FlashCreatorSeedInvalid] | 72 | 1 | T76 | 12 | T77 | 12 | T374 | 48 | ||||
| auto[FlashOwnerSeedInvalid] | 96 | 1 | T84 | 36 | T85 | 24 | T81 | 12 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |