Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
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Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
77.78 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv


Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 14 1 13 92.86
Crosses 49 13 36 73.47


Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
op_cp 5 1 4 80.00 100 1 1 0
state_cp 7 0 7 100.00 100 1 1 0
wip_cp 2 0 2 100.00 100 1 1 2


Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
state_x_wip_cross 14 1 13 92.86 100 1 1 0
state_x_op_cross 35 12 23 65.71 100 1 1 0


Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 1 4 80.00


Automatically Generated Bins for op_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[OpDisable] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[OpAdvance] 78 1 T19 1 T39 2 T40 1
auto[OpGenId] 15 1 T40 1 T45 1 T42 1
auto[OpGenSwOut] 30 1 T40 1 T8 1 T51 2
auto[OpGenHwOut] 31 1 T91 1 T6 1 T7 1


Summary for Variable state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for state_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] 1852 1 T39 2 T43 1 T91 6
auto[StInit] 158 1 T39 1 T40 2 T41 1
auto[StCreatorRootKey] 49 1 T14 1 T39 1 T7 1
auto[StOwnerIntKey] 46 1 T19 1 T45 1 T46 1
auto[StOwnerKey] 33 1 T6 1 T92 1 T51 1
auto[StDisabled] 428 1 T4 1 T16 1 T39 13
auto[StInvalid] 45 1 T13 1 T33 1 T34 1


Summary for Variable wip_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wip_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3528 1 T1 1 T2 1 T3 1
auto[1] 154 1 T19 1 T39 2 T40 3


Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 14 1 13 92.86 1


Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins
state_cpwip_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] [auto[1]] 0 1 1


Covered bins
state_cp   wip_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[0] 1834 1 T39 2 T43 1 T91 6
auto[StReset] auto[1] 18 1 T178 1 T96 2 T30 1
auto[StInit] auto[0] 70 1 T91 3 T178 2 T179 1
auto[StInit] auto[1] 88 1 T39 1 T40 2 T41 1
auto[StCreatorRootKey] auto[0] 33 1 T14 1 T7 1 T44 1
auto[StCreatorRootKey] auto[1] 16 1 T39 1 T8 1 T178 1
auto[StOwnerIntKey] auto[0] 34 1 T46 1 T47 1 T28 1
auto[StOwnerIntKey] auto[1] 12 1 T19 1 T45 1 T180 1
auto[StOwnerKey] auto[0] 26 1 T92 1 T51 1 T52 1
auto[StOwnerKey] auto[1] 7 1 T6 1 T181 1 T182 1
auto[StDisabled] auto[0] 415 1 T4 1 T16 1 T39 13
auto[StDisabled] auto[1] 13 1 T40 1 T51 1 T183 1
auto[StInvalid] auto[0] 45 1 T13 1 T33 1 T34 1


Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 35 12 23 65.71 12


Automatically Generated Cross Bins for state_x_op_cross

Element holes
state_cpop_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] * -- -- 5


Uncovered bins
state_cp   op_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]] [auto[OpDisable]] -- -- 4
[auto[StOwnerKey]] [auto[OpGenId]] 0 1 1
[auto[StOwnerKey]] [auto[OpDisable]] 0 1 1
[auto[StDisabled]] [auto[OpDisable]] 0 1 1


Covered bins
state_cp   op_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[OpAdvance] 15 1 T178 1 T96 2 T184 1
auto[StReset] auto[OpGenId] 1 1 T185 1 - - - -
auto[StReset] auto[OpGenSwOut] 1 1 T30 1 - - - -
auto[StReset] auto[OpGenHwOut] 1 1 T186 1 - - - -
auto[StInit] auto[OpAdvance] 42 1 T39 1 T41 1 T43 1
auto[StInit] auto[OpGenId] 8 1 T40 1 T42 1 T187 1
auto[StInit] auto[OpGenSwOut] 19 1 T40 1 T51 1 T9 1
auto[StInit] auto[OpGenHwOut] 19 1 T91 1 T7 1 T42 4
auto[StCreatorRootKey] auto[OpAdvance] 7 1 T39 1 T61 1 T188 1
auto[StCreatorRootKey] auto[OpGenId] 2 1 T189 1 T190 1 - -
auto[StCreatorRootKey] auto[OpGenSwOut] 3 1 T8 1 T191 1 T192 1
auto[StCreatorRootKey] auto[OpGenHwOut] 4 1 T178 1 T193 1 T194 1
auto[StOwnerIntKey] auto[OpAdvance] 6 1 T19 1 T180 1 T195 1
auto[StOwnerIntKey] auto[OpGenId] 2 1 T45 1 T196 1 - -
auto[StOwnerIntKey] auto[OpGenSwOut] 1 1 T197 1 - - - -
auto[StOwnerIntKey] auto[OpGenHwOut] 3 1 T198 1 T199 1 T200 1
auto[StOwnerKey] auto[OpAdvance] 2 1 T201 1 T202 1 - -
auto[StOwnerKey] auto[OpGenSwOut] 2 1 T181 1 T203 1 - -
auto[StOwnerKey] auto[OpGenHwOut] 3 1 T6 1 T182 1 T204 1
auto[StDisabled] auto[OpAdvance] 6 1 T40 1 T183 1 T191 1
auto[StDisabled] auto[OpGenId] 2 1 T205 1 T206 1 - -
auto[StDisabled] auto[OpGenSwOut] 4 1 T51 1 T207 1 T208 1
auto[StDisabled] auto[OpGenHwOut] 1 1 T191 1 - - - -