Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11450

1

T1

25

T2

3

T3

7

auto[Attestation]

8167

1

T1

18

T2

5

T3

1

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2848	1			T1	7		T13	4		T15	1
auto[Aes]	3624	1			T1	7		T2	1		T3	1
auto[Kmac]	3440	1			T1	7		T2	2		T3	2
auto[Otbn]	3586	1			T1	5		T2	2		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7963	1			T1	8		T2	8		T3	8
auto[OpGenId]	6119	1			T1	17		T2	3		T3	4
auto[OpGenSwOut]	6272	1			T1	14		T2	5		T3	2
auto[OpGenHwOut]	7226	1			T1	12		T3	2		T4	2
auto[OpDisable]	132	1			T39	1		T40	1		T43	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10295

1

T1

18

T2

8

T3

8

auto[OpDoneFail]

17417

1

T1

33

T2

8

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6514	1			T1	13		T2	1		T3	1
auto[StInit]	4229	1			T1	6		T2	2		T3	2
auto[StCreatorRootKey]	3104	1			T1	6		T2	2		T3	2
auto[StOwnerIntKey]	2628	1			T1	5		T2	2		T3	2
auto[StOwnerKey]	2376	1			T1	5		T2	2		T3	2
auto[StDisabled]	7818	1			T1	16		T2	7		T3	7
auto[StInvalid]	1043	1			T13	25		T33	24		T34	27

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	301	1			T1	1		T13	1		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	134	1			T26	1		T39	1		T40	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	78	1			T46	1		T43	3		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	65	1			T18	1		T39	2		T165	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	70	1			T39	4		T40	1		T7	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	229	1			T18	1		T26	2		T39	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	33	1			T13	1		T23	2		T60	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	340	1			T13	5		T16	1		T39	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	114	1			T1	1		T4	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	93	1			T39	1		T166	1		T167	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	66	1			T39	3		T43	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	60	1			T39	3		T40	2		T165	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	239	1			T2	1		T74	1		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	25	1			T13	1		T34	1		T168	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	290	1			T16	1		T19	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	104	1			T15	1		T39	2		T40	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	90	1			T1	1		T39	1		T40	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	54	1			T4	1		T39	2		T166	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	67	1			T3	1		T39	1		T40	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	207	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	33	1			T13	1		T34	1		T60	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	367	1			T1	2		T13	2		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T39	2		T40	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	98	1			T39	2		T40	1		T166	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	68	1			T39	1		T40	1		T43	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	63	1			T18	1		T26	1		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	173	1			T1	1		T16	2		T74	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	30	1			T13	1		T60	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	98	1			T39	4		T40	4		T43	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	134	1			T1	1		T39	2		T40	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T39	1		T40	1		T169	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	90	1			T26	1		T40	2		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	47	1			T39	1		T40	2		T170	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	184	1			T1	1		T16	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	34	1			T13	1		T34	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	79	1			T39	3		T40	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	99	1			T13	1		T39	4		T165	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	93	1			T39	2		T166	1		T171	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	68	1			T40	3		T166	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	58	1			T1	1		T26	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	243	1			T1	1		T74	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	33	1			T13	1		T33	2		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	85	1			T39	1		T40	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	112	1			T40	5		T171	2		T43	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	59	1			T26	1		T39	2		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	64	1			T1	1		T2	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	54	1			T1	2		T74	1		T40	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	215	1			T26	1		T39	2		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	38	1			T60	1		T24	2		T168	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	88	1			T43	2		T91	1		T7	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	121	1			T40	1		T41	1		T169	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T39	1		T46	1		T170	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T39	1		T171	1		T169	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	42	1			T39	1		T25	1		T7	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	255	1			T2	2		T16	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	41	1			T13	1		T33	1		T60	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	280	1			T1	1		T16	1		T39	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	110	1			T1	1		T16	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	56	1			T16	1		T40	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	52	1			T40	1		T171	1		T7	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T43	1		T7	2		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	168	1			T1	1		T26	1		T39	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	28	1			T33	2		T34	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	478	1			T1	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	142	1			T1	1		T14	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	89	1			T172	1		T7	2		T173	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	81	1			T39	2		T174	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	91	1			T15	1		T27	1		T39	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	298	1			T1	1		T3	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	30	1			T13	1		T33	1		T34	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	410	1			T1	1		T13	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	142	1			T16	1		T40	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	102	1			T39	1		T40	1		T175	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	86	1			T40	1		T175	1		T176	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	89	1			T39	1		T40	2		T166	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	298	1			T1	1		T16	1		T39	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	43	1			T34	1		T23	2		T24	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	477	1			T1	1		T13	1		T32	7
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	134	1			T39	2		T40	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T39	1		T45	1		T127	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	88	1			T27	1		T39	2		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	80	1			T4	1		T32	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	284	1			T32	1		T26	1		T39	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	33	1			T13	1		T33	1		T34	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	46	1			T40	1		T7	6		T69	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	99	1			T1	1		T26	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	66	1			T15	1		T27	1		T39	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	54	1			T39	1		T40	1		T177	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T39	1		T43	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	167	1			T39	1		T40	1		T165	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	39	1			T13	1		T34	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	68	1			T39	1		T40	2		T43	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	132	1			T14	1		T174	1		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	96	1			T39	2		T174	1		T43	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	77	1			T16	1		T39	2		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	95	1			T15	2		T16	2		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	307	1			T1	1		T26	1		T39	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T13	1		T23	2		T168	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	66	1			T40	3		T43	2		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	124	1			T4	1		T14	1		T176	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T40	1		T43	1		T176	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	95	1			T39	2		T40	2		T165	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	89	1			T26	1		T40	1		T167	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	286	1			T18	1		T27	1		T39	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	32	1			T34	1		T168	2		T156	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T40	3		T43	3		T91	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	113	1			T18	1		T32	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T3	1		T32	1		T39	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T32	1		T39	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	90	1			T40	1		T165	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	271	1			T1	1		T18	1		T32	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	30	1			T13	1		T60	1		T168	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	195	1			T18	1		T39	6		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	715	1			T1	1		T13	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	198	1			T39	7		T40	2		T166	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	739	1			T1	1		T2	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	192	1			T1	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	653	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	214	1			T18	1		T26	1		T39	5
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	699	1			T1	3		T13	3		T16	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	194	1			T26	1		T39	1		T40	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	470	1			T1	2		T13	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	204	1			T1	1		T26	1		T39	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	469	1			T1	1		T13	2		T74	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	158	1			T1	3		T2	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	469	1			T26	1		T39	3		T40	7
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	186	1			T39	3		T46	1		T171	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	517	1			T2	2		T13	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	153	1			T16	1		T40	2		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	599	1			T1	3		T16	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	247	1			T15	1		T39	4		T166	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	962	1			T1	3		T3	1		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	259	1			T39	2		T40	4		T166	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	911	1			T1	2		T13	3		T16	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	259	1			T4	1		T32	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	941	1			T1	1		T13	2		T32	8
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	153	1			T15	1		T39	5		T40	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	369	1			T1	1		T13	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	253	1			T15	2		T16	3		T39	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	552	1			T1	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	272	1			T39	1		T40	4		T165	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	526	1			T4	1		T14	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T3	1		T32	2		T39	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	497	1			T1	1		T13	1		T18	2