Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31831

1

T1

53

T2

19

T3

21

auto[1]

269

1

T113

5

T114

10

T130

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31840	1			T1	53		T2	19		T3	21
auto[134217728:268435455]	10	1			T114	1		T225	2		T392	1
auto[268435456:402653183]	9	1			T114	1		T224	2		T234	2
auto[402653184:536870911]	12	1			T130	2		T299	1		T392	1
auto[536870912:671088639]	7	1			T224	1		T336	1		T393	1
auto[671088640:805306367]	10	1			T224	1		T290	1		T335	2
auto[805306368:939524095]	5	1			T299	1		T333	1		T336	1
auto[939524096:1073741823]	14	1			T113	1		T333	1		T326	2
auto[1073741824:1207959551]	8	1			T333	1		T218	1		T335	2
auto[1207959552:1342177279]	6	1			T113	1		T224	1		T234	1
auto[1342177280:1476395007]	12	1			T114	1		T332	1		T333	2
auto[1476395008:1610612735]	7	1			T114	1		T224	1		T299	1
auto[1610612736:1744830463]	9	1			T114	1		T393	1		T394	1
auto[1744830464:1879048191]	6	1			T234	1		T269	1		T395	1
auto[1879048192:2013265919]	8	1			T225	1		T392	1		T333	1
auto[2013265920:2147483647]	10	1			T113	1		T130	1		T392	1
auto[2147483648:2281701375]	13	1			T114	1		T392	1		T332	1
auto[2281701376:2415919103]	6	1			T392	1		T393	1		T220	1
auto[2415919104:2550136831]	6	1			T299	1		T333	1		T290	1
auto[2550136832:2684354559]	13	1			T114	1		T234	1		T396	1
auto[2684354560:2818572287]	3	1			T333	1		T262	1		T395	1
auto[2818572288:2952790015]	10	1			T276	1		T290	1		T220	1
auto[2952790016:3087007743]	4	1			T234	1		T333	1		T395	1
auto[3087007744:3221225471]	5	1			T392	1		T396	1		T394	1
auto[3221225472:3355443199]	11	1			T276	1		T333	1		T336	1
auto[3355443200:3489660927]	10	1			T113	1		T224	1		T392	2
auto[3489660928:3623878655]	3	1			T130	1		T397	1		T282	1
auto[3623878656:3758096383]	7	1			T333	1		T326	3		T335	1
auto[3758096384:3892314111]	7	1			T113	1		T114	1		T392	1
auto[3892314112:4026531839]	11	1			T114	2		T234	1		T396	1
auto[4026531840:4160749567]	11	1			T131	1		T225	1		T234	1
auto[4160749568:4294967295]	7	1			T392	1		T396	1		T333	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31831	1			T1	53		T2	19		T3	21
auto[0:134217727]	auto[1]	9	1			T392	1		T326	1		T241	1
auto[134217728:268435455]	auto[1]	10	1			T114	1		T225	2		T392	1
auto[268435456:402653183]	auto[1]	9	1			T114	1		T224	2		T234	2
auto[402653184:536870911]	auto[1]	12	1			T130	2		T299	1		T392	1
auto[536870912:671088639]	auto[1]	7	1			T224	1		T336	1		T393	1
auto[671088640:805306367]	auto[1]	10	1			T224	1		T290	1		T335	2
auto[805306368:939524095]	auto[1]	5	1			T299	1		T333	1		T336	1
auto[939524096:1073741823]	auto[1]	14	1			T113	1		T333	1		T326	2
auto[1073741824:1207959551]	auto[1]	8	1			T333	1		T218	1		T335	2
auto[1207959552:1342177279]	auto[1]	6	1			T113	1		T224	1		T234	1
auto[1342177280:1476395007]	auto[1]	12	1			T114	1		T332	1		T333	2
auto[1476395008:1610612735]	auto[1]	7	1			T114	1		T224	1		T299	1
auto[1610612736:1744830463]	auto[1]	9	1			T114	1		T393	1		T394	1
auto[1744830464:1879048191]	auto[1]	6	1			T234	1		T269	1		T395	1
auto[1879048192:2013265919]	auto[1]	8	1			T225	1		T392	1		T333	1
auto[2013265920:2147483647]	auto[1]	10	1			T113	1		T130	1		T392	1
auto[2147483648:2281701375]	auto[1]	13	1			T114	1		T392	1		T332	1
auto[2281701376:2415919103]	auto[1]	6	1			T392	1		T393	1		T220	1
auto[2415919104:2550136831]	auto[1]	6	1			T299	1		T333	1		T290	1
auto[2550136832:2684354559]	auto[1]	13	1			T114	1		T234	1		T396	1
auto[2684354560:2818572287]	auto[1]	3	1			T333	1		T262	1		T395	1
auto[2818572288:2952790015]	auto[1]	10	1			T276	1		T290	1		T220	1
auto[2952790016:3087007743]	auto[1]	4	1			T234	1		T333	1		T395	1
auto[3087007744:3221225471]	auto[1]	5	1			T392	1		T396	1		T394	1
auto[3221225472:3355443199]	auto[1]	11	1			T276	1		T333	1		T336	1
auto[3355443200:3489660927]	auto[1]	10	1			T113	1		T224	1		T392	2
auto[3489660928:3623878655]	auto[1]	3	1			T130	1		T397	1		T282	1
auto[3623878656:3758096383]	auto[1]	7	1			T333	1		T326	3		T335	1
auto[3758096384:3892314111]	auto[1]	7	1			T113	1		T114	1		T392	1
auto[3892314112:4026531839]	auto[1]	11	1			T114	2		T234	1		T396	1
auto[4026531840:4160749567]	auto[1]	11	1			T131	1		T225	1		T234	1
auto[4160749568:4294967295]	auto[1]	7	1			T392	1		T396	1		T333	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1476

1

T1

3

T13

4

T16

2

auto[1]

1706

1

T1

2

T4

3

T13

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	121	1			T40	1		T167	1		T43	1
auto[134217728:268435455]	122	1			T26	1		T39	3		T40	2
auto[268435456:402653183]	98	1			T1	1		T4	1		T39	1
auto[402653184:536870911]	91	1			T13	2		T40	2		T45	1
auto[536870912:671088639]	91	1			T16	1		T39	4		T40	1
auto[671088640:805306367]	77	1			T39	1		T167	1		T43	3
auto[805306368:939524095]	109	1			T1	2		T13	1		T27	1
auto[939524096:1073741823]	97	1			T1	2		T39	2		T40	2
auto[1073741824:1207959551]	93	1			T27	1		T39	1		T41	1
auto[1207959552:1342177279]	97	1			T13	1		T15	1		T33	1
auto[1342177280:1476395007]	95	1			T14	1		T15	1		T27	2
auto[1476395008:1610612735]	104	1			T13	2		T39	2		T40	1
auto[1610612736:1744830463]	94	1			T16	1		T33	1		T40	1
auto[1744830464:1879048191]	112	1			T16	1		T40	2		T41	2
auto[1879048192:2013265919]	87	1			T16	1		T39	2		T40	1
auto[2013265920:2147483647]	106	1			T39	2		T40	3		T165	1
auto[2147483648:2281701375]	99	1			T16	1		T19	1		T39	5
auto[2281701376:2415919103]	86	1			T40	1		T91	1		T211	1
auto[2415919104:2550136831]	124	1			T39	2		T40	2		T171	1
auto[2550136832:2684354559]	112	1			T39	2		T40	2		T43	2
auto[2684354560:2818572287]	101	1			T16	1		T19	1		T27	1
auto[2818572288:2952790015]	102	1			T39	2		T40	3		T43	1
auto[2952790016:3087007743]	86	1			T39	1		T40	1		T165	1
auto[3087007744:3221225471]	101	1			T39	1		T41	1		T34	1
auto[3221225472:3355443199]	121	1			T13	1		T16	1		T39	2
auto[3355443200:3489660927]	86	1			T13	1		T39	3		T43	1
auto[3489660928:3623878655]	91	1			T16	1		T39	2		T40	1
auto[3623878656:3758096383]	106	1			T39	3		T40	1		T166	1
auto[3758096384:3892314111]	97	1			T27	1		T39	1		T41	1
auto[3892314112:4026531839]	89	1			T4	2		T33	1		T40	3
auto[4026531840:4160749567]	91	1			T39	1		T40	4		T41	1
auto[4160749568:4294967295]	96	1			T26	1		T39	2		T40	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T40	1		T167	1		T43	1
auto[0:134217727]	auto[1]	63	1			T25	1		T260	1		T228	1
auto[134217728:268435455]	auto[0]	47	1			T39	1		T40	2		T60	1
auto[134217728:268435455]	auto[1]	75	1			T26	1		T39	2		T166	1
auto[268435456:402653183]	auto[0]	43	1			T1	1		T47	1		T7	1
auto[268435456:402653183]	auto[1]	55	1			T4	1		T39	1		T40	1
auto[402653184:536870911]	auto[0]	43	1			T13	2		T171	1		T125	1
auto[402653184:536870911]	auto[1]	48	1			T40	2		T45	1		T43	1
auto[536870912:671088639]	auto[0]	46	1			T39	2		T40	1		T23	1
auto[536870912:671088639]	auto[1]	45	1			T16	1		T39	2		T43	2
auto[671088640:805306367]	auto[0]	40	1			T39	1		T167	1		T43	3
auto[671088640:805306367]	auto[1]	37	1			T7	1		T53	1		T216	1
auto[805306368:939524095]	auto[0]	49	1			T40	1		T43	3		T60	1
auto[805306368:939524095]	auto[1]	60	1			T1	2		T13	1		T27	1
auto[939524096:1073741823]	auto[0]	53	1			T1	2		T39	1		T40	1
auto[939524096:1073741823]	auto[1]	44	1			T39	1		T40	1		T23	1
auto[1073741824:1207959551]	auto[0]	44	1			T41	1		T60	1		T25	1
auto[1073741824:1207959551]	auto[1]	49	1			T27	1		T39	1		T7	1
auto[1207959552:1342177279]	auto[0]	46	1			T13	1		T39	2		T7	1
auto[1207959552:1342177279]	auto[1]	51	1			T15	1		T33	1		T39	2
auto[1342177280:1476395007]	auto[0]	44	1			T27	2		T40	1		T7	1
auto[1342177280:1476395007]	auto[1]	51	1			T14	1		T15	1		T40	1
auto[1476395008:1610612735]	auto[0]	36	1			T39	1		T125	1		T7	2
auto[1476395008:1610612735]	auto[1]	68	1			T13	2		T39	1		T40	1
auto[1610612736:1744830463]	auto[0]	39	1			T16	1		T45	1		T47	1
auto[1610612736:1744830463]	auto[1]	55	1			T33	1		T40	1		T43	4
auto[1744830464:1879048191]	auto[0]	54	1			T41	2		T54	1		T25	1
auto[1744830464:1879048191]	auto[1]	58	1			T16	1		T40	2		T23	1
auto[1879048192:2013265919]	auto[0]	40	1			T39	2		T43	1		T60	1
auto[1879048192:2013265919]	auto[1]	47	1			T16	1		T40	1		T166	1
auto[2013265920:2147483647]	auto[0]	50	1			T40	1		T125	1		T6	1
auto[2013265920:2147483647]	auto[1]	56	1			T39	2		T40	2		T165	1
auto[2147483648:2281701375]	auto[0]	46	1			T16	1		T39	3		T43	1
auto[2147483648:2281701375]	auto[1]	53	1			T19	1		T39	2		T40	1
auto[2281701376:2415919103]	auto[0]	41	1			T7	1		T51	2		T42	1
auto[2281701376:2415919103]	auto[1]	45	1			T40	1		T91	1		T211	1
auto[2415919104:2550136831]	auto[0]	55	1			T43	1		T7	2		T8	1
auto[2415919104:2550136831]	auto[1]	69	1			T39	2		T40	2		T171	1
auto[2550136832:2684354559]	auto[0]	47	1			T39	1		T40	1		T43	1
auto[2550136832:2684354559]	auto[1]	65	1			T39	1		T40	1		T43	1
auto[2684354560:2818572287]	auto[0]	44	1			T27	1		T39	2		T40	1
auto[2684354560:2818572287]	auto[1]	57	1			T16	1		T19	1		T39	3
auto[2818572288:2952790015]	auto[0]	46	1			T40	2		T7	1		T379	1
auto[2818572288:2952790015]	auto[1]	56	1			T39	2		T40	1		T43	1
auto[2952790016:3087007743]	auto[0]	40	1			T40	1		T43	1		T7	1
auto[2952790016:3087007743]	auto[1]	46	1			T39	1		T165	1		T23	1
auto[3087007744:3221225471]	auto[0]	50	1			T39	1		T34	1		T60	1
auto[3087007744:3221225471]	auto[1]	51	1			T41	1		T171	1		T24	1
auto[3221225472:3355443199]	auto[0]	58	1			T13	1		T39	1		T40	1
auto[3221225472:3355443199]	auto[1]	63	1			T16	1		T39	1		T40	3
auto[3355443200:3489660927]	auto[0]	48	1			T7	1		T48	1		T156	1
auto[3355443200:3489660927]	auto[1]	38	1			T13	1		T39	3		T43	1
auto[3489660928:3623878655]	auto[0]	45	1			T39	2		T40	1		T6	1
auto[3489660928:3623878655]	auto[1]	46	1			T16	1		T86	1		T51	1
auto[3623878656:3758096383]	auto[0]	50	1			T39	2		T6	1		T7	1
auto[3623878656:3758096383]	auto[1]	56	1			T39	1		T40	1		T166	1
auto[3758096384:3892314111]	auto[0]	48	1			T27	1		T167	1		T168	1
auto[3758096384:3892314111]	auto[1]	49	1			T39	1		T41	1		T113	1
auto[3892314112:4026531839]	auto[0]	33	1			T40	2		T61	1		T398	1
auto[3892314112:4026531839]	auto[1]	56	1			T4	2		T33	1		T40	1
auto[4026531840:4160749567]	auto[0]	44	1			T40	3		T41	1		T43	1
auto[4026531840:4160749567]	auto[1]	47	1			T39	1		T40	1		T43	1
auto[4160749568:4294967295]	auto[0]	49	1			T39	2		T40	1		T34	2
auto[4160749568:4294967295]	auto[1]	47	1			T26	1		T40	3		T43	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1479

1

T1

4

T13

5

T16

3

auto[1]

1706

1

T1

1

T4

3

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T13	1		T27	2		T39	1
auto[134217728:268435455]	102	1			T16	1		T39	1		T40	1
auto[268435456:402653183]	103	1			T1	1		T39	3		T40	1
auto[402653184:536870911]	122	1			T13	1		T16	1		T27	1
auto[536870912:671088639]	101	1			T33	1		T39	2		T40	2
auto[671088640:805306367]	106	1			T39	2		T40	1		T41	1
auto[805306368:939524095]	80	1			T14	1		T39	2		T170	1
auto[939524096:1073741823]	103	1			T39	4		T40	3		T171	1
auto[1073741824:1207959551]	84	1			T1	2		T13	1		T45	1
auto[1207959552:1342177279]	102	1			T15	1		T16	1		T39	1
auto[1342177280:1476395007]	116	1			T39	3		T40	1		T23	1
auto[1476395008:1610612735]	107	1			T16	2		T167	1		T43	1
auto[1610612736:1744830463]	94	1			T39	1		T40	1		T41	1
auto[1744830464:1879048191]	112	1			T39	1		T40	5		T166	1
auto[1879048192:2013265919]	107	1			T15	1		T16	1		T33	1
auto[2013265920:2147483647]	84	1			T13	2		T39	2		T40	3
auto[2147483648:2281701375]	98	1			T39	1		T40	1		T165	1
auto[2281701376:2415919103]	105	1			T26	2		T39	2		T40	1
auto[2415919104:2550136831]	97	1			T39	1		T40	4		T41	1
auto[2550136832:2684354559]	90	1			T13	1		T171	1		T43	2
auto[2684354560:2818572287]	85	1			T19	1		T39	3		T40	1
auto[2818572288:2952790015]	95	1			T13	1		T16	1		T27	1
auto[2952790016:3087007743]	84	1			T4	2		T39	2		T40	1
auto[3087007744:3221225471]	110	1			T16	1		T33	1		T39	1
auto[3221225472:3355443199]	102	1			T13	1		T39	2		T40	1
auto[3355443200:3489660927]	95	1			T4	1		T39	1		T40	5
auto[3489660928:3623878655]	94	1			T39	3		T40	2		T166	1
auto[3623878656:3758096383]	107	1			T1	1		T19	1		T39	1
auto[3758096384:3892314111]	106	1			T1	1		T27	1		T39	3
auto[3892314112:4026531839]	93	1			T39	4		T40	1		T166	1
auto[4026531840:4160749567]	90	1			T39	1		T41	1		T43	2
auto[4160749568:4294967295]	107	1			T27	1		T43	1		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T27	2		T39	1		T171	1
auto[0:134217727]	auto[1]	56	1			T13	1		T43	1		T5	1
auto[134217728:268435455]	auto[0]	52	1			T16	1		T39	1		T43	1
auto[134217728:268435455]	auto[1]	50	1			T40	1		T43	1		T6	1
auto[268435456:402653183]	auto[0]	50	1			T23	1		T168	1		T69	1
auto[268435456:402653183]	auto[1]	53	1			T1	1		T39	3		T40	1
auto[402653184:536870911]	auto[0]	57	1			T13	1		T27	1		T39	1
auto[402653184:536870911]	auto[1]	65	1			T16	1		T40	3		T166	1
auto[536870912:671088639]	auto[0]	52	1			T39	1		T40	1		T60	1
auto[536870912:671088639]	auto[1]	49	1			T33	1		T39	1		T40	1
auto[671088640:805306367]	auto[0]	51	1			T40	1		T41	1		T168	1
auto[671088640:805306367]	auto[1]	55	1			T39	2		T23	1		T43	1
auto[805306368:939524095]	auto[0]	36	1			T39	1		T7	2		T51	1
auto[805306368:939524095]	auto[1]	44	1			T14	1		T39	1		T170	1
auto[939524096:1073741823]	auto[0]	47	1			T39	1		T40	2		T43	1
auto[939524096:1073741823]	auto[1]	56	1			T39	3		T40	1		T171	1
auto[1073741824:1207959551]	auto[0]	33	1			T1	2		T13	1		T45	1
auto[1073741824:1207959551]	auto[1]	51	1			T165	1		T7	1		T114	1
auto[1207959552:1342177279]	auto[0]	50	1			T45	1		T167	1		T43	2
auto[1207959552:1342177279]	auto[1]	52	1			T15	1		T16	1		T39	1
auto[1342177280:1476395007]	auto[0]	50	1			T39	1		T43	1		T7	1
auto[1342177280:1476395007]	auto[1]	66	1			T39	2		T40	1		T23	1
auto[1476395008:1610612735]	auto[0]	52	1			T16	1		T167	1		T60	1
auto[1476395008:1610612735]	auto[1]	55	1			T16	1		T43	1		T7	2
auto[1610612736:1744830463]	auto[0]	52	1			T39	1		T40	1		T41	1
auto[1610612736:1744830463]	auto[1]	42	1			T69	1		T260	1		T42	1
auto[1744830464:1879048191]	auto[0]	42	1			T39	1		T40	1		T7	1
auto[1744830464:1879048191]	auto[1]	70	1			T40	4		T166	1		T43	1
auto[1879048192:2013265919]	auto[0]	43	1			T39	1		T40	2		T43	1
auto[1879048192:2013265919]	auto[1]	64	1			T15	1		T16	1		T33	1
auto[2013265920:2147483647]	auto[0]	41	1			T13	2		T39	2		T40	1
auto[2013265920:2147483647]	auto[1]	43	1			T40	2		T114	1		T51	1
auto[2147483648:2281701375]	auto[0]	49	1			T40	1		T23	2		T228	1
auto[2147483648:2281701375]	auto[1]	49	1			T39	1		T165	1		T168	1
auto[2281701376:2415919103]	auto[0]	48	1			T39	1		T47	1		T8	1
auto[2281701376:2415919103]	auto[1]	57	1			T26	2		T39	1		T40	1
auto[2415919104:2550136831]	auto[0]	37	1			T40	2		T41	1		T125	1
auto[2415919104:2550136831]	auto[1]	60	1			T39	1		T40	2		T171	1
auto[2550136832:2684354559]	auto[0]	38	1			T43	1		T352	1		T42	1
auto[2550136832:2684354559]	auto[1]	52	1			T13	1		T171	1		T43	1
auto[2684354560:2818572287]	auto[0]	39	1			T39	2		T47	1		T168	1
auto[2684354560:2818572287]	auto[1]	46	1			T19	1		T39	1		T40	1
auto[2818572288:2952790015]	auto[0]	43	1			T39	3		T40	1		T34	1
auto[2818572288:2952790015]	auto[1]	52	1			T13	1		T16	1		T27	1
auto[2952790016:3087007743]	auto[0]	41	1			T39	1		T40	1		T25	1
auto[2952790016:3087007743]	auto[1]	43	1			T4	2		T39	1		T43	2
auto[3087007744:3221225471]	auto[0]	45	1			T16	1		T40	2		T7	2
auto[3087007744:3221225471]	auto[1]	65	1			T33	1		T39	1		T40	1
auto[3221225472:3355443199]	auto[0]	40	1			T13	1		T39	1		T40	1
auto[3221225472:3355443199]	auto[1]	62	1			T39	1		T43	1		T7	2
auto[3355443200:3489660927]	auto[0]	40	1			T39	1		T40	1		T125	1
auto[3355443200:3489660927]	auto[1]	55	1			T4	1		T40	4		T211	1
auto[3489660928:3623878655]	auto[0]	41	1			T39	1		T166	1		T34	2
auto[3489660928:3623878655]	auto[1]	53	1			T39	2		T40	2		T165	1
auto[3623878656:3758096383]	auto[0]	58	1			T1	1		T19	1		T40	2
auto[3623878656:3758096383]	auto[1]	49	1			T39	1		T43	2		T113	1
auto[3758096384:3892314111]	auto[0]	51	1			T1	1		T27	1		T23	1
auto[3758096384:3892314111]	auto[1]	55	1			T39	3		T171	1		T43	3
auto[3892314112:4026531839]	auto[0]	48	1			T39	1		T7	2		T86	1
auto[3892314112:4026531839]	auto[1]	45	1			T39	3		T40	1		T166	1
auto[4026531840:4160749567]	auto[0]	42	1			T39	1		T113	1		T7	1
auto[4026531840:4160749567]	auto[1]	48	1			T41	1		T43	2		T7	2
auto[4160749568:4294967295]	auto[0]	63	1			T27	1		T6	1		T25	1
auto[4160749568:4294967295]	auto[1]	44	1			T43	1		T113	1		T51	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1495

1

T1

3

T13

3

T16

4

auto[1]

1690

1

T1

2

T4

3

T13

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T14	1		T16	1		T39	1
auto[134217728:268435455]	101	1			T40	2		T43	2		T54	1
auto[268435456:402653183]	105	1			T16	1		T40	1		T41	1
auto[402653184:536870911]	107	1			T39	3		T40	3		T34	1
auto[536870912:671088639]	93	1			T39	1		T40	1		T45	1
auto[671088640:805306367]	94	1			T16	1		T39	2		T40	1
auto[805306368:939524095]	91	1			T16	1		T39	1		T41	1
auto[939524096:1073741823]	115	1			T15	1		T19	1		T27	1
auto[1073741824:1207959551]	106	1			T13	1		T39	4		T40	2
auto[1207959552:1342177279]	102	1			T4	1		T16	1		T39	3
auto[1342177280:1476395007]	81	1			T39	2		T40	2		T25	1
auto[1476395008:1610612735]	87	1			T40	1		T41	1		T43	1
auto[1610612736:1744830463]	87	1			T39	2		T40	2		T41	1
auto[1744830464:1879048191]	92	1			T13	1		T19	1		T39	1
auto[1879048192:2013265919]	104	1			T1	1		T15	1		T16	1
auto[2013265920:2147483647]	100	1			T39	2		T43	3		T47	1
auto[2147483648:2281701375]	100	1			T13	1		T39	1		T40	3
auto[2281701376:2415919103]	103	1			T1	1		T39	2		T40	1
auto[2415919104:2550136831]	105	1			T26	1		T33	1		T39	5
auto[2550136832:2684354559]	90	1			T43	1		T60	1		T6	1
auto[2684354560:2818572287]	110	1			T27	1		T39	3		T40	1
auto[2818572288:2952790015]	108	1			T27	2		T39	1		T40	2
auto[2952790016:3087007743]	100	1			T16	1		T39	1		T40	5
auto[3087007744:3221225471]	119	1			T1	1		T4	1		T13	1
auto[3221225472:3355443199]	119	1			T1	1		T4	1		T13	1
auto[3355443200:3489660927]	99	1			T13	1		T27	1		T33	1
auto[3489660928:3623878655]	93	1			T27	1		T39	1		T40	1
auto[3623878656:3758096383]	100	1			T1	1		T16	1		T39	3
auto[3758096384:3892314111]	104	1			T39	3		T43	3		T60	1
auto[3892314112:4026531839]	75	1			T39	2		T40	1		T43	2
auto[4026531840:4160749567]	94	1			T13	2		T39	1		T40	2
auto[4160749568:4294967295]	96	1			T33	1		T39	2		T165	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	50	1			T16	1		T39	1		T40	1
auto[0:134217727]	auto[1]	55	1			T14	1		T40	1		T41	1
auto[134217728:268435455]	auto[0]	47	1			T40	1		T43	1		T7	2
auto[134217728:268435455]	auto[1]	54	1			T40	1		T43	1		T54	1
auto[268435456:402653183]	auto[0]	52	1			T40	1		T41	1		T113	1
auto[268435456:402653183]	auto[1]	53	1			T16	1		T43	1		T68	1
auto[402653184:536870911]	auto[0]	44	1			T40	2		T34	1		T54	1
auto[402653184:536870911]	auto[1]	63	1			T39	3		T40	1		T171	1
auto[536870912:671088639]	auto[0]	44	1			T40	1		T45	1		T216	1
auto[536870912:671088639]	auto[1]	49	1			T39	1		T114	1		T274	1
auto[671088640:805306367]	auto[0]	43	1			T39	2		T171	1		T43	1
auto[671088640:805306367]	auto[1]	51	1			T16	1		T40	1		T43	2
auto[805306368:939524095]	auto[0]	47	1			T16	1		T41	1		T170	1
auto[805306368:939524095]	auto[1]	44	1			T39	1		T43	1		T91	1
auto[939524096:1073741823]	auto[0]	46	1			T27	1		T7	1		T156	1
auto[939524096:1073741823]	auto[1]	69	1			T15	1		T19	1		T39	1
auto[1073741824:1207959551]	auto[0]	45	1			T39	3		T40	1		T60	1
auto[1073741824:1207959551]	auto[1]	61	1			T13	1		T39	1		T40	1
auto[1207959552:1342177279]	auto[0]	45	1			T16	1		T39	1		T40	1
auto[1207959552:1342177279]	auto[1]	57	1			T4	1		T39	2		T40	2
auto[1342177280:1476395007]	auto[0]	43	1			T39	1		T40	2		T25	1
auto[1342177280:1476395007]	auto[1]	38	1			T39	1		T228	1		T51	1
auto[1476395008:1610612735]	auto[0]	40	1			T40	1		T41	1		T168	1
auto[1476395008:1610612735]	auto[1]	47	1			T43	1		T7	1		T225	1
auto[1610612736:1744830463]	auto[0]	41	1			T23	1		T6	1		T69	1
auto[1610612736:1744830463]	auto[1]	46	1			T39	2		T40	2		T41	1
auto[1744830464:1879048191]	auto[0]	49	1			T13	1		T19	1		T39	1
auto[1744830464:1879048191]	auto[1]	43	1			T40	2		T24	1		T7	1
auto[1879048192:2013265919]	auto[0]	50	1			T16	1		T39	1		T40	1
auto[1879048192:2013265919]	auto[1]	54	1			T1	1		T15	1		T39	1
auto[2013265920:2147483647]	auto[0]	57	1			T39	2		T43	1		T47	1
auto[2013265920:2147483647]	auto[1]	43	1			T43	2		T51	1		T216	1
auto[2147483648:2281701375]	auto[0]	45	1			T40	1		T23	1		T69	1
auto[2147483648:2281701375]	auto[1]	55	1			T13	1		T39	1		T40	2
auto[2281701376:2415919103]	auto[0]	48	1			T34	1		T43	1		T7	2
auto[2281701376:2415919103]	auto[1]	55	1			T1	1		T39	2		T40	1
auto[2415919104:2550136831]	auto[0]	54	1			T39	3		T34	1		T43	1
auto[2415919104:2550136831]	auto[1]	51	1			T26	1		T33	1		T39	2
auto[2550136832:2684354559]	auto[0]	46	1			T43	1		T60	1		T6	1
auto[2550136832:2684354559]	auto[1]	44	1			T7	1		T260	1		T51	1
auto[2684354560:2818572287]	auto[0]	55	1			T39	2		T40	1		T171	1
auto[2684354560:2818572287]	auto[1]	55	1			T27	1		T39	1		T171	1
auto[2818572288:2952790015]	auto[0]	50	1			T27	1		T39	1		T40	1
auto[2818572288:2952790015]	auto[1]	58	1			T27	1		T40	1		T166	1
auto[2952790016:3087007743]	auto[0]	47	1			T40	4		T43	1		T57	1
auto[2952790016:3087007743]	auto[1]	53	1			T16	1		T39	1		T40	1
auto[3087007744:3221225471]	auto[0]	53	1			T1	1		T39	1		T40	1
auto[3087007744:3221225471]	auto[1]	66	1			T4	1		T13	1		T26	1
auto[3221225472:3355443199]	auto[0]	51	1			T1	1		T13	1		T40	1
auto[3221225472:3355443199]	auto[1]	68	1			T4	1		T39	2		T166	1
auto[3355443200:3489660927]	auto[0]	45	1			T27	1		T39	2		T167	1
auto[3355443200:3489660927]	auto[1]	54	1			T13	1		T33	1		T40	1
auto[3489660928:3623878655]	auto[0]	47	1			T27	1		T43	1		T7	2
auto[3489660928:3623878655]	auto[1]	46	1			T39	1		T40	1		T125	1
auto[3623878656:3758096383]	auto[0]	44	1			T1	1		T40	1		T43	1
auto[3623878656:3758096383]	auto[1]	56	1			T16	1		T39	3		T23	1
auto[3758096384:3892314111]	auto[0]	54	1			T39	2		T60	1		T168	1
auto[3758096384:3892314111]	auto[1]	50	1			T39	1		T43	3		T57	1
auto[3892314112:4026531839]	auto[0]	30	1			T39	1		T40	1		T255	1
auto[3892314112:4026531839]	auto[1]	45	1			T39	1		T43	2		T7	2
auto[4026531840:4160749567]	auto[0]	43	1			T13	1		T39	1		T60	1
auto[4026531840:4160749567]	auto[1]	51	1			T13	1		T40	2		T165	1
auto[4160749568:4294967295]	auto[0]	40	1			T39	1		T167	1		T23	1
auto[4160749568:4294967295]	auto[1]	56	1			T33	1		T39	1		T165	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1497

1

T1

2

T13

4

T16

3

auto[1]

1690

1

T1

3

T4

3

T13

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T1	1		T40	1		T43	2
auto[134217728:268435455]	93	1			T1	1		T39	3		T40	1
auto[268435456:402653183]	105	1			T16	2		T39	2		T34	1
auto[402653184:536870911]	106	1			T27	1		T39	1		T40	1
auto[536870912:671088639]	107	1			T39	1		T40	1		T165	1
auto[671088640:805306367]	101	1			T39	4		T40	3		T45	1
auto[805306368:939524095]	99	1			T13	1		T16	1		T19	1
auto[939524096:1073741823]	105	1			T39	3		T40	4		T34	1
auto[1073741824:1207959551]	97	1			T39	1		T40	3		T43	1
auto[1207959552:1342177279]	91	1			T40	2		T43	1		T125	1
auto[1342177280:1476395007]	89	1			T33	1		T39	1		T40	3
auto[1476395008:1610612735]	112	1			T19	1		T39	6		T43	3
auto[1610612736:1744830463]	109	1			T1	1		T4	1		T27	1
auto[1744830464:1879048191]	100	1			T39	1		T40	2		T45	1
auto[1879048192:2013265919]	93	1			T39	2		T40	3		T6	1
auto[2013265920:2147483647]	102	1			T16	1		T39	2		T166	1
auto[2147483648:2281701375]	93	1			T39	3		T40	1		T41	1
auto[2281701376:2415919103]	104	1			T4	1		T13	1		T39	3
auto[2415919104:2550136831]	88	1			T16	1		T39	1		T40	1
auto[2550136832:2684354559]	75	1			T39	1		T40	1		T43	3
auto[2684354560:2818572287]	93	1			T1	1		T4	1		T16	1
auto[2818572288:2952790015]	100	1			T27	1		T39	1		T40	4
auto[2952790016:3087007743]	114	1			T26	1		T33	1		T39	4
auto[3087007744:3221225471]	104	1			T13	1		T167	1		T43	2
auto[3221225472:3355443199]	109	1			T14	1		T16	1		T39	1
auto[3355443200:3489660927]	112	1			T13	1		T26	1		T39	1
auto[3489660928:3623878655]	101	1			T13	1		T15	2		T39	1
auto[3623878656:3758096383]	103	1			T1	1		T13	1		T39	1
auto[3758096384:3892314111]	90	1			T16	1		T39	2		T40	4
auto[3892314112:4026531839]	92	1			T13	1		T27	1		T39	1
auto[4026531840:4160749567]	98	1			T13	1		T39	2		T41	1
auto[4160749568:4294967295]	93	1			T39	2		T23	1		T43	1