Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2843

1

T1

5

T4

2

T13

8

auto[1]

265

1

T113

8

T114

6

T130

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T39	1		T40	1		T167	1
auto[134217728:268435455]	87	1			T15	1		T39	1		T40	1
auto[268435456:402653183]	110	1			T39	2		T40	1		T165	1
auto[402653184:536870911]	95	1			T13	1		T45	1		T41	1
auto[536870912:671088639]	103	1			T13	1		T39	2		T40	2
auto[671088640:805306367]	90	1			T33	1		T39	2		T40	2
auto[805306368:939524095]	90	1			T1	1		T16	2		T39	1
auto[939524096:1073741823]	80	1			T16	1		T39	1		T43	1
auto[1073741824:1207959551]	107	1			T40	1		T166	1		T43	1
auto[1207959552:1342177279]	112	1			T13	1		T16	1		T27	1
auto[1342177280:1476395007]	93	1			T39	2		T40	2		T166	1
auto[1476395008:1610612735]	104	1			T27	1		T39	2		T40	4
auto[1610612736:1744830463]	94	1			T13	1		T16	1		T33	1
auto[1744830464:1879048191]	114	1			T39	1		T40	2		T166	1
auto[1879048192:2013265919]	97	1			T13	1		T16	1		T40	2
auto[2013265920:2147483647]	106	1			T27	1		T39	2		T34	1
auto[2147483648:2281701375]	84	1			T27	1		T39	1		T170	1
auto[2281701376:2415919103]	99	1			T1	1		T33	1		T39	1
auto[2415919104:2550136831]	91	1			T1	1		T39	2		T40	2
auto[2550136832:2684354559]	101	1			T15	1		T27	1		T40	3
auto[2684354560:2818572287]	86	1			T1	1		T39	4		T40	2
auto[2818572288:2952790015]	92	1			T39	3		T43	3		T113	1
auto[2952790016:3087007743]	90	1			T39	2		T40	1		T43	4
auto[3087007744:3221225471]	102	1			T4	1		T13	1		T26	1
auto[3221225472:3355443199]	87	1			T19	1		T45	1		T171	1
auto[3355443200:3489660927]	103	1			T1	1		T13	1		T27	1
auto[3489660928:3623878655]	105	1			T4	1		T13	1		T19	1
auto[3623878656:3758096383]	88	1			T14	1		T39	2		T40	1
auto[3758096384:3892314111]	100	1			T16	1		T39	1		T40	1
auto[3892314112:4026531839]	97	1			T39	2		T43	1		T60	1
auto[4026531840:4160749567]	102	1			T39	2		T40	2		T167	1
auto[4160749568:4294967295]	104	1			T16	1		T26	1		T39	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	85	1			T39	1		T40	1		T167	1
auto[0:134217727]	auto[1]	10	1			T113	1		T392	1		T290	1
auto[134217728:268435455]	auto[0]	82	1			T15	1		T39	1		T40	1
auto[134217728:268435455]	auto[1]	5	1			T113	1		T114	1		T401	1
auto[268435456:402653183]	auto[0]	99	1			T39	2		T40	1		T165	1
auto[268435456:402653183]	auto[1]	11	1			T332	1		T396	1		T276	1
auto[402653184:536870911]	auto[0]	90	1			T13	1		T45	1		T41	1
auto[402653184:536870911]	auto[1]	5	1			T396	1		T326	1		T220	1
auto[536870912:671088639]	auto[0]	97	1			T13	1		T39	2		T40	2
auto[536870912:671088639]	auto[1]	6	1			T130	1		T333	1		T227	1
auto[671088640:805306367]	auto[0]	86	1			T33	1		T39	2		T40	2
auto[671088640:805306367]	auto[1]	4	1			T336	1		T400	1		T404	1
auto[805306368:939524095]	auto[0]	80	1			T1	1		T16	2		T39	1
auto[805306368:939524095]	auto[1]	10	1			T131	2		T393	1		T220	2
auto[939524096:1073741823]	auto[0]	68	1			T16	1		T39	1		T43	1
auto[939524096:1073741823]	auto[1]	12	1			T299	1		T336	1		T241	1
auto[1073741824:1207959551]	auto[0]	104	1			T40	1		T166	1		T43	1
auto[1073741824:1207959551]	auto[1]	3	1			T335	1		T395	1		T406	1
auto[1207959552:1342177279]	auto[0]	104	1			T13	1		T16	1		T27	1
auto[1207959552:1342177279]	auto[1]	8	1			T114	1		T392	1		T276	1
auto[1342177280:1476395007]	auto[0]	79	1			T39	2		T40	2		T166	1
auto[1342177280:1476395007]	auto[1]	14	1			T114	1		T224	2		T299	2
auto[1476395008:1610612735]	auto[0]	96	1			T27	1		T39	2		T40	4
auto[1476395008:1610612735]	auto[1]	8	1			T225	1		T299	1		T332	1
auto[1610612736:1744830463]	auto[0]	87	1			T13	1		T16	1		T33	1
auto[1610612736:1744830463]	auto[1]	7	1			T114	1		T131	1		T332	1
auto[1744830464:1879048191]	auto[0]	104	1			T39	1		T40	2		T166	1
auto[1744830464:1879048191]	auto[1]	10	1			T130	1		T234	1		T333	1
auto[1879048192:2013265919]	auto[0]	90	1			T13	1		T16	1		T40	2
auto[1879048192:2013265919]	auto[1]	7	1			T113	1		T392	1		T290	2
auto[2013265920:2147483647]	auto[0]	92	1			T27	1		T39	2		T34	1
auto[2013265920:2147483647]	auto[1]	14	1			T224	1		T225	2		T332	1
auto[2147483648:2281701375]	auto[0]	75	1			T27	1		T39	1		T170	1
auto[2147483648:2281701375]	auto[1]	9	1			T113	2		T224	1		T299	1
auto[2281701376:2415919103]	auto[0]	92	1			T1	1		T33	1		T39	1
auto[2281701376:2415919103]	auto[1]	7	1			T130	1		T225	2		T333	1
auto[2415919104:2550136831]	auto[0]	80	1			T1	1		T39	2		T40	2
auto[2415919104:2550136831]	auto[1]	11	1			T224	2		T131	1		T326	1
auto[2550136832:2684354559]	auto[0]	92	1			T15	1		T27	1		T40	3
auto[2550136832:2684354559]	auto[1]	9	1			T299	1		T234	2		T336	1
auto[2684354560:2818572287]	auto[0]	79	1			T1	1		T39	4		T40	2
auto[2684354560:2818572287]	auto[1]	7	1			T234	1		T326	2		T403	1
auto[2818572288:2952790015]	auto[0]	85	1			T39	3		T43	3		T25	1
auto[2818572288:2952790015]	auto[1]	7	1			T113	1		T276	1		T335	1
auto[2952790016:3087007743]	auto[0]	84	1			T39	2		T40	1		T43	4
auto[2952790016:3087007743]	auto[1]	6	1			T114	1		T225	1		T299	1
auto[3087007744:3221225471]	auto[0]	90	1			T4	1		T13	1		T26	1
auto[3087007744:3221225471]	auto[1]	12	1			T299	2		T234	1		T333	1
auto[3221225472:3355443199]	auto[0]	81	1			T19	1		T45	1		T171	1
auto[3221225472:3355443199]	auto[1]	6	1			T131	1		T225	1		T220	1
auto[3355443200:3489660927]	auto[0]	89	1			T1	1		T13	1		T27	1
auto[3355443200:3489660927]	auto[1]	14	1			T130	1		T392	1		T396	1
auto[3489660928:3623878655]	auto[0]	97	1			T4	1		T13	1		T19	1
auto[3489660928:3623878655]	auto[1]	8	1			T131	1		T276	1		T333	2
auto[3623878656:3758096383]	auto[0]	80	1			T14	1		T39	2		T40	1
auto[3623878656:3758096383]	auto[1]	8	1			T131	2		T290	2		T400	1
auto[3758096384:3892314111]	auto[0]	96	1			T16	1		T39	1		T40	1
auto[3758096384:3892314111]	auto[1]	4	1			T276	1		T336	1		T282	1
auto[3892314112:4026531839]	auto[0]	92	1			T39	2		T43	1		T60	1
auto[3892314112:4026531839]	auto[1]	5	1			T396	1		T336	2		T394	1
auto[4026531840:4160749567]	auto[0]	96	1			T39	2		T40	2		T167	1
auto[4026531840:4160749567]	auto[1]	6	1			T114	1		T395	1		T301	1
auto[4160749568:4294967295]	auto[0]	92	1			T16	1		T26	1		T39	1
auto[4160749568:4294967295]	auto[1]	12	1			T113	2		T224	1		T396	1